CAT24AA01WI-3 [CATALYST]
1-Kb and 2-Kb I2C CMOS Serial EEPROM; 1 - KB和2 KB的I2C CMOS串行EEPROM
| 型号： | CAT24AA01WI-3 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 1-Kb and 2-Kb I2C CMOS Serial EEPROM |
| 文件： | 总13页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24AA01, CAT24AA02
1-Kb and 2-Kb I2C CMOS Serial EEPROM
FEATURES
DESCRIPTION
Supports Standard and Fast I2C Protocol
1.7 V to 5.5 V Supply Voltage Range
16-Byte Page Write Buffer
The CAT24AA01/24AA02 are 1-Kb and 2-Kb CMOS
Serial EEPROM devices internally organized as
128x8/256x8 bits.
They feature a 16-byte page write buffer and support
both the Standard (100kHz) and the Fast (400kHz)
I2C protocols.
Hardware Write Protection for entire memory
Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA)
In contrast to the CAT24C01/24C02, the
CAT24AA01/24AA02 have no external address
pins, and are therefore suitable in applications
that require a single CAT24AA01/02 on the I2C
bus.
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial temperature range
RoHS-compliant TSOT-23 5-lead and SOIC
8-lead packages
For Ordering Information details, see page 12.
PIN CONFIGURATION
FUNCTIONAL SYMBOL
SOIC (W)
V
CC
TSOT-23 (TD)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
SCL
VSS
1
2
3
5
WP
WP
SCL
WP
SCL
SDA
SDA
4
VCC
CAT24AA01
CAT24AA02
SDA
* For the location of Pin 1, please consult the corresponding
package drawing.
V
SS
PIN FUNCTIONS
Pin Name
SDA
SCL
Function
Serial Data/Address
Clock Input
WP
Write Protect
Power Supply
Ground
VCC
VSS
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-1120 Rev. B
CAT24AA01, CAT24AA02
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
Units
ºC
Storage Temperature
Voltage on any Pin with Respect to Ground(2)
–65 to +150
–0.5 to +6.5
V
REABILITY CHARACTERISTICS(3)
Symbol
Parameter
Min
1,000,000
100
Units
(4)
NEND
Endurance
Program/Erase Cycles
Years
TDR
Data Retention
D.C. OPERATING CHARACTERISTICS
CC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
V
Symbol
ICCR
ICCW
ISB
Parameter
Test Conditions
Read, fSCL = 400 kHz
Write
Min
Max
Units
mA
mA
μA
μA
V
Read Current
0.5
Write Current
1
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
All I/O Pins at GND or VCC
Pin at GND or VCC
1
1
IL
VIL
-0.5
VCC x 0.3
VIH
VCC x 0.7 VCC + 0.5
V
VOL1
VOL2
VCC ≥ 2.5 V, IOL = 3.0 mA
0.4
0.2
V
VCC < 2.5 V, IOL = 1.0 mA
V
PIN IMPEDANCE CHARACTERISTICS
CC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
V
Symbol Parameter
Conditions
VIN = 0V
VIN = 0V
VIN < VIH
VIN > VIH
Max
8
Units
pF
(3)
CIN
CIN
IWP
SDA I/O Pin Capacitance
(3)
(5)
Input Capacitance (other pins)
WP Input Current
6
pF
100
1
μA
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode @ 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
Doc. No. MD-1120 Rev. B
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24AA01, CAT24AA02
A.C. CHARACTERISTICS (1)
VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C.
Standard
Min Max
100
Fast
Symbol
Parameter
Units
Min
Max
FSCL
tHD:STA
tLOW
Clock Frequency
400
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
μs
ns
ns
μs
μs
ms
ms
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
4.7
0
Data In Setup Time
250
100
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
1000
300
300
300
(2)
tF
tSU:STO
tBUF
4
0.6
1.3
4.7
tAA
3.5
0.9
tDH
Ti(2)
100
100
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
100
100
tSU:WP
tHD:WP
tWR
0
0
WP Hold Time
2.5
2.5
Write Cycle Time
5
1
5
1
(2, 3)
tPU
Power-up to Ready Mode
A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
≤ 50ns
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.3 x VCC, 0.7 x VCC
0.5 x VCC
Current Source: IOL = 3mA (VCC ≥ 2.5V); IOL = 1mA (VCC < 2.5V); CL = 100pF
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-1120 Rev. B
CAT24AA01, CAT24AA02
POWER-ON RESET (POR)
FUNCTIONAL DESCRIPTION
The CAT24AA01/02 supports the Inter-Integrated
Circuit (I2C) Bus protocol. The protocol relies on the
use of a Master device, which provides the clock and
directs bus traffic, and Slave devices which execute
requests. The CAT24AA01/02 operates as a Slave
device. Both Master and Slave can transmit or
receive, but only the Master can assign those roles.
Each CAT24AA01/02 incorporates Power-On Reset
(POR) circuitry which protects the internal logic
against powering up in the wrong state. The device
will power up into Standby mode after VCC exceeds
the POR trigger level and will power down into Reset
mode when VCC drops below the POR trigger level.
This bi-directional POR behavior protects the
device against brown-out failure, following a
temporary loss of power.
I2C BUS PROTOCOL
The 2-wire I2C bus consists of two lines, SCL and
SDA, connected to the VCC supply via pull-up
resistors. The Master provides the clock to the SCL
line, and the Master and Slaves drive the SDA line. A
‘0’ is transmitted by pulling a line LOW and a ‘1’ by
releasing it HIGH. Data transfer may be initiated only
when the bus is not busy (see A.C. Characteristics).
During data transfer, SDA must remain stable while
SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a
START or STOP condition (Figure 1). A START is
generated by a HIGH to LOW transition, while a
STOP is generated by a LOW to HIGH transition. The
START acts like a wake-up call. Absent a START, no
Slave will respond to the Master. The STOP
completes all commands.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8-bit Slave
address (Figure 2). The first four bits of the Slave
address are 1010 (Ah).
For the CAT24AA01/02 the next three bits must
be 000.
PIN DESCRIPTION
¯¯
The last bit, R/W, instructs the Slave to either provide
SCL: The Serial Clock input pin accepts the clock
signal generated by the Master.
(1) or accept (0) data, i.e. it signals a Read (1) or a
Write (0) request.
SDA: The Serial Data I/O pin accepts input data and
delivers output data. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and
delivered on the negative edge of SCL.
Acknowledge
During the 9th clock cycle following every byte sent
onto the bus, the transmitter releases the SDA line,
allowing the receiver to respond. The receiver then
either acknowledges (ACK) by pulling SDA LOW, or
does not acknowledge (NoACK) by letting SDA stay
HIGH (Figure 3). Bus timing is illustrated in Figure 4.
WP: When the Write Protect input pin is forced HIGH
by an external source, all write operations are
inhibited. When the pin is not driven by an external
source, it is pulled LOW internally.
Doc. No. MD-1120 Rev. B
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24AA01, CAT24AA02
Figure 1: Start/Stop Timing
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2: Slave Address Bits
Figure 3: Acknowledge Timing
¯¯
R/W
1
0
1
0
0
0
0
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY (RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
Figure 4: Bus Timing
t
t
t
R
F
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
t
DH
AA
SDA OUT
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-1120 Rev. B
CAT24AA01, CAT24AA02
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave
¯¯
address with the R/W bit set to ‘0’. The Master then
sends an address byte and a data byte and concludes
the session by creating a STOP condition on the bus.
The Slave responds with ACK after every byte sent by
the Master (Figure 5). The STOP starts the internal
Write cycle, and while this operation is in progress
(tWR), the SDA output is tri-stated and the Slave does
not acknowledge the Master (Figure 6).
Page Write
The Byte Write operation can be expanded to Page
Write, by sending more than one data byte to the
Slave before issuing the STOP condition (Figure 7).
Up to 16 distinct data bytes can be loaded into the
internal Page Write Buffer starting at the address
provided by the Master. The page address is latched,
and as long as the Master keeps sending data, the
internal byte address is incremented up to the end of
page, where it then wraps around (within the page).
New data can therefore replace data loaded earlier.
Following the STOP, data loaded during the Page
Write session will be written to memory in a single
internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress,
the Slave will not acknowledge the Master. This
feature enables the Master to immediately follow-up
with a new Read or Write request, rather than wait for
the maximum specified Write time (tWR) to elapse.
Upon receiving a NoACK response from the Slave,
the Master simply repeats the request until the Slave
responds with ACK.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is
left floating or is grounded, it has no impact on the
Write operation. The state of the WP pin is strobed on
the last falling edge of SCL immediately preceding the
1st data byte (Figure 8). If the WP pin is HIGH during
the strobe interval, the Slave will not acknowledge the
data byte and the Write request will be rejected.
Delivery State
The CAT24AA01/02 is shipped erased, i.e., all
bytes are FFh.
Doc. No. MD-1120 Rev. B
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24AA01, CAT24AA02
Figure 5: Byte Write Sequence
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
T
O
P
SLAVE
ADDRESS
ADDRESS
BYTE
DATA
BYTE
a
7
÷ a
d ÷ d
7 0
0
S
P
A
C
K
A
C
K
A
C
K
SLAVE
Figure 6: Write Cycle Timing
SCL
th
8
SDA
Bit
ACK
Byte n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7: Page Write Sequence
S
T
A
R
T
BUS ACTIVITY:
MASTER
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+x
S
T
O
P
ADDRESS
BYTE
SLAVE
ADDRESS
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
n = 1
x ≤ 15
Figure 8: WP Timing
ADDRESS
BYTE
DATA
BYTE
1
8
9
1
7
8
SCL
a
7
a
0
d
d
0
SDA
WP
t
SU:WP
t
HD:WP
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. MD-1120 Rev. B
CAT24AA01, CAT24AA02
READ OPERATIONS
Immediate Read
To read data from memory, the Master creates a
START condition on the bus and then broadcasts a
¯¯
Slave address with the R/W bit set to ‘1’. The Slave
responds with ACK and starts shifting out data
residing at the current address. After receiving the
data, the Master responds with NoACK and
terminates the session by creating a STOP condition
on the bus (Figure 9). The Slave then returns to
Standby mode.
Selective Read
To read data residing at a specific address, the
selected address must first be loaded into the internal
address register. This is done by starting a Byte Write
sequence, whereby the Master creates a START
condition, then broadcasts a Slave address with the
¯¯
R/W bit set to ‘0’ and then sends an address byte to
the Slave. Rather than completing the Byte Write
sequence by sending data, the Master then creates a
START condition and broadcasts a Slave address
¯¯
with the R/W bit set to ‘1’. The Slave responds with
ACK after every byte sent by the Master and then
sends out data residing at the selected address. After
receiving the data, the Master responds with NoACK
and then terminates the session by creating a STOP
condition on the bus (Figure 10).
Sequential Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 11). During Sequential
Read the internal byte address is automatically
incremented up to the end of memory, where it then
wraps around to the beginning of memory. For the
CAT24AA01, the internal address counter will not
wrap around at the end of the 128 byte memory
space.
Doc. No. MD-1120 Rev. B
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24AA01, CAT24AA02
Figure 9: Immediate Read Sequence and Timing
N
O
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
A T
C O
K P
SLAVE
ADDRESS
S
P
A
C
K
DATA
BYTE
SLAVE
SCL
SDA
8
9
th
8
Bit
DATA OUT
NO ACK
STOP
Figure 10: Selective Read Sequence
N
S
T
A
R
T
S
T
A
R
T
O
BUS ACTIVITY:
MASTER
S
A T
C O
K P
ADDRESS
BYTE
SLAVE
ADDRESS
SLAVE
ADDRESS
S
S
P
A
C
K
A
C
K
A
C
K
DATA
BYTE
SLAVE
Figure 11: Sequential Read Sequence
N
O
S
T
O
P
BUS ACTIVITY:
SLAVE
A
C
K
A
C
K
A
C
K
A
C
K
MASTER
ADDRESS
P
A
C
K
SLAVE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. MD-1120 Rev. B
CAT24AA01, CAT24AA02
PACKAGE OUTLINE DRAWINGS
(1)(2)
SOIC 8-Lead 150mils (W)
SYMBOL
MIN
NOM
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
A
A1
b
1.35
0.10
0.33
0.19
4.80
5.80
3.80
c
E1
E
D
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MS-012.
Doc. No. MD-1120 Rev. B
10
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24AA01, CAT24AA02
TSOT 5-Lead (TD)(1)(2)
SYMBOL
MIN
NOM
MAX
1.00
0.10
0.90
0.45
0.20
D
A
A1
A2
b
e
0.01
0.80
0.30
0.12
0.05
0.87
c
0.15
D
2.90 BSC
2.80 BSC
1.60 BSC
0.95TYP
0.40
E1
E
E
E1
e
L
0.30
0º
0.50
8º
L1
L2
θ
0.60 REF
0.25 BSC
TOP VIEW
A2 A
A1
θ
L
b
c
L2
L1
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-193.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. MD-1120 Rev. B
CAT24AA01, CAT24AA02
EXAMPLE OF ORDERING INFORMATION(1)
Prefix
Device # Suffix
CAT
24AA02
TD
I
–
G
T3
Temperature Range
I: Industrial (-40ºC to 85ºC)
Tape & Reel
T: Tape & Reel
3: 3,000/Reel
Company ID
Product Number
24AA01
10: 10,000/Reel
24AA02
Lead Finish
G: NiPdAu
Package
Blank: Matte-Tin
TD: TSOT-23 5-lead
W: SOIC 8-lead
For Product Top Mark Codes, click here:
http://www.catsemi.com/techsupport/producttopmark.asp
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard plated finish is NiPdAu.
(3) The device used in the above example is a CAT24AA02TDI-GT3 (TSOT-23 5-lead, Industrial Temperature, NiPdAu, Tape & Reel,
3,000/Reel).
(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Doc. No. MD-1120 Rev. B
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
REVISION HISTORY
Date
Rev. Reason
12/07/2007
A
Initial Issue
Add CAT24AA01
Add link to Product Top Mark Code
03/12/2008
B
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™
I2C™ is a trademark of Philips Corporation. Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where
personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Document No: MD-1120
Revision:
B
Issue date:
03/12/08
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