CAT22C10PA-20TE13 [CATALYST]
256-Bit Nonvolatile CMOS Static RAM; 256位非易失CMOS静态RAM![CAT22C10PA-20TE13](http://pdffile.icpdf.com/pdf1/p00115/img/icpdf/CAT22C10J-30TE13_626555_icpdf.jpg)
型号: | CAT22C10PA-20TE13 |
厂家: | ![]() |
描述: | 256-Bit Nonvolatile CMOS Static RAM |
文件: | 总10页 (文件大小:74K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
![](http://public.icpdf.com/style/img/ads.jpg)
CAT22C10
256-Bit Nonvolatile CMOS Static RAM
FEATURES
■ Single 5V Supply
■ Low CMOS Power Consumption:
–Active: 40mA Max.
■ Fast RAM Access Times:
–Standby: 30 µA Max.
–200ns
–300ns
■ JEDEC Standard Pinouts:
–18-pin DIP
■ Infinite E2PROM to RAM Recall
■ CMOS and TTL Compatible I/O
■ Power Up/Down Protection
–16-pin SOIC
■ 10 Year Data Retention
■ Commercial, Industrial and Automotive
■ 100,000 Program/Erase Cycles (E2PROM)
Temperature Ranges
DESCRIPTION
TheCAT22C10NVRAMisa256-bitnonvolatilememory
organized as 64 words x 4 bits. The high speed Static
RAM array is bit for bit backed up by a nonvolatile
E2PROM array which allows for easy transfer of data
from RAM array to E2PROM (STORE) and from
E2PROM to RAM (RECALL). STORE operations are
completed in 10ms max. and RECALL operations typi-
cally within 1.5µs. The CAT22C10 features unlimited
RAM write operations either through external RAM
writes or internal recalls from E2PROM. Internal false
store protection circuitry prohibits STORE operations
when VCC is less than 3.0V.
The CAT22C10 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles (E2PROM)
and has a data retention of 10 years. The device is
availableinJEDECapproved18-pinplasticDIPand16-
pin SOIC packages.
PIN FUNCTIONS
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
Pin Name
A0–A5
I/O0–I/O3
WE
Function
Address
Data In/Out
Write Enable
Chip Select
Recall
A
A
A
A
1
2
3
4
5
6
1 6
1 5
1 4
13
12
11
10
9
V
cc
A
4
3
2
1
V
1 8
1
NC
cc
5
A
4
2
3
4
5
6
7
8
1 7
1 6
1 5
1 4
13
NC
I/O
I/O
I/O
I/O
4
3
2
1
A
A
5
I/O
3
A
2
CS
3
A
0
A
I/O
I/O
I/O
1
2
1
0
RECALL
STORE
VCC
CS
A
0
CS
V
7
8
WE
RECALL
ss
STORE
12
Store
V
11
WE
ss
+5V
STORE
9
10
RECALL
VSS
Ground
22C10 F01
22C10 F02
NC
No Connect
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25018-0A 2/98 N-1
1
CAT22C10
BLOCK DIAGRAM
E2PROM ARRAY
A
A
A
ROW
STATIC RAM
0
1
2
STORE
SELECT
ARRAY
RECALL
A
A
A
3
4
5
COLUMN SELECT
CONTROL
LOGIC
READ/WRITE
CIRCUITS
STORE
RECALL
I/O I/O I/O I/O
3
CS WE
0
1
2
5153 FHD F02
MODE SELECTION(1)(2)(3)
Input
Mode
CS
WE
RECALL
STORE
I/O
Output High-Z
Output Data
Input Data
Standby
H
L
X
H
L
H
H
H
L
H
H
H
H
H
L
RAM Read
RAM Write
L
(E2PROM→RAM)
(E2PROM→RAM)
(RAM→E2PROM)
(RAM→E2PROM)
X
H
X
H
H
X
H
X
Output High-Z RECALL
Output High-Z RECALL
Output High-Z STORE
Output High-Z STORE
L
H
H
L
POWER-UP TIMING(4)
Symbol
Parameter
Min.
0.5
Max.
Units
VCCSR
VCC Slew Rate
0.005
V/ms
Note:
(1) RECALL signal has priority over STORE signal when both are applied at the same time.
(2) STORE is inhibited when RECALL is active.
(3) The store operation is inhibited when V is below ≈ 3.0V.
CC
(4) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25018-0A 2/98 N-1
2
CAT22C10
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on Any Pin with
Respect to Ground(2) ..............-2.0 to +VCC +2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
100,000
10
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)
NEND
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
100
Volts
(1)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
= +5V ±10%, unless otherwise specified.
V
CC
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
ICC
Current Consumption
(Operating)
40
mA
All Inputs = 5.5V
TA = 0°C
All I/O’s Open
ISB
Current Consumption
(Standby)
30
µA
CS = VCC
All I/O’s Open
ILI
Input Current
10
10
µA
µA
V
0 ≤ VIN ≤ 5.5V
ILO
Output Leakage Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
RAM Data Holding Voltage
0 ≤ VOUT ≤ 5.5V
VIH
VIL
2
0
VCC
0.8
V
VOH
VOL
VDH
2.4
V
IOH = –2mA
IOL = 4.2mA
VCC
0.4
5.5
V
1.5
V
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol
Parameter
Max.
Unit
pF
Conditions
VI/O = 0V
VIN = 0V
(1)
CI/O
Input/Output Capacitance
Input Capacitance
10
6
(1)
CIN
pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to V +1V.
CC
Doc. No. 25018-0A 2/98 N-1
3
CAT22C10
A.C. CHARACTERISTICS, Write Cycle
V
= +5V ±10%, unless otherwise specified.
CC
22C10-20
22C10-30
Symbol
tWC
Parameter
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Write Cycle Time
CS Write Pulse Width
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid Time
200
150
50
300
150
50
tCW
tAS
CL = 100pF
+1TTL gate
VOH = 2.2V
VOL = 0.65V
VIH = 2.2V
VIL = 0.65V
tWP
150
25
150
25
tWR
tDW
100
0
100
0
tDH
Data Hold Time
(1)
tWZ
Output Disable Time
Output Enable Time
100
100
tOW
0
0
A.C. CHARACTERISTICS, Read Cycle
= +5V ±10%, unless otherwise specified.
V
CC
22C10-20
22C10-30
Symbol
tRC
Parameter
Read Cycle Time
Address Access Time
CS Access Time
Min.
Max.
Min.
Max.
Unit
ns
Conditions
CL = 100pF
+1TTL gate
VOH = 2.2V
VOL = 0.65V
VIH = 2.2V
VIL = 0.65V
200
300
tAA
200
200
300
300
ns
tCO
ns
tOH
Output Data Hold Time
CS Enable Time
0
0
0
0
ns
(1)
tLZ
ns
(1)
tHZ
CS Disable Time
100
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25018-0A 2/98 N-1
4
CAT22C10
A.C. CHARACTERISTICS, Store Cycle
= +5V ±10%, unless otherwise specified.
V
CC
Limits
Symbol
tSTC
Parameter
Store Time
Min.
200
0
Max.
Units
ms
ns
Conditions
10
tSTP
Store Pulse Width
Store Disable Time
Store Enable Time
CL = 100pF + 1TTL gate
VOH = 2.2V, VOL = 0.65V
VIH = 2.2V, VIL = 0.65V
(1)
tSTZ
100
ns
(1)
tOST
ns
A.C. CHARACTERISTICS, Recall Cycle
= +5V ±10%, unless otherwise specified.
V
CC
Limits
Symbol
tRCC
Parameter
Min.
1.4
Max.
Units
µs
Conditions
Recall Cycle Time
Recall Pulse Width
Recall Disable Time
Recall Enable Time
Recall Data Access Time
tRCP
300
ns
CL = 100pF + 1TTL gate
VOH = 2.2V, VOL = 0.65V
VIH = 2.2V, VIL = 0.65V
tRCZ
100
1.1
ns
tORC
0
ns
tARC
µs
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25018-0A 2/98 N-1
5
CAT22C10
intotheStaticRAM.WhentheSTOREinputistakenlow,
it initiates a store operation which transfers the entire
Static RAM array contents into the E2PROM array.
DEVICE OPERATION
The configuration of the CAT22C10 allows a common
address bus to be directly connected to the address
inputs. Additionally, the Input/Output (I/O) pins can be
directly connected to a common I/O bus if the bus has
less than 1 TTL load and 100pF capacitance. If not, the
I/O path should be buffered.
Standby Mode
The chip select (CS) input controls all of the functions of
the CAT22C10. When a high level is supplied to the CS
pin, the device goes into the standby mode where the
outputs are put into a high impendance state and the
power consumption is drastically reduced. With ISB less
than 100µA in standby mode, the designer has the
flexibility to use this part in battery operated systems.
When the chip select (CS) pin goes low, the device is
activated. When CS is forced high, the device goes into
thestandbymodeandconsumesverylittlecurrent.With
the nonvolatile functions inhibited, the device operates
like a Static RAM. The Write Enable (WE) pin selects a
write operation when WE is low and a read operation
whenWEishigh. Ineitherofthesemodes, anarraybyte
(4 bits) can be addressed uniquely by using the address
lines (A0–A5), and that byte will be read or written to
through the Input/Output pins (I/O0–I/O3).
Read
When the chip is enabled (CS = low), the nonvolatile
functions are inhibited (STORE = high and RECALL =
high). WiththeWriteEnable(WE)pinheldhigh, thedata
intheStaticRAMarraymaybeaccessedbyselectingan
address with input pins A0–A5. This will occur when the
outputs are connected to a bus which is loaded by no
morethan100pFand1TTLgate.Iftheloadingisgreater
than this, some additional buffering circuitry is recom-
mended.
The nonvolatile functions are inhibited by holding the
STORE input and the RECALL input high. When the
RECALL input is taken low, it initiates a recall operation
whichtransfersthecontentsoftheentireE2PROMarray
Figure 1. Read Cycle Timing
t
RC
ADDRESS
t
AA
t
CO
CS
t
t
t
LZ
OH
HZ
HIGH-Z
DATA I/O
DATA VALID
5153 FHD F06
Doc. No. 25018-0A 2/98 N-1
6
CAT22C10
Write
With the chip enabled and the nonvolatile functions
inhibited, the Write Enable (WE) pin will select the write
mode when driven to a low level. In this mode, the
address must be supplied for the byte being written.
After the set-up time (tAS), the input data must be
supplied to pins I/O0–I/O3. When these conditions, in-
cluding the write pulse width time (tWP) are met, the data
will be written to the specified location in the Static RAM.
A write function may also be initiated from the standby
mode by driving WE low, inhibiting the nonvolatile func-
tions,supplyingvalidaddresses,andthentakingCS low
and supplying input data.
Figure 2. Write Cycle Timing
t
WC
ADDRESS
t
CW
CS
t
t
t
WP
WR
AS
WE
t
t
DH
DW
DATA VALID
DATA IN
t
t
OW
WZ
HIGH-Z
DATA OUT
5153 FHD F04
Figure 3. Early Write Cycle Timing
t
WC
ADDRESS
CS
t
CW
t
AS
t
WR
t
WP
WE
t
t
DH
DW
DATA VALID
DATA IN
DATA OUT
HIGH-Z
5153 FHD F05
Doc. No. 25018-0A 2/98 N-1
7
CAT22C10
Recall
place independent of the state of CS, WE or A0–A5. The
STOREpinmustbeheldlowforthedurationoftheStore
Pulse Width (tSTP) to ensure that a store operation is
initiated. Once initiated, the STORE pin becomes a
“Don’t Care”, and the store operation will complete its
transfer of the entire contents of the Static RAM array
into the E2PROM array within the Store Cycle time
(tSTC).Ifastoreoperationisinitiatedduringawritecycle,
the contents of the addressed Static RAM byte and its
corresponding byte in the E2PROM array will be un-
known.
At anytime, except during a store operation, taking the
RECALL pin low will initiate a recall operation. This is
independent of the state of CS, WE, or A0–A5. After the
RECALL pin has been held low for the duration of the
Recall Pulse Width (tRCP), the recall will continue inde-
pendent of any other inputs. During the recall, the entire
contentsoftheE2PROMarrayistransferredtotheStatic
RAM array. The first byte of data may be externally
accessedaftertherecalleddataaccesstimefromendof
recall (tARC) is met. After this, any other byte may be
accessed by using the normal read mode.
During the store operation, the outputs are in a high
impedance state. A minimum of 100,000 store opera-
tions can be performed reliably and the data written into
the E2PROM array has a minimum data retention time
of 10 years.
If the RECALL pin is held low for the entire Recall Cycle
time (tRCC), the contents of the Static RAM may be
immediately accessed by using the normal read mode.
A recall operation can be performed an unlimited num-
ber of times without affecting the integrity of the data.
DATA PROTECTION DURING POWER-UP AND
POWER-DOWN
The outputs I/O0–I/O3 will go into the high impedance
state as long as the RECALL signal is held low.
The CAT22C10 has on-chip circuitry which will prevent
a store operation from occurring when VCC falls below
3.0Vtyp. Thisfunctioneliminatesthepotentialhazardof
spurious signals initiating a store operation when the
system power is below 3.0V typ.
Store
At any time, except during a recall operation, taking the
STORE pin low will initiate a store operation. This takes
Figure 4. Recall Cycle Timing
t
RCC
ADDRESS
t
RCP
RECALL
CS
t
ARC
t
ORC
HIGH-Z
DATA I/O
DATA UNDEFINED
DATA VALID
t
5153 FHD F08
RCZ
Figure 5. Store Cycle Timing
t
STC
t
STP
STORE
t
t
STZ
OST
HIGH-Z
DATA I/O
5153 FHD F07
Doc. No. 25018-0A 2/98 N-1
8
CAT22C10
ORDERING INFORMATION
Prefix
Device #
22C10
Suffix
CAT
J
I
-20
-TE13
Optional
Company ID
Temperature Range
Product
Number
Tape & Reel
TE13: 2000/Reel
Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*
Package
Speed
20: 200ns
30: 300ns
P: PDIP
J: SOIC (JEDEC)
* -40˚ to +125˚C is available upon request
22C10 F08
Notes:
(1) The device used in the above example is a 22C10JI-20TE13 (SOIC, Industrial Temperature, 200ns Access Time, Tape & Reel)
Doc. No. 25018-0A 2/98 N-1
9
CAT22C10
Doc. No. 25018-0A 2/98 N-1
10
相关型号:
![](http://pdffile.icpdf.com/pdf2/p00232/img/page/CAT22C10WA-2_1363065_files/CAT22C10WA-2_1363065_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00232/img/page/CAT22C10WA-2_1363065_files/CAT22C10WA-2_1363065_2.jpg)
CAT22C10W-20TE13
IC 64 X 4 NON-VOLATILE SRAM, 200 ns, PDSO16, LEAD AND HALOGEN FREE, SOIC-16, Static RAM
CATALYST
©2020 ICPDF网 联系我们和版权申明