CAT150169MWI-G [CATALYST]
EEPROM,;
| 型号： | CAT150169MWI-G |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总15页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT15008, CAT15016
Voltage Supervisor with 8-Kb and 16-Kb
SPI Serial CMOS EEPROM
FEATURES
DESCRIPTION
The CAT15008/16 (see table below) are memory and
supervisory solutions for microcontroller based systems. A
CMOS serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together. Memory interface is via SPI bus serial
interface.
Precision Power Supply Voltage Monitor
5V, 3.3V, 3V & 2.5V systems
7 threshold voltage options
Active High or Low Reset
Valid reset guaranteed at VCC = 1V
10MHz SPI compatible
The CAT15008/16 provides a precision VCC sense
circuit with two reset output options: CMOS active low
output or CMOS active high. The RESET output is
active whenever VCC is below the reset threshold or
falls below the reset threshold voltage.
32-byte page write buffer
Low power CMOS technology
1,000,000 Program/Erase cycles
100 year data retention
The power supply monitor and reset circuit protect
system controllers during power up/down and against
brownout conditions. Seven reset threshold voltages
support 5V, 3.3V, 3V and 2.5V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 240ms after the supply
voltage exceeds the reset threshold level.
Industrial temperature range
RoHS-compliant 8-pin SOIC package
For Ordering Information details, see page 14.
PIN CONFIGURATION
SOIC (W)
MEMORY SIZE SELECTOR
¯¯
CS
1
2
3
4
8
7
6
5
VCC
Product
15008
Memory density
8-Kbit
¯¯¯¯
SO
RST/RST
¯¯¯
WP
SCK
15016
16-Kbit
SI
VSS
PIN FUNCTION
THRESHOLD SUFFIX SELECTOR
Pin Name
Function
Nominal Threshold
Voltage
Threshold Suffix
Designation
¯¯
CS
Chip Select
4.63V
4.38V
4.00V
3.08V
2.93V
2.63V
2.32V
L
M
J
SO
Serial Data Output
Write Protect
Ground
¯¯¯
WP
VSS
SI
T
S
R
Z
Serial Data Input
Serial Clock Input
Reset Output
Power Supply
SCK
¯¯¯¯
RST/RST
VCC
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1125 Rev. A
CAT15008, CAT15016
BLOCK DIAGRAM
VCC
SO
SCK
SI
VOLTAGE
DETECTOR
EEPROM
RST or RST
CS
WP
VSS
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
Units
°C
Storage Temperature
Voltage on Any Pin with Respect to Ground(2)
-65 to +150
-0.5 to +6.5
V
RELIABILITY CHARACTERISTICS(3)
Symbol Parameter
NEND(4) Endurance
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
TDR
Data Retention
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +5.5V unless otherwise specified.
Limits
Min.
Typ.
Max.
2
Symbol Parameter
ICC Supply Current
Test Condition
Units
Read or Write at 10MHz, SO open
mA
¯¯
12
10
25
20
2
VCC < 5.5V; VIN = VSS or VCC, CS = VCC
ISB
Standby Current
μA
¯¯
CC < 3.6V; VIN = VSS or VCC, CS = VCC
V
IL
I/O Pin Leakage
Pin at GND or VCC
μA
VIL
Input Low Voltage
-0.5
0.3 VCC
V
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
0.7 VCC
VCC + 0.5
0.4
V
V
V
VCC ≥ 2.5V, IOL = 3.0mA
VCC ≥ 2.5V, IOH = -1.6mA
Output High Voltage VCC - 0.8
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5V, 25°C
Doc. No. 1125 Rev. A
2
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT15008, CAT15016
A.C. CHARACTERISTICS (MEMORY)(1)
VCC = 2.5V to 5.5V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
Min.
DC
20
Max.
Units
MHz
ns
fSCK
tSU
tH
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
10
20
ns
tWH
tWL
tLZ
40
ns
40
ns
¯¯¯¯¯
HOLD to Output Low Z
25
2
ns
(2)
tRI
Input Rise Time
Input Fall Time
µs
(2)
tFI
2
µs
¯¯¯¯¯
tHD
tCD
0
ns
HOLD Setup Time
¯¯¯¯¯
HOLD Hold Time
10
ns
tV
Output Valid from Clock Low
Output Hold Time
40
ns
tHO
0
ns
tDIS
tHZ
Output Disable Time
20
25
ns
¯¯¯¯¯
HOLD to Output High Z
ns
¯¯
tCS
15
15
15
10
10
ns
CS High Time
¯¯
tCSS
tCSH
tWPS
tWPH
ns
CS Setup Time
¯¯
ns
CS Hold Time
¯¯¯
ns
WP Setup Time
¯¯¯
WP Hold Time
ns
(4)
tWC
Write Cycle Time
5
1
ms
ms
(2) (3)
tPU
Power-up to Ready Mode
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
¯¯
tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
(4)
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Levels
≤ 10ns
0.3 VCC to 0.7 VCC
Timing Reference Levels
Output Load
0.5 VCC
Current Source: IOL max/ IOH max; CL = 50pF
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1125 Rev. A
CAT15008, CAT15016
ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)
VCC = Full range, TA = -40ºC to +85ºC unless otherwise noted. Typical values at TA = +25ºC and VCC = 5V for
L/M/J versions, VCC = 3.3V for T/S versions, VCC = 3V for R version and VCC = 2.5V for Z version.
Symbol
Parameter
Threshold Conditions
Min
Typ
Max Units
4.70
VTH
Reset Threshold Voltage
TA = +25ºC
L
4.56
4.50
4.31
4.25
3.93
3.89
3.04
3.00
2.89
2.85
2.59
2.55
2.28
2.25
4.63
TA = -40ºC to +85ºC
4.75
TA = +25ºC
4.38
4.00
3.08
2.93
2.63
2.32
4.45
M
J
TA = -40ºC to +85ºC
TA = +25ºC
4.50
4.06
TA = -40ºC to +85ºC
TA = +25ºC
4.10
3.11
V
T
S
R
Z
TA = -40ºC to +85ºC
TA = +25ºC
3.15
2.96
3.00
2.66
2.70
2.35
2.38
TA = -40ºC to +85ºC
TA = +25ºC
TA = -40ºC to +85ºC
TA = +25ºC
TA = -40ºC to +85ºC
Symbol Parameter
Reset Threshold Tempco
VCC to Reset Delay(2)
Conditions
Min
Typ(1) Max Units
30
20
ppm/ºC
µs
tRPD
VCC = VTH to (VTH -100mV)
TA = -40ºC to +85ºC
tPURST Reset Active Timeout Period
140
240
460
0.3
0.4
0.3
ms
V
VCC = VTH min, ISINK = 1.2mA
R/S/T/Z
¯¯¯¯¯¯
RESET Output Voltage Low
VCC = VTH min, ISINK = 3.2mA
J/L/M
(Push-pull, active LOW,
CAT150xx9)
VOL
VCC > 1.0V, ISINK = 50µA
VCC = VTH max, ISOURCE = -500µA
R/S/T/Z
0.8VCC
¯¯¯¯¯¯
(Push-pull, active LOW,
CAT150xx9)
RESET Output Voltage High
VOH
V
VCC = VTH max, ISOURCE = -800µA
J/L/M
VCC - 1.5
VCC > VTH max, ISINK = 1.2mA
R/S/T/Z
RESET Output Voltage Low
0.3
0.4
VOL
V
V
(Push-pull, active HIGH,
CAT150xx1)
VCC > VTH max, ISINK = 3.2mA
J/L/M
RESET Output Voltage High
1.8V < VCC ≤ VTH min,
ISOURCE = -150µA
VOH
0.8VCC
(Push-pull, active HIGH,
CAT150xx1)
Notes:
(1) Production testing done at TA = +25ºC; limits over temperature guaranteed by design only.
(2) RESET output for the CAT150xx9; RESET output for the CAT150xx1.
Doc. No. 1125 Rev. A
4
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT15008, CAT15016
PIN DESCRIPTION
DEVICE OPERATION
¯¯¯¯¯¯
RESET/RESET: Reset output is available in two
The CAT15008/16 products combine the accurate
voltage monitoring capabilities of a standalone voltage
supervisor with the high quality and reliability of
standard EEPROMs from Catalyst Semiconductor.
versions: CMOS Active Low (CAT150xx9) and CMOS
Active High (CAT150xx1). Both versions are push-pull
outputs for high efficiency.
SI: The serial data input pin accepts op-codes,
addresses and data. In SPI modes (0,0) and (1,1)
input data is latched on the rising edge of the SCK
clock input.
RESET CONTROLLER DESCRIPTION
The reset signal is asserted LOW for the CAT150xx9
and HIGH for the CAT150xx1 when the power supply
voltage falls below the threshold trip voltage and
remains asserted for at least 140ms (tPURST) after the
power supply voltage has risen above the threshold.
Reset output timing is shown in Figure 1.
SO: The serial data output pin is used to transfer data
out of the device. In SPI modes (0,0) and (1,1) data is
shifted out on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT15008/16.
The CAT15008/16 devices protect µPs against brown-out
failure. Short duration VCC transients of 4µsec or less and
100mV amplitude typically do not generate a Reset pulse.
¯¯
CS: The chip select input pin is used to enable/disable
¯¯
the CAT15008/16. When CS is high, the SO output is
tri-stated (high impedance) and the device is in
Standby Mode (unless an internal write operation is in
progress). Every communication session between host
and CAT15008/16 must be preceded by a high to low
transition and concluded with a low to high transition of
¯¯
the CS input.
¯¯¯
WP: The write protect input pin will allow all write
¯¯¯
operations to the device when held high. When WP
pin is tied low and the WPEN bit in the Status
Register (refer to Status Register description, later in
this Data Sheet) is set to “1”, writing to the Status
Register is disabled.
VTH
VCC
V
RVALID
tRPD
tPURST
tRPD
tPURST
RESET
RESET
CAT150xx9
CAT150xx1
Figure 1. RESET Output Timing
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1125 Rev. A
CAT15008, CAT15016
Figure 2 shows the maximum pulse duration of
negative-going VCC transients that do not cause a reset
condition. As the amplitude of the transient goes further
below the threshold (increasing VTH - VCC), the
maximum pulse duration decreases. In this test, the
VCC starts from an initial voltage of 0.5V above the
threshold and drops below it by the amplitude of the
overdrive voltage (VTH - VCC).
EMBEDDED EEPROM DESCRIPTION
The CAT15008/16 devices support the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8-bit instruction register. The
instruction set and associated op-codes are listed in
Table 1.
Reading data stored in the CAT15008/16 is accom–
plished by simply providing the READ command and an
address. Writing to the CAT15008/16, in addition to a
WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits
in a Status Register, as will be explained later.
T
AMB
= 25ºC
¯¯
After a high to low transition on the CS input pin, the
CAT15008/16 will accept any one of the six instruction
op-codes listed in Table 1 and will ignore all other
possible 8-bit combinations. The communication
protocol follows the timing from Figure 3.
CAT150xxZ
CAT150xxM
Table 1: Instruction Set
Instruction
WREN
WRDI
Opcode
Operation
0000 0110 Enable Write Operations
0000 0100 Disable Write Operations
0000 0101 Read Status Register
0000 0001 Write Status Register
0000 0011 Read Data from Memory
0000 0010 Write Data to Memory
RESET OVERDRIVE V - V
[mV]
TH
CC
RDSR
Figure 2. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
WRSR
READ
WRITE
Figure 3. Synchronous Data Timing
t
CS
V
IH
CS
V
IL
t
t
CSH
CSS
V
V
IH
t
t
WL
SCK
SI
WH
t
IL
t
H
SU
V
IH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
V
OH
HI-Z
HI-Z
SO
V
OL
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. 1125 Rev. A
6
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT15008, CAT15016
STATUS REGISTER
The Status Register, as shown in Table 2, contains a
number of status and control bits.
user is allowed to protect a quarter, one half or the entire
memory, by setting these bits according to Table 3. The
protected blocks then become read-only.
¯¯¯¯
The RDY (Ready) bit indicates whether the device is
busy with a write operation. This bit is automatically
set to 1 during an internal write cycle, and reset to 0
when the device is ready to accept commands. For
the host, this bit is read only.
The WPEN (Write Protect Enable) bit acts as an enable
¯¯¯
for the WP pin. Hardware write protection is enabled
¯¯¯
when the WP pin is low and the WPEN bit is 1. This
condition prevents writing to the status register and to
the block protected sections of memory. While
hardware write protection is active, only the non-block
protected memory can be written. Hardware write
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is
in a Write Enable state and when set to 0, the device
is in a Write Disable state.
¯¯¯
protection is disabled when the WP pin is high or the
¯¯¯
WPEN bit is 0. The WPEN bit, WP pin and WEL bit
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the
user with the WRSR command and are non-volatile. The
combine to either permit or inhibit Write operations, as
detailed in Table 4.
Table 2. Status Register
7
6
0
5
0
4
0
3
2
1
0
WPEN
BP1
BP0
WEL
¯R¯D¯Y¯
Table 3. Block Protection Bits
Status Register Bits
Array Address Protected
Protection
BP1
BP0
0
0
None
No Protection
15008: 0300-03FF
15016: 0600-07FF
15008: 0200-03FF
15016: 0400-07FF
15008: 0000-03FF
15016: 0000-07FF
0
1
1
1
0
1
Quarter Array Protection
Half Array Protection
Full Array Protection
Table 4. Write Protect Enable Operation
¯¯¯
WP
WPEN
WEL
Protected Blocks
Protected
Unprotected Blocks
Status Register
Protected
Writable
0
0
1
1
X
X
X
0
1
0
1
0
1
Protected
Writable
Protected
Writable
Protected
Writable
X
Protected
Low
Low
High
High
Protected
Protected
Protected
Protected
Writable
Protected
Protected
Protected
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 1125 Rev. A
CAT15008, CAT15016
WRITE OPERATIONS
¯¯
The CAT15008/16 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the
memory array or to the status register. In addition, the
address of the memory location(s) to be written must be
outside the protected area, as defined by BP0 and BP1
bits from the status register.
take the CS input high after the WREN instruction, as
otherwise the Write Enable Latch will not be properly
set. WREN timing is illustrated in Figure 4. The WREN
instruction must be sent prior any WRITE or WRSR
instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 5. Disabling write
operations by resetting the WEL bit, will protect the
device against inadvertent writes.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT15008/16. Care must be taken to
Figure 4. WREN Timing
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 5. WRDI Timing
CS
SCK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. 1125 Rev. A
8
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT15008, CAT15016
Byte Write
Page Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16-bit
address and data as shown in Figure 6. Only 10
significant address bits are used by the CAT15008
and 11 by the CAT15016. The rest are don’t care bits,
as shown in Table 5. Internal programming will start
After sending the first data byte to the CAT15008/16,
the host may continue sending data, up to a total of 32
bytes, according to timing shown in Figure 7. After
each data byte, the lower order address bits are
automatically incremented, while the higher order
address bits (page address) remain unchanged. If
during this process the end of page is exceeded, then
loading will “roll over” to the first byte in the page, thus
possibly overwriting previoualy loaded data. Following
completion of the write cycle, the CAT15008/16 is
automatically returned to the write disable state.
¯¯
after the low to high CS transition. During an internal
write cycle, all commands, except for RDSR (Read
¯¯¯¯
Status Register) will be ignored. The RDY bit will
¯¯¯¯
indicate if the internal write cycle is in progress (RDY
high), or the the device is ready to accept commands
¯¯¯¯
(RDY low).
Table 5. Byte Address
Device
Address Significant Bits
A9 - A0
Address Don't Care Bits
A15 - A10
# Address Clock Pulse
CAT15008
CAT15016
16
16
A10 - A0
A15 - A11
Figure 6. Byte WRITE Timing
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
OPCODE
BYTE ADDRESS*
DATA IN
A
A
0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
N
HIGH IMPEDANCE
SO
* Please check the Byte Address Table (Table 5)
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 7. Page WRITE Timing
CS
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SCK
SI
DATA IN
Data Data
Byte 2 Byte 3
BYTE ADDRESS*
OPCODE
Data
Data Byte N
0
0
0
0
0
0
1
0
A
A
0
0
Byte 1
N
7..1
HIGH IMPEDANCE
SO
*Please check the Byte Address Table. (Table 5)
Note: Dashed Line = mode (1, 1) - - - - - -
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. 1125 Rev. A
CAT15008, CAT15016
Write Status Register
Write Protection
¯¯¯
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 8. Only
bits 2, 3 and 7 can be written using the WRSR
command.
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being
inadvertently altered. When WP is low and the WPEN
bit is set to “1”, write operations to the Status Register
¯¯¯
¯¯¯
¯¯
are inhibited. WP going low while CS is still low will
interrupt a write to the status register. If the internal
¯¯¯
write cycle has already been initiated, WP going low
will have no effect on any write operation to the Status
¯¯¯
Register. The WP pin function is blocked when the
¯¯¯
WPEN bit is set to “0”. The WP input timing is shown
in Figure 9.
Figure 8. WRSR Timing
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
7
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) - - - - - -
¯¯¯
Figure 9. WP Timing
t
t
WPH
WPS
CS
SCK
WP
WP
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. 1125 Rev. A
10
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT15008, CAT15016
READ OPERATIONS
Read Status Register
Read from Memory Array
To read the status register, the host simply sends a
RDSR command. After receiving the last bit of the
command, the CAT15008/16 will shift out the contents
of the status register on the SO pin (Figure 11). The
status register may be read at any time, including
during an internal write cycle.
To read from memory, the host sends a READ
instruction followed by a 16-bit address (see Table 5 for
the number of significant address bits).
After receiving the last address bit, the CAT15008/16
will respond by shifting out data on the SO pin (as
shown in Figure 10). Sequentially stored data can be
read out by simply continuing to run the clock. The
internal address pointer is automatically incremented
to the next higher address as data is shifted out. After
reaching the highest memory address, the address
counter “rolls over” to the lowest memory address, and
the read cycle can be continued indefinitely. The read
¯¯
operation is terminated by taking CS high.
Figure 10. READ Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
OPCODE
BYTE ADDRESS*
A
A
0
SI
0
0
0
0
0
0
1
1
N
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
* Please check the Byte Address Table (Table 5).
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 11. RDSR Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line = mode (1, 1) - - - - - -
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 1125 Rev. A
CAT15008, CAT15016
PACKAGE OUTLINES
8-LEAD 150 MIL SOIC (W)
E1
E
h x 45
D
C
A
q1
e
A1
L
b
SYMBOL
MIN
0.10
1.35
0.33
0.19
4.80
5.80
3.80
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
A1
A
b
C
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.50
1.27
8°
L
q1
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC specification MS-012 dimensions.
Doc. No. 1125 Rev. A
12
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT15008, CAT15016
PACKAGE MARKING
8-LEAD SOIC
150XXZWI
4YYWWA
○
CSI = Catalyst Semiconductor, Inc.
XX = Device Code (see Marking Code table below)
Z = Supervisory Output Code (see Marking Code table below)
I = Temperature Range
YY = Production Year
WW = Production Week
A = Product Revision
4 = Lead Finish NiPdAu
Device Marking Codes
XX
15008
15016
08
16
Supervisory Marking Codes
Z
output active low
output active high
9
1
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. 1125 Rev. A
CAT15008, CAT15016
ORDERING INFORMATION
Prefix
Device # Suffix
15008
CAT
9
S
W
I
-
G
T3
Lead Finish
G: NiPdAu
Company ID
Temperature Range
I = Industrial (-40ºC to 85ºC)
Tape & Reel
T: Tape & Reel
3: 3000 units / Reel
Product Type with
Memory Density
15008: 8-Kb EEPROM
15016: 16-Kb EEPROM
Package
W: SOIC
Reset Threshold Voltage
L: 4.50V – 4.75V
M: 4.25V – 4.50V
J: 3.89V – 4.10V
T: 3.00V – 3.15V
S: 2.85V – 3.00V
R: 2.55V – 2.70V
Z: 2.25V – 2.38V
Supervisor Output Type
9: CMOS Active Low
1: CMOS Active High
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu pre-plated (PPF) lead frames.
(3) The device used in the above example is a CAT150089SWI-GT3 (8Kb EEPROM, with Active Low CMOS Reset output, with a reset threshold
between 2.85V - 3.00V, SOIC package, Industrial Temperature, NiPdAu, Tape and Reel.
(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Doc. No. 1125 Rev. A
14
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
REVISION HISTORY
Date
Rev. Reason
Initial Issue
01/15/07
A
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Beyond Memory™, DPP™, EZDim™, MiniPot™, and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal
injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Document No: 1125
Revision:
A
Issue date:
01/15/07
相关型号：
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