PACS1284-04 [CALMIRCO]
P/ACTIVE IEEE 1284 ECP/EPP TERMINATION NETWORK; P / ACTIVE IEEE 1284 ECP / EPP终端网络
| 型号： | PACS1284-04 |
| 厂家： | 
CALIFORNIA MICRO DEVICES CORP |
| 描述： | P/ACTIVE IEEE 1284 ECP/EPP TERMINATION NETWORK |
| 文件： | 总7页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PACS1284
IEEE 1284 ECP/EPP Termination Network
Product Description
Features
•
•
Single chip IEEE 1284 parallel port termination
28-pin QSOP package, smallest physical
solution
17 terminating lines in a single package
In-system ESD protection to 8KV, HBM
In-system ESD protection to 4KV per
IEC 61000-4-2
Protects downstream devices to 30V
Lead-free version available
California Micro Devices’ PACS1284 Parallel Port Ter-
mination Network provides a complete integrated solu-
tion for the entire IEEE 1284 interface in a single
QSOP package.
•
•
•
To support the bi-directional transfer data rates of
enhanced high-speed parallel ports, the IEEE 1284
Standard recommends a combined termination/pull-up
filter network between the driver/receiver and the cable
at both ends of the parallel port interface. In addition,
government EMC compatibility requirements impose
strict filtering requirements on the parallel port. The
•
•
Applications
California Micro Devices PACS1284 addresses all
these requirements by providing a seventeen-line IEEE
1284-compliant network in a thin film integrated circuit.
The device provides a complete parallel port termina-
tion solution for space critical applications by integrat-
ing a total of 60 discrete components. In addition, all
the I/O pins are ESD protected for contact discharges
up to 4KV per the Human Body Model (HBM), with the
output pins having the highest probability of ESD pulse
exposure protected to 8KV (HBM), thereby providing
the necessary robustness for the port’s application
environment.
•
•
•
•
ECP/EPP Parallel Port termination
PC Peripherals
Notebook and Desktop computers
Engineering Workstations and Servers
The PACS1284 is manufactured in a 28-pin QSOP
package and is available with optional lead-free finish-
ing.
Electrical Schematic
R1 = 2.2kΩ
R2 = 33Ω
R1 = 4.7kΩ
R2 = 33Ω
PACS1284-02:
PACS1284-04:
18
R3 = 2.2kΩ
R3 = 4.7kΩ
C
= 220pF
C = 180pF
28
27
26
25
24
23
22 21
20
19
17
16
15
R1
C
R3
R1
C
R1
R1
R1
R1
R1
R1
C
R3
C
R1
R3
C
R1
C
R3
C
R1
C
R1
R3
R2
R2
R2
R2
R2
R2
R2
R2
R2
C
C
C
C
C
C
C
C
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
© 2004 California Micro Devices Corp. All rights reserved.
06/07/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
1
PACS1284
PACKAGE / PINOUT DIAGRAM
1
2
3
4
28
27
26
CAP-FILTERED; R3 PULL-UP
CAP-FILTERED; R1 PULL-UP
CAP-FILTERED; R1 PULL-UP
CAP-FILTERED; R1 PULL-UP
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
GND
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
25
24
23
22
21
20
19
18
17
16
15
5
6
7
8
CONNECTOR SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
9
V
CC
10
11
12
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
SUPERCHIP SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
13
14
28-pin QSOP
Note: This drawing is not to scale.
PIN DESCRIPTIONS
PINS
PIN NAME
DESCRIPTION
1, 2, 27
Cap-filtered;
R1 Pull-up
IEEE 1284 signals which require no series termination; pull-up is R1 value.
IEEE 1284 signals which require no series termination; pull-up is R3 value.
IEEE 1284 signals on the Super I/O Chip side which require series termination.
8, 10, 12,
15, 28
Cap-filtered;
R3 Pull-up
3-7,
9,11,
13,14
SuperChip Side
Series-terminated
16-19,
21,
Connector Side
Series-terminated
IEEE 1284 signals on the Parallel Port Connector side which require series termination.
23-26
20
22
V
Supply rail for the device
CC
GND
Ground reference for the device
Ordering Information
STANDARD VALUES
Product
R1 (Ω)
2.2k
R2 (Ω)
33
R3 (Ω)
2.2k
C (pF)
220
PACS1284-02
PACS1284-04
4.7k
33
4.7k
180
PART NUMBERING INFORMATION
Standard FInish
Lead-free Finish
Ordering Part
Ordering Part
1
1
Pins
28
Package
QSOP
Number
Part Marking
PACS128402Q
PACS128404Q
Number
Part Marking
PACS128402QR
PACS128404QR
PACS1284-02Q
PACS1284-04Q
PACS1284-02QR
PACS1284-04QR
28
QSOP
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
© 2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
06/07/04
PACS1284
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNITS
V
Voltage
6.0
V
CC
Input Voltage Range, no clamping
Storage Temperature Range
Power Dissipation per Resistor
Package Power Dissipation
-6.0 to 6.0
-65 to +150
100
V
°C
mW
W
1.00
STANDARD OPERATING CONDITIONS
PARAMETER
RATING
UNITS
V
Voltage
5.0
V
CC
Operating Temperature
0 to +70
°C
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL PARAMETER
CONDITIONS
Measured at T =25°C
MIN
TYP
MAX UNITS
TOL
Absolute Resistance Tolerance
(R1, R2, R3)
10
%
R
A
TOL
I
Absolute Capacitance Tolerance
Leakage current to GND
Measured at 1MHz, 2.5VDC, T =25°C
20
1
%
µA
kV
C
A
Measured at 5.0VDC, T =25°C
LEAK
A
V
Peak Discharge Voltage at any I/O Per MIL-STD-883, Method 3015
4
8
4
ESD
ESD
ESD
(HBM); C
=100pF;
Discharge
R
=1.5KΩ; Notes 2,3
Discharge
V
V
In-System ESD Protection
In-System ESD Protection
Per MIL-STD-883, Method 3015
kV
(HBM); C
=100pF;
Discharge
R
=1.5KΩ; Notes 2,3
Discharge
Per IEC 61000-4-2 Level 2;
=150pF; R
kV
V
C
=330Ω;
Discharge
Discharge
Notes 2,3
V
Clamping voltage under ESD
discharge
ESD applied to connector pin, mea-
sured at corresponding input pin; +8kV
discharge, Human Body Model
Note 2
30
CL
Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified.
Note 2: Guaranteed by design.
Note 3: ESD contact discharge between pin 22 (GND) and pins 1, 2, 8, 10, 12, 15, 16, 17, 18, 19, 21, 23, 24, 25, 26, 27, & 28 (one
at a time, all other I/O pins open), pin 20=5V; pin 22=GND
© 2004 California Micro Devices Corp. All rights reserved.
06/07/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
3
PACS1284
Performance Information
Filter Capacitors
The three plotted lines in Figure 1 depict the following
measurements:
Figure 1 shows typical insertion loss graphs for the
PACS1284, for Data and Strobe signals. The curves
are dependent on the physical location of the filter ele-
ments with respect to the ground and V
the device.
•
•
•
Line labeled "A" is measured between pin 14
(input) and pin 16 (output).
Line labeled "B" is measured between pin 3 (input)
and pin 26 (output).
Line labeled "C" is measured between pin 6 (input)
and pin 23 (output).
terminals of
CC
These graphs are measured in a 50 Ohm environment.
The signal is introduced at the series resistor input and
the output is measured at the corresponding filter
capacitor.
The "A" graph depicts “worst case” filter performance,
while "C" represents a “best case” situation. Graphs of
all other filter elements will fall between these two. (The
filter insertion loss was measured using a Hewlett
Packard HP8753C Analyzer.)
0
in dB
S
21
-10
-20
-30
-40
-50
A
B
C
300
450
600
750
900
1050 1200
(FREQUENCY, MHz)
Figure 1. Typical Filter Insertion Loss for PACS1284 (S in dB, T =25°C)
21
A
© 2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
06/07/04
PACS1284
Application Information
Termination Considerations
Interfacing to IEEE 1284 Connectors
IEEE 1284 defines three interface connectors:
The IEEE 1284 specification requires both termination
and EMI filtering on a total of 17 signal lines. Control
and Status lines (8 in total) only require a pull-up resis-
tor and a filter capacitor. The Data lines and Strobe
also require a series termination resistor in addition to
the pull-up resistors and filter capacitors. See Table 1,
in conjunction with the schematic diagram on page 1.
•
•
•
1284 A is a 25-pin DB series connector which is
the de facto PC standard for the host connection.
1284 B is a 36-pin, 0.085 inch centerline connector
used on the peripheral device.
1284 C is a new 36-pin, 0.050 inch centerline con-
nector which can be used for both host and periph-
eral.
Table 1: IEEE 1284 Termination Requirements
Figure 2A shows a possible hook-up between the
1284-A connector on a PC motherboard and the
PACS1284, illustrating how the pin configuration of the
PACS1284 allows for easy interconnect between the
two. The dotted I/O signals of the PACS1284 will
typically be connected to a Super I/O chip on the
motherboard.
SIGNAL TERMINATION REQUIREMENTS
Signal Name
Data1 - Data8
Strobe
Series Termination
Yes
Yes
Init
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Figure 2B shows a possible hook-up between the
1284-B connector on a peripheral and the PACS1284.
AutoFeedXT
Selectin
ACK
Figure 2C shows a possible hook-up between the
1284-C connector and the PACS1284.
Busy
Paper Empty
Select
Fault
Figure 2A:
Figure 2B:
Figure 2C:
1284-A Connector
1284-B Connector
1284-C Connector
Host/Peripheral
Host
Peripheral
14
25
36
19
36
18
20
2
19
18
1
13
1
1
12
PACS 84
PACS1284
1
PACS1284
1
1
= GND
=V
CC
Figure 2. Example Connections of IEEE 1284 Connectors with PACS1284
© 2004 California Micro Devices Corp. All rights reserved.
06/07/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
5
PACS1284
Application Information (continued)
Table 2 provides the IEEE 1284 signal assignments for
the three connectors, and example PACS1284 pin con-
nections.
Similarly, when a 1284-A host is connected to a 1284-
C peripheral, the “Peripheral Logic High” and “Host
Logic High” are not used. These two signals are
optionally used to detect a “Power Off” or “Cable Dis-
connect” state for host and peripheral, respectively.
When connecting a 1284-A host to a 1284-B periph-
eral, the “Peripheral Logic High” signal is not used.
Table 2: IEEE 1284 Connector Pinouts and PACS1284 Connection Guidelines
1284-C
36-PIN HIGH
DENSITY
PACS1284
PIN TYPE
1284-A
1284-B
25-PIN DSUB 36-PIN CHAMP
SIGNAL
STROBE
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
ACK
PIN
1
SIGNAL
STROBE
Data 1
PIN
1
SIGNAL
STROBE
Data 1
PIN
15
6
P-Port conn. side, series-terminated (16-19, 21, or 23-26)
P-Port conn. side, series-terminated (16-19, 21, or 23-26)
P-Port conn. side, series-terminated (16-19, 21, or 23-26)
P-Port conn. side, series-terminated (16-19, 21, or 23-26)
P-Port conn. side, series-terminated (16-19, 21, or 23-26)
P-Port conn. side, series-terminated (16-19, 21, or 23-26)
P-Port conn. side, series-terminated (16-19, 21, or 23-26)
P-Port conn. side, series-terminated (16-19, 21, or 23-26)
P-Port conn. side, series-terminated (16-19, 21, or 23-26)
Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28)
2
2
3
Data 2
3
Data 2
7
4
Data 3
4
Data 3
8
5
Data 4
5
Data 4
9
6
Data 5
6
Data 5
10
11
12
13
3
7
Data 6
7
Data 6
8
Data 7
8
Data 7
9
Data 8
9
Data 8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ACK
10
11
12
13
14
32
31
36
19
20
21
22
23
24
25
26
27
28
29
30
33
34
35
15
16
17
18
ACK
Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28)
BUSY
BUSY
BUSY
1
Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28)
PError
Select
PError
PError
5
Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28)
Select
Select
2
Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28)
AUTOFD
FAULT
INIT
AUTOFD
FAULT
AUTOFD
FAULT
17
4
Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28)
Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28)
INIT
INIT
14
16
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
18
Capacitor-filtered (1, 2, 8, 10, 12, 15, 27, or 28)
Selectin
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Selectin
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Not Defined
Not Defined
Not Defined
Not Defined
Logic Ground
Chassis GND
Peripheral Logic
Selectin
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Not Required
Host Logic High
© 2004 California Micro Devices Corp. All rights reserved.
6
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
06/07/04
PACS1284
Mechanical Details
QSOP Mechanical Specifications:
Mechanical Package Diagrams
PACS1284 devices are packaged in 28-pin QSOP
packages. Dimensions are presented below.
For complete information on the QSOP-28 package,
see the California Micro Devices QSOP Package Infor-
mation document.
TOP VIEW
D
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PACKAGE DIMENSIONS
Package
Pins
QSOP (JEDEC name is SSOP)
28
E
H
Pin 1 Marking
Millimeters
Inches
Dimensions
Min
Max
1.75
0.25
0.30
0.25
9.98
3.98
Min
Max
13 14
1
2
3
4
5
6
7
8
9
10 11 12
A
1.35
0.10
0.20
0.18
9.80
3.81
0.053
0.004
0.008
0.007
0.386
0.150
0.069
0.010
0.012
0.010
0.393
0.157
A1
SIDE VIEW
B
A
C
A1
SEATING
PLANE
D
B
e
E
e
0.64 BSC
0.025 BSC
END VIEW
H
L
5.79
0.40
6.20
1.27
0.228
0.016
0.244
0.050
C
# per tube
50 pieces*
2500 pieces
# per tape
and reel
L
Controlling Dimensions: inches
* This is an approximate amount which may vary.
Package Dimensions for QSOP-28
© 2004 California Micro Devices Corp. All rights reserved.
06/07/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
7
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