CM1209-06MR [CALMIRCO]

4,6 & 8 Channel ESD Protection Arrays with Zener Supply Clamp; 4,6和8通道ESD保护阵列与齐纳钳位供应
CM1209-06MR
型号: CM1209-06MR
厂家: CALIFORNIA MICRO DEVICES CORP    CALIFORNIA MICRO DEVICES CORP
描述:

4,6 & 8 Channel ESD Protection Arrays with Zener Supply Clamp
4,6和8通道ESD保护阵列与齐纳钳位供应

瞬态抑制器 二极管 光电二极管 局域网
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CM1209  
4,6 & 8 Channel ESD Protection Arrays  
with Zener Supply Clamp  
Features  
Product Description  
Four, six or eight channels of ESD protection for  
high data rate signals  
The CM1209 family of diode arrays are designed to  
provide either 4, 6 or 8 channels of ESD protection for  
electronic components or sub-systems. Each channel  
consists of a pair of diodes which steer the ESD cur-  
Zener diode protects supply rail and eliminates the  
need for external by-pass capacitors  
+15 kV contact, +15 kV air ESD protection per  
channel (IEC 61000-4-2 standard)  
Low loading capacitance of 6pF typical  
Low supply current  
rent pulse either to the positive (V ) or negative (V )  
P
N
supply. In addition, there is an integral Zener diode  
between V and V to suppress any voltage distur-  
P
N
bance due to these ESD current pulses. The CM1209  
devices will protect against ESD pulses up to 15kV  
contact discharge per the International Standard  
IEC61000-4-2.  
Available in miniature MSOP and SOIC packages  
Lead-free versions available  
Applications  
These devices are particularly well-suited for portable  
electronics (e.g. cellular phones, PDAs, notebook com-  
puters) because of its small package footprint, high  
ESD protection level, and low loading capacitance.  
They are also suitable for protecting video output lines  
and I/O ports in computers, set top boxes, digital TVs  
and peripheral equipment.  
ESD protection for a variety of electronic equip-  
ment  
Set Top Boxes  
Digital TVs  
I/O & VGA Port protection  
Desktop and Notebook computers  
PDAs  
Cellular Phones  
The CM1209 family of devices is optionally available  
with lead-free finishing.  
Electrical Schematics  
8
7
6
5
8
7
5
10  
9
7
6
V
V
V
P
P
P
V
V
V
N
N
N
1
2
3
4
1
2
3
4
1
2
3
4
5
CM1209-04  
4-Channel  
CM1209-06  
6-Channel  
CM1209-08  
8-Channel  
© 2004 California Micro Devices Corp. All rights reserved.  
01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112  
L
Tel: 408.263.3214  
L
Fax: 408.263.7846  
L
www.calmicro.com  
1
CM1209  
PACKAGE / PINOUT DIAGRAMS  
TOP VIEW  
TOP VIEW  
TOP VIEW  
1
2
3
4
5
10  
9
CH 1  
CH 2  
CH 3  
CH 8  
CH 7  
VP  
CH 1  
CH 2  
VN  
1
2
3
4
8
7
6
5
CH 1  
CH 2  
VN  
1
2
3
4
8
7
6
5
CH 6  
VP  
CH 4  
CH 3  
VP  
8
CH 5  
CH 4  
7
CH 6  
CH 4  
VN  
CH 3  
VN  
VN  
6
CH 5  
8-pin MSOP  
CM1209-04MS/MR  
8-pin SOIC/MSOP  
CM1209-06SN/SM  
CM1209-06MS/MR  
10-pin MSOP  
CM1209-08MS/MR  
Note: These drawings are not to scale.  
PIN DESCRIPTIONS  
CM1209-04  
CM1209-06  
CM1209-08  
NAME  
CH 1  
CH 2  
CH 3  
CH 4  
CH 5  
CH 6  
CH 7  
CH 8  
PIN NO.  
PIN NO  
PIN NO  
TYPE  
I/O  
DESCRIPTION  
ESD Channel 1  
ESD Channel 2  
ESD Channel 3  
ESD Channel 4  
ESD Channel 5  
ESD Channel 6  
ESD Channel 7  
ESD Channel 8  
1
2
7
8
1
2
4
5
6
8
1
2
I/O  
3
I/O  
4
I/O  
6
I/O  
7
I/O  
9
I/O  
10  
5
I/O  
V
3,4,5  
6
3
7
GND  
Negative voltage supply rail or ground reference  
rail.  
N
V
8
Supply Positive voltage supply rail.  
P
© 2004 California Micro Devices Corp. All rights reserved.  
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112  
L
Tel: 408.263.3214  
L
Fax: 408.263.7846  
L
www.calmicro.com  
01/09/04  
CM1209  
Ordering Information  
PART NUMBERING INFORMATION  
Standard Finish  
Lead-free Finish  
Ordering Part  
Ordering Part  
1
1
# of Channels  
Pins  
8
Package  
MSOP-8  
SOIC-8  
Number  
Part Marking  
0904  
Number  
CM1209-04MR  
Part Marking  
4
6
6
8
CM1209-04MS  
CM1209-06SN  
CM1209-06MS  
CM1209-08MS  
0914  
8
CM1209-06S  
0906  
CM1209-06SM CM1209-06SM  
8
MSOP-8  
MSOP-10  
CM1209-06MR  
CM1209-08MR  
0916  
0918  
10  
0908  
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.  
Specifications  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
RATING  
UNITS  
Supply Voltage (V - V )  
6.0  
V
P
N
Diode Forward DC Current (Note 1)  
Operating Temperature Range  
Storage Temperature Range  
20  
mA  
°C  
°C  
V
-40 to +85  
-65 to +150  
DC Voltage at any channel input  
(V - 0.5) to (V + 0.5)  
N P  
Package Power Rating  
SOIC Package  
350  
200  
mW  
mW  
MSOP Package  
Note 1: Only one diode conducting at a time.  
STANDARD OPERATING CONDITIONS  
PARAMETER  
RATING  
-40 to +85  
0 to 5.5  
UNITS  
°C  
Operating Temperature Range  
Operating Supply Voltage (V - V )  
V
P
N
© 2004 California Micro Devices Corp. All rights reserved.  
01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214  
L
Fax: 408.263.7846  
L
www.calmicro.com  
3
CM1209  
Specifications (cont’d)  
ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1)  
SYMBOL PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
I
Supply Current  
(V -V )=5.5V; T =25°C  
10  
µA  
P
P
N
A
V
ESD Diode Forward Voltage  
I = 20mA; T =25°C  
0.65  
0.95  
V
V
F
F
A
V
Zener Clamp Reverse Breakdown  
Voltage  
At 1mA; T =25°C  
7
ZBD  
A
I
Channel Leakage Current  
Channel Input Capacitance  
T =25°C  
+0.1  
6
+1.0  
8
µA  
LEAK  
A
C
At 1 MHz, V =5V, via 10K;  
pF  
IN  
P
V =0V, V =2.5V;  
N
IN  
Notes 2 and 6  
V
ESD Protection  
ESD  
Peak Discharge Voltage at any  
channel input and V rail  
P
Notes 2, 3, 5, and 6  
Notes 2, 3, 5, and 6  
+15  
+15  
kV  
kV  
Contact discharge per  
IEC 61000-4-2 standard  
Air discharge per  
IEC 61000-4-2 standard  
V
Channel Clamp Voltage  
At 8kV ESD HBM;  
CL  
T =25°C; Notes 2, 4 and 6  
A
Positive Transients  
Negative Transients  
+12.5  
- 5.1  
V
V
Z
Dynamic Resistance of Channel Input I = 1A; T =25°C; See  
0.70  
POS  
A
for Positive Transients  
Figure 2; Note 6 applies  
Z
Dynamic Resistance of Channel Input I = 1A; T =25°C; See  
0.45  
NEG  
A
for Negative Transients  
Figure 2; Note 6 applies  
Note 1: All parameters specified at TA=-40 to +85°C unless otherwise noted.  
Note 2: These parameters guaranteed by design and characterization.  
Note 3: From I/O pins to VP or VN only.  
Note 4: Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5K, VP = 5.0V, VN grounded.  
Note 5: Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330, VP = 5.0V, VN grounded.  
Note 6: These measurements performed with no external capacitor on VP..  
© 2004 California Micro Devices Corp. All rights reserved.  
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112  
L
Tel: 408.263.3214  
L
Fax: 408.263.7846  
L
www.calmicro.com  
01/09/04  
CM1209  
Performance Information  
10  
8
Slope = I/ZPOS  
6
VZBD  
4
Slope = I/ZNEG  
2
0
0
1
2
3
4
5
Voltage [V]  
Vin  
Figure 2. IV Curve for CM1209  
Figure 1. Typical Variation of Channel Input  
Capacitance (CIN) vs. Channel Input Voltage (VIN)  
(V = 5V via 10K resistor, V = 0V)  
P
N
Application Information  
3
7
0.22µF*  
CM1209-06  
1 2 4 5 6 8  
Expansion  
Connector  
I/O Port  
Buffers  
Typical ESD Protection  
* Optional capacitor should be placed as close as  
possible to the V pin on all CM1209 devices.  
P
Refer to ’Design Considerations’ text.  
Figure 3. Application Example Using the CM1209-06 for I/O Port Protection  
© 2004 California Micro Devices Corp. All rights reserved.  
01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214  
L
Fax: 408.263.7846  
L
www.calmicro.com  
5
CM1209  
Application Information  
Design Considerations  
In order to realize the maximum protection against  
ESD pulses, care must be taken in the PCB layout to  
minimize parasitic series inductances on the Supply/  
Ground rails as well as the signal trace segment  
between the signal input (typically a connector) and the  
ESD protection device. Refer to Figure 4, which illus-  
trates an example of a positive ESD pulse striking an  
input channel. The parasitic series inductance back to  
The CM1209 has an integrated Zener diode between  
V and V . This greatly reduces the effect of supply rail  
P
N
inductance L on V by clamping V at the breakdown  
2
CL  
P
voltage of the Zener diode. However, for the lowest  
possible V , especially when V is biased at a voltage  
CL  
P
significantly below the Zener breakdown voltage, it is  
recommended that a 0.22µF ceramic chip capacitor be  
connected between V and the ground plane.  
P
the power supply is represented by L and L . The volt-  
1
2
As a general rule, the ESD Protection Array should be  
located as close as possible to the point of entry of  
expected electrostatic discharges. The power supply  
bypass capacitor mentioned above should be as close  
age V on the line being protected is:  
CL  
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt  
+ L2 x d(IESD ) / dt  
to the V pin of the Protection Array as possible, with  
P
where I  
the positive supply voltage.  
is the ESD current pulse, and V  
is  
SUPPLY  
ESD  
minimum PCB trace lengths to the power supply,  
ground planes and between the signal input and the  
ESD device to minimize stray series inductance.  
An ESD current pulse can rise from zero to its peak  
value in a very short time. As an example, a level 4  
contact discharge per the IEC61000-4-2 standard  
results in a current pulse that rises from zero to 30  
Additional Information  
See California Micro Devices Application Note AP209,  
“Design Considerations for ESD Protection", under  
Applications at www.calmicro.com.  
Amps in 1ns. Here d(I  
)/dt can be approximated by  
ESD  
-9  
I  
/t, or 30/(1x10 ). So just 10nH of series induc-  
ESD  
tance (L and L combined) will lead to a 300V incre-  
1
2
ment in V  
!
CL  
Similarly for negative ESD pulses, parasitic series  
inductance from the V pin to the ground rail will lead  
N
to drastically increased negative voltage on the line  
being protected.  
L2  
POSITIVE SUPPLY RAIL  
VP  
PATH OF ESD CURRENT PULSE I  
ESD  
L1  
LINE BEING  
PROTECTED  
D1  
SYSTEM OR  
CIRCUITRY  
BEING  
0.22µF  
ONE  
CHANNEL  
OF  
CM1209  
CHANNEL  
INPUT  
20A  
PROTECTED  
D2  
VCL  
0A  
GROUND RAIL  
VN  
CHASSIS GROUND  
Figure 4. Application of Positive ESD Pulse between Input Channel and Ground  
© 2004 California Micro Devices Corp. All rights reserved.  
6
430 N. McCarthy Blvd., Milpitas, CA 95035-5112  
L
Tel: 408.263.3214  
L
Fax: 408.263.7846  
L
www.calmicro.com  
01/09/04  
CM1209  
Mechanical Details  
CM1209 devices are packaged in 8-pin and 10-pin  
MSOP and 8-pin SOIC packages. Dimensions for  
these packages are presented on the following pages.  
For complete information on the MSOP-8/-10 or SOIC-  
8 packages, see the specific California Micro Devices  
Package Information document.  
MSOP-8 Mechanical Specifications  
Mechanical Package Diagrams  
PACKAGE DIMENSIONS  
TOP VIEW  
Package  
Pins  
MSOP  
8
D
Millimeters  
Inches  
8
7
6
5
Dimensions  
Min  
Max  
1.17  
0.25  
Min  
Max  
0.046  
0.010  
A
0.87  
0.05  
0.034  
0.002  
A1  
B
0.30 (typ)  
0.18  
0.012 (typ)  
0.007  
E
H
Pin 1  
Marking  
C
D
2.90  
2.90  
3.10  
3.10  
0.114  
0.114  
0.122  
0.122  
E
e
0.65 BSC  
0.025 BSC  
1
2
3
4
H
L
4.78  
0.52  
4.98  
0.54  
0.188  
0.017  
0.196  
0.025  
SIDE VIEW  
# per tube  
80 pieces*  
4000 pieces  
# per tape  
and reel  
A
SEATING  
PLANE  
A1  
Controlling dimension: inches  
B
e
* This is an approximate number which may vary.  
END VIEW  
C
L
Package Dimensions for MSOP-8  
© 2004 California Micro Devices Corp. All rights reserved.  
01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214  
L
Fax: 408.263.7846  
L
www.calmicro.com  
7
CM1209  
Mechanical Details (cont’d)  
MSOP-10 Mechanical Specifications  
Mechanical Package Diagrams  
PACKAGE DIMENSIONS  
TOP VIEW  
Package  
Pins  
MSOP  
10  
D
8
Millimeters  
Inches  
10  
9
7
6
Dimensions  
Min  
Max  
0.95  
0.15  
0.40  
Min  
Max  
0.038  
0.006  
0.016  
A
0.75  
0.05  
0.18  
0.028  
0.002  
0.006  
A1  
B
E
H
Pin 1  
Marking  
C
0.18  
0.007  
D
2.90  
2.90  
3.10  
3.10  
0.114  
0.114  
0.122  
0.122  
E
e
0.50 BSC  
0.0196 BSC  
1
2
3
4
5
H
L
4.76  
0.40  
5.00  
0.70  
0.187  
0.0137  
0.197  
0.029  
SIDE VIEW  
# per tube  
80 pieces*  
4000  
# per tape  
and reel  
A
SEATING  
PLANE  
A1  
Controlling dimension: inches  
B
e
* This is an approximate number which may vary.  
END VIEW  
C
L
Package Dimensions for MSOP-10  
© 2004 California Micro Devices Corp. All rights reserved.  
8
430 N. McCarthy Blvd., Milpitas, CA 95035-5112  
L
Tel: 408.263.3214  
L
Fax: 408.263.7846  
L
www.calmicro.com  
01/09/04  
CM1209  
Mechanical Details (cont’d)  
SOIC-8 Mechanical Specifications  
Mechanical Package Diagrams  
PACKAGE DIMENSIONS  
Package  
Pins  
SOIC  
8
TOP VIEW  
D
Millimeters  
Inches  
8
7
6
5
Dimensions  
Min  
Max  
1.75  
0.25  
0.51  
0.25  
5.00  
4.19  
Min  
Max  
A
1.35  
0.10  
0.33  
0.19  
4.80  
3.80  
0.053  
0.004  
0.013  
0.007  
0.189  
0.150  
0.069  
0.010  
0.020  
0.010  
0.197  
0.165  
A1  
B
E
H
Pin 1  
Marking  
C
D
E
e
1.27 BSC  
0.050 BSC  
1
2
3
4
H
L
5.80  
0.40  
6.20  
1.27  
0.228  
0.016  
0.244  
0.050  
SIDE VIEW  
# per tube  
100 pcs*  
2500 pcs  
# per tape  
and reel  
A
SEATING  
PLANE  
A1  
Controlling dimension: inches  
B
e
* This is an approximate number which may vary.  
END VIEW  
C
L
Package Dimensions for SOIC-8  
© 2004 California Micro Devices Corp. All rights reserved.  
01/09/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214  
L
Fax: 408.263.7846  
L
www.calmicro.com  
9

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