TMC1103 [CADEKA]
Triple Video A/D Converter with Clamps 8-Bit, 50Msps; 三路视频A / D转换器，线夹8位， 50MSPS
| 型号： | TMC1103 |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Triple Video A/D Converter with Clamps 8-Bit, 50Msps |
| 文件： | 总16页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.cadeka.com
TMC1 1 0 3
Trip le Vid e o A/D Co n ve rt e r w it h Cla m p s
8 -Bit , 5 0 Ms p s
Features
Applications
• 8-bit resolution
• 50 Msps conversion rate
• Low power: 100mW per channel @ 20 Msps
• Integral track/hold
• Video digitizing (composite and Y-C)
• VGA and CCD digitizing
• LCD projection panels
• Image scanners
• Independent Input Clamps
• Independent clock inputs
• Integral and differential linearity error 0.5 LSB
• Differential phase 0.7 degree
• Differential gain 1.8%
• Personal computer video boards
• Multimedia systems
• Low cost, high speed data conversion
• Single +5V power supply
• Three-state TTL/CMOS-compatible outputs
• Low cost
Description
Incorporated into the TMC1103 are three analog-to-digital
(A/D) converters, each with an independent clock, reference
voltage and input clamp. Analog signals are converted to
Triple 8-bit digital words at sample rates up to 50 Msps
(Megasamples per second) per channel.
submicron CMOS technology reduce typical power dissipa-
tion to 100 mW per converter.
Power is derived from a single +5 Volt power supply. Out-
puts are three-state outputs and TTL/CMOS-compatible.
TMC1103 package is a 80-lead Metric Quad Flat Pack
(MQFP). Performance specifications are guaranteed from
0°C to 70°C.
Integral Track/Hold circuits deliver excellent performance
on signals with full-scale spectral components up to
12 MHz. Innovative two-step conversion architecture and
Block Diagram
R
TA
BA
R
8-bit
A/D Converter
V
INA
Clamp
Clamp
Clamp
DA
OE
7-0
A
V
CLPA
CLP
A
CLK
A
R
TB
BB
R
8-bit
A/D Converter
V
INB
DA
7-0
B
OE
V
CLPB
CLP
B
CLK
B
R
TC
BC
R
8-bit
A/D Converter
V
INC
DA
7-0
C
OE
V
CLPC
CLP
C
CLK
C
65-1103-01
Rev. 1.2.0
TMC1103
PRODUCT SPECIFICATION
A/D Converter
0.1µF
Circuit Function
Analog
Input
V
INX
Within the TMC1103 are three 8-bit A/D converters, each
employing two-step architecture to convert an analog input
to a digital output at rates up to 50 Msps. Input signals are
held in integral track/hold stages during the conversion pro-
cess. Operation is pipelined, with one input sample taken and
V
CLPX
65-1103-02
CLP
X
one output word provided for each CLK cycle.
X
Input Clamp Circuit
Each of the three converters function identically. In the fol-
lowing descriptions ‘X’ refers to a generic input/output or
clock where ‘X’ is equivalent to A, B or C.
Digital Inputs and Outputs
Sampling of the applied input signal occurs on the falling
edge of the CLK signal (Figure 1). Output data is delayed
X
The first step in the conversion process is a coarse 4-bit
quantization. This determines the range of the subsequent
fine 4-bit quantization step. To eliminate spurious codes, the
fine 4-bit A/D quantizer output is gray-coded and converted
to binary before it is combined with the coarse result to form
a complete 8-bit result.
by 2 1/2 CLK cycles and is valid following the rising edge
X
of CLK . Previous output data remains valid for t
(Out-
put Hold Time). New data becomes valid t (Output Delay
X
HO
D
Time) after this rising edge of CLK .
X
Whenever the analog input signal is sampled and found to be
at a level beyond the A/D conversion range, the output limits
at 00h or FFh, as appropriate.
Analog Input and Voltage References
Each A/D accepts analog signals in the range RBX to RTX into
digital data. Input signals outside this range produce “satu-
rated” 00h or FFh output codes. The device will not
Table 1. A/D Output Coding
Input Voltage
+ 1 LSB
Output
FF
be damaged by signals within the range A
to V .
GND
DDA
R
TX
Input range is very flexible and extends from the +5 Volt
power supply to ground. Nominal input range is 2 Volts,
extending from 0.6V to 2.6V. Characterization and
performance is specified over this range. However, the
part will function with a full-scale range from 1.0V to 5.0V.
A smaller input range may simplify analog signal condition-
ing circuitry, at the expense of additional noise sensitivity
and some reduced differential linearity performance.
R
TX
FF
R
TX
- 1 LSB
• • •
FE
• • •
80
R
R
+ 128 LSB
+ 127 LSB
• • •
BX
7F
BX
• • •
01
External voltage reference sources are connected to the R
TX
R
BX
+ 1 LSB
and R pins. R can be grounded. Within each A/D con-
BX BX
R
BX
00
verter is a reference resistor ladder comprising 255 resistors
that are accessed by the TMC1103 comparators. R is con-
TX
R
BX
- 1 LSB
00
nected to the top of the ladder, R to the bottom. Gain and
BX
offset errors are directly related to the accuracy and stability
of the applied reference voltages.
Note: 1 LSB = (R – R ) / 255
TX BX
The outputs of the TMC1103 are CMOS- and
TTL-compatible, and are capable of driving four low-power
Input Clamps
Schottky TTL loads. An Output Enable control, OE , places
X
A clamp circuit is connected to the input pin V of each of
the three A/D converters. With CLP LOW, the input pin is
clamped to the voltage at V
INX
the A/D outputs in a high-impedance state when HIGH.
X
The outputs are enabled when OE is LOW.
X
. If CLP is HIGH, the
CLPX
X
input pin is high impedance. Clamping adds an offset voltage
to an AC coupled signal to adjust this signal’s amplitude to
the A/D converter input voltage range.
Power and Ground
The TMC1103 operates from a single +5 Volt power supply.
For optimum performance, an analog ground plane should
be placed under the TMC1103 the A pins
should be connected to the system analog ground plane.
The analog input is corrected through a 0.1mF capacitor to
and D
GND
GND
V
. The source impedance of the analog source should be
INX
less than 50 Ohms. Current pulses through the capacitor over
several clamp cycles until the voltage across the capacitor
equals the difference between V
and the voltage at the
CLPX
analog source during the clamping period. When the switch
is open, the voltage on the coupling capacitor is added to the
analog input, producing a a DC offset input signal.
2
PRODUCT SPECIFICATION
TMC1103
Pin Assignments
64
41
Pin
1
Name
Pin
Name
Pin
Name
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
NC
21 DGND
22 DGND
23 NC
41 DC
42 OE
V
DD
7
65
40
2
DA
DA
DA
OE
5
6
7
C
B
7
6
5
4
3
2
1
0
3
43
44
V
DD
V
DD
DB
DB
DB
DB
DB
DB
DB
DB
4
24 NC
5
OE
25 DGND
26 DGND
45 CLK
46 NC
A
DD
DD
C
6
V
V
7
27
V
47
48
V
DDA
V
INC
DD
8
NC
28 CLP
29 CLP
30 CLP
31 NC
A
B
C
9
CLK
49 AGND
A
10 NC
50
51
52
53
R
TC
R
BC
R
BB
R
TB
11
12
V
DGND
DGND
NC
80
DDA
INA
25
V
32 DGND
33 DGND
13 AGND
1
24
14
15
16
17
18
R
R
34 DC
35 DC
36 DC
37 DC
38 DC
39 DC
40 DC
54 AGND
DGND
DGND
TA
0
1
2
3
4
5
6
65-1103-03
55
56
V
V
BA
INB
V
CLPA
V
CLPB
V
CLPC
DA
DA
DA
DA
DA
DDA
0
1
2
3
4
57 NC
58 CLK
59 NC
B
19 DGND
20 DGND
60
V
DD
3
PRODUCT SPECIFICATION
TMC1103
Pin Descriptions
Pin Name
Pin Number
Value
Pin Function Description
A/D Converters
V
V
, V
INC
,
12, 55, 48
14, 53, 50
15, 52, 51
9, 58, 45
R
R
to Analog Inputs. The input voltage conversion range lies between the
INA INB
TX
voltage applied to the R and R pins.
TX BX
BX
R
, R , R
TA TB TC
2.6V
Reference Voltage, Top Inputs. DC voltages applied to R , R
TA TB
and R define highest value of V
.
TC INX
R
, R , R
BA BB BC
0.6V
Reference Voltage, Bottom Inputs. DC voltages applied to R
,
BA
R
BB
and R
BC
define lowest value of V .
INX
CLK , CLK ,
CLK
CMOS Clock Inputs. CMOS-compatible. V is sampled on the falling
INX
A
C
B
edge of CLK .
X
DA
DB
DC
4, 3, 2, 80, 79, CMOS/ Data outputs, Converter A (D = MSB). Eight-bit CMOS- and
7
7-0
7-0
7-0
78, 77, 76
TTL
TTL-compatible digital outputs. Valid data is output on the rising
edge of CLK .
X
63, 64, 65, 66, CMOS/ Data outputs, Converter B (D = MSB). Eight-bit CMOS- and
7
67, 68, 69, 70
TTL
TTL-compatible digital outputs. Valid data is output on the rising
edge of CLK .
X
41, 40, 39, 38, CMOS/ Data outputs, Converter C (D = MSB). Eight-bit CMOS- and
7
37, 36, 35, 34
TTL
TTL-compatible digital outputs. Valid data is output on the rising
edge of CLK .
X
OE , OE , OE
5, 62, 42
CMOS Output Enable Inputs. CMOS-compatible. When LOW, the A/D
output is enabled. When HIGH, the output is in a high-impedance
state.
A
B
C
Clamps
V
V
, V
,
16, 17, 18
28, 29, 30
R
R
to Clamp Reference Voltage. One reference for each clamp. A V
CLPA CLPB
CLPB
TX INX
input is clamped to V when CLP is low.
CLPX X
BX
CLP , CLP ,
CLP
CMOS Clamp Pulse Inputs. One input for each A/D clamp. When CLP is
A
C
B
X
low, the V
INX
input is clamped to the V clamp voltage.
CLPX
Power
V
11, 47, 56
+5V
+5V
Analog Supply Voltage. +5 Volt power inputs. These should come
from the same power source and be decoupled to A
DDA
.
GND
Digital Supply Voltage. +5 Volt power inputs. These should come
from the same power source and be decoupled to A
V
DD
6, 7, 27, 28, 29,
30, 43, 44, 60,
61
.
GND
A
13, 49, 54
0.0V
0.0V
Analog Ground. Ground connections. These pins should be
connected to the system analog ground plane.
GND
D
16, 17, 18, 19,
20, 21, 22, 25,
26, 32, 33, 71,
72, 74, 75
Digital Ground. Ground connections. These pins should be
connected to the system analog ground plane.
GND
No Connect
N/C
1, 8, 10, 23, 24,
31, 46, 57, 59,
73
open
Not Connected.
4
PRODUCT SPECIFICATION
TMC1103
Sample N+3
t
STD
Sample N+2
V
Sample N
INX
Sample N+1
t
t
1/f
S
PWL
PWH
CLK
X
t
DO
t
HO
Hi-Z
DX
Data N-3
Data N-2
Data N-1
Data N
7-0
t
t
ENA
DIS
OE
X
65-1103-04
Figure 1. Timing
Equivalent Circuits and Threshold Levels
V
DD
V
DD
p
n
p
Digital
Input
Digital
Output
n
27011B
27014B
GND
Figure 3. Equivalent Digital Output Circuit
GND
Figure 2. Equivalent Digital Input Circuit
5
TMC1103
PRODUCT SPECIFICATION
Equivalent Circuits and Threshold Levels (continued)
V
V
RT
DDA
t
ENA
V
IN
t
OE
0.5V
DIS
Three-State
Outputs
2.0V
0.8V
7048B
0.5V
High Impedance
29030
A
GND
V
RB
Figure 4. Equivalent Analog Input Circuit
Figure 5. Threshold Levels for Three-State Measurements
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Condition
Min
Typ
Max
Unit
Power Supply Voltages
VDDA
Measured to A
Measured to D
Measured to V
Measured to D
-0.5
-0.5
-0.5
-0.5
+7.0
+7.0
+0.5
+0.5
V
V
V
V
GND
GND
DD
VDD
VDDA
AGND
GND
Digital Inputs
Applied Voltage
Forced current
Analog Inputs
Applied Voltage
Forced current
Digital Outputs
Applied voltage
Forced current
Short circuit duration
Temperature
Operating, ambient
Junction
Measured to DGND
-0.5
V
V
V
+ 0.5
V
DD
-10.0
+10.0
mA
Measured to A
-0.5
+0.5
DDA
V
GND
GND
-10.0
+10.0
mA
Measured to D
-0.5
-6.0
+ 0.5
V
DD
+6.0
mA
Single output in HIGH state to ground)
1 second
-20
-65
110
°C
°C
°C
°C
°C
V
+150
+300
+220
+150
±150
Lead, soldering
Vapor Phase soldering
Storage
10 seconds
1 minute
Electrostatic Discharge
EIAJ test method
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating
conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed
only if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
6
PRODUCT SPECIFICATION
TMC1103
Operating Conditions
Parameter
Min.
4.75
-0.1
Nom
5.0
0
Max.
5.25
0.1
Units
V
V
A
V
V
V
V
V
V
V
, V
Power Supply Voltage
DD DDA
Analog Ground (Measured to D
Reference Voltage, Top
Reference Voltage, Bottom
Reference Voltage Differential
Analog Input Range
)
V
GND
RTX
RBX
GND
2.6
0.6
2.0
V
DDA
V
0
V
-V
1.0
5.0
V
RTX RBX
V
RB
V
RT
V
INX
CLPX
IH
Clamp Reference Voltage, 50W max source
Input Voltage, Logic HIGH
0
V
0.7 V
DD
V
DD
V
Input Voltage, Logic LOW
GND
0.3 V
DD
V
IL
I
I
Output Current, Logic HIGH
Output Current, Logic LOW
-4.0
4.0
70
mA
mA
°C
OH
OL
T
Ambient Temperature, Still Air
0
A
Electrical Characteristics
Parameter
Conditions
Min.
Typ1
Max.
Units
I
Power Supply Current1
C
LOAD
= 35pF, f = f (3 A/Ds)
CK S
DD
f = 20 Msps
70
94
90
mA
mA
mA
S
f = 40 Msps
S
120
135
f = 50 Msps
S
105
I
Power Supply Current,
Quiescent
V
= V
DD DDA
= Max.
DDQ
CLK = LOW
29
45
55
65
mA
mA
X
CLK = HIGH
X
PD
Total Power Dissipation1
Input Capacitance, Analog
C
= 35pF, f
CK
= f (3 A/Ds)
S
LOAD
f = 20 Msps
S
300
425
490
4
470
630
710
mW
mW
mW
pF
f = 40 Msps
S
f = 50 Msps
S
C
AI
CLK = LOW
X
CLK = HIGH
12
pF
X
R
R
Input Resistance
500
200
kW
W
IN
Reference Resistance
Input Current, Analog
Input Current, HIGH
Input Current, LOW
270
340
±5
REF
I
I
I
I
mA
mA
mA
mA
CB
V
DD
V
DD
V
DD
= Max., V = V
IN
±5
IH
DD
= Max., V = 0V
IN
±5
IL
Hi-Z Output Leakage Current,
Output HIGH
= Max., V = V
IN
±5
OZH
DD
I
I
Hi-Z Output Leakage Current,
Output LOW
V
= Max., V = V
IN
±5
mA
OZL
OS
DD
DD
Short-Circuit Current
35
mA
7
TMC1103
PRODUCT SPECIFICATION
Electrical Characteristics (continued)
Parameter
Conditions
= -2.5mA
Min.
3.5
Typ1
Max.
Units
V
V
OH
Output Voltage, HIGH
I
I
I
OH
OH
OL
= Max.
= Max.
2.4
V
V
OL
Output Voltage, LOW
0.4
10
V
C
C
Digital Input Capacitance
Digital Output Capacitance
4
pF
pF
DI
10
DO
Note:
1. Typical values with V
= V
DDA
= Nom and T = Nom, Maximum values with V
DD
= V = Max. and T = Min.
DDA A
DD
A
Switching Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
f
t
t
Conversion Rate
TMC1103-20
S
20
40
50
Msps
Msps
Msps
TMC1103-40
TMC1103-50
CLKX Pulsewidth, HIGH
TMC1103-20
PWH
PWL
14
14
13
ns
ns
ns
TMC1103-40
TMC1103-50
CLKX Pulsewidth, LOW
TMC1103-20
8
8
7
ns
ns
ns
ps
ns
ps
mS
ns
ns
ns
ns
ns
TMC1103-40
TMC1103-50
E
Aperture Error
30
2
AP
t
t
t
t
t
t
t
t
Sampling Time Offset
Sampling Time Skew
Clamp Pulse Width1
Clamp Delay Time
Output Hold Time
Output Delay Time
Output Enable Time
Output Disable Time
1
5
STO
STS
CPW
CDLY
HO
150
400
+20 < T < +70°C
2
100
9
A
300
CLOAD = 15pF
14
27
42
DO
ENA
DIS
8
PRODUCT SPECIFICATION
TMC1103
System Performance Characteristics
Parameter
Conditions
= 2.6V
Min.
Typ.
Max.
Units
E
LI
Integral Linearity Error,
Independent
V
V
±0.5
LSB
RT
E
Differential Linearity Error
Bandwidth1
= 0.6V
±0.5
LSB
MHz
MHz
MHz
mV
LD
RB
BW
TMC1203-20
TMC1203-40
TMC1203-50
10
12
12
80
E
E
Offset Voltage, Top
(R – V for most positive
code transition)
V
= 2.6V, V
= 0.6V
= 0.6V
-40
-95
OT
RT
RB
RB
T
IN
Offset Voltage, Bottom
V
RT
= 2.6V, V
-30
mV
OB
(R – V for most negative
B
IN
code transition)
OFF
dg
Offset Voltage, Clamp
Differential Gain
±20
mV
%
CL
f = 14.3Msps
NTSC 40 IRE Mod Ramp
1.8
0.7
45
S
V
V
= +5.0V, T =25°C
DDA
= 2.6V, V
A
= 0.6V
RB
RT
dp
Differential Phase
f = 14.3Msps
deg
dB
S
NTSC 40 IRE Mod Ramp
V
V
= +5.0V, T =25°C
DDA
= 2.6V, V
A
= 0.6V
RB
RT
= 5.0 MHz
XTALK Channel Crosstalk
SNR Signal-to-Noise Ratio
f
N
f = 20Msps, V = 2.6V, V
= 0.6V
S
N
N
N
N
RT
RB
f
f
f
f
= 1.24MHz
= 2.48MHz
= 6.98MHz
= 10.0MHz
46
46
45
45
dB
dB
dB
dB
f = 40Msps, V = 2.6V, V
= 0.6V
= 0.6V
S
N
N
N
RT
RB
f
f
f
= 1.24MHz
= 6.98MHz
= 12.0MHz
42
41
40
dB
dB
dB
f = 50Msps, V = 2.6V, V
S
N
N
N
RT
RB
f
f
f
= 1.24MHz
= 6.98MHz
= 12.0MHz
40
40
40
dB
dB
dB
9
TMC1103
PRODUCT SPECIFICATION
System Performance Characteristics (continued)
Parameter
Conditions
Min.
Typ.
Max.
Units
SFDR Spurious-Free Dynamic Range
f = 20Msps, V = 2V p-p
S
N
N
N
N
IN
f
f
f
f
= 1.24MHz
= 2.48MHz
= 6.98MHz
= 10.0MHz
53
48
44
40
dB
dB
dB
dB
f = 40Msps, V = 2V p-p
S
N
N
N
IN
f
f
f
= 1.24MHz
= 6.98MHz
= 12.0MHz
49
44
38
dB
dB
dB
f = 50Msps, V = 2V p-p
S
N
N
N
IN
f
f
f
= 1.24MHz
= 6.98MHz
= 12.0MHz
46
40
37
dB
dB
dB
Notes:
1. Bandwidth is the frequency up to which a full-scale sinewave can be digitized without spurious codes.
2. Values shown in Typ. column are typical for V = V = +5V and T = 25°C.
DD DDA
A
3. SNR values do not include the harmonics of the fundamental frequency.
4. SFDR is the ratio in dB of fundamental amplitude to the harmonic with the highest amplitude.
5. Characteristics specified for V = 2.6V, V
RT
= 0.6V.
RB
10
PRODUCT SPECIFICATION
TMC1103
Typical Performance Characteristics
60
35
30
25
20
15
10
5
50
40
30
f
= 20Msps
S
20
10
0
0
0
10
20
30
(Msps)
40
50
0
5
10
15
(Msps)
20
25
f
S
f
IN
65-1103-05
65-1103-06
Figure 6. Typical I
vs f (Single A/D)
Figure 7. Typical SFDR vs f
DD
S
IN
50
40
50
40
30
20
30
20
f
= 20Msps
S
f
= 20Msps
S
10
0
10
0
0
5
10
15
(MHz)
20
25
0
1
2
3
4
5
V
IN
f
IN
65-1103-08
65-1103-07
Figure 8. Typical SNR vs f
IN
Figure 9. Typical SNR vs Full Scale Input Range
11
TMC1103
PRODUCT SPECIFICATION
Application Notes
The circuit in Figure 10 employs a band-gap reference to
The voltage reference at R can be adjusted from 0.0 to 2.4
TX
generate a variable R reference voltages for the TMC1103
volts while R is grounded. Schottky diodes can be used at
TX
BX
as well as a bias voltage to offset the wideband input amplifi-
ers to mid-range. The operational amplifier in the reference
circuitry is a standard 741-type.
V
to restrict the wideband amplifier output to between
INX
-0.3V and V
+0.3V. Diode protection is good practice to
DD
limit the analog input voltage at V
range.
to the safe operating
INX
+5V
0.1µF
0.1µF
1k½
LM185-1.2
+5V
V
V
DD
0.1µF
DDA
Gain Adjust
+
–
20½
V
+5V
DDP
R
R
R
2k½
0.1µF
TA
TB
TC
1k½
0.1µF
0.1µF
R
R
R
BA
BB
BC
1k½
GREEN
Digital
Video
DA
7-0
100
0.1µF
+
–
GREEN
Video
Input
Output
V
INA
OE
A
A
75½
V
CLPA
CLK
1k½
CLP
A
TMC1103
10k½
1k½
BLUE
Digital
Video
Output
DB
7-0
100
OE
0.1µF
B
B
+
BLUE
Video
Input
V
V
INB
CLPB
CLK
–
75½
1k½
CLP
B
RED
Digital
Video
Output
10k½
1k½
DC
7-0
V
CLPC
CLP
OE
C
C
C
100
Pixel
Clock
0.1µF
CLK
+
–
RED
Video
Input
V
INC
75½
A
D
GND
GND
1k½
VCLAMP
CLAMP
10k½
1k½
65-1103-09
Figure 10. Typical Interface Circuit – High Performance
Grounding
Printed Circuit Board Layout
The TMC1103 has separate analog and digital circuits. To
keep digital system noise from the A/D converter, it is rec-
Designing with high performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor A/D conversion. Consider the following sug-
gestions when doing the layout:
ommended that power supply voltages (V
and V )
DD
DDA
come from the same source, and that ground connections
(D and A ) be made to the analog ground plane, and
GND GND
as close as possible to the device pins. Power supply pins
should be individually decoupled at the pin. The digital cir-
cuitry that gets its input from the TMC1103 should be
referred to the system digital ground plane.
1. Keep the critical analog traces (V , R , R ) as short
TX BX
N
as possible and as far as possible from all digital signals.
The TMC1103 should be located close to the analog
input connectors.
12
PRODUCT SPECIFICATION
TMC1103
2. Segregate traces:
5. Decoupling capacitors should be applied liberally to
pins. Remember that not all power supply pins
V
DD
• A/D analog
• D/A analog
• Clocks
are created equal. They supply different circuits on the
integrated circuit, each of which generate varying
amounts and types of noise. For best results, use 0.1mF
ceramic capacitors. Lead lengths should be minimized.
• Digital
Treat analog inputs as transmission lines. Cleanly route
traces over the ground plane bearing in mind that the
return currents will flow through the ground plane
beneath the traces. Do not route digital traces nearby.
A few inches of digital trace less than a few line widths
from an analog trace will cross-couple noise into
adjacent analog circuits.
6. CLK should be handled carefully. Jitter and noise on
X
this clock may degrade performance. Terminate the
clock line, if needed, to eliminate overshoot and ringing.
Related Products
• TMC1175A, TMC1275 8-Bit Video A/D Converters
• TMC1173A, TMC1273 3V, Low-Power 8-Bit Video
A/D Converters
3. The power plane for the TMC1103 should be separate
from that which supplies the rest of the digital circuitry.
A single power plane should be used for all of the V
DD
• TMC1203 Triple 8-bit A/D Converter
pins. If the power supply for the TMC1103 is the same
as that of the system's digital circuitry, power to the
TMC1103 should be decoupled with ferrite beads and
0.1mF capacitors to reduce noise.
• TMC3003/TMC3503 Triple Video D/A Converters
• TMC2242B/TMC2243/TMC2246A Digital Filters
4. The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
13
TMC1103
PRODUCT SPECIFICATION
Notes:
14
PRODUCT SPECIFICATION
TMC1103
Mechanical Dimensions – 80-Lead MQFP Package
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Min.
Max.
2. Controlling dimension is millimeters.
A
—
.134
—
—
3.40
—
3. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall be .08mm (.003in.) maximum in excess of
the "B" dimension. Dambar cannot be located on the lower radius
or the foot.
A1
A2
B
.010
.100
.012
.005
.904
.783
.667
.547
.25
.120
.018
.009
.923
.791
.687
.555
2.55
.30
3.05
.45
3, 5
5
4. "L" is the length of terminal for soldering to a substrate.
5. "B" & "C" includes lead finish thickness.
C
.13
.23
D
22.95
19.90
16.95
13.90
23.45
20.10
17.45
14.10
D1
E
E1
e
.0315 BSC
.80 BSC
4
L
.025
.041
.65
1.03
N
80
24
16
80
24
16
ND
NE
a
0¡
7¡
0¡
7¡
ccc
—
.004
—
0.10
D
D1
.20 (.008) Min.
e
0¡ Min.
.13 (.30)
.005 (.012)
Datum Plane
R
E1
C
E
Pin 1
Identifier
a
.13 (.005) R Min.
B
L
0.063" Ref (1.60mm)
Lead Detail
See Lead Detail
Base Plane
A2
A
-C-
LEAD COPLANARITY
ccc
Seating Plane
A1
C
15
TMC1103
PRODUCT SPECIFICATION
Ordering Information
Conversion
Product Number Rate (Msps) Temperature Range Screening
Package
Package Marking
1103KLC20
TMC1103KLC20
TMC1103KLC40
TMC1103KLC50
20 Msps
40 Msps
50 Msps
T = 0°C to 70°C
Commercial 80-Lead MQFP
Commercial 80-Lead MQFP
Commercial 80-Lead MQFP
A
T = 0°C to 70°C
A
1103KLC40
T = 0°C to 70°C
A
1103KLC50
6/22/98 0.0m 002
Stock# DS70001103
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