CDK8307CITQ80 [CADEKA]
12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS; 12月13日位， 20/40/ 50 / 65MSPS ，八通道，超低功耗ADC LVDS
| 型号： | CDK8307CITQ80 |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS |
| 文件： | 总29页 (文件大小：1423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY Data Sheet
Amplify the Human Experience
CDK8307
12/13-bit, 20/40/50/65MSPS, Eight Channel,
Ultra Low Power ADC with LVDS
F E A T U R E S
General Description
nꢀ
20/40/50/65MSPS maximum sampling rate
The CDK8307 is a high performance low power octal analog-to-digital
converter (ADC). The ADC employs internal reference circuitry, a serial control
interface and serial LVDS output data, and is based on a proprietary structure.
nꢀ
Low Power Dissipation
– 22mW/channel at 20MSPS
– 34mW/channel at 40MSPS
– 40mW/channel at 50MSPS
– 50mW/channel at 65MSPS
72.2dB SNR at 8MHz FIN
An integrated PLL multiplies the input sampling clock by a factor of 12 or 14,
according to the LVDS output setting. The multiplied clock is used for data
serialization and data output. Data and frame synchronization output clocks are
supplied for data capture at the receiver.
nꢀ
nꢀ
nꢀ
nꢀ
0.5μs startup time from Sleep
15μs startup time from Power Down
Various modes and configuration settings can be applied to the ADC through
the serial control interface (SPI). Each channel can be powered down inde-
pendently and data format can be selected through this interface. A full chip
idle mode can be set by a single external pin. Register settings determines the
exact function of this external pin.
Internal reference circuitry requires no
external components
nꢀ
nꢀ
Internal offset correction
Reduced power dissipation modes available
– 32mW/channel at 50MSPS
– 71.5dB SNR at 8MHz FIN
Coarse and fine gain control
1.8V supply voltage
The CDK8307 is designed to easily interface with field-programmable gate
arrays (FPGAs) from several vendors.
nꢀ
nꢀ
nꢀ
The very low startup times of the CDK8307 allow significant power reduction
in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when
the receive path is idle.
Serial LVDS output
– 12- and 14-bit output available
Package alternatives
nꢀ
Block Diagram
– TQFP-80
– QFN-64
A P P L I C A T I O N S
FCLKP
nꢀ
Medical Imaging
Serial Control
Interface
Clock
Input
FCLKN
LCLKP
LCLKN
PLL
LVDS
LVDS
nꢀ
Wireless Infrastructure
nꢀ
Test and Measurement
IP1
IN1
D1N
D1P
Digital
Gain
ADC
nꢀ
Instrumentation
IP2
IN2
D2N
D2P
Digital
Gain
ADC
LVDS
•
•
•
•
•
•
•
•
•
IP8
IN8
D8N
D8P
Digital
Gain
ADC
LVDS
©2009 CADEKA Microcircuits LLC
www.cadeka.com
PRELIMINARY Data Sheet
Table of Contents
Features.................................................................. 1
Applications ............................................................ 1
General Description................................................ 1
Block Diagram ........................................................ 1
Table of Contents ................................................... 2
Ordering Information............................................. 3
Pin Configurations.................................................. 4
Pin Assignments .................................................. 5-8
Absolute Maximum Ratings................................... 9
Reliability Information........................................... 9
ESD Protection........................................................ 9
Recommended Operating Conditions.................... 9
Electrical Characteristics...................................... 10
Electrical Characteristics – CDK8307A................ 10
Electrical Characteristics – CDK8307B................ 11
Electrical Characteristics – CDK8307C................ 11
Electrical Characteristics – CDK8307C
Table 6. LVDS Output Drive Strength for
LCLK, FCLK, and Data ............................... 18
Table 7. LVDS Internal Termination
Programmability ....................................... 19
Table 8. Bit Clock Internal Termination.................... 19
Table 9. Analog Input Invert................................... 19
Table 10. LVDS Test Patterns.................................. 20
Table 11. Programmable Gain................................. 20
Table 12. Gain Setting for Channels 1-8 .................. 21
Table 13. LVDS Clock Programmability and
Data Output Modes................................. 21
Figure 6. Phase Programmability Modes for LCLK..... 22
Figure 7. SDR Interface Modes ............................... 22
Table 14. Number of Serial Output Bits ................... 22
Table 15. Full Scale Control.................................... 23
Table 16. Register Values with Corresponding
Charge in Full-Scale Range...................... 23
Table 17. Clock Frequency...................................... 23
Table 18. Clock Frequency Settings......................... 23
Table 19. Performance Control................................ 24
Table 20. Performance Control Settings................... 24
Table 21. External Common Mode Voltage
(Continued)........................................................... 12
Electrical Characteristics – CDK8307D................ 12
Digital and Timing Electrical Characteristics ...... 13
LVDS Timing Diagrams......................................... 14
Figure 1. 12-bit Output, DDR Mode......................... 14
Figure 2. 14-bit Output, DDR Mode......................... 14
Figure 3. 12-bit Output, SDR Mode......................... 14
Figure 4. Data Timing............................................ 14
Serial Interface..................................................... 15
Timing Diagram .................................................... 15
Figure 5. Serial Port Interface Timing Diagram..... 15
Table 1. Serial Port Interface Timing Definitions ... 15
Register Initialization............................................. 15
Serial Register Map ..........................................16-17
Table 2. Summary of Functions Supported
Buffer Driving Strength ........................... 24
Theory of Operation ............................................. 25
Recommended Usage........................................... 25
Analog Input......................................................... 25
Figure 8. Input Configuration Diagram ................ 25
DC-Coupling.......................................................... 25
Figure 9. DC-Coupled Input................................ 25
AC-Coupling.......................................................... 26
Figure 10. Transformer Coupled Input................. 26
Figure 11. AC-Coupled Input .............................. 26
Figure 12. Alternative Input Network................... 26
Clock Input and Jitter Considerations...................... 27
Mechanical Dimensions ...................................28-29
QFN-64 Package.................................................... 28
TQFP-80 Package.................................................. 29
by Serial Interface ................................16-17
Description of Serial Registers ........................17-24
Table 3. Software Reset......................................... 17
Table 4. Power-Down Modes .................................. 17
Table 5. LVDS Drive Strength Programmability......... 18
©2009 CADEKA Microcircuits LLC
www.cadeka.com
2
PRELIMINARY Data Sheet
Ordering Information
Part Number
Speed
Package
TQFP-80
Pb-Free RoHS Compliant Operating Temperature Range Packaging Method
CDK8307AITQ80*
20MSPS
20MSPS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Tray
Tray
Tray
Tray
Tray
Tray
Tray
Tray
Tray
Tray
Tray
Tray
CDK8307AILP64*
QFN-64
QFN-64
TQFP-80
QFN-64
QFN-64
TQFP-80
QFN-64
QFN-64
TQFP-80
QFN-64
QFN-64
CDK8307AILP64B2** 20MSPS
CDK8307BITQ80*
CDK8307BILP64*
40MSPS
40MSPS
CDK8307BILP64B2** 40MSPS
CDK8307CITQ80*
CDK8307CILP64*
50MSPS
50MSPS
CDK8307CILP64B2** 50MSPS
CDK8307DITQ80*
CDK8307DILP64*
65MSPS
65MSPS
CDK8307DILP64B2** 65MSPS
Moisture sensitivity level for all parts is MSL-3. *Preliminary. **Preliminary, pinout matches AD9222.
©2009 CADEKA Microcircuits LLC
www.cadeka.com
3
PRELIMINARY Data Sheet
Pin Configurations
QFN-64
QFN-64 (B2 Version: AD9222 Pinout Option)
IP1
IN1
IN8
AVDD
IP3
AVDD
IP6
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
IP8
AVSS
IP2
AVSS
IN7
IN3
IN6
3
3
AVDD
IN4
AVDD
IN5
4
4
IN2
IP7
5
5
IP4
IP5
AVSS
IP3
AVSS
IN6
6
6
CDK8307
CDK8307
AVDD
AVDD
CLKN
CLKP
AVDD
AVDD
DVSS
DVDD
D4N
AVDD
PD
7
7
QFN-64
QFN-64
IN3
IP6
8
8
CSN
SDATA
SCLK
AVDD
DCVSS
DVDD
D5P
AVSS
IP4
AVSS
IN5
9
9
10
11
12
13
14
15
16
10
11
12
13
14
15
16
IN4
IP5
DVSS
PD
AVSS
DVSS
DVDD
D8N
D8P
DVSS
D1P
D1N
D4P
D5N
TQFP-80
AVDD
IP1
AVDD
IN8
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
IN1
IP8
3
AVSS
IP2
AVSS
IN7
4
5
IN2
IP7
6
AVDD
AVSS
IP3
AVDD
AVSS
IN6
7
8
CDK8307
9
TQFP-80
IN3
IP6
10
11
12
13
14
15
16
17
18
19
20
AVSS
IP4
AVSS
IN5
IN4
IP5
AVDD
DVSS
PD
AVDD
DVSS
RESETN
DVSS
DVSS
FCLKN
FCLKP
DVSS
DVSS
LCLKP
LCLKN
©2009 CADEKA Microcircuits LLC
www.cadeka.com
4
PRELIMINARY Data Sheet
Pin Assignments
Pin No.
QFN-64
Pin Name
Description
49, 50, 57
AVDD
AVSS
IP1
Analog power supply, 1.8V
Analog ground
3, 6, 9, 37, 40, 43, 46, 52
1
Positive differential input signal, channel 1
2
4
5
IN1
IP2
IN2
Negative differential input signal, channel 1
Positive differential input signal, channel 2
Negative differential input signal, channel 2
Positive differential input signal, channel 3
Negative differential input signal, channel 3
Positive differential input signal, channel 4
Negative differential input signal, channel 4
7
8
IP3
IN3
IP4
IN4
10
11
38
IP5
IN5
Positive differential input signal, channel 5
Negative differential input signal, channel 5
Positive differential input signal, channel 6
Negative differential input signal, channel 6
Positive differential input signal, channel 7
Negative differential input signal, channel 7
Positive differential input signal, channel 8
Negative differential input signal, channel 8
Digital ground
39
41
IP6
42
IN6
44
IP7
45
IN7
47
IP8
48
IN8
12, 14, 36
35
DVSS
DVDD
PD
Digital and I/O power supply, 1.8V
Power-down input
13
15
D1P
D1N
D2P
D2N
D3P
D3N
D4P
D4N
D5P
D5N
D6P
D6N
D7P
D7N
D8P
D8N
FCLKP
FCLKN
LCLKP
LCLKN
LVDS channel 1, positive output
LVDS channel 1, negative output
LVDS channel 2, positive output
LVDS channel 2, negative output
LVDS channel 3, positive output
LVDS channel 3, negative output
LVDS channel 4, positive output
LVDS channel 4, negative output
LVDS channel 5, positive output
LVDS channel 5, negative output
LVDS channel 6, positive output
LVDS channel 6, negative output
LVDS channel 7, positive output
LVDS channel 7, negative output
LVDS channel 8, positive output
LVDS channel 8, negative output
LVDS frame clock (1x), positive output
LVDS frame clock (1x), negative output
LVDS bit clock, positive output
16
17
18
19
20
21
22
27
28
29
30
31
32
33
34
23
24
25
26
LVDS bit clock, negative output
©2009 CADEKA Microcircuits LLC
www.cadeka.com
5
PRELIMINARY Data Sheet
Pin Assignments (Continued)
Pin No.
Pin Name
NC
Description
51, 54, 55, 56
Not connected
53
58
59
60
61
62
63
64
VCM
Common mode output pin, 0.5 AVDD
Positive differential input clock
Negative differential input clock.
Digital CMOS inputs supply voltage (1.7V to 3.6V)
Chip select enable. Active low.
Serial data input
CLKP
CLKN
OVDD
CSN
SDATA
SCLK
Serial clock input
RESETN
Reset SPI interface
QFN-64 (B2 version: AD9222 pinout option)
1, 4, 7, 8, 11, 12, 37, 42, 45, 48,
AVDD
Analog power supply, 1.8V
51, 59, 62
0
AVSS
IP1
Analog ground (Exposed paddle, Pin 0, bottom of package)
Positive differential input signal, channel 1
Negative differential input signal, channel 1
Positive differential input signal, channel 2
Negative differential input signal, channel 2
Positive differential input signal, channel 3
Negative differential input signal, channel 3
Positive differential input signal, channel 4
Negative differential input signal, channel 4
Positive differential input signal, channel 5
Negative differential input signal, channel 5
Positive differential input signal, channel 6
Negative differential input signal, channel 6
Positive differential input signal, channel 7
Negative differential input signal, channel 7
Positive differential input signal, channel 8
Negative differential input signal, channel 8
Digital ground
60
61
IN1
IP2
64
63
IN2
IP3
2
3
IN3
IP4
6
5
IN4
IP5
43
44
IN5
IP6
47
46
IN6
IP7
49
50
IN7
IP8
53
52
IN8
DVSS
DVDD
PD
13, 36
14, 35
41
Digital and I/O power supply, 1.8V
Power-down input
22
D1P
D1N
D2P
D2N
D3P
D3N
D4P
D4N
D5P
D5N
LVDS channel 1, positive output
21
LVDS channel 1, negative output
20
LVDS channel 2, positive output
19
LVDS channel 2, negative output
18
LVDS channel 3, positive output
17
LVDS channel 3, negative output
16
LVDS channel 4, positive output
15
LVDS channel 4, negative output
34
LVDS channel 5, positive output
33
LVDS channel 5, negative output
©2009 CADEKA Microcircuits LLC
www.cadeka.com
6
PRELIMINARY Data Sheet
Pin Assignments (Continued)
Pin No.
Pin Name
D6P
Description
32
LVDS channel 6, positive output
LVDS channel 6, negative output
LVDS channel 7, positive output
LVDS channel 7, negative output
LVDS channel 8, positive output
LVDS channel 8, negative output
LVDS frame clock (1X), positive output
LVDS frame clock (1X), negative output
LVDS bit clock, positive output
LVDS bit clock, negative output
Not connected
31
D6N
30
D7P
29
D7N
28
D8P
27
D8N
26
FCLKP
FCLKN
LCKP
LCKN
NC
25
24
23
54
55
NC
Not connected
56
VCM
NC
Common mode output pin, 0.5*AVDD
Not connected
57
58
NC
Not connected
10
CLKP
CLKN
CSN
Positive differential input clock
Negative differential input clock.
Chip select enable. Active Low
Serial data input
9
40
39
SDATA
SCLK
38
Serial clock input
TQFP
1, 7, 14, 47, 54, 60, 63, 70
AVDD
AVSS
Analog power supply, 1.8V
Analog ground
4, 8, 11, 50, 53, 57, 61, 68, 73,
74, 79, 80
2
IP1
IN1
IP2
Positive differential input signal, channel 1
Negative differential input signal, channel 1
Positive differential input signal, channel 2
Negative differential input signal, channel 2
Positive differential input signal, channel 3
Negative differential input signal, channel 3
Positive differential input signal, channel 4
Negative differential input signal, channel 4
Positive differential input signal, channel 5
Negative differential input signal, channel 5
Positive differential input signal, channel 6
Negative differential input signal, channel 6
Positive differential input signal, channel 7
Negative differential input signal, channel 7
Positive differential input signal, channel 8
Negative differential input signal, channel 8
Digital ground
3
5
6
IN2
IP3
9
10
IN3
IP4
12
13
IN4
IP5
48
49
IN5
IP6
51
52
IN6
IP7
55
56
IN7
IP8
58
59
15, 17, 18, 26, 36, 43, 44, 46
25, 35
IN8
DVSS
DVDD
Digital and I/O power supply, 1.8V
©2009 CADEKA Microcircuits LLC
www.cadeka.com
7
PRELIMINARY Data Sheet
Pin Assignments (Continued)
Pin No.
Pin Name
PD
Description
16
Power-down input
19
LCKP
LCKN
D1P
LVDS bit clock, positive output
LVDS bit clock, negative output
LVDS channel 1, positive output
LVDS channel 1, negative output
LVDS channel 2, positive output
LVDS channel 2, negative output
LVDS channel 3, positive output
LVDS channel 3, negative output
LVDS channel 4, positive output
LVDS channel 4, negative output
LVDS channel 5, positive output
LVDS channel 5, negative output
LVDS channel 6, positive output
LVDS channel 6, negative output
LVDS channel 7, positive output
LVDS channel 7, negative output
LVDS channel 8, positive output
LVDS channel 8, negative output
LVDS frame clock (1x), positive output
LVDS frame clock (1x), negative output
Reset SPI interface
20
21
22
D1N
23
D2P
24
D2N
27
D3P
28
D3N
29
D4P
30
D4N
31
D5P
32
D5N
33
D6P
34
D6N
37
D7P
38
D7N
39
D8P
40
D8N
41
FCLKP
FCLKN
RESETN
NC
42
45
62, 64, 66, 67, 69
Not connected
65
71
72
75
76
77
78
VCM
CLKP
CLKN
OVDD
CSN
Common mode output pin, 0.5 AVDD
Positive differential input clock
Negative differential input clock.
Digital CMOS inputs supply voltage (1.7V to 3.6V)
Chip select enable. Active low.
Serial data input
SDATA
SCLK
Serial clock input
©2009 CADEKA Microcircuits LLC
www.cadeka.com
8
PRELIMINARY Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device
function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
Reference Pin
Min
Max
Unit
AVDD
AVSS
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
+2.3
+2.3
+3.9
+0.3
+2.3
+2.3
+2.3
+3.9
V
V
V
V
V
V
V
V
DVDD
DVSS
OVDD
AVSS
AVSS, DVSS
DVSS / AVSS
AVSS
Analog inputs and outpts (IPx, INx)
CLKx
AVSS
LVDS outputs
Digital inputs
DVSS
DVSS
Reliability Information
Parameter
Min
-60
Typ
Max
Unit
Junction Temperature
TBD
°C
°C
Storage Temperature Range
Lead Temperature (Soldering, 10s)
+150
J-STD-020
ESD Protection
Product
QFN-64
TQFP-80
Human Body Model (HBM)
TBD
TBD
TBD
TBD
Charged Device Model (CDM)
Recommended Operating Conditions
Parameter
Min
-40
Typ
Max
+85
Unit
°C
Operating Temperature Range
This device can be damaged by ESD. Even though this product is protected with state-of-the-art ESD protection
circuitry, damage may occur if the device is not handled with appropriate precautions. ESD damage may range
from device failure to performance degradation. Analog circuitry may be more susceptible to damage as vary small
parametric changes can result in specification noncompliance.
©2009 CADEKA Microcircuits LLC
www.cadeka.com
9
PRELIMINARY Data Sheet
Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DC Accuracy
No Missing Codes
Offset Error
Guaranteed
1
Offset error after digital offset cancellation
LSB
Gain Error
-6
6
%FS
Gain matching between channels. ±3sigma
value at worst case conditions.
Gain Matching
-0.5
0.5
%FS
DNL
Differential Non-Linearity
Integral Non-Linearity
12-bit level
12-bit level
±0.2
±0.6
LSB
LSB
V
INL
VCMO
Common Mode Voltage Output
VAVDD/2
Analog Input
VCMI
Input Common Mode
Analog input common mode voltage
Differential input voltage range
Differential input capacitance
Input bandwidth
VCM -0.1
500
VCM +0.2
V
2.0
2
Vpp
pF
VFSR
Full Scale Range
Input Capacitance
Bandwidth
MHz
Power Supply
AVDD
Analog Supply Voltage
1.7
1.7
1.7
1.8
1.8
1.8
2.0
2.0
3.6
V
V
V
DVDD
Digital Supply Voltage
Digital and output driver supply voltage
OVDD
Digital CMOS Input Supply Voltage
Electrical Characteristics - CDK8307A
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
SNR
Signal to Noise Ratio
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
72.2
71.5
82
dBFS
dBFS
dBc
SINAD
SFDR
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
HD2
95
dBc
HD3
82
dBc
ENOB
11.6
bits
Signal applied to 7 channels (FIN0).
Crosstalk
Measurement taken on one channel with full
scale at FIN1. FIN1 = 8MHz, FIN0 = 9.9MHz
95
dBc
Power Supply
47
50
85
90
175
10
43
44
16
mA
mA
Analog supply current
Digital and output driver supply
Digital supply current
mW
mW
mW
μW
Analog power Dissipation
Digital power Dissipation
Total power Dissipation
Power Down Dissipation
Sleep Mode Dissipation
Sleep Channel Mode Dissipation
Sleep Channel Mode Savings
mW
mW
mW
Power dissipation with all chs in sleep mode
Power dissipation savings per channel off
Clock Inputs
20
MSPS
MSPS
Maximum Conversion Rate
Minimum Conversion Rate
15
©2009 CADEKA Microcircuits LLC
www.cadeka.com
10
PRELIMINARY Data Sheet
Electrical Characteristics - CDK8307B
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
SNR
Signal to Noise Ratio
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
72.2
71.5
82
dBFS
dBFS
dBc
SINAD
SFDR
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
HD2
95
dBc
HD3
82
dBc
ENOB
11.6
bits
Signal applied to 7 channels (FIN0).
Crosstalk
Measurement taken on one channel with full
scale at FIN1. FIN1 = 8MHz, FIN0 = 9.9MHz
95
dBc
Power Supply
91
60
mA
mA
Analog supply current
Digital and output driver supply
Digital supply current
164
108
272
10
mW
mW
mW
μW
Analog power Dissipation
Digital power Dissipation
Total power Dissipation
Power Down Dissipation
Sleep Mode Dissipation
Sleep Channel Mode Dissipation
Sleep Channel Mode Savings
67
mW
mW
mW
Power dissipation with all chs in sleep mode
Power dissipation savings per channel off
72
23
Clock Inputs
40
MSPS
MSPS
Maximum Conversion Rate
Minimum Conversion Rate
20
Electrical Characteristics - CDK8307C
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
SNR
Signal to Noise Ratio
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
72.2
71.5
82
dBFS
dBFS
dBc
SINAD
SFDR
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
HD2
95
dBc
HD3
82
dBc
ENOB
11.6
bits
Signal applied to 7 channels (FIN0).
Crosstalk
Measurement taken on one channel with full
scale at FIN1. FIN1 = 8MHz, FIN0 = 9.9MHz
95
dBc
Power Supply
112
66
mA
mA
Analog supply current
Digital supply current
Analog power Dissipation
Digital power Dissipation
Total power Dissipation
Power Down Dissipation
Sleep Mode Dissipation
Digital and output driver supply
202
119
321
10
mW
mW
mW
μW
78
mW
©2009 CADEKA Microcircuits LLC
www.cadeka.com
11
PRELIMINARY Data Sheet
Electrical Characteristics - CDK8307C Continued
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Power dissipation with all chs in sleep mode
Power dissipation savings per channel off
80
28
mW
mW
Sleep Channel Mode Dissipation
Sleep Channel Mode Savings
Clock Inputs
50
MSPS
MSPS
Maximum Conversion Rate
Minimum Conversion Rate
20
Electrical Characteristics - CDK8307D
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
SNR
Signal to Noise Ratio
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
72.2
71.5
82
dBFS
dBFS
dBc
SINAD
SFDR
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
HD2
95
dBc
HD3
82
dBc
ENOB
11.6
bits
Signal applied to 7 chs (FIN0). Measurement
Crosstalk
taken on one ch, full scale at FIN1. FIN1
8MHz, FIN0 = 9.9MHz
=
95
dBc
Power Supply
145
67
mA
mA
Analog supply current
Digital and output driver supply
Digital supply current
261
121
382
10
mW
mW
mW
μW
Analog power Dissipation
Digital power Dissipation
Total power Dissipation
Power Down Dissipation
Sleep Mode Dissipation
Sleep Channel Mode Dissipation
Sleep Channel Mode Savings
96
mW
mW
mW
Power dissipation with all chs in sleep mode
Power dissipation savings per channel off
98
38
Clock Inputs
65
MSPS
MSPS
Maximum Conversion Rate
Minimum Conversion Rate
20
©2009 CADEKA Microcircuits LLC
www.cadeka.com
12
PRELIMINARY Data Sheet
Digital and Timing Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Clock Inputs
Duty Cycle
Compliance
20
80
%high
CMOS, LVDS, LVPECL
200
200
800
mVpp
mVpp
V
Differential input swing
Input range
Input range
800
0.3
Differential input swing, sine wave clock input
Keep voltages within gnd and voltage of AVDD
Differential
Input common mode voltage
Input capacitance
VAVDD -0.3
2
pF
Logic Inputs (CMOS)
VOVDD ≥ 3.0V
2
V
V
VIH
VIL
High Level Input Voltage
VOVDD = 1.7V – 3.0V
VOVDD ≥ 3.0V
0.8 • VOVDD
0
0.8
0.2 • VOVDD
10
V
Low Level Input Voltage
VOVDD = 1.7V – 3.0V
0
V
IIH
IIL
CI
High Level Input Leakage Current
Low Level Input Leakage Current
Input Capacitance
-10
-10
μA
μA
pF
10
3
Data Outputs (LVDS)
Compliance
LVDS
VOUT
VCM
Digital Output Voltage
Output Common Mode Voltage
Output Coding
247
454
mV
V
1.125
1.375
Default/Optional
Offset Binary/2‘s Complement
Timing Characteristics
TAP
Aperture Delay
0.8
ns
ps
εRMS
Aperture Jitter
Power Down
<0.5
Start up time from Power Down to Active
Mode. References have reached 99% of final
value. (See section Clock Frequency)
clock
cycles
TPD
350
900
TSLP
TOVR
TLAT
Sleep Mode
Start up time from Sleep Mode to Active Mode
0.5
1
μs
Out Of Range Recovery Time
Pipeline Delay
clk cycles
clk cycles
14
LVDS Output Timing Characterisctics
tdata
LCLK to Data Delay Time
Clock Propagation Delay
Excluding programmable phase shift
50
ps
ns
TBD
TPROP
% LCLK
cycle
LVDS Bit-Clock Duty-Cycle
Frame clock cycle-to-cycle jitter
Data Rise- and Fall Time
45
55
% LCLK
cycle
2.5
Calculated from -100mV to +100mV,
and vice-versa
TEDGE
TBD
TBD
ns
ns
Calculated from -100mV to +100mV,
and vice-versa
TCLKEDGE
Clock Rise- and Fall Time
Note:
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum.
©2009 CADEKA Microcircuits LLC
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13
PRELIMINARY Data Sheet
LVDS Timing Diagrams
Analog Input
ADC Clock
TLVDS
LCLKP
LCLKN
FCLKN
FCLKP
D10 D11 D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D0
D1
N
D2
N
D3
N
D4
N
D5
N
D6
N
D7
N
D8
N
D9 D10
Dxx<1:0>
N-2 N-2 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1
N
N
N
TPROP
Figure 1. 12-bit Output, DDR Mode
Analog Input
ADC Clock
TLVDS
LCLKP
LCLKN
FCLKN
FCLKP
D0 D1 D2 D3
N-1 N-1 N-1 N-1
D5 D6 D7 D8 D9 D10 D11 D12 D13 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
D4
N-1
Dxx<1:0>
N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1
N
N
N
N
N
N
N
N
N
N
N
N
N
N
TPROP
Figure 2. 14-bit Output, DDR Mode
Analog Input
ADC Clock
TLVDS
LCLKP
LCLKN
FCLKN
FCLKP
D10 D11 D0 D1
N-2 N-2 N-1 N-1
D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
D2
N-1
Dxx<1:0>
N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1
N
N
N
N
N
N
N
N
N
N
N
TPROP
Figure 3. 12-bit Output, SDR Mode
TLVDS
LCLKP
LCLKN
Dxx<1:0>
TLVDS/2
tdata
Figure 4. Data Timing
©2009 CADEKA Microcircuits LLC
www.cadeka.com
14
PRELIMINARY Data Sheet
Serial Interface
The CDK8307 configuration registers can be accessed through a serial interface formed by the pins SDATA (serial
interface data), SCLK (serial interface clock) and CSN (chip select, active low). The following occurs when CSN is set low:
nꢀ
Serial data are shifted into the chip
nꢀ
At every rising edge of SCLK, the value present at SDATA is latched
nꢀ
SDATA is loaded into the register every 24th rising edge of SCLK
Multiples of 24-bit words data can be loaded within a single active CSN pulse. If more than 24 bits are loaded into
SDATA during one active CSN pulse, only the first 24 bits are kept. The excess bits are ignored. Every 24-bit word is
divided into two parts:
nꢀ
The first eight bits form the register address
nꢀ
The remaining 16 bits form the register data
Acceptable SCLK frequencies are from 20MHz down to a few hertz. Duty-cycle does not have to be tightly controlled.
Timing Diagram
Figure 5 shows the timing of the serial port interface. Table 1 below explains the timing variables used in the Timing
Diagram.
tch
tcs
thi
tclk
ts
tch
i
tlo
th
CSN
SCLK
A7
A6
A5
A4
A3
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4 D3
D2
D1 D0
SDATA
Figure 5. Serial Port Interface Timing Diagram
Table 1. Serial Port Interface Timing Definitions
Parameter
Description
Minimum Value
Unit
t
Setup time between CSN and SCLK
Hold time between CSN and SCLK
SCLK high time
8
8
ns
ns
ns
ns
ns
ns
ns
cs
t
ch
t
20
20
50
5
hi
lo
t
SCLK low time
t
clk
SCLK period
t
Data setup time
s
t
Data hold time
5
h
Register Initialization
Before CDK8307 can be used, the internal registers must be initialized to their default values. This can be done
immediately after applying supply voltage to the circuit. Initialization can be done in one of two ways:
1. By applying a low-going pulse on the RESET pin
2. By using the serial interface to set the RST bit high. Internal registers are reset to default values when this
bit is set. The RST bit is self-reset to zero. When using this method, do not apply any low-going pulse on the
RESETN pin.
©2009 CADEKA Microcircuits LLC
www.cadeka.com
15
PRELIMINARY Data Sheet
Serial Register Map
Table 2. Summary of Functions Supported by the Serial Interface
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Software reset.
This bit is self-clearing
Channel-specific power-down
Go to sleep-mode
Default
Inactive
X
X
rst
00
X
X
X
X
X
X
X
pd_ch<8:1>
sleep
Inactive
Inactive
Inactive
X
X
pd
Go to power-down
0F
PD pin
Configures the PD pin for
sleep-mode
configured for
power-down
mode
X
X
pd_pin_cfg
LVDS current drive programma-
bility for LCLKP and LCLKN pins
X
X
X
ilvds_lclk<2:0>
3.5mA drive
3.5mA drive
3.5mA drive
ilvds_
frame<2:0>
LVDS current drive programma-
bility for FCLKP and FCLKN pins
X
X
X
11
12
LVDS current drive programma-
bility for output data pins
X
X
ilvds_dat<2:0>
en_lvds_term
Enables internal termination
for LVDS buffers
Termination
disabled
X
1
1
1
Programmable termination
for LCLKN and LCLKP buffers
Termination
disabled
X
X
X
X
X
X
term_lclk<2:0>
term_
frame<2:0>
Programmable termination
for FCLKN and FCLKP buffers
Termination
disabled
X
X
X
Programmable termination
for output data buffers
Termination
disabled
X
X
X
term_dat<2:0>
invert_ch<8:1>
en_ramp
Swaps the polarity of the
analog input pins electrically
IPx is
positive input
X
X
X
X
0
X
0
X
24
25
Enables a repeating full-scale
ramp pattern on the outputs
Inactive
Inactive
Inactive
Enable the mode wherein the
0
0
X
X
X
0
X
X
0
X
X
X
dual_custom_pat output toggles between two
defined codes
single_custom_
pat
Enables the mode wherein the
output is a constant specified code
Bits for the single custom pattern
bits_cus-
tom1<13:0>
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
and for the first code of the dual Inactive
26
27
custom pattern. <0> is the LSB
bits_cus-
tom2<13:0>
Bits for the second code of the
Inactive
X
X
X
X
dual custom pattern
X
X
gain_ch1<3:0>
gain_ch2<3:0>
gain_ch3<3:0>
gain_ch4<3:0>
gain_ch5<3:0>
gain_ch6<3:0>
gain_ch7<3:0>
gain_ch8<3:0>
Programmable gain for channel 1 0dB gain
Programmable gain for channel 2 0dB gain
Programmable gain for channel 3 0dB gain
Programmable gain for channel 4 0dB gain
Programmable gain for channel 5 0dB gain
Programmable gain for channel 6 0dB gain
Programmable gain for channel 7 0dB gain
Programmable gain for channel 8 0dB gain
X
X
X
X
2A
2B
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
©2009 CADEKA Microcircuits LLC
www.cadeka.com
16
PRELIMINARY Data Sheet
Table 2. Summary of Functions Supported by the Serial Interface (Continued)
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
Controls the phase of LCLK
output relative to data
X
X
phase_ddr<1:0>
90 degrees
42
45
0
X
X
0
pat_deskew
pat_sync
Enable deskew pattern mode
Enable sync pattern mode
Inactive
Inactive
Binary two's complement
format for ADC output data
Straight
X
btc_mode
msb_first
en_sdr
offset binary
Serialized ADC output data
comes out with MSB first
LSB-first
output
X
Enable SDR output mode. LCLK
becomes a 12x input clock
DDR
output mode
X
1
46
Rising edge
of LCLK
comes in the
middle of the
data window
Controls whether the LCLK ris-
ing or falling edge comes in the
middle of the data window when
operating in SDR mode
X
fall_sdr
X
X
X
X
perfm_cntrl
ext_vcm_bc
ADC performance control
Nominal
50
VCM buffer driving strength
control
X
X
X
X
Nominal
Controls LVDS power down
mode
X
0
lvds_pd_mode
lvds_num_bits
High z mode
13-bit
52
53
Sets the number of LVDS
output bits
X
X
X
X
X
X
fs_cntrl
clk_freq
Fine adjust ADC full scale range 0% change
Input clock frequency 65MHz
55
56
Description of Serial Registers
Table 3. Software Reset
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Self-clearing software reset
Default
Inactive
X
rst
00
Setting the rst register bit to '1', resets all internal registers including the rst register bit itself.
Table 4. Power-Down Modes
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
Inactive
X
X
X
X
X
X
X
X
pd_ch<8:1>
sleep
Channel-specific power-down
Go to sleep-mode
X
Inactive
Inactive
X
pd
Go to power-down
0F
52
X
pd_pin_cfg
Configures the PD pin for
sleep-mode
PD pin con-
figured for
power-down
mode.
Controls LVDS power down
mode
X
lvds_pd_mode
High z mode
©2009 CADEKA Microcircuits LLC
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17
PRELIMINARY Data Sheet
Setting pd_ch<n> = '1', powers down channel <n> of the ADC. Setting sleep = '1', powers down the entire chip, except
the band-gap reference circuit.
Setting pd = '1' completely powers down the chip, including the band-gap reference circuit. Start-up time from this mode
is significantly longer than from the sleep and pd_ch<n> modes.
Setting pdn_pin_cfg = '1' configures the circuit to enter sleep mode when the PD pin is set high. When pdn_pin_cfg =
'0', which is the default, the circuit enters power down mode when the PD pin is set high.
The lvds_pd_mode register configures whether the LVDS data output drivers are powered down or not in sleep and
sleep channel modes. LCLK and FCLK drivers are not affected by this register, and are always on in sleep and sleep
channel modes. If lvds_pd_mode is set low (default), the LVDS output is put in high Z, and the driver is completely
powered down. If lvds_pd_mode is set high, the LVDS output is set to constant 0, and the driver is still on during sleep
and sleep channel modes.
Table 5. LVDS Drive Strength Programmability
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
X
X
X
ilvds_lclk<2:0>
LVDS current drive programma- 3.5mA drive
bility for LCLKP and LCLKN pins.
X
X
X
ilvds_
frame<2:0>
LVDS current drive programma- 3.5mA drive
bility for FCLKP and FCLKN pins.
11
X
X
X
ilvds_dat<2:0>
LVDS current drive programma- 3.5mA drive
bility for output data pins.
The current delivered by the LVDS output drivers can be configured as shown in Table 6. The default current is 3.5mA,
which is what the LVDS standard specifies.
Setting the ilvds_lclk<2:0> register controls the current drive strength of the LVDS clock output on the LCLKP and LCLKN
pins.
Setting the ilvds_frame<2:0> register controls the current drive strength of the frame clock output on the FCLKP and
FCLKN pins.
Setting the ilvds_dat<2:0> register controls the current drive strength of the data outputs on the D[8:1]P and D[8:1]
N pins.
Table 6. LVDS Output Drive Strength for LCLK, FCLK, and Data
ilvds_*<2:0>
LVDS Drive Strength
3.5 mA (default)
2.5 mA
000
001
010
011
100
101
110
111
1.5 mA
0.5 mA
7.5 mA
6.5 mA
5.5 mA
4.5 mA
©2009 CADEKA Microcircuits LLC
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18
PRELIMINARY Data Sheet
Table 7. LVDS Internal Termination Programmability
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
X
1
1
1
en_lvds_term
Enables internal termination for
LVDS buffers
Termination
disabled
X
X
X
term_lclk<2:0>
Programmable termination for
LCLKN and LCLKP buffers
Termination
disabled
12
X
X
X
term_
frame<2:0>
Programmable termination for
FCLKN and FCLKP buffers
Termination
disabled
X
X
X
term_dat<2:0>
Programmable termination for
DxP and DxN buffers
Termination
disabled
The off-chip load on the LVDS buffers may represent a characteristic impedance that is not perfectly matched with
the PCB traces. This may result in reflections back to the LVDS outputs and loss of signal integrity. This effect can be
mitigated by enabling an internal termination between the positive and negative outputs of each LVDS buffer. Internal
termination mode can be selected by setting the en_lvds_term bit to '1'. Once this bit is set, the internal termination
values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. Table
8 shows how the internal termination of the LVDS buffers are programmed. The values are typical values and can vary
by up to ±20% from device to device and across temperature.
Table 8. Bit Clock Internal Termination
term_*<2:0>
LVDS Internal Termination
000
001
010
011
100
101
110
111
Termination Disabled
260Ω
150Ω
94Ω
125Ω
80Ω
66Ω
55Ω
Table 9. Analog Input Invert
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
X
X
X
X
X
X
X
X
invert_ch<8:1>
Swaps the polarity of the analog IPx is positive
input pins electrically input
24
The IPx pin represents the positive analog input pin, and INx represents the negative (complementary) input. Setting
the bits marked invert_ch <8:1> (individual control for each channel) causes the inputs to be swapped. INx would then
represent the positive input, and IPx the negative input.
©2009 CADEKA Microcircuits LLC
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19
PRELIMINARY Data Sheet
Table 10. LVDS Test Patterns
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
Inactive
X
0
0
X
0
0
en_ramp
Enables a repeating full-scale
ramp pattern on the outputs
dual_custom_pat Enable the mode wherein the
output toggles between two
defined codes
Inactive
Inactive
25
26
0
X
0
X
X
X
single_custom_
pat
Enables the mode wherein the
output is a constant specified code
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
bits_cus-
tom1<13:0>
Bits for the single custom pattern Inactive
and for the first code of the dual
custom pattern. <0> is the LSB
X
X
X
bits_cus-
tom2<13:0>
Bits for the second code of the
dual custom pattern
Inactive
27
45
0
X
X
0
pat_deskew
pat_sync
Enable deskew pattern mode
Enable sync pattern mode
Inactive
Inactive
To ease the LVDS synchronization setup of CDK8307, several test patterns can be set up on the outputs. Normal ADC
data are replaced by the test pattern in these modes. Setting en_ramp to '1' sets up a repeating full-scale ramp pattern
on all data outputs. The ramp starts at code zero and is increased 1LSB every clock cycle. It returns to zero code and
starts the ramp again after reaching the full-scale code.
A constant value can be set up on the outputs by setting single_custom_pat to '1', and programming the desired value
in bits_custom1<13:0>. In this mode, bits_custom1<13:0> replaces the ADC data at the output, and is controlled by
LSB-first and MSB-first modes in the same way as normal ADC data are.
The device may also be made to alternate between two codes by programming dual_custom_pat to '1'. The two codes
are the contents of bits_custom1<13:0> and bits_custom2<13:0>. Two preset patterns can also be selected:
1. Deskew pattern: Set using pat_deskew, this mode replaces the ADC output with '01010101010101' (two LSBs
removed in 12 bit mode).
2. Sync pattern: Set using pat_sync, the normal ADC word is replaced by a fixed 1111110000000 word.
Note: Only one of the above patterns should be selected at the same time.
Table 11. Programmable Gain
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
X
X
X
X
gain_ch1<3:0>
gain_ch2<3:0>
gain_ch3<3:0>
gain_ch4<3:0>
gain_ch5<3:0>
gain_ch6<3:0>
gain_ch7<3:0>
gain_ch8<3:0>
Programmable gain for channel 1 0dB gain
Programmable gain for channel 2 0dB gain
Programmable gain for channel 3 0dB gain
Programmable gain for channel 4 0dB gain
Programmable gain for channel 5 0dB gain
Programmable gain for channel 6 0dB gain
Programmable gain for channel 7 0dB gain
Programmable gain for channel 8 0dB gain
X
X
X
X
2A
2B
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CDK8307 includes a purely digital programmable gain option in addition to the Full-scale Control. The programmable
gain of each channel can be individually set using a set of four bits, indicated as gain_chn<3:0> for Channel x. The gain
setting is coded in binary from 0dB to 12dB, as shown in Table 12 on the following page.
©2009 CADEKA Microcircuits LLC
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20
PRELIMINARY Data Sheet
Table 12. Gain Setting for Channels 1-8
gain_chx<3:0>
0000
Channel x Gain Setting
0dB
1dB
0001
0010
2dB
0011
3dB
0100
4dB
0101
5dB
0110
6dB
0111
7dB
1000
8dB
1001
9dB
1010
10dB
1011
11dB
1100
12dB
1101
Do not use
Do not use
Do not use
1110
1111
Table 13. LVDS Clock Programmability and Data Output Modes
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
phase_ddr<1:0>
btc_mode
Description
Default
Controls the phase of LCLK out-
put relative to data
X
X
90 degrees
42
Binary two's complement format Straight offset
for ADC output data
X
binary
Serialized ADC output data
comes out with MSB first
LSB-first
output
X
msb_first
Enable SDR output mode. LCLK
becomes a 12x input clock
DDR output
mode
X
X
en_sdr
46
Rising edge
of LCLK
comes in the
middle of the
data window
Controls whether the LCLK ris-
ing or falling edge comes in the
middle of the data window when
operating in SDR mode
X
fall_sdr
The output interface of CDK8307 is normally a DDR interface, with the LCLK rising and falling edge transitions in the
middle of alternate data windows. The phase for LCLK can be programmed relative to the output frame clock and data
using bits phase_ddr<1:0>. The LCLK phase modes are shown in Figure 6. The default timing is identical to setting
phase_ddr<1:0> = '10'.
©2009 CADEKA Microcircuits LLC
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21
PRELIMINARY Data Sheet
PHASE_DDR<1:0>=’00’
PHASE_DDR<1:0>=’10’
FCLKN
FCLKP
LCLKP
LCLKN
FCLKN
FCLKP
LCLKN
LCLKP
Dxx<1:0>
Dxx<1:0>
PHASE_DDR<1:0>=’01’
PHASE_DDR<1:0>=’11’
FCLKN
FCLKP
LCLKN
LCLKP
FCLKN
FCLKP
LCLKP
LCLKN
Dxx<1:0>
Dxx<1:0>
Figure 6. Phase Programmability Modes for LCLK
The device can also be made to operate in SDR mode by setting the en_sdr bit to '1'. The bit clock (LCLK) is output at
12x times the input clock in this mode, two times the rate in DDR mode. Depending on the state of fall_sdr, LCLK may
be output in either of the two manners shown in Figure 7. As can be seen in Figure 7, only the LCLK rising (or falling)
edge is used to capture the output data in SDR mode. The SDR mode is not recommended beyond 40MSPS because the
LCLK frequency becomes very high.
EN_SDR=’1’, FALL_SDR_’0’
FCLKN
EN_SDR=’1’, FALL_SDR_’1’
FCLKN
FCLKP
LCLKP
LCLKN
FCLKP
LCLKN
LCLKP
Dxx<1:0>
Dxx<1:0>
Figure 7. SDR Interface Modes
The default data output format is offset binary. Two's complement mode can be selected by setting the btc_mode bit to
'1' which inverts the MSB.
The first bit of the frame (following the rising edge of FCLKP) is the LSB of the ADC output for default settings. Program-
ming the msb_first mode results in reverse bit order, and the MSB is output as the first bit following the FCLKP rising edge.
Table 14. Number of Serial Output Bits
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
X
0
lvds_num_bits
Sets the number if LVDS output bits 12-bit
53
The ADCs have 13-bit resolution. There are two options for the serial LVDS outputs, 12 bits or 14 bits, selected by reg-
ister values '00' and '10', respectively. In 12-bit mode, the LSB bit from the ADCs are removed in the output stream. In
14-bit mode, a '0' is added in the LSB position. Power down mode must be activated after or during a change in the
number of output bits.
©2009 CADEKA Microcircuits LLC
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22
PRELIMINARY Data Sheet
Table 15. Full Scale Control
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
X
X
X
X
X
X
fs_cntrl<5:0>
Fine adjust ADC full scale range 0% change
55
The full-scale voltage range of CDK8307 can be adjusted using an internal 6-bit DAC controlled by the fs_cntrl register.
Changing the value in the register by one step, adjusts the full-scale range approximately 0.3%. This leads to a maximum
range of ±10% adjustment. Table 16 shows how the register settings correspond to the full-scale range. Note that the
values for full-scale range adjustment are approximate. The DAC is, however, guaranteed to be monotonous.
The full-scale control and the programmable gain features differ in two major ways:
1. The full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable
gain is a digital feature.
2. The programmable gain feature has much coarser gain steps and larger range than the full-scale control.
Table 16. Register Values with Corresponding Change in Full-Scale Range
fs_cntrl <5:0>
111111
...
Full-Scale Range Adjustment
+9.7%
...
100001
100000
011111
...
+0.3%
+0%
-0.3%
...
000000
-10%
Table 17. Clock Frequency
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Input clock frequency
Default
65MHz
X
X
clk_freq<1:0>
56
To optimize startup time a register is provided where the input clock frequency can be set. Some internal circuitry has
startup times that are frequency independent. Default counter values are set to accommodate these startup times at
the maximum clock frequency. This will lead to increased startup times at low clock frequency. Setting the value of this
register to the nearest higher clock frequency will reduce the count values of the internal counters, to better fit the actual
startup time, such that the startup time will be reduced.
Table 18. Clock Frequency Settings
clk_freq <1:0>
Clock Frequency (MHz)
00
01
10
11
65
45
30
20
©2009 CADEKA Microcircuits LLC
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23
PRELIMINARY Data Sheet
Table 19. Performance Control
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
Nominal
X
X
X
perfm_
ADC performance control
cntrl<2:0>
50
X
X
ext_vcm_
bc<1:0>
VCM buffer driving strength
control
Nominal
There are two registers that impact performance and power dissipation.
The perfm_cntrl register adjusts the performance level of the ADC core. If full performance is required, the nominal
setting must be used. The lowest code can be used in situations where power dissipation is critical and performance is
less important. For most conditions the performance at the minimum setting will be similar to nominal setting. However,
only 10-bit performance can be expected at worst case conditions. The power dissipation savings shown in Table 20 are
only approximate numbers for the ADC current alone.
Table 20. Performance Control Settings
performance_control <2:0>
Power Dissipation
-40% (lower performance)
-30%
100
101
110
-20%
111
-10%
000 (default)
001
Nominal
Do not use
Do not use
Do not use
010
011
The ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the VCM pin. If this pin is
not in use, the buffer can be switched off. If current is drawn from the VCM pin, the driving strength can be increased
to keep the voltage on this pin at the correct level.
Table 21. External Common Mode Voltage Buffer Driving Strength
ext_vcm_bc <1:0>
VCM Buffer Driving Strength
00
01 (default)
10
Off (VCM floating)
Low
High
Max
11
©2009 CADEKA Microcircuits LLC
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24
PRELIMINARY Data Sheet
differential shunt capacitor at the chip side of the resistors
may be used to provide dynamic charging currents and
may improve performance. The resistors form a low pass
filter with the capacitor, and values must therefore be
determined by requirements for the application.
Therory of Operation
The CDK8307 is an 8-channel, high-speed, CMOS ADC.
The 13-bits given out by each channel are serialized to
12, 13 or 14-bits and sent out on a single pair of pins in
LVDS format. All eight channels of the CDK8307 operate
from a single differential or single ended clock. The sam-
pling clocks for each of the eight channels are generated
from the clock input using a carefully matched clock buf-
fer tree. The 12x/13x/14x clock required for the serializer
is generated internally from FCLK using a phase-locked
loop (PLL). A 6x/6.5x/7x and 1x clock are also output in
LVDS format, along with the data to enable easy data
capture.TheCDK8307usesinternallygeneratedreferences
that can be shorted across several devices to improve
gain-matching. The differential reference value is 1V. This
results in a differential input of -1V to correspond to the
zero code of the ADC, and a differential input of +1V to
correspond to the full-scale code (code 8191).
Figure 8. Input Configuration Diagram
DC-Coupling
Figure 9 shows a recommended configuration for DC-
coupling. Note that the common mode input voltage must
be controlled according to specified values. Preferably, the
CM_EXT output should be used as a reference to set the
common mode voltage.
The ADC employs a pipelined converter architecture.
Each stage feeds its output data into the digital error
correction logic, ensuring excellent differential linearity
and no missing codes at 13-bit level.
The CDK8307 operates from two sets of supplies and
grounds. The analog supply and ground set is identified
as AVDD and AVSS, while the digital set is identified by
DVDD and DVSS.
The input amplifier could be inside a companion chip or
it could be a dedicated amplifier. Several suitable single
ended to differential driver amplifiers exist in the market.
The system designer should make sure the specifications
of the selected amplifier is adequate for the total system,
and that driving capabilities comply with the CDK8307
input specifications.
Recommended Usage
Analog Input
The analog input to the CDK8307 is a switched capacitor
track-and-hold amplifier optimized for differential opera-
tion. Operation at common mode voltages at mid supply
is recommended even if performance will be good for the
ranges specified. The VCM pin provides a voltage suitable
as common mode voltage reference. The internal buffer
for the VCM voltage can be switched off, and driving
capabilities can be changed programming the ext_vcm_
bc<1:0> register.
Detailed configuration and usage instructions must be
found in the documentation of the selected driver, and
the values given in Figure 10 must be varied according to
the recommendations for the driver.
43Ω
33pF
43Ω
Figure 8 shows a simplified drawing of the input network.
The signal source must have sufficiently low output
impedance to charge the sampling capacitors within one
clock cycle. A small external resistor (e.g. 22Ω) in series
with each input is recommended as it helps reducing
transient currents and dampens ringing behavior. A small
Figure 9. DC-Coupled Input
©2009 CADEKA Microcircuits LLC
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25
PRELIMINARY Data Sheet
AC-Coupling
A signal transformer or series capacitors can be used
to make an AC-coupled input network. Figure 8 shows
a recommended configuration using a transformer. Make
sure that a transformer with sufficient linearity is selected,
and that the bandwidth of the transformer is appropriate.
The bandwidth should exceed the sampling rate of the
ADC with at least a factor of 10. It is also important to
keep phase mismatch between the differential ADC inputs
small for good HD2 performance. This type of transformer
coupled input is the preferred configuration for high
frequency signals as most differential amplifiers do
not have adequate performance at high frequen-
cies. Magnetic coupling between the transformers
and PCB traces may impact channel crosstalk, and
must hence be taken into account during PCB layout.
Ω
Ω
pF
Figure 11. AC-Coupled Input
Note that startup time from Sleep Mode and Power Down
Mode will be affected by this filter as the time required
to charge the series capacitors is dependent on the filter
cut-off frequency.
If the input signal has a long traveling distance, and the
kick-backs from the ADC not are effectively terminated
at the signal source, the input network of Figure 12 can
be used. The configuration is designed to attenuate the
kickback from the ADC and to provide an input impedance
that looks as resistive as possible for frequencies below
Nyquist.
33Ω
RT
47Ω
33Ω
33Ω
220Ω
33Ω
120nH
1:1
Figure 10. Transformer Coupled Input
If the input signal is traveling a long physical distance
from the signal source to the transformer (for example a
long cable), kick-backs from the ADC will also travel along
this distance. If these kick-backs are not terminated prop-
erly at the source side, they are reflected and will add to
the input signal at the ADC input. This could reduce the
ADC performance. To avoid this effect, the source must
effectively terminate the ADC kick-backs, or the traveling
distance should be very short. If this problem could not be
avoided, the circuit in Figure 10 can be used.
pF
RT
68Ω
optional
120nH
Figure 12: Alternative Input Network
Values of the series inductor will however depend on
board design and conversion rate. In some instances a
shunt capacitor in parallel with the termination resistor
(e.g. 33pF) may improve ADC performance further. This
capacitor attenuate the ADC kick-back even more, and
minimize the kicks traveling towards the source. However,
the impedance match seen into the transformer becomes
worse.
Figure 11 shows AC-coupling using capacitors. Resistors
from the CM_EXT output, RCM, should be used to bias the
differential input signals to the correct voltage. The series
capacitor, CI, form the high-pass pole with these resistors,
and the values must therefore be determined based on
the requirement to the high-pass cut-off frequency.
©2009 CADEKA Microcircuits LLC
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26
PRELIMINARY Data Sheet
For applications where jitter may limit the obtainable per-
formance, it is of utmost importance to limit the clock
jitter. This can be obtained by using precise and stable
clock references (e.g. crystal oscillators with good jitter
specifications) and make sure the clock distribution is well
controlled. It might be advantageous to use analog power
and ground planes to ensure low noise on the supplies
to all circuitry in the clock distribution. It is of utmost im-
portance to avoid crosstalk between the ADC output bits
and the clock and between the analog input signal and
the clock since such crosstalk often results in harmonic
distortion.
Clock Input and Jitter Considerations
Typicallyhigh-speedADCsusebothclockedgestogenerate
internal timing signals. In the CDK8307 only the rising
edge of the clock is used. Hence, input clock duty cycles
between 20% and 80% is acceptable.
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally, and hence a wide
common mode voltage range is accepted. Differential
clock sources as LVDS, LVPECL or differential sine wave
can be connected directly to the input pins. For CMOS
inputs, the CLKN pin should be connected to ground, and
the CMOS clock signal should be connected to CLKP. For
differential sine wave clock input the amplitude must be
The jitter performance is improved with reduced rise and
fall times of the input clock. Hence, optimum jitter per-
formance is obtained with LVDS or LVPECL clock with fast
edges. CMOS and sine wave clock inputs will result in
slightly degraded jitter performance.
at least ±0.8V .
pp
The quality of the input clock is extremely important for
high-speed, high-resolution ADCs. The contribution to
SNR from clock jitter with a full scale signal at a given
frequency is shown in equation below.
If the clock is generated by other circuitry, it should be re-
timed with a low jitter master clock as the last operation
before it is applied to the ADC clock input.
•
•
•
•
SNR
= 20 log (2 π F εt)
jitter
IN
where F is the signal frequency, and εt is the total rms
IN
jitter measured in seconds. The rms jitter is the total of all
jitter sources including the clock generation circuitry, clock
distribution and internal ADC circuitry.
©2009 CADEKA Microcircuits LLC
www.cadeka.com
27
PRELIMINARY Data Sheet
Mechanical Dimensions
QFN-64
Inches
Typ
Millimeters
Typ
aaa
C
A
ccc C
Symbol
Min
Max
Min
Max
A
D
A
A
–
0.00
–
–
0.035
0.002
0.028
–
0.00
–
–
0.01
0.65
0.2 REF
0.25
9.00 BSC
8.75 BSC
5.2
9.00 BSC
8.75 BSC
5.2
0.9
0.05
0.7
A2
A3
A
A
A
0.0004
0.026
1
2
3
D1
0.008 REF
0.010
0.354 BSC
0.354 BSC
0.205
0.354 BSC
0.344 BSC
0.205
b
D
0.008
0.197
0.197
0.012
0.213
0.213
0.2
5.0
5.0
0.30
5.4
aaa
C B
A1
D
1
D
2
E
E
1
E
2
5.4
F
G
L
0.05
0.0096
0.012
–
0.0168
0.016
0.020 BSC
–
–
1.3
0.24
0.3
–
0.42
0.4
0.50 BSC
–
–
0.6
0.5
0.024
0.020
e
θ
0°
12°
0°
12°
1
E
E1
Tolerance of Form and Position
aaa
bbb
ccc
0.10
0.10
0.05
0.004
0.004
0.002
Pin 1 ID
0.05 Dia.
NOTES:
1. All dimensions are in millimeters.
2. Die thickness allowable is 0.305mm maximum (.012 inches maximum)
3. Dimensioning & tolerances conform to ASME y14.5m. -1994.
4. Dimension applies to plated terminal and is measured between 0.20 and 0.25mm from terminal tip.
5. The pin #1 identifier must be placed on the top surface of the package by using indentation mark
or other feature of package body.
seating
plane
θ1
1.14
bbb C
B
6. Exact shape and size of this feature is optional.
C
7. Package warpage max 0.08mm.
B
bbb C A
1.14
8. Applied for exposed pad and terminals. Exclude embedding part of exposed pad from measuring.
9. Applied only to terminals.
TOP VIEW
SIDE VIEW
10. Package corners unless otherwise specipied are r0.175±0.025mm.
F
D2
Pin 1 ID
Dia. 0.20
0.45
G
E2
L
e
b
L
0.10 M
C A B
BOTTOM VIEW
©2009 CADEKA Microcircuits LLC
www.cadeka.com
28
PRELIMINARY Data Sheet
Mechanical Dimensions (Continued)
TQFP-80
TQFP-80
Symbol
A
Dimensions (mm)
1.20
A
1
A
2
0.10 ±0.05
1.00 ±0.05
A
3
0.25
b
0.22 ±0.05
0.145 +0.055
0.145 -0.045
c
D
E
12.00 ±0.20
12.00 ±0.20
e
0.50
HD
HE
L
14.00 ±0.20
14.00 ±0.20
0.50
Lp
0.60 ±0.15
1.00 ±0.20
0.08
L
1
x
y
0.08
ZD
ZE
1.25
1.25
3° +5°
3° -3°
θ
NOTE:
Each lead centerline is located within 0.08mm of
its true position at maximum material condition.
Detail of Lead End
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
Amplify the Human Experience
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
designed by
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved.
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