CDK3405 [CADEKA]
8-bit, 180MSPS, Triple Video DACs; 8位， 180MSPS ，三路视频数模转换器
| 型号： | CDK3405 |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | 8-bit, 180MSPS, Triple Video DACs |
| 文件： | 总11页 (文件大小：1297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
CDK3405
8-bit, 180MSPS, Triple Video DACs
F E A T U R E S
General Description
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8-bit resolution, 180MSPS
CDK3405 is a low-cost triple D/A converter that is tailored to fit graphics and
video applications where speed is critical.
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±2.5% gain matching
±0.5% linearity error
CMOS-level inputs are converted to analog current outputs that can drive
25-37.5Ω loads corresponding to doubly-terminated 50-75Ω loads. A sync
current following SYNC input timing is added to the IO output. BLANK
will override RGB inputs, setting IO , IO and IO currents to zero when
BLANK = L. Although appropriate for many applications, the internal 1.25V
reference voltage can be overridden by the V input.
Sync and blank controls
1.0Vpp video into 37.5Ω or 75Ω load
Internal bandgap voltage reference
Low glitch energy
G
G
B
R
Single +3.3V power supply
REF
Few external components are required, just the current reference resistor,
current output load resistors, bypass capacitors, and decoupling capacitors.
A P P L I C A T I O N S
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Video signal conversion
– RGB
Package is a 48-lead TQFP. Fabrication technology is CMOS. Performance is
guaranteed from -40°C to +125°C.
– YCBCR
– Composite, Y, C
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Multimedia systems
Block Diagram
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Image processing
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PC Graphics
SYNC
SYNC
BLANK
8
8
8
8-bit D/A
Converter
IO
IO
IO
G7-0
B7-0
G
B
R
8-bit D/A
Converter
8-bit D/A
Converter
R7-0
CLOCK
COMP
R
V
REF
REF
+1.25V
Ref
Ordering Information
Part Number
Package
Pb-Free
Yes
RoHS Compliant Operating Temp Range Packaging Method Package Quantity
CDK3405ATQ48
CDK3405ATQ48Y
TQFP-48
TQFP-48
Yes
Yes
-40°C to +125°C
-40°C to +125°C
Tray
Tray
250
Yes
1,250
Moisture sensitivity level for all parts is MSL-3.
©2009-2010 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
Pin Configuration
TQFP-48
1
2
3
4
5
6
7
8
36
35
34
33
32
31
30
29
28
27
26
25
GND
GND
G0
G1
G2
G3
G4
G5
G6
V
REF
COMP
IO
R
NC
IO
TQFP
CDK3405
G
NC
V
V
AA
AA
9
IO
B
G7
BLANK
SYNC
10
11
12
NC
GND
GND
Pin Assignments
Pin No.
Pin Name
Description
Clock and Pixel I/O
24
Clock Input
CLK
R7-0
G7-0
B7-0
41-48
Red Pixel Data Inputs
Green Pixel Data Inputs
Blue Pixel Data Inputs
3-10
16-23
Controls
12
Sync Pulse Input
Blanking Input
SYNC
11
BLANK
Video Outputs
34
32
28
IOR
IOG
IOB
Red Current Output
Green Current Output
Blue Current Output
Voltage Reference
36
37
35
V
Input for DACs or Voltage Reference Output (1.25V)
REF
R
Current-Setting Resistor
Compensation Capacitor
SET
COMP
Power and Ground
13, 29, 30
V
AA
Analog Power Supply
1, 2, 14,
15, 25, 26,
39, 40
GND
NC
Ground
27, 31, 33
No Connect
©2009-2010 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper
device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect
the operating conditions noted on the tables and plots.
Parameter
Min
Max
4.0
Unit
V
Power Supply Voltage
V
AA
(Measured to GND)
-0.5
Digital Inputs
Applied Voltage (measured to GND)(2)
Forced Current(3,4)
-0.5
-5.0
V
V
V
+ 0.5
V
AA
5.0
mA
Analog Inputs
Applied Voltage (measured to GND)(2)
Forced Current(3,4)
-0.5
+ 0.5
V
AA
-10.0
10.0
mA
Analog Outputs
Applied Voltage (measured to GND)(2)
Forced Current(3,4)
-0.5
+ 0.5
V
AA
-60.0
60.0
mA
sec
Short Circuit Duration (single output in HIGH state to GND)
unlimited
Reliability Information
Parameter
Min
-40
Max
Unit
Temperature
Operating, Ambient
Junction
125
150
300
220
150
°C
°C
Lead Soldering (10 seconds)
Vapor Phase Soldering (1 minute)
Storage
°C
°C
-65
°C
Package Thermal Resistance (θ )
65
°C/W
JA
Notes:
1. Functional operation under any of these conditions is NOT implied.
Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
CDK3405 Power Derating
3
2.5
2
4. Current is specified as conventional current flowing into the device.
TQFP-48
1.5
1
ESD Protection
Parameter
TQFP-48
TBD
0.5
0
Human Body Model (HBM)
Charged Device Model (CDM)
TBD
-40 -20
0
20 40 60 80 100 120
Ambient Temperature (°C)
Recommended Operating Conditions
Symbol
VAA
Parameter
Min
Typ
Max
Unit
Power Supply Voltage
Reference Voltage, External
Compensation Capacitor
Output Load
3.0
1.0
3.3
1.25
0.1
3.6
1.5
V
V
VREF
CC
µF
Ω
RL
37.5
TA
Ambient Temperature, Still Air
-40
+125
°C
©2009-2010 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Electrical Characteristics
(T = 25°C, V =3.3V, V
= 1.25V, R = 37.5Ω, unless otherwise noted)
A
AA
REF
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TA = 25°C (1)
TA = -40°C to +125°C (2)
80
85
95
mA
mA
IDD
Power Supply Current
PD
Total Power Dissipation(2)
TA = -40°C to +125°C
300
mW
Digital Inputs
VIH
Input Voltage, HIGH (1)
Input Voltage, LOW (1)
Input Current, HIGH (1)
Input Current, LOW (1)
Input Capacitance
TA = -40°C to +125°C
TA = -40°C to +125°C
TA = -40°C to +125°C
TA = -40°C to +125°C
2.5
V
VIL
0.8
1
V
IIH
-1
-1
μA
μA
pF
IIL
1
CI
4
Analog Outputs
Output Current (1)
Output Resistance
Output Capacitance
30
mA
kΩ
pF
RO
CO
40
7
Reference Output
VREF
Reference Voltage Output (1)
TA = -40°C to +125°C
1.135
1.25
1.365
V
Notes:
1. 100% tested at 25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
Switching Characteristics
(T = 25°C, V =3.3V, V
= 1.25V, R = 37.5Ω, unless otherwise noted)
A
AA
REF
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Clock Input
Conversion Rate (1)
Pulse-width HIGH (2)
Pulse-width LOW (2)
TA = -40°C to +125°C
TA = -40°C to +125°C
TA = -40°C to +125°C
180
MSPS
ns
tPWH
2
2
tPWL
ns
Data Inputs
TA = 25°C (1)
TA = -40°C to +125°C (2)
TA = 25°C (1)
1.5
2
ns
ns
ns
ns
tS
Setup
Hold
0.6
0.6
tH
TA = -40°C to +125°C (2)
Data Outputs, with 50Ω doubly terminated load
tD
Clock to Output Delay
Output Risetime
Output Falltime
Settling Time
TA = -40°C to +125°C
TA = -40°C to +125°C
TA = -40°C to +125°C
1.6
0.6
0.4
2.5
0.3
ns
ns
ns
ns
ns
tR
tF
tSET
tSKEW
Output Skew
Notes:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
©2009-2010 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
DC Performance
(T = 25°C, V =3.3V, V
= 1.25V, R = 37.5Ω, unless otherwise noted)
A
AA
REF
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Resolution
8
bits
LSB
LSB
LSB
LSB
%FS
%FS
%FS
mA
TA = 25°C (1)
TA = -40°C to +125°C (2)
TA = 25°C (1)
TA = -40°C to +125°C (2)
TA = -40°C to +125°C (2)
TA = -40°C to +125°C (1)
TA = -40°C to +125°C (1)
TA = 25°C (1)
-0.5
-0.5
-0.5
-0.5
0.5
0.5
INL
Integral Linearity Error
0.5
DNL
Differential Linearity Error
0.5
Offset Error
0.01
2.5
Gain Matching Error
Absolute Gain Error
-2.5
-3.5
18.0
18.0
3.5
18.7
18.7
19.4
19.4
TA = -40°C to +125°C (2)
mA
Full-Scale Output Current
TA = -40°C to +125°C , With internal
reference. Trim RSET to calibrate full-scale
current.
18.7
0
mA
PSRR
Power Supply Rejection Ratio
TA = -40°C to +125°C (2)
-0.01
0.01
%/%
Notes:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
AC Performance
(T = 25°C, V = 3.3V, V
= 1.25V, R = 37.5Ω, unless otherwise noted)
A
AA
REF
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Analog Outputs
Glitch Energy
20
30
50
60
pVsec
dB
DAC-to-DAC Crosstalk
Data Feedthrough
Clock Feedthrough
dB
dB
Notes:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
©2009-2010 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
Table 1. Output Voltage vs. Input Code, SYNC and BLANK, V
= 1.25V, R
= 348Ω, R = 37.5Ω
REF L
REF
BLUE AND RED
GREEN
RGB7-0 (MSB…LSB)
SYNC
BLANK
VOUT (V)
0.700
0.700
0.697
0.695
•
SYNC
BLANK
VOUT (V)
1.007
0.700
1.004
1.001
•
1111 1111
1111 1111
1111 1110
1111 1101
•
1
0
1
1
•
1
1
1
1
•
1
0
1
1
•
1
1
1
1
•
•
•
•
•
•
•
•
1000 0000
0111 1111
0111 1111
•
1
1
0
•
1
1
1
•
0.351
0.349
0.349
•
1
1
0
•
1
1
1
•
0.658
0.656
0.349
•
•
•
•
•
•
•
•
0000 0010
0000 0001
0000 0000
0000 0000
XXXX XXXX
XXXX XXXX
1
1
1
0
1
0
1
1
1
1
0
0
0.005
0.003
0.000
0.000
0.000
0.000
1
1
1
0
1
0
1
1
1
1
0
0
0.312
0.310
0.307
0.000
0.307
0.000
1/f
s
t
t
PWL
PWH
CLK
t
t
H
s
Pixel Data
and Controls
Data N
Data N+1
Data N+2
3%/FS
90%
10%
t
D
t
SET
t
t
F
R
OUTPUT
50%
Figure 1. CDK3405 Timing Diagram
©2009-2010 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
BLANK gates the D/A inputs. If BLANK = HIGH, the D/A
inputs control the output currents to be added to the out-
put blanking level. If BLANK = Low, data inputs and the
pedestal are disabled.
Functional Description
WithintheCDK3405arethreeidentical8-bitD/A converters,
each with a current source output. External loads are
required to convert the current to voltage outputs. Data
inputs RGB7-0 are overridden by the BLANK input. SYNC
= H activates, sync current from I for sync-on-green
OS
video signals.
Data: 660mV max.
V
AA
IOS
V
AA
SYNC
G7-0
Pedestal: 54mV
Sync: 286mV
Figure 3. Normal Output Levels
V
AA
Sync Pulse Input - SYNC
B7-0
R7-0
Bringing SYNC LOW, disables a current source which su-
perimposes a sync pulse on the IO output. SYNC and
G
V
AA
pixel data are registered on the rising edge of CLK. SYNC
does not override any other data and should be used only
during the blanking interval. If sync pulses are not re-
quired, SYNC should be connected to GND.
Blanking Input - BLANK
Figure 2. CDK3405 Current Source Structure
When BLANK is LOW, pixel data inputs are ignored and
the D/A converter outputs are driven to the blanking level.
BLANK is registered on the rising edge of CLK.
Digital Inputs
Incoming GBR data is regsitered on the rising edge of the
clock input, CLK. Analog outputs follow the rising edge of
CLK after a delay, t
.
D/A Outputs
DO
Each D/A output is a current source from the V
supply.
DDA
Clock Input - CLK
Expressed in current units, the GBR transformation from
data to current is as follows:
Pixel data is registered on the rising edge of CLK. CLK
should be driven by a dedicated buffer to avoid reflection
induced jitter, overshoot, and undershoot.
G = G7-0 & BLANK + SYNC * 112
B = B7-0 & BLANK
Pixel Data Inputs - R7-0, B7-0, G7-0
R = R7-0 & BLANK
RGB digital inputs are registered on the rising edge of CLK.
Typical LSB current step is 73.2μA. To obtain a voltage
output, a resistor must be connected to ground. Output
voltage depends upon this external resistor, the reference
voltage, and the value of the gain-setting resistor con-
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure
3 and Table 1, on the previous page) of the D/A convert-
ers during CRT retrace intervals. BLANK forces the D/A
outputs to the blanking level while SYNC = L turns off a
nected between R
and GND.
REF
To implement a doubly-terminated 75Ω transmission line,
a shunt 75Ω resistor should be placed adjacent to the
analog output pin. With a terminated 75Ω line connected
to the analog output, the load on the CDK3405 current
source is 37.5Ω.
current source, I , that is connected to the green D/A
OS
converter. SYNC = H adds a 112/256 fraction of full-scale
current to the green output. SYNC = L extinguishes the
sync current during the sync tip.
©2009-2010 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
The CDK3405 may also be operated with a single 75Ω
terminating resistor. To lower the output voltage swing
to the desired range, the nominal value of the resistor on
and GND. Voltage across R
is the reference voltage,
SET
V
which can be derived from either the 1.25 volt in-
REF,
ternal bandgap reference or an external voltage reference
connected to V . To minimize noise, a 0.1μF capacitor
R
should be doubled.
REF
REF
should be connected between V
and ground. I
is
SET
REF
R, G, and B Current Outputs - IO , IO , IO
B
R
G
mirrored to each of the GBR output current sources. To
minimize noise, a 0.1μF capacitor should be connected
Current source outputs can drive VESA VSIS, and RS-
343A/SMPTE-170M compatible levels into doubly-termi-
nated 75Ω lines. Sync pulses can be added to the green
between the COMP pin and the analog supply voltage V .
AA
output. When SYNC is HIGH, the current added to IO is:
G
Voltage Reference Output/Input - V
REF
IO = 2.33 (V / R )
REF
S
REF
An internal voltage source of +1.25V is output on the V
REF
pin. An external +1.25V reference may be applied to over-
Current-Setting Resistor - R
REF
ride the internal reference. Decoupling V
a 0.1µF ceramic capacitor is required.
to GND with
REF
Full-scale output current of each D/A converter is deter-
mined by the value of the resistor connected between
Power and Ground
R
and GND. Nominal value of R
is found from:
REF
REF
Required power is a single +3.3V supply. To minimize power
supply induced noise, analog +3.3V should be connected
to all three supply pins with 0.1µF and 0.01µF decoupling
R
= 5.31 (V /I )
REF
REF FS
where I is the full-scale (white) output current (in amps)
from the D/A converter (without sync). Sync is 0.439 * I .
FS
FS
capacitors placed adjacent to each V pin or pin pair.
AA
D/A full-scale (white) current may also be calculated from:
The high slew-rate of digital data makes capacitive cou-
pling to the outputs of any D/A converter a potential
problem. Since the digital signals contain high-frequency
components of the CLK signal, as well as the video out-
put signal, the resulting data feedthrough often looks
like harmonic distortion or reduced signal-to-noise perfor-
mance. All ground pins should be connected to a common
solid ground plane for best performance.
I
= V /R
FS L
FS
Where V is the white voltage level and R is the total
FS
L
resistive load (Ω) on each D/A converter. V is the blank
FS
to full-scale voltage.
Voltage Reference
Full scale current is a multiple of the current I
through
SET
an external resistor, R
connected between the R
pin
REF
SET
©2009-2010 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
4. If the digital power supply has a dedicated power plane
layer, it should not be placed under the CDK3405,
the voltage reference, or the analog outputs. Capacitive
coupling of digital power supply noise from this layer
to the CDK3405 and its related analog circuitry can
have an adverse effect on performance.
Applications Dicussion
Figure 9 (on the following page) illustrates a typical CDK3405
interface circuit. In this example, an optional 1.2V band-
gap reference is connected to the V
output, overriding
REF
the internal voltage reference source.
Grounding
5. CLK should be handled carefully. Jitter and noise on this
clock will degrade performance. Terminate the clock line
carefully to eliminate overshoot and ringing.
It is important that the CDK3405 power supply is well-
regulated and free of high-frequency noise. Careful power
supply decoupling will ensure the highest quality video
signals at the output of the circuit. The CDK3405 has
separate analog and digital circuits. To keep digital system
noise fromtheD/Aconverter, itisrecommendedthatpower
supply voltages come from the system analog power
source and all ground connections (GND) be made to the
analog ground plane. Power supply pins should be indi-
vidually decoupled at the pin.
Improved Transisiton Times
Output shunt capacitance dominates slowing of output
transition times, whereas series inductance causes a small
amount of ringing that affects overshoot and settling time.
With a doubly terminated 75Ω load, transition times can
be improved by matching the capacitive impedance output
of the CDK3405. Output capacitance can be matched with
a 220nH inductor in series with the 75Ω source termination.
Printed Circuit Board Layout
W1
COAX
32
IO
G
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall
system performance is strongly influenced by the board
layout. Capacitive coupling from digital to analog circuits
may result in poor D/A conversion. Consider the following
suggestions when doing the layout:
R1
75Ω
U1
CDK3405
W2
COAX
29
33
IO
B
R2
75Ω
1. Keep the critical analog traces (V , I , COMP, IO ,
REF REF
S
W3
COAX
IO , IO ) as short as possible and as far as possible
R
G
IO
R
from all digital signals. The CDK3405 should be
located near the board edge, close to the analog out-put
connectors.
R3
75Ω
L1
220nH
L2
220nH
L3
220nH
R4
75Ω
R5
75Ω
R6
75Ω
2. The power plane for the CDK3405 should be separate
from that which supplies the digital circuitry. A single
power plane should be used for all of the V pins. If
AA
Figure 4. Schematic, Transition Time Sharpening Circuit
the power supply for the CDK3405 is the same
as that of the system’s digital circuitry, power to the
CDK3405 should be decoupled with 0.1µF and
0.01µF capacitors and isolated with a ferrite bead.
A 220nH inductor trims the performance of a 4ft cable,
quite well. In Figures 5 through 8, the glitch at 12.5ns, is
due to a reflection from the source. Not shown, are smaller
glitches at 25 and 37.5ns, corresponding to secondary and
3. The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short tertiary reflections. Inductor values should be selected to
leads.
match the length and type of the cable.
©2009-2010 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.1
-5
0
5
10
15
20
-5
0
5
10
15
20
Time (ns)
Time (ns)
Figure 5. Unmatched t
Figure 7. Unmatched t
F
R
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.1
-5
0
5
10
15
20
-5
0
5
10
15
20
Time (ns)
Time (ns)
Figure 8. Matched t
Figure 6. Matched t
F
R
+3.3V
10µF
0.1µF
0.01µF
0.1µF
Red
o
GND
75Ω
75Ω
75Ω
V
V
AA
AA
Z
= 75Ω
IOR
IOG
IOB
RED PIXEL
INPUT
(13)
(29, 30)
R7-0
G7-0
B7-0
Green w/Sync
75Ω
75Ω
75Ω
Z
= 75Ω
o
Blue
GREEN PIXEL
INPUT
Z
= 75Ω
o
CDK3405
Triple 8-bit D/A Converter
BLUE PIXEL
INPUT
V
AA
COMP
CLOCK
SYNC
BLANK
CLK
SYNC
BLANK
3.3kΩ
(not required without external reference)
0.1µF
VREF
RREF
0.1µF
LM185-1.2
(Optional)
348Ω
Figure 9. Typical Interface Circuit Diagram
Evaluation boards are available (CEB3405), contact CADEKA for more information.
Related Products
n
ꢀ
CDK3400/3401 Triple 10-bit 180MSPS DACs
CDK3404 Triple 8-bit 180MSPS DAC
n
ꢀ
©2009-2010 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
Mechanical Dimensions
TQFP-48 Package
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相关型号：
CDK3405CTQ48
D/A Converter, 1 Func, Parallel, 8 Bits Input Loading, 0.0025us Settling Time, PQFP48, TQFP-48
EXAR
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