BS62UV1027SC [BSI]
Ultra Low Power/Voltage CMOS SRAM 128K X 8 bit; 超低功率/电压CMOS SRAM 128K ×8位
| 型号： | BS62UV1027SC |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Ultra Low Power/Voltage CMOS SRAM 128K X 8 bit |
| 文件： | 总10页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power/Voltage CMOS SRAM
128K X 8 bit
BSI
BS62UV1027
• Data retention supply voltage as low as 1.2V
FEATURES
• Wide Vcc operation voltage :
C-grade : 1.8V ~ 3.6V
I-grade : 1.9V ~ 3.6V
(Vcc_min.=1.65V at 25oC)
• Ultra low power consumption :
• Easy expansion with CE2, CE1 and OE options
DESCRIPTION
The BS62UV1027 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.05uA at 2.0V/25oC and maximum access time of 85ns at 85oC.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
Vcc = 2.0V C-grade : 7mA (Max.) operating current
I -grade : 8mA (Max.) operating current
0.05uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade : 13mA (Max.) operating current
I- grade : 15mA (Max.) operating current
0.10uA (Typ.) CMOS standby current
• High speed access time :
The BS62UV1027 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
-85
-10
85ns (Max.)
100ns (Max.)
The BS62UV1027 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP, 8mmx13.4
mm STSOP and 8mmx20mm TSOP.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
(ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
PKG TYPE
(ICCSB1, Max)
C-grade:1.8~3.6V
I-grade:1.9~3.6V
Vcc=
3.0V
Vcc=
2.0V
Vcc=
3.0V
Vcc=
2.0V
-32
SOP
TSOP
BS62UV1027SC
BS62UV1027TC
BS62UV1027JC
BS62UV1027STC
BS62UV1027PC
BS62UV1027DC
BS62UV1027SI
BS62UV1027TI
BS62UV1027JI
BS62UV1027STI
BS62UV1027PI
BS62UV1027DI
-32
-32
STSOP 32
+0 O C to +70 O
C
C
1.8V ~ 3.6V
1.9V ~ 3.6V
1.3uA
0.5uA
1.0uA
13mA
7mA
8mA
SOJ
85/100
85/100
-
-32
PDIP
DICE
SOP
-32
-32
TSOP
-
SOJ 32
STSOP
-40 O C to +85 O
2.5uA
15mA
-32
32
PDIP-
DICE
BLOCK DIAGRAM
PIN CONFIGURATIONS
NC
A16
A14
A12
A7
1
VCC
A15
CE2
WE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
A6
A7
A12
A14
A16
A15
A13
A8
3
4
5
A13
A8
Address
Memory Array
1027 x 1027
20
1027
A6
6
BS62UV1027SC
BS62UV1027SI
BS62UV1027PC
BS62UV1027PI
BS62UV1027JC
BS62UV1027JI
Row
Decoder
Input
A5
7
A9
A4
8
A11
OE
Buffer
A3
9
A2
10
11
12
13
14
15
16
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A9
A11
A1
A0
DQ0
DQ1
DQ2
GND
1027
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
8
8
Data
Output
Buffer
128
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
Column Decoder
14
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
CE2
CE1
WE
BS62UV1027TC
Control
BS62UV1027STC
BS62UV1027TI
BS62UV1027STI
Address Input Buffer
9
OE
Vdd
Gnd
10
11
12
13
14
15
16
A5 A4 A3 A2 A1 A0 A10
A6
A5
A4
A1
A2
A3
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 2.1
Jan. 2004
R0201-BS62UV1027
1
BSI
BS62UV1027
PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
WE
X
CE1
H
CE2
X
OE
X
I/O OPERATION
Vcc CURRENT
Not selected
(Power Down)
High Z
I
CCSB, ICCSB1
X
X
L
X
Output Disabled
Read
H
L
H
H
L
High Z
DOUT
DIN
ICC
ICC
ICC
H
L
H
Write
L
L
H
X
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
TEMPERATURE
0 O C to +70 O
SYMBOL
PARAMETER
Terminal Voltage with
Respect to GND
RATING
-0.5 to
Vcc+0.5
UNITS
RANGE
Vcc
V
TERM
BIAS
STG
T
V
T
T
P
Commercial
Industrial
C
1.8V ~ 3.6V
1.9V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +85
-60 to +150
1.0
O C
O C
W
-40 O C to +85O
C
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
IN
IN
C
V
=0V
6
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
8
pF
1. This parameter is guaranteed and not 100% tested.
Revision 2.1
Jan. 2004
R0201-BS62UV1027
2
BSI
BS62UV1027
DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
PARAMETER
MIN. TYP. (1) MAX.
UNITS
PARAMETER
TEST CONDITIONS
NAME
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Guaranteed Input Low
Voltage(2)
0.6
0.8
-0.3(5)
--
V
IL
V
1.4
2.0
Guaranteed Input High
Voltage(2)
VIH
IIL
--
--
--
Vcc+0.3
V
IN
Input Leakage Current
Output Leakage Current
Vcc = Max, V = 0V to Vcc
--
1
1
uA
uA
IH
IL,
Vcc = Max, CE1= V , CE2= V or
OE = VIH, VI/O = 0V to Vcc
ILO
--
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc = Max, IOL = 0.1mA
Vcc = Max, IOL = 2.0mA
Vcc = Min, IOH = -0.1mA
0.2
0.4
VOL
VOH
ICC
Output Low Voltage
Output High Voltage
--
--
--
V
V
Vcc-0.2
2.4
--
--
OH
Vcc = Min, I = -1.0mA
--
--
8
IL
IH
Operating Power Supply CE1 = V , CE2 = V ,
mA
mA
uA
Current
I
DQ = 0mA, F = Fmax(3)
--
15
--
--
0.1
0.5
1.0
2.5
CE1 = VIH, or CE2 = VIL
,
ICCSB
Standby Current-TTL
DQ
I
= 0mA
--
--
CE1≧Vcc-0.2V or CE2≦0.2V,
IN≧Vcc-0.2V or VIN≦0.2V
--
0.05
0.10
(4)
ICCSB1
Standby Current-CMOS
V
--
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
4. IccSB1(Max.) is 0.5uA/1.3uA at Vcc=2.0V/3.0V and TA=70oC.
5. VIL = -1.5V for pulse width less than 30ns
DATA RETENTION CHARACTERISTICS ( TA = -40oC to + 85oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
VDR
Vcc for Data Retention
1.2
--
--
V
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
(3)
ICCDR
Data Retention Current
--
0
0.03
0.3
uA
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
TRC
1. Vcc = 1.2V, TA = + 25OC
2. tRC = Read Cycle Time
3. IccDR(Max.) is 0.2uA at TA=70OC.
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
DR ≥ 1.2V
V
Vcc
Vcc
Vcc
CE1
t
R
t
CDR
≥
CE1 Vcc - 0.2V
VIH
VIH
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
VDR ≧ 1.2V
Vcc
Vcc
Vcc
t
R
t
CDR
CE2 ≦ 0.2V
VIL
VIL
CE2
Revision 2.1
R0201-BS62UV1027
3
Jan.
2004
BSI
BS62UV1027
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
JEDEC
PARAMETER
CYCLE TIME : 85ns
CYCLE TIME : 100ns
PARAMETER
(Vcc = 1.9~3.6V)
(Vcc = 1.9~3.6V)
DESCRIPTION
Read Cycle Time
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
NAME
t
t
85
--
--
--
--
--
--
--
--
--
--
--
--
--
85
85
85
40
--
100
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
100
50
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAX
RC
t
t
Address Access Time
AVQV
AA
t
t
Chip Select Access Time
--
--
(CE1)
(CE2)
E1LQV
ACS1
t
t
Chip Select Access Time
--
--
E2HOV
ACS2
t
t
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
--
GLQV
OE
t
t
15
15
15
--
15
15
15
--
(CE1)
(CE2)
E1LQX
CLZ1
t
t
--
--
E2HOX
CLZ2
t
t
--
--
GLQX
OLZ
t
t
(CE1)
(CE2)
35
35
30
40
40
35
E1HQZ
CHZ1
t
t
--
--
E2HQZ
CHZ2
t
t
--
--
GHQZ
OHZ
t
t
Data Hold from Address Change
AXOX
OH
15
--
--
15
--
--
ns
Revision 2.1
Jan. 2004
R0201-BS62UV1027
4
BSI
BS62UV1027
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE1
t
t
ACS1
ACS2
CE2
(5)
CHZ2
t
CHZ1,
t
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
t
OLZ
CE1
(5)
t
ACS1
t
t
OHZ
(1,5)
(5)
t
t
CLZ1
CHZ1
CE2
t
ACS2
(2,5)
CHZ2
t
(5)
CLZ2
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL
5. The parameter is guaranteed but not 100% tested.
.
Revision 2.1
Jan. 2004
R0201-BS62UV1027
5
BSI
BS62UV1027
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 85ns
(Vcc = 1.9~3.6V)
CYCLE TIME : 100ns
PARAMETER
(Vcc = 1.9~3.6V)
DESCRIPTION
Write Cycle Time
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tE2LAX
tWLQZ
tDVWH
tWHDX
tGHQZ
85
85
0
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tCW
tAS
Chip Select to End of Write
Address Setup Time
--
--
Address Valid to End of Write
Write Pulse Width
85
40
0
--
100
50
0
--
tAW
tWP
tWR1
tWR2
tWHZ
tDW
tDH
--
--
Write recovery Time
--
--
(CE1,WE)
(CE2)
Write recovery Time
0
--
0
--
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
--
35
--
--
40
--
35
0
40
0
--
--
--
35
--
40
tOHZ
tWHOX
tOW
End of Write to Output Active
10
--
--
10
--
--
ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR1
t
(11)
t
CW
(5)
CE1
(5)
(11)
(2)
CE2
t
t
CW
WP
t
WR2
t
AW
(3)
t
AS
WE
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 2.1
Jan. 2004
R0201-BS62UV1027
6
BSI
BS62UV1027
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
CW
t
(5)
(5)
CE1
(11)
CW
CE2
t
t
WR2
t
AW
(3)
t
WP
(2)
WE
t
AS
(4,10)
t
t
OW
(7)
(8)
t
WHZ
D OUT
t
DW
(8,9)
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
Revision 2.1
R0201-BS62UV1027
7
Jan.
2004
BSI
BS62UV1027
ORDERING INFORMATION
BS62UV1027 X X Z Y Y
SPEED
85: 85ns
10: 100ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
J: SOJ
S: SOP
P: PDIP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
D: DICE
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
b
WITH PLATING
c
c1
BASE METAL
b1
SECTION A-A
SOP -32
Revision 2.1
Jan. 2004
R0201-BS62UV1027
8
BSI
BS62UV1027
PACKAGE DIMENSIONS (continued)
STSOP - 32
TSOP - 32
Revision 2.1
R0201-BS62UV1027
9
Jan.
2004
BSI
BS62UV1027
PACKAGE DIMENSIONS (continued)
SOJ - 32
PDIP - 32
Revision 2.1
R0201-BS62UV1027
10
Jan.
2004
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