BS62LV8005 [BSI]
Very Low Power/Voltage CMOS SRAM 1M X 8 bit; 非常低的功率/电压CMOS SRAM 1M ×8位
| 型号： | BS62LV8005 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power/Voltage CMOS SRAM 1M X 8 bit |
| 文件： | 总10页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
1M X 8 bit
BSI
BS62LV8005
GENERAL DESCRIPTION
FEATURES
• Wide Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
The BS62LV8005 is a high performance, very low power CMOS
Static Random Access Memory organized as 1,048,576 words by 8 bits
and operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
3uA and maximum access time of 55ns in 5V operation.
Vcc = 5V C-grade: 45mA (Max.) operation current
I -grade: 50mA (Max.) operating current
3uA (Typ.) CMOS standby current
• High speed access time :
-55
-70
55ns (Max) at Vcc = 5V
70ns (Max) at Vcc = 5V
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable(CE2) and active LOW output
enable (OE) and three-state output drivers.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS62LV8005 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
The BS62LV8005 is available in 44 pin TSOP2 and 48-pin BGA type.
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
(SI TAN,DMBaYx )
Operating
PRODUCT
FAMILY
OPERATING
Vcc
( I , Max )
CC
CCSB1
PKG TYPE
TEMPERATURE
RANGE
Vcc=5V
55 / 70
55 / 70
Vcc=5V
30uA
Vcc=5V
45mA
50mA
BS62LV8005EC
BS62LV8005BC
BS62LV8005EI
BS62LV8005BI
TSOP2-44
+0OC to +70OC 4.5V ~ 5.5V
-40OC to +85OC 4.5V ~ 5.5V
BGA-48-0810
TSOP2-44
50uA
BGA-48-0810
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A5
2
A3
A6
3
A2
A7
4
A1
OE
5
A0
CE2
A8
A13
A17
A15
6
CE1
7
NC
NC
8
NC
NC
Address
A18
9
DQ0
DQ7
DQ6
GND
VCC
DQ5
DQ4
NC
Memory Array
2048 X 4096
22
10
2048
BS62LV8005EC
DQ1
A16
A14
A12
A7
Row
11
VCC
Input
BS62LV8005EI
12
GND
13
DQ2
Decoder
Buffer
14
DQ3
15
A6
NC
16
NC
NC
A9
A5
17
WE
A4
18
A19
A10
A11
A12
A13
A14
19
A18
4096
20
A17
21
A16
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
22
8
Column I/O
A15
Input
Buffer
Write Driver
Sense Amp
1
2
3
4
5
6
8
8
Data
A
B
C
D
E
F
OE
A0
A3
A1
A4
A2
CE2
NC
NC
512
Output
Buffer
Column Decoder
18
NC
NC
NC
D1
CE1
NC
CE1
CE2
WE
OE
A5
A6
D0
VSS
VCC
D4
Control
Address Input Buffer
A17
VCC
A14
A12
A9
A7
D5
D6
VCC
VSS
Vdd
Gnd
A11A9 A8 A3 A2 A1 A0A10 A19
D2
NC
NC
A16
A15
A13
A10
D7
NC
A19
D3
NC
NC
G
H
WE
A11
A18
A8
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.4
April 2002
R0201-BS62LV8005
1
BSI
PIN DESCRIPTIONS
Name
BS62LV8005
Function
A0-A19 Address Input
These 20 address inputs select one of the 1,048,576 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
WE
X
X
CE1
H
X
CE2
X
L
OE
X
X
I/O OPERATION
Vcc CURRENT
Not selected
High Z
I
CCSB, ICCSB1
(Power Down)
Output Disabled
Read
H
H
L
L
L
L
H
H
H
H
L
X
High Z
DOUT
DIN
ICC
ICC
ICC
Write
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
SYMBOL
VTERM
TBIAS
TSTG
PARAMETER
RATING
UNITS
AMBIENT
TEMPERATURE
0 O C to +70 O
RANGE
Vcc
Terminal Voltage with
Respect to GND
-0.5 to
V
Vcc+0.5
Commercial
Industrial
C
4.5V ~ 5.5V
4.5V ~ 5.5V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
-40 O C to +85O
C
PT
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
IOUT
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
CIN
VIN=0V
10
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
12
pF
1. This parameter is guaranteed and not tested.
Revision 2.4
April 2002
R0201-BS62LV8005
2
BSI
BS62LV8005
DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP. (1) MAX.
-0.5 -- 0.8
NAME
Guaranteed Input Low
Vcc=5V
Vcc=5V
VIL
V
Voltage(2)
Guaranteed Input High
Voltage(2)
VIH
IIL
2.2
--
--
--
--
Vcc+0.2
V
Input Leakage Current
Vcc = Max, VIN = 0V to Vcc
1
1
uA
uA
Vcc = Max, CE1 = VIH or CE2 = VIL or
OE = VIH, VI/O = 0V to Vcc
IOL
Output Leakage Current
--
Vcc=5V
VOL
VOH
ICC
Output Low Voltage
Output High Voltage
Vcc = Max, IOL = 2mA
Vcc = Min, IOH = -1mA
--
2.4
--
--
--
--
0.4
--
V
V
Vcc=5V
Vcc=5V
Operating Power Supply CE1= VIL, CE2= VIH, IDQ = 0mA,
45
mA
Current
F = Fmax(3)
Vcc=5V
Vcc=5V
ICCSB
Standby Current-TTL
CE1 = VIH, CE2= VIL,
I
DQ = 0mA
--
--
--
3
2
mA
uA
CE1ЊVcc-0.2V, CE2Љ0.2V
IN Њ Vcc - 0.2V or VIN Љ 0.2V
ICCSB1
Standby Current-CMOS
30
V
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
CE1ЊVcc - 0.2V or CE2 Љʳ 0.2V or
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE1 Њ Vcc - 0.2V or CE2 Љʳ 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
ICCDR
Data Retention Current
--
0
0.4
2.5
uA
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
TRC
O
1. Vcc = 1.5V, TA = + 25 C
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
t
Vcc
R
t
CDR
≥
CE1 Vcc - 0.2V
VIH
VIH
CE1
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
DR Њ 1.5V
V
Vcc
Vcc
t
Vcc
R
t
CDR
CE2 Љ 0.2V
VIL
VIL
CE2
Revision 2.4
April 2002
R0201-BS62LV8005
3
BSI
BS62LV8005
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
Ω
Ω
1928
1928
5PF
CHANGE
5.0V
5.0V
OUTPUT
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
ANY CHANGE
PERMITTED
100PF
INCLUDING
INCLUDING
UNKNOWN
Ω
Ω
1020
1020
JIG AND
SCOPE
JIG AND
SCOPE
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC , Vcc = 5V )
READ CYCLE
JEDEC
PARAMETER
NAME
BS62LV8005-70
BS62LV8005- 55
MIN. TYP. MAX.
DESCRIPTION
Read Cycle Time
UNIT
PARAMETER
MIN. TYP. MAX.
NAME
tAVAX
tAVQV
tE1LQV
tE2LQV
tGLQV
tELQX
tGLQX
tEHQZ
tGHQZ
tAXOX
70
--
--
--
--
--
--
--
--
--
--
55
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
t RC
t AA
t ACS1
t ACS2
t OE
t CLZ
t OLZ
t CHZ
t OHZ
Address Access Time
--
--
70
70
70
35
--
55
55
55
30
--
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
(CE1)
(CE2)
--
--
--
--
--
10
10
0
10
10
0
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
--
35
30
30
25
0
0
t OH
Output Disable to Output Address Change
10
--
--
10
--
--
ns
Revision 2.4
April 2002
R0201-BS62LV8005
4
BSI
BS62LV8005
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE2
t
t
ACS2
ACS1
CE1
(5)
CHZ
(5)
CLZ
t
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
CE2
CE1
t
ACS2
t
OLZ
(5)
t
ACS1
t
t
OHZ
(5)
CLZ
(1,5)
CHZ
t
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL
.
.
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.4
April 2002
R0201-BS62LV8005
5
BSI
BS62LV8005
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC , Vcc = 5.0V )
WRITE CYCLE
JEDEC
PARAMETER
NAME
BS62LV8005-70
BS62LV8005-55
UNIT
PARAMETER
NAME
DESCRIPTION
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tE1LWH
tAVWL
tWC
tCW
tAS
Write Cycle Time
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set up Time
--
--
tAVWH
tWLWH
tWHAX
tWLOZ
tDVWH
tWHDX
tGHOZ
tWHQX
tAW
tWP
tWR
tWHZ
tDW
tDH
Address Valid to End of Write
Write Pulse Width
70
35
0
--
--
55
30
0
--
--
Write Recovery Time
(CE2,CE1 , WE)
--
--
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
0
30
--
0
25
--
30
0
25
0
--
--
tOHZ
tOW
Output Disable to Output in High Z
Endot Write to Output Active
0
30
--
0
25
--
5
5
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(5)
CE2
(11)
CW
t
(5)
CE1
t
AW
(3)
t
WP
(2)
t
AS
(4,10)
OHZ
WE
t
D OUT
t
DH
t
DW
D IN
Revision 2.4
April 2002
R0201-BS62LV8005
6
BSI
BS62LV8005
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
CE2
(11)
CW
t
(5)
CE1
t
WR
t
AW
(3)
t
WP
(2)
t
DH
WE
t
AS
(4,10)
(7)
(8)
t
WHZ
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
Revision 2.4
April 2002
R0201-BS62LV8005
7
BSI
BS62LV8005
ORDERING INFORMATION
BS62LV8005
X X ˀˀ Y Y
SPEED
55: 55ns
70: 70ns
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
E: TSOP2-44
B: BGA-48-0810
PACKAGE DIMENSIONS
TSOP2-44
Revision 2.4
April 2002
R0201-BS62LV8005
8
BSI
BS62LV8005
PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
D1
N
48
D
10.0
E
8.0
D1
5.25
E1
3.75
e
0.75
SOLDER BALL
0.35̈́ 0.05
VIEW A
48 mini-BGA (8 x 10mm)
Revision 2.4
April 2002
R0201-BS62LV8005
9
BSI
REVISION HISTORY
BS62LV8005
Revision Description
Date
Note
2.2
2001 Data Sheet release
Apr. 15, 2001
2.3
Modify Standby Current (Typ. and Jun. 29, 2001
Max.)
2.4
Modify some AC parameters.
April,11,2002
Revision 2.4
April 2002
R0201-BS62LV8005
10
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