BS62LV4007SIP70 [BSI]
Very Low Power/Voltage CMOS SRAM 512K X 8 bit; 非常低的功率/电压CMOS SRAM 512K ×8位
| 型号： | BS62LV4007SIP70 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power/Voltage CMOS SRAM 512K X 8 bit |
| 文件： | 总10页 (文件大小：374K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
512K X 8 bit
BSI
BS62LV4007
FEATURES
DESCRIPTION
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
The BS62LV4007 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
2.0uA at 5.0V/25oC and maximum access time of 55ns at 5.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable
(CE) , and active LOW output enable (OE) and three-state output
drivers.
Vcc = 5.0V C-grade: 68mA (@55ns) operating current
I -grade: 70mA (@55ns) operating current
C-grade: 58mA (@70ns) operating current
I -grade: 60mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
• High speed access time :
-55
-70
55ns
70ns
The BS62LV4007 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4007 is available in the JEDEC standard 32L SOP, TSOP
, PDIP, TSOP II and STSOP package.
• Automatic power down when chip is deselected
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• Three state outputs and TTL compatible
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PKG
PRODUCT
FAMILY
OPERATING
Vcc
( I CCSB1 , Max )
( I CC , Max )
TYPE
TEMPERATURE RANGE
55ns:4.5~5.5V
70ns:4.5~5.5V
Vcc =5.0V
Vcc = 5.0V
55ns
Vcc =5.0V
30uA
70ns
-
BS62LV4007TC
BS62LV4007STC
BS62LV4007SC
BS62LV4007EC
BS62LV4007PC
BS62LV4007TI
BS62LV4007STI
BS62LV4007SI
BS62LV4007EI
BS62LV4007PI
TSOP 32
-
STSOP 32
+0 O C to +70O
C
C
4.5V ~ 5.5V
4.5V ~ 5.5V
55 / 70
55 / 70
68mA
70mA
58mA
-
SOP 32
-
32
TSOP2 32
PDIP
-
-
TSOP 32
-
STSOP 32
O
40 C to +85O
60mA
-
60uA
-
SOP 32
-
TSOP2 32
-
PDIP 32
BLOCK DIAGRAM
PIN CONFIGURATIONS
A18
A16
A14
A12
A7
1
VCC
A15
A17
WE
A13
A8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
A13
A17
A15
A18
A16
A14
A12
A7
3
4
Address
Input
Memory Array
5
22
2048
Row
Decoder
A6
6
A5
7
A9
2048 X 2048
A4
BS62LV4007SC
BS62LV4007SI
BS62LV4007EC
BS62LV4007EI
BS62LV4007PC
BS62LV4007PI
8
A11
OE
Buffer
A3
9
A6
A5
A4
A2
10
11
12
13
14
15
16
A10
CE
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
2048
DQ0
DQ1
DQ2
GND
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
8
8
Data
Output
Buffer
256
1
2
3
4
5
6
7
8
32
A11
A9
A8
OE
A10
CE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Column Decoder
16
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
CE
WE
OE
Control
BS62LV4007TC
BS62LV4007STC
BS62LV4007TI
BS62LV4007STI
Address Input Buffer
9
10
11
12
13
14
15
16
Vdd
GND
A11 A9 A8 A3 A2 A1 A0 A10
A6
A5
A4
A1
A2
A3
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.1
Jan. 2004
R0201-BS62LV4007
1
BSI
BS62LV4007
PIN DESCRIPTIONS
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 8-bit words in the RAM
CE Chip Enable Input
WE Write Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
GND
TRUTH TABLE
MODE
Not selected
Output Disabled
Read
WE
X
CE
H
L
OE
X
I/O OPERATION
High Z
Vcc CURRENT
ICCSB, ICCSB1
H
H
High Z
ICC
ICC
ICC
OUT
IN
H
L
L
D
Write
L
L
X
D
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
TEMPERATURE
0 O C to +70 O
SYMBOL
VTERM
TBIAS
TSTG
PARAMETER
RATING
UNITS
V
RANGE
Vcc
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
Commercial
Industrial
C
4.5V ~ 5.5V
4.5V ~ 5.5V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +85
-60 to +150
1.0
O C
-40 O C to +85O
C
O C
W
PT
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
IOUT
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
CIN
VIN=0V
6
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
8
pF
1. This parameter is guaranteed and not 100% tested.
Revision 1.1
Jan. 2004
R0201-BS62LV4007
2
BSI
BS62LV4007
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
PARAMETER
(1)
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
NAME
Guaranteed Input Low
Voltage
Vcc = 5.0 V
Vcc = 5.0 V
VIL
-0.5
--
0.8
V
(3)
Guaranteed Input High
IH
V
2.2
--
--
--
Vcc+0.3
1
V
(3)
Voltage
IL
IN
I
Input Leakage Current
Vcc = Max, V = 0V to Vcc
uA
IH
IH
Vcc = Max, CE = V , or OE = V ,
ILO
Output Leakage Current
--
--
--
--
--
1
uA
V
I/O = 0V to Vcc
Vcc = 5.0 V
Vcc = 5.0 V
0.4
--
OL
OL
V
Output Low Voltage
Output High Voltage
Vcc = Max, I = 2.0mA
V
V
OH
V
OH
= -1.0mA
Vcc = Min, I
2.4
(5)
55ns
70ns
70
60
IL
DQ
CE = V , I = 0mA,
F=Fmax(2)
CC
I
Operating Power Supply
Current
--
--
--
--
--
mA
mA
uA
Vcc = 5.0 V
CCSB
IH
DQ
I
CE = V , I = 0mA
Vcc = 5.0 V
Vcc = 5.0 V
1.0
60
Standby Current-TTL
(4)
CE
Vcc-0.2V,
≧
≧
Standby Current-CMOS
ICCSB1
2.0
IN
IN
V
Vcc - 0.2V or V
0.2V
≦
1. Typical characteristics are at TA = 25oC.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. IccSB1_MAX. is 30uA at Vcc=5.0V and TA=70oC. 5. Icc_MAX. is 68mA(@55ns) / 58mA(@70ns) at Vcc=5.0V and TA=0~70oC.
2. Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
CE ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
ICCDR
Data Retention Current
--
0
0.3
1.3
uA
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
TRC
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
3. IccDR_MAX. is 0.8uA at TA=70OC.
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
Vcc
CE
t
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
Revision 1.1
R0201-BS62LV4007
3
Jan.
2004
BSI
BS62LV4007
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
(Vcc = 4.5~5.5V)
MIN. TYP. MAX.
CYCLE TIME : 55ns
(Vcc = 4.5~5.5V)
PARAMETER
DESCRIPTION
Read Cycle Time
UNIT
NAME
MIN.
TYP.
MAX.
tAVAX
tAVQV
tELQV
tGLQV
tELQX
tGLQX
tEHQZ
tGHQZ
tRC
55
--
--
--
70
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
--
55
55
30
--
70
70
35
--
tACS
tOE
Chip Select Access Time
--
--
--
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
--
--
tCLZ
tOLZ
tCHZ
tOHZ
10
10
--
--
10
10
--
--
--
--
--
30
25
35
30
--
--
--
tAXOX
tOH
Data Hold from Address Change
10
--
--
10
--
--
ns
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
Revision 1.1
Jan. 2004
R0201-BS62LV4007
4
BSI
BS62LV4007
READ CYCLE2 (1,3,4)
CE
t
ACS
(5)
CHZ
t
(5)
t
CLZ
D OUT
READ CYCLE3 (1,4)
t
RC
ADDRESS
OE
t
AA
t
OH
t
OE
t
OLZ
CE
(5)
t
ACS
t
t
OHZ
(1,5)
CHZ
(5)
CLZ
t
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
5. The parameter is guaranteed but not 100% tested.
.
.
Revision 1.1
Jan. 2004
R0201-BS62LV4007
5
BSI
BS62LV4007
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 55ns
(Vcc = 4.5~5.5V)
MIN. TYP. MAX.
CYCLE TIME : 70ns
(Vcc = 4.5~5.5V)
MIN. TYP. MAX.
PARAMETER
DESCRIPTION
Write Cycle Time
UNIT
NAME
tAVAX
tE1LWH
tAVWL
tWC
55
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
tAS
Chip Select to End of Write
Address Set up Time
--
--
tAVWH
tWLWH
tWHAX
tWLOZ
tDVWH
tWHDX
tGHOZ
tWHQX
tAW
tWP
tWR
tWHZ
tDW
tDH
Address Valid to End of Write
Write Pulse Width
55
30
0
--
70
35
0
--
--
--
Write Recovery Time
(CE , WE)
--
--
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
Endot Write to Output Active
--
25
--
--
30
--
25
0
30
0
--
--
tOHZ
tOW
--
25
--
--
30
--
5
5
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(11)
CW
t
(5)
CE
t
AW
t
WP
(2)
t
AS
WE
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 1.1
Jan. 2004
R0201-BS62LV4007
6
BSI
BS62LV4007
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
t
CW
(5)
CE
t
AW
t
WP
(2)
WE
t
AS
(4,10)
t
OW
(7)
(8)
t
WHZ
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
Revision 1.1
R0201-BS62LV4007
7
Jan.
2004
BSI
BS62LV4007
ORDERING INFORMATION
BS62LV4007 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
S: SOP
E: TSOP 2
ST: Small TSOP
T: TSOP
P: PDIP
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
b
WITH PLATING
c
c1
BASE METAL
b1
SECTION A-A
SOP -32
Revision 1.1
Jan. 2004
R0201-BS62LV4007
8
BSI
BS62LV4007
TSOP2 - 32
TSOP - 32
Revision 1.1
R0201-BS62LV4007
9
Jan.
2004
BSI
BS62LV4007
PACKAGE DIMENSIONS (continued)
STSOP - 32
PDIP - 32
Revision 1.1
R0201-BS62LV4007
10
Jan.
2004
相关型号：
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