BS62LV2005TI [BSI]

Very Low Power/Voltage CMOS SRAM 256K X 8 bit; 非常低的功率/电压CMOS SRAM 256K ×8位


型号：	BS62LV2005TI
厂家：	BRILLIANCE SEMICONDUCTOR
描述：	Very Low Power/Voltage CMOS SRAM 256K X 8 bit 非常低的功率/电压CMOS SRAM 256K ×8位静态存储器
文件：	总10页 (文件大小：280K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Very Low Power/Voltage CMOS SRAM

256K X 8 bit

BSI

BS62LV2005

DESCRIPTION

FEATURES

The BS62LV2005 is a high performance, very low power CMOS

Static Random Access Memory organized as 262,144 words by 8 bits

and operates from a wide range of 4.5V to 5.5V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with a typical CMOS standby current of

0.6uA and maximum access time of 55ns in 5V operation.

• Wide Vcc operation voltage : 4.5V ~ 5.5V

• Very low power consumption :

Vcc = 5.0V C-grade : 35mA (Max.) operating current

I- grade : 40mA (Max.) operating current

0.6uA (Typ.) CMOS standby current

• High speed access time :

Easy memory expansion is provided by an active LOW chip

enable (CE1), an active HIGH chip enable (CE2), and active LOW

output enable (OE) and three-state output drivers.

-70

-55

70ns(Max.) at Vcc = 5.0V

55ns(Max.) at Vcc = 5.0V

The BS62LV2005 has an automatic power down feature, reducing the

power consumption significantly when chip is deselected.

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

The BS62LV2005 is available in the JEDEC standard 32 pin

450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE2, CE1, and OE options

PRODUCT FAMILY

POWER DISSIPATION

SPEED

STANDBY

Operating

PRODUCT

FAMILY

OPERATING

Vcc

(ns)

(ICCSB1, Max)

(ICC , Max)

PKG TYPE

TEMPERATURE

RANGE

Vcc=5.0V

6uA

Vcc=5.0V

35mA

BS62LV2005TC

BS62LV2005STC

BS62LV2005SC

BS62LV2005TI

BS62LV2005STI

BS62LV2005SI

TSOP 32

+0^OC to +70^OC 4.5V ~ 5.5V

-40^OC to +85^OC 4.5V ~ 5.5V

55 / 70

STSOP 32

SOP 32

TSOP 32

25uA

40mA

STSOP 32

SOP 32

BLOCK DIAGRAM

PIN CONFIGURATIONS

A11

A10

CE1

DQ7

DQ6

DQ5

DQ4

DQ3

GND

DQ2

DQ1

DQ0

A13

A17

A13

CE2

A15

VCC

A17

A16

A14

A12

A15

Address

Memory Array

1024 x 2048

A16

1024

Row

BS62LV2005TC

BS62LV2005STC

BS62LV2005TI

BS62LV2005STI

A14

A12

Input

Decoder

Buffer

2048

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Data

Column I/O

Input

Buffer

Write Driver

Sense Amp

A17

A16

A14

A12

VCC

A15

CE2

A13

Data

256

Output

Buffer

Column Decoder

BS62LV2005SC

BS62LV2005SI

A11

CE1

CE2

Vdd

Gnd

Control

Address Input Buffer

A10

CE1

DQ7

DQ6

DQ5

DQ4

DQ3

DQ0

DQ1

DQ2

GND

A9 A8 A3 A2 A1 A0 A10

A11

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

Revision 2.4

April 2002

R0201-BS62LV2005

BSI

BS62LV2005

PIN DESCRIPTIONS

Name

Function

A0-A17 Address Input

These 18 address inputs select one of the 262,144 x 8-bit words in the RAM

CE1 Chip Enable 1 Input

CE2 Chip Enable 2 Input

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when

data read from or write to the device. If either chip enable is not active, the device is

deselected and is in a standby power mode. The DQ pins will be in the high

impedance state when the device is deselected.

WE Write Enable Input

OE Output Enable Input

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

These 8 bi-directional ports are used to read data from or write data into the RAM.

DQ0-DQ7 Data Input/Output

Ports

Vcc

Power Supply

Ground

Gnd

TRUTH TABLE

MODE

CE1

CE2

I/O OPERATION

High Z

Vcc CURRENT

Not selected

I_CCSB, I_CCSB1

(Power Down)

Output Disabled

Read

High Z

I_CC

OUT

Write

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

OPERATING RANGE

SYMBOL

PARAMETER

RATING

UNITS

AMBIENT

TEMPERATURE

0 ^OC to +70 ^O

RANGE

Vcc

Terminal Voltage with

Respect to GND

-0.5 to

TERM

BIAS

STG

Vcc+0.5

Commercial

Industrial

4.5V ~ 5.5V

Temperature Under Bias

Storage Temperature

Power Dissipation

-40 to +125

-60 to +150

1.0

^OC

-40 ^OC to +85^O

CAPACITANCE ⁽¹⁾(TA = 25^oC, f = 1.0 MHz)

DC Output Current

OUT

SYMBOL

CIN

PARAMETER

CONDITIONS

MAX.

UNIT

Input

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these

or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

=0V

Capacitance

Input/Output

Capacitance

CDQ

VI/O=0V

1. This parameter is guaranteed and not tested.

Revision 2.4

April 2002

R0201-BS62LV2005

BSI

BS62LV2005

DC ELECTRICAL CHARACTERISTICS ( TA = 0^oC to + 70^oC )

PARAMETER

UNITS

PARAMETER

TEST CONDITIONS

MIN. TYP. ⁽¹⁾MAX.

-0.5 -- 0.8

NAME

Guaranteed Input Low

Vcc=5.0V

V^IL

Voltage⁽²⁾

Guaranteed Input High

Voltage⁽²⁾

V^IH

I^IL

2.2

Vcc+0.2

Input Leakage Current

Vcc = Max, V^IN= 0V to Vcc

Vcc = Max, CE1= V^IH, CE2= V^IL,or

OE = V^IH, V^I/O= 0V to Vcc

I^OL

Output Leakage Current

Vcc=5.0V

V^OL

V^OH

Output Low Voltage

Output High Voltage

Vcc = Max, I^OL= 2mA

Vcc = Min, I^OH= -1mA

0.4

2.4

Operating Power Supply CE1 = V^IL, or CE2 = V^IH

Vcc=5.0V

I^CC

Current

^DQ= 0mA, F = Fmax⁽³⁾

CE1 = V^IH, or CE2 = V^IL

I^CCSB

Standby Current-TTL

^DQ= 0mA, F = Fmax⁽³⁾

CE1ЊVcc-0.2V, CE2Љ0.2V,

^INЊVcc-0.2V or V^INЉ0.2V

I^CCSB1

Standby Current-CMOS

0.6

1. Typical characteristics are at TA = 25 C.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t_RC

DATA RETENTION CHARACTERISTICS ( TA = 0^oC to + 70^oC )

(1)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN. TYP.

MAX.

UNITS

CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,

V^INЊ Vcc - 0.2V or V^INЉ 0.2V

V_DR

Vcc for Data Retention

1.5

CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,

V^INЊ Vcc - 0.2V or V^INЉ 0.2V

I_CCDR

Data Retention Current

0.01

Chip Deselect to Data

Retention Time

Operation Recovery Time

t_CDR

t_R

See Retention Waveform

(2)

T_RC

1. Vcc = 1.5V, T_A= + 25 C

2. t_RC= Read Cycle Time

LOW V_CCDATA RETENTION WAVEFORM (1) ( CE1 Controlled )

Data Retention Mode

^DR≥ 1.5V

Vcc

CDR

≥

CE1 Vcc - 0.2V

VIH

CE1

LOW V_CCDATA RETENTION WAVEFORM (2) ( CE2 Controlled )

Data Retention Mode

VDR Њ 1.5V

Vcc

CDR

CE2 Љ 0.2V

VIL

CE2

Revision 2.4

April 2002

R0201-BS62LV2005

BSI

BS62LV2005

KEY TO SWITCHING WAVEFORMS

AC TEST CONDITIONS

Input Pulse Levels

Vcc/0V

5ns

WAVEFORM

INPUTS

OUTPUTS

Input Rise and Fall Times

Input and Output

MUST BE

STEADY

MUST BE

STEADY

Timing Reference Level

0.5Vcc

MAY CHANGE

FROM H TO L

WILL BE

CHANGE

AC TEST LOADS AND WAVEFORMS

FROM H TO L

Ω

1928

5PF

MAY CHANGE

FROM L TO H

WILL BE

5.0V

CHANGE

OUTPUT

FROM L TO H

DON T CARE:

CHANGE :

STATE

100PF

ANY CHANGE

PERMITTED

INCLUDING

Ω

1020

Ω

1020

JIG AND

SCOPE

JIG AND

SCOPE

UNKNOWN

DOES NOT

APPLY

CENTER

FIGURE 1A

FIGURE 1B

LINE IS HIGH

IMPEDANCE

”OFF ”STATE

THEVENIN EQUIVALENT

667

Ω

OUTPUT

1.73V

ALL INPUT PULSES

Vcc

GND

10%

90% 90%

10%

→

←

← 5ns

FIGURE 2

AC ELECTRICAL CHARACTERISTICS ( TA = 0^oC to + 70^oC, Vcc = 5.0V )

READ CYCLE

JEDEC

PARAMETER

NAME

BS62LV2005-55

MIN. TYP. MAX.

BS62LV2005-70

MIN. TYP. MAX.

PARAMETER

DESCRIPTION

Read Cycle Time

UNIT

NAME

t_AVAX

t_AVQV

t_E1LQV

t_E2HOV

t_GLQV

t_E1LQX

t_E2HOX

t_GLQX

t_E1HQZ

t_E2HQZ

t_GHQZ

t_RC

t_AA

t_ACS1

t_ACS2

t_OE

t_CLZ1

t_CLZ2

t_OLZ

t_CHZ1

t_CHZ2

t_OHZ

Address Access Time

Chip Select Access Time

(CE1)

(CE2)

Chip Select Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Output Disable to Output in High Z

(CE1)

(CE2)

(CE1)

(CE2)

t_AXOX

t_OH

Output Disable to Output Address Change

Revision 2.4

April 2002

R0201-BS62LV2005

BSI

BS62LV2005

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1 ^(1,2,4)

ADDRESS

D _OUT

READ CYCLE2 ^(1,3,4)

CE1

ACS1

ACS2

CE2

(5)

CLZ

CHZ1, t CHZ2

D _OUT

READ CYCLE3 ^(1,4)

ADDRESS

OLZ

CE1

(5)

(1,5)

ACS1

t^OC^HH^ZZ1

(5)

CLZ1

CE2

ACS2

(2,5)

CHZ2

(5)

CLZ2

D _OUT

NOTES:

1. WE is high for read Cycle.

2. Device is continuously selected when CE1 = V^ILand CE2= VIH.

3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.

4. OE = V^IL

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

Revision 2.4

April 2002

R0201-BS62LV2005

BSI

BS62LV2005

AC ELECTRICAL CHARACTERISTICS ( TA = 0^oC to + 70^oC, Vcc = 5.0V )

WRITE CYCLE

JEDEC

PARAMETER

BS62LV2005-55

BS62LV2005-70

UNIT

PARAMETER

DESCRIPTION

Write Cycle Time

MIN. TYP. MAX.

NAME

t_AVAX

t_E1LWH

t_AVWL

t_AVWH

t_WLWH

t_WHAX

t_E2LAX

t_WLOZ

t_DVWH

t_WHDX

t_GHOZ

t_WHQX

t_WC

t_CW

Chip Select to End of Write

Address Set up Time

t_AS

t_AW

Address Valid to End of Write

Write Pulse Width

t_WP

t _WR1

t _WR2

t_WHZ

t_DW

Write Recovery Time

(CE1 , WE)

(CE2)

Write Recovery Time

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

t_DH

t_OHZ

t_OW

Output Disable to Output in High Z

End of Write to Output Active

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1 ⁽¹⁾

ADDRESS

(3)

WR1

(11)

(5)

CE1

(5)

(11)

(2)

CE2

WR2

(3)

(4,10)

OHZ

D _OUT

D _IN

Revision 2.4

April 2002

R0201-BS62LV2005

BSI

BS62LV2005

(1,6)

WRITE CYCLE2

ADDRESS

(11)

(5)

CE1

(11)

CE2

WR2

(3)

(2)

(4,10)

(7)

(8)

WHZ

D _OUT

(8,9)

D _IN

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.

All signals must be active to initiate a write and any one signal can terminate a write by going

inactive. The data input setup and hold timing should be referenced to the second transition edge

of the signal that terminates the write.

3. T^WRis measured from the earlier of CE1 or WE going high or CE2 going low at the end of write

cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the

outputs must not be applied.

5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low

transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V^IL).

7. DOUT is the same phase of write data of this write cycle.

8. DOUT is the read data of next address.

9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input

signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C^L= 5pF as shown in Figure 1B. The

parameter is guaranteed but not 100% tested.

11. T^CWis measured from the later of CE1 going low or CE2 going high to the end of write.

Revision 2.4

April 2002

R0201-BS62LV2005

BSI

BS62LV2005

ORDERING INFORMATION

BS62LV2005

X X ˀˀ Y Y

SPEED

70: 70ns

55: 55ns

GRADE

C: +0 C ~ +70 C

I: -40 C ~ +85 C

PACKAGE

T: TSOP (8mm x 20mm)

ST: Small TSOP (8mm x 13.4mm)

S: SOP

PACKAGE DIMENSIONS

STSOP - 32

Revision 2.4

April 2002

R0201-BS62LV2005

BSI

BS62LV2005

PACKAGE DIMENSIONS (continued)

TSOP - 32

WITH PLATING

BASE METAL

SECTION A-A

SOP -32

Revision 2.4

April 2002

R0201-BS62LV2005

BSI

REVISION HISTORY

BS62LV2005

Revision Description

Date

Note

2.2

2001 Data Sheet release

Apr. 15, 2001

2.3

Modify Standby Current (Typ. and Jun. 29, 2001

Max.)

2.4

Modify some AC parameters.

Modify 5V ICCSB1_Max(I-grade)

from 10uA to 25uA.

April,11,2002

Revision 2.4

April 2002

R0201-BS62LV2005

BS62LV2005TI [BSI]

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