BS62LV1027SAG70 [BSI]
Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 0.450 INCH, GREEN, PLASTIC, SOP-32;
| 型号： | BS62LV1027SAG70 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 0.450 INCH, GREEN, PLASTIC, SOP-32 静态存储器 光电二极管 |
| 文件： | 总11页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Automotive Grade
Very Low Power CMOS SRAM
128K X 8 bit
BS62LV1027
Green package materials are compliant to RoHS
n FEATURES
n DESCRIPTION
ŸWide VCC operation voltage : 2.4V ~ 5.5V
ŸVery low power consumption :
The BS62LV1027 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.02uA at 3.0V/25OC and maximum access time of 70ns at
2.7V/125OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
The BS62LV1027 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV1027 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 600mil Plastic DIP, 8mmx13.4mm STSOP,
8mmx20mm TSOP and 36-ball BGA package.
VCC = 3.0V Operation current : 15mA (Max.) at 70ns
2mA (Max.) at 1MHz
Standby current : 0.02uA (Typ.)at 25OC
VCC = 5.0V Operation current : 39mA (Max.) at 70ns
10mA (Max.) at 1MHz
Standby current : 0.4uA (Typ.) at 25OC
ŸHigh speed access time :
-70
70ns (Max.) at VCC : 2.7~5.5V
ŸAutomatic power down when chip is deselected
ŸEasy expansion with CE2, CE1 and OE options
ŸThree state outputs and TTL compatible
ŸFully static operation
ŸData retention supply voltage as low as 1.5V
n POWER CONSUMPTION
POWER DISSIPATION
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
PKG TYPE
(ICC, Max.)
(ICCSB1, Typ.)
(ICCSB1, Max.)
VCC=5.0V
1MHz fMax.
VCC=3.0V
VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V
1MHz
fMax.
BS62LV1027HA
BS62LV1027PA
BS62LV1027SA
BS62LV1027STA
BS62LV1027TA
BGA-36-0608
PDIP-32
Automotive
Grade
0.4uA
0.02uA
15uA
8.0uA
10mA
39mA
2mA
15mA
SOP-32
-40OC to +125OC
STSOP-32
TSOP-32
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A11
A9
A8
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A6
A7
A12
A14
A16
A15
A13
A8
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
Address
Input
Memory Array
10
1024
Row
Decoder
BS62LV1027STA
BS62LV1027TA
1024 x 1024
Buffer
9
10
11
12
13
14
15
16
A9
A11
A6
A5
A4
A1
A2
A3
1024
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Data
Input
Buffer
8
8
8
Column I/O
Write Driver
Sense Amp
8
Data
Output
Buffer
1
2
3
4
5
6
128
NC
A16
A14
A12
A7
1
32
VCC
A15
CE2
WE
A13
A8
A
B
C
D
E
F
A0
A1
CE2
A3
A6
A8
Column Decoder
2
31
30
29
28
27
26
3
DQ4
DQ5
VSS
VCC
DQ6
DQ7
A9
A2
WE
NC
A4
A5
A7
DQ0
DQ1
VCC
VSS
DQ2
DQ3
A14
4
7
CE2
CE1
WE
5
Control
Address Input Buffer
A6
6
A5
7
A9
OE
A4
8
BS62LV1027PA 25
BS62LV1027SA
A11
OE
VCC
A3
9
24
23
22
21
20
19
18
17
GND
A5 A10 A4 A3 A2 A1 A0
A2
10
11
12
13
14
15
16
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A1
NC
CE1
A11
NC
A16
A12
A0
DQ0
DQ1
DQ2
GND
G
H
OE
A15
A13
A10
36-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS62LV1027A
Revision 2.2A
Mar. 2006
1
BS62LV1027
n PIN DESCRIPTIONS
Name
Function
These 17 address inputs select one of the 131,072 x 8-bit in the RAM
A0-A16 Address Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read form or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
WE Write Enable Input
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
There 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
VCC
Power Supply
Ground
GND
n TRUTH TABLE
CE1
WE
X
OE
X
MODE
CE2
I/O OPERATION VCC CURRENT
H
X
L
L
L
X
L
Not selected
(Power Down)
High Z
ICCSB, ICCSB1
X
X
Output Disabled
Read
H
H
H
H
H
High Z
DOUT
DIN
ICC
ICC
ICC
H
L
Write
L
X
n ABSOLUTE MAXIMUM RATINGS (1)
n OPERATING RANGE
AMBIENT
TEMPERATURE
-40OC to + 125OC
SYMBOL
VTERM
TBIAS
PARAMETER
RATING
UNITS
V
RANG
VCC
Terminal Voltage with
Respect to GND
-0.5(2) to 7.0
-40 to +125
-60 to +150
1.0
Automotive
2.4V ~ 5.5V
Temperature Under
Bias
OC
n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
TSTG
Storage Temperature
Power Dissipation
DC Output Current
OC
PT
W
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
IOUT
20
mA
Input
Capacitance
CIN
CIO
VIN = 0V
VI/O = 0V
6
8
pF
pF
Input/Output
Capacitance
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
1. This parameter is guaranteed and not 100% tested.
2. –2.0V in case of AC pulse width less than 30 ns.
Revision 2.2A
Mar. 2006
R0201-BS62LV1027A
2
BS62LV1027
n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +125OC)
PARAMETER
PARAMETER
Power Supply
TEST CONDITIONS
MIN.
2.4
-0.5(2)
2.2
--
TYP.(1)
MAX.
UNITS
V
NAME
VCC
--
--
--
--
--
--
--
5.5
VIL
VIH
Input Low Voltage
0.8
V
Input High Voltage
VCC+0.3(3)
V
IIL
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
VCC = Max, VIN = 0V to VCC
1
1
UA
UA
V
VCC = Max, CE1= VIH, CE2= VIL, or
OE = VIH, VI/O = 0V to VCC
ILO
--
VCC=3.0V
VOL
VOH
ICC
VCC = Max, IOL = 2.0mA
VCC = Min, IOH = -1.0mA
--
0.4
--
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
2.4
V
Operating Power Supply CE1 = VIL, CE2 = VIH,
--
--
--
--
15
39
2
mA
MA
mA
(4)
Current
IDQ = 0mA, f = fMax
Operating Power Supply CE1 = VIL, CE2 = VIH,
ICC1
ICCSB
Current
IDQ = 0mA, f = 1MHz
10
0.5
1.0
8.0
15
CE1 = VIH, or CE2 = VIL,
IDQ = 0mA
--
--
--
--
--
--
Standby Current – TTL
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
0.02
0.4
ICCSB1
Standby Current – CMOS
uA
1. Typical characteristics are at TA=25OC and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. fMax.=1/tRC.
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +125OC)
SYMBOL
VDR
PARAMETER
VCC for Data Retention
Data Retention Current
TEST CONDITIONS
MIN.
1.5
--
TYP. (1)
--
MAX.
--
UNITS
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
V
ICCDR
0.02
5.0
uA
Chip Deselect to Data
Retention Time
tCDR
tR
0
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
tRC
1. VCC=1.5V, TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
DR≧1.5V
VCC
VCC
VCC
tCDR
tR
CE1≧VCC - 0.2V
VIH
VIH
CE1
Revision 2.2A
Mar. 2006
R0201-BS62LV1027A
3
BS62LV1027
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
DR≧1.5V
VCC
VCC
VCC
tCDR
tR
CE2≦0.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
1V/ns
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
Input and Output Timing
Reference Level
0.5Vcc
MAY CHANGE
WILL BE CHANGE
FROM “H” TO “L”
FROM “H” TO “L”
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
CL = 5pF+1TTL
CL = 30pF+1TTL
Output Load
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
VCC
1 TTL
90%
90%
Output
10%
10%
GND
(1)
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
®
¬
®
¬
CL
DOES NOT
APPLY
Rise Time :
1V/ns
Fall Time :
1V/ns
1. Including jig and scope capacitance.
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +125OC)
READ CYCLE
CYCLE TIME : 70ns
(VCC = 2.7~5.5V)
JEDEC
PARAMETER
NAME
PARANETER
DESCRIPTION
UNITS
NAME
MIN.
TYP.
MAX.
Read Cycle Time
70
--
--
--
70
70
70
35
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAX
tAVQX
tRC
tAA
Address Access Time
--
--
--
--
--
--
--
--
--
--
--
Chip Select Access Time
(CE1)
(CE2)
--
tE1LQV
tE2HQV
tGLQV
tE1LQX
tE2HQX
tGLQX
tE1HQZ
tE2LQZ
tGHQZ
tAVQX
tACS1
tACS2
tOE
Chip Select Access Time
--
Output Enable to Output Valid
Chip Select to Output Low Z
--
(CE1)
(CE2)
10
10
5
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
tOH
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
--
--
(CE1)
(CE2)
--
35
35
30
--
Chip Select to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
--
--
10
Revision 2.2A
R0201-BS62LV1027A
4
Mar.
2006
BS62LV1027
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
READ CYCLE 2 (1,3,4)
CE1
tACS1
CE2
DOUT
tACS2
(5)
tCHZ1, tCHZ2
(5)
tCLZ
READ CYCLE 3 (1, 4)
ADDRESS
tRC
tAA
OE
tOH
tOE
tOLZ
CE1
(5)
tACS1
tOH(1Z,5)
(5)
tCLZ1
tCHZ1
CE2
DOUT
tACS2
(2,5)
tCHZ2
(5)
tCLZ2
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
Revision 2.2A
Mar. 2006
R0201-BS62LV1027A
5
BS62LV1027
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +125OC)
WRITE CYCLE
CYCLE TIME : 70ns
(VCC = 2.7~5.5V)
JEDEC
PARAMETER
NAME
PARANETER
DESCRIPTION
UNITS
NAME
MIN.
TYP.
MAX.
Write Cycle Time
70
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tE2LAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
tCW
tAS
Chip Select to End of Write
Address Set up Time
70
0
--
--
Address Valid to End of Write
Write Pulse Width
70
35
0
--
tAW
--
tWP
Write Recovery Time
(CE1, WE)
(CE2)
--
tWR1
tWR2
tWHZ
tDW
tDH
Write Recovery Time
0
--
Write to Output High Z
--
30
--
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
30
0
--
--
30
--
tOHZ
tOW
5
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
OE
(3)
tWR1
(11)
tCW
(5)
(5)
CE1
CE2
(11)
(2)
tCW
(3)
tWR2
tAW
tWP
WE
tAS
(4,10)
tOHZ
DOUT
tDH
tDW
DIN
Revision 2.2A
Mar. 2006
R0201-BS62LV1027A
6
BS62LV1027
WRITE CYCLE 2 (1,6)
ADDRESS
tWC
(11)
tCW
(5)
(5)
CE1
CE2
WE
(11)
(2)
tCW
(3)
tAW
tWR2
tWP
tAS
(4,10)
tWHZ
(7)
(8)
tOW
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and
WE low. All signals must be active to initiate a write and any one signal can terminate a
write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of
write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.t CW is measured from the later of CE1 going low or CE2 going high to the end of write.
Revision 2.2A
R0201-BS62LV1027A
7
Mar.
2006
BS62LV1027
n ORDERING INFORMATION
BS62LV1027
X
X
Z Y Y
SPEED
70: 70ns
PKG MATERIAL
-: Normal
G: Green, RoHS Compliant
GRADE
A: -40OC to +125OC
(Automotive Grade)
PACKAGE
H: BGA-36-0608
P: PDIP
S: SOP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
b
WITH PLATING
c
c1
b1
BASE METAL
SECTION A-A
SOP -32
Revision 2.2A
Mar. 2006
R0201-BS62LV1027A
8
BS62LV1027
n PACKAGE DIMENSIONS (continued)
STSOP - 32
TSOP - 32
Revision 2.2A
R0201-BS62LV1027A
9
Mar.
2006
BS62LV1027
PACKAGE DIMENSIONS (continued)
PDIP - 32
NOTES
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
D1
VIEW A
36 mini-BGA (6 x 8mm)
Revision 2.2A
Mar. 2006
R0201-BS62LV1027A
10
BS62LV1027
n Revision History
Revision No.
2.2.A
History
Draft Date
Mar. 27,2006
Remark
Add Automotive
Revision 2.2A
R0201-BS62LV1027A
11
Mar.
2006
相关型号：
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