BS616UV4016DI-85 [BSI]
Ultra Low Power/High Speed CMOS SRAM 256K X 16 Bit; 超低功耗/高速CMOS SRAM 256K ×16位
| 型号： | BS616UV4016DI-85 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Ultra Low Power/High Speed CMOS SRAM 256K X 16 Bit |
| 文件： | 总10页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power/High Speed CMOS SRAM
256K X 16 bit
BSI
BS616UV4016
ŸI/O Configuration x8/x16 selectable by LB and UB pin.
n FEATURES
ŸThree state outputs and TTL compatible
ŸFully static operation
ŸData retention supply voltage as low as 1.2V
n DESCRIPTION
ŸWide VCC operation voltage :
C-grade : 1.8V ~ 3.6V
I-grade : 1.9V ~ 3.6V
(VCC_min.=1.65V at 25OC)
ŸUltra low power consumption :
The BS616UV4016 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates form a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical CMOS standby current of
0.3uA at 2.0V/25OC and maximum access time of 85ns at 85OC.
Easy memory expansion is provided by an active LOW chip enable (CE)
and active LOW output enable (OE) and three-state output drivers.
The BS616UV4016 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV4016 is available in DICE form, JEDEC standard 44-pin
TSOP Type II and 48-ball BGA package.
VCC = 2.0V
C-grade : 10mA(Max.) operating current
I-grade : 12mA(Max.) operating current
0.3uA (Typ.) CMOS standby current
C-grade : 13mA(Max.) operating current
I-grade : 15mA(Max.) operating current
0.45uA (Typ.) CMOS standby current
VCC = 3.0V
ŸHigh speed access time :
-85
-10
85ns (Max.)
100ns (Max.)
ŸAutomatic power down when chip is deselected
ŸEasy expansion with CE and OE options
n PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
(ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
VCC
RANGE
PKG TYPE
(ICCSB1, Max)
C-grade : 1.8~3.6V
I-grade : 1.9~3.6V
VCC=3.0V VCC=2.0V VCC=3.0V VCC=2.0V
BS616UV4016DC
BS616UV4016EC
BS616UV4016AC
BS616UV4016DI
BS616UV4016EI
BS616UV4016AI
DICE
+0OC to +70OC
-40OC to +85OC
1.8V ~ 3.6V
1.9V ~ 3.6V
85/100
85/100
6.0uA
8.0uA
3.0uA
5.0uA
13mA
15mA
10mA
12mA
TSOP2-44
BGA-48-0608
DICE
TSOP2-44
BGA-48-0608
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
CE
A3
A4
A5
IO0
IO1
IO2
IO3
VCC
GND
IO4
IO5
IO6
IO7
WE
A17
A16
A15
A14
A13
IO15
IO14
IO13
IO12
GND
VCC
IO11
IO10
IO9
IO8
NC
A8
A9
A10
A11
A12
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A6
A7
Address
Input
1024
Memory Array
10
BS616UV4016EC
BS616UV4016EI
Row
Decoder
A8
Buffer
1024 x 4096
A9
A10
A11
A12
2048
IO0
Column I/O
16
16
Data
Input
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
.
1
2
3
4
5
6
16
16
.
Data
Output
Buffer
.
.
256
A
B
C
D
E
F
UB
IO8
IO9
OE
A0
A1
A2
NC
IO0
IO2
VCC
VSS
IO6
IO7
NC
Column Decoder
IO15
LB
A3
A5
A4
A6
CE
IO1
IO3
IO4
IO5
WE
A11
8
IO10
CE
WE
OE
UB
LB
Address Input Buffer
Control
VSS IO11
VCC IO12
IO14 IO13
A17
NC
A14
A12
A9
A7
A16
A15
A13
A10
A13 A14 A15 A16 A17 A0 A1 A2
VCC
GND
G
H
IO15
NC
NC
A8
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616UV4016
Revision 1.3
Sep. 2005
1
BSI
BS616UV4016
n PIN DESCRIPTIONS
Name
Function
These 18 address inputs select one of the 262,144 x 16-bit words in the RAM
A0-A17 Address Input
CE Chip Enable 1 Input
CE is active LOW. Chip enable must be active when data read form or write to the
device. If either chip enable is not active, the device is deselected and is in standby
power mode. The IO pins will be in the high impedance state when the device is
deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the IO
pins; when WE is LOW, the data present on the IO pins will be written into the selected
memory location.
WE Write Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the IO pins and they
will be enabled. The IO pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
OE Output Enable Input
LB and UB Data Byte Control Input
16 bi-directional ports are used to read data from or write data into the RAM.
IO0-IO15 Data Input/Output
Ports
VCC
Power Supply
Ground
GND
n TRUTH TABLE
MODE
IO0~IO7
High Z
High Z
High Z
High Z
DOUT
IO8~IO15
High Z
High Z
High Z
High Z
DOUT
VCC CURRENT
CE
H
WE
X
OE
X
LB
X
H
L
UB
X
H
X
L
ICCSB, ICCSB1
Chip De-selected
(Power Down)
X
X
X
ICCSB, ICCSB1
L
H
H
ICC
ICC
ICC
ICC
ICC
ICC
ICC
ICC
Output Disabled
Read
L
H
H
X
L
L
L
L
H
L
L
H
L
L
High Z
DOUT
DOUT
H
L
High Z
DIN
L
DIN
Write
X
H
L
L
X
DIN
H
DIN
X
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
R0201-BS616UV4016
Revision 1.3
Sep. 2005
2
BSI
BS616UV4016
n ABSOLUTE MAXIMUM RATINGS (1)
n OPERATING RANGE
AMBIENT
TEMPERATURE
0OC to + 70OC
SYMBOL
PARAMETER
RATING
-0.5(2) to 4.6V
-40 to +85
UNITS
RANG
Vcc
Terminal Voltage with
Respect to GND
Temperature Under
Bias
VTERM
V
Commercial
Industrial
1.8V ~ 3.6V
1.9V ~ 3.6V
TBIAS
OC
-40OC to + 85OC
TSTG
PT
Storage Temperature
Power Dissipation
DC Output Current
-60 to +150
OC
W
1.0
20
n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
IOUT
MA
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
CIN
CIO
VIN = 0V
VI/O = 0V
6
8
pF
pF
Capacitance
Input/Output
Capacitance
1. This parameter is guaranteed and not 100% tested.
2. –2.0V in case of AC pulse width less than 30 ns
n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
PARAMETER
PARAMETER
TEST CONDITIONS
MIN.
1.9
TYP.(1)
MAX.
UNITS
V
NAME
VCC
Power Supply
--
--
--
--
--
--
--
--
--
3.6
0.6
0.8
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
-0.3(2)
V
VIL
VIH
Input Low Voltage
1.4
2.0
Input High Voltage
VCC+0.3(3)
V
VIN = 0V to VCC
,
IIL
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
--
--
--
1
1
uA
uA
V
CE = VIH
VI/O = 0V to VCC
ILO
CE= VIH, or OE = VIH
VCC = Max, IOL = 0.1mA
VCC = Max, IOL = 2.0mA
VCC = Min, IOH = -0.1mA
VCC = Min, IOH = -1.0mA
CE = VIL,
0.2
0.4
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VOL
VOH
ICC
VCC-0.2
2.4
--
V
12
15
Operating Power Supply
Current
(4)
--
--
--
mA
mA
uA
IIO = 0mA, f = FMAX
CE = VIH,
IIO = 0mA
0.5
1.0
5.0
8.0
ICCSB
Standby Current – TTL
CE≧VCC-0.2V,
0.3
(5)
ICCSB1
Standby Current – CMOS
VIN≧VCC-0.2V or VIN≦0.2V
0.45
1. Typical characteristics are at TA=25OC.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. ICCSB1(MAX) is 3.0/6.0uA at VCC=2.0V/3.0V and TA=70OC.
R0201-BS616UV4016
Revision 1.3
Sep. 2005
3
BSI
BS616UV4016
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
PARAMETER
TEST CONDITIONS
CE≧VCC-0.2V,
MIN.
TYP. (1)
MAX.
UNITS
VDR
VCC for Data Retention
1.2
--
--
V
VIN≧VCC-0.2V or VIN≦0.2V
CE≧VCC-0.2V,
(3)
ICCDR
Data Retention Current
--
0
0.15
1.7
uA
VIN≧VCC-0.2V or VIN≦0.2V
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
tRC
1. VCC=1.2V, TA=25OC.
2. tRC = Read Cycle Time.
3. ICCRD_Max. is 1.2uA at TA=70OC.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled)
Data Retention Mode
V
DR≧1.0V
VCC
VCC
VCC
CE
tCDR
tR
CE≧VCC - 0.2V
VIH
VIH
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
1V/ns
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
Input and Output Timing
Reference Level
0.5Vcc
MAY CHANGE
WILL BE CHANGE
FROM “H” TO “L”
FROM “H” TO “L”
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
CL = 5pF+1TTL
CL = 30pF+1TTL
Output Load
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
VCC
1 TTL
90%
90%
Output
10%
10%
GND
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
(1)
®
¬
®
¬
DOES NOT
APPLY
CL
Rise Time:
1V/ns
Fall Time:
1V/ns
1. Including jig and scope capacitance.
R0201-BS616UV4016
Revision 1.3
4
Sep.
2005
BSI
BS616UV4016
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 85ns CYCLE TIME : 100ns
PARANETER
DESCRIPTION
Read Cycle Time
(VCC=1.9~3.6V)
(VCC=1.9~3.6V)
UNITS
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tAVQX
tELQV
tBLQV
tGLQV
tELQX
tBLQX
tGLQX
tEHQZ
tBHQZ
tGHQZ
tAVQX
tRC
tAA
85
--
--
--
--
--
--
--
--
--
--
--
--
--
--
85
85
40
40
--
100
--
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
50
50
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select Access Time
(CE)
tACS
--
--
(1)
Data Byte Control Access Time
(LB, UB)
tBA
--
--
tOE
tCLZ
tBE
Output Enable to Output Valid
Chip Select to Output Low Z
--
--
(CE)
15
15
15
--
15
15
15
--
Data Byte Control to Output Low Z (LB, UB)
Output Enable to Output Low Z
--
--
tOLZ
tCHZ
tBDO
tOHZ
tOH
--
--
Chip Select to Output High Z
(CE)
35
35
35
--
40
40
40
--
Data Byte Control to Output High Z (LB, UB)
--
--
Output Enable to Output High Z
Data Hold from Address Change
--
--
15
15
NOTE :
1. tBA is 40ns/50ns(@speed=85ns/100ns) with address toggle; tBA is 85ns/100ns(@speed=85ns/100ns) without address toggle
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
READ CYCLE 2 (1,3,4)
CE
tACS
tBA
tBE
LB, UB
DOUT
(5)
tCHZ
tBDO
(5)
tCLZ
R0201-BS616UV4016
Revision 1.3
5
Sep.
2005
BSI
BS616UV4016
READ CYCLE 3 (1, 4)
tRC
ADDRESS
OE
tAA
tOH
tOE
tOLZ
tACS
CE
(5)
tO(H1Z,5)
tCHZ
(5)
tCLZ
tBA
tBE
LB, UB
DOUT
tBDO
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BS616UV4016
Revision 1.3
Sep. 2005
6
BSI
BS616UV4016
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 85ns CYCLE TIME : 100ns
PARANETER
DESCRIPTION
Write Cycle Time
(VCC=1.9~3.6V)
(VCC=1.9~3.6V)
UNITS
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tAVWL
tAVWH
tELWH
tBLWH
tWLWH
tWHAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
tAS
tAW
tCW
85
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
100
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Set up Time
Address Valid to End of Write
Chip Select to End of Write
85
85
35
40
0
--
100
100
40
50
0
--
(CE)
--
--
(1)
Data Byte Control to End of Write
(LB, UB)
tBW
--
--
tWP
tWR
tWHZ
tDW
tDH
Write Pulse Width
--
--
Write Recovery Time
(CE, WE)
--
--
Write to Output High Z
--
35
--
--
40
--
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
35
0
40
0
--
--
tOHZ
tOW
--
35
--
--
40
--
10
10
NOTE:
1. tBW is 35ns/40ns (@speed=85ns/100ns) with address toggle; tBW is 85ns/100ns (@speed=85ns/100ns) without address toggle.
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
OE
(11)
tCW
(5)
CE
tBW
LB, UB
(3)
tWR
tAW
(2)
tWP
WE
tAS
(4,10)
tOHZ
DOUT
tDH
tDW
DIN
R0201-BS616UV4016
Revision 1.3
7
Sep.
2005
BSI
BS616UV4016
WRITE CYCLE 2 (1,6)
tWC
ADDRESS
(11)
tCW
(5)
CE
tBW
LB, UB
WE
(3)
tAW
tWR
(2)
tWP
tAS
(4,10)
tWHZ
(7)
(8)
tOW
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be
active to initiate a write and any one signal can terminate a write by going inactive. The data input
setup and hold timing should be referenced to the second transition edge of the signal that terminates
the write.
3. tWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, IO pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition,
output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, IO pins are in the output state. Then the data input signals of opposite
phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.t CW is measured from the later of CE going low to the end of write.
R0201-BS616UV4016
Revision 1.3
Sep. 2005
8
BSI
BS616UV4016
n ORDERING INFORMATION
BS616UV4016 X
X
Z Y Y
SPEED
85: 85ns
10: 100ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I : -40oC ~ +85oC
PACKAGE
D: DICE
E: TSOP 2-44
A: BGA-48-0608
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not
authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in
significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
NOTES
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
D1
VIEW A
48 mini-BGA (6 x 8mm)
R0201-BS616UV4016
Revision 1.3
Sep. 2005
9
BSI
BS616UV4016
n PACKAGE DIMENSIONS (continued)
TSOP2-44
R0201-BS616UV4016
Revision 1.3
10
Sep.
2005
相关型号：
©2020 ICPDF网 联系我们和版权申明