BS616UV2019DC85 [BSI]
Ultra Low Power CMOS SRAM 128K X 16 bit; 超低功耗CMOS SRAM 128K ×16位
| 型号： | BS616UV2019DC85 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Ultra Low Power CMOS SRAM 128K X 16 bit |
| 文件： | 总11页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power CMOS SRAM
128K X 16 bit
BS616UV2019
Pb-Free and Green package materials are compliant to RoHS
n FEATURES
ŸWide VCC low operation voltage :
n DESCRIPTION
The BS616UV2019 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 131,072 by 16 bits and
operates form a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.2uA at 2.0V/25OC and maximum access time of 85ns at
85OC.
C-grade : 1.8V ~ 3.6V
I-grade : 1.9V ~ 3.6V
ŸUltra low power consumption :
VCC = 2.0V
Operation current : 10mA (Max.) at 85ns
1mA (Max.) at 1MHz
Standby current : 0.2uA (Typ.) at 25OC
Operation current : 13mA (Max.) at 85ns
2mA (Max.) at 1MHz
VCC = 3.0V
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
Standby current : 0.3uA (Typ.) at 25OC
ŸHigh speed access time :
-85
-10
85ns (Max.)
100ns (Max.)
The BS616UV2019 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616UV2019 is available in DICE form, JEDEC standard
48-pin TSOP Type I package and 48-ball BGA package.
ŸAutomatic power down when chip is deselected
ŸEasy expansion with CE and OE options
ŸI/O Configuration x8/x16 selectable by LB and UB pin.
ŸThree state outputs and TTL compatible
ŸFully static operation
ŸData retention supply voltage as low as 1.5V
n POWER CONSUMPTION
POWER DISSIPATION
Operating
STANDBY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
1MHz
fMax.
1MHz
fMax.
BS616UV2019DC
BS616UV2019AC
BS616UV2019TC
BS616UV2019AI
BS616UV2019TI
DICE
Commercial
3.0uA
5.0uA
2.0uA
1.5mA
2.0mA
11mA
0.8mA
1.0mA
8mA
BGA-48-0608
TSOP I-48
BGA-48-0608
TSOP I-48
+0OC to +70OC
Industrial
3.0uA
13mA
10mA
-40OC to +85OC
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
A6
A7
A8
A9
A10
A11
A15
A14
A13
A12
Address
Input
1024
Memory Array
10
A8
8
Row
NC
NC
WE
CE2
NC
UB
LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Decoder
Buffer
1024 x 2048
BS616UV2019TC
BS616UV2019TI
2048
DQ0
Data
Input
Buffer
16
16
Column I/O
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
.
GND
CE
A0
16
.
16
Data
Output
Buffer
.
.
128
1
2
3
4
5
6
Column Decoder
DQ15
A
B
C
D
E
F
LB
OE
A0
A1
A2
NC
7
CE2,CE
WE
D8
D9
UB
D10
D11
D12
D13
NC
A3
A5
A4
A6
CE
D1
D0
D2
Address Input Buffer
OE
Control
UB
LB
A16 A0 A1 A2 A3 A4 A5
VSS
VCC
D14
D15
NC
NC
NC
A14
A12
A9
A7
D3
VCC
VSS
D6
VCC
VSS
A16
A15
A13
A10
D4
D5
G
H
WE
A11
D7
A8
NC
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS616UV2019
Revision 1.3
May. 2006
1
BS616UV2019
n PIN DESCRIPTIONS
Name
Function
These 17 address inputs select one of the 262,144 x 16 bit in the RAM
A0-A16 Address Input
CE is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected. (48B BGA ignore CE2 pin)
CE Chip Enable 1 Input
CE2 Chip Enable 2 Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
WE Write Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
OE Output Enable Input
LB and UB Data Byte Control Input
16 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ15 Data Input/Output
Ports
VCC
Power Supply
Ground
VSS
n TRUTH TABLE
MODE
CE2(1)
DQ0~DQ7 DQ8~DQ15 VCC CURRENT
CE
H
WE
X
OE
X
LB
X
X
H
L
UB
X
X
H
X
L
X
L
High Z
High Z
High Z
High Z
High Z
DOUT
High Z
High Z
High Z
High Z
High Z
DOUT
ICCSB, ICCSB1
Chip De-selected
(Power Down)
X
X
X
ICCSB, ICCSB1
X
X
H
H
X
X
ICCSB, ICCSB1
L
H
H
ICC
ICC
ICC
ICC
ICC
ICC
ICC
ICC
Output Disabled
Read
L
H
H
X
L
L
L
L
H
H
H
L
L
H
L
L
High Z
DOUT
DOUT
H
L
High Z
DIN
L
DIN
Write
X
H
L
L
X
DIN
H
DIN
X
1. 48BGA ignore CE2 condition.
2. H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
Revision 1.3
R0201-BS616UV2019
2
May.
2006
BS616UV2019
n ABSOLUTE MAXIMUM RATINGS (1)
n OPERATING RANGE
AMBIENT
TEMPERATURE
0OC to + 70OC
SYMBOL
VTERM
TBIAS
PARAMETER
RATING
-0.5(2) to 5.0
-40 to +125
-60 to +150
1.0
UNITS
V
RANG
VCC
Terminal Voltage with
Respect to GND
Commercial
Industrial
1.8V ~ 3.6V
1.9V ~ 3.6V
Temperature Under
Bias
OC
-40OC to + 85OC
TSTG
Storage Temperature
Power Dissipation
DC Output Current
OC
PT
W
n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
IOUT
20
mA
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
Input
Capacitance
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CIN
CIO
VIN = 0V
VI/O = 0V
6
8
pF
pF
Input/Output
Capacitance
1. This parameter is guaranteed and not 100% tested.
2. –2.0V in case of AC pulse width less than 30 ns.
n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
PARAMETER
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
NAME
Power Supply
1.9
--
3.6
V
VCC
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
0.6
0.8
Input Low Voltage
-0.3(2)
--
--
--
--
--
--
--
--
--
V
V
VIL
VIH
IIL
1.4
2.2
Input High Voltage
VCC+0.3(3)
VIN = 0V to VCC
CE= VIH or CE2(7) = VIL
VI/O = 0V to VCC
CE= VIH or CE2(7) = VIL or OE = VIH
VCC = Max, IOL = 0.1mA
VCC = Max, IOL = 2.0mA
VCC = Min, IOH = -0.1mA
VCC = Min, IOH = -1.0mA
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
--
--
--
1
1
uA
uA
V
,
ILO
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
0.2
0.4
VOL
VOH
1.6
2.4
--
V
CE = VIL and CE2(7) = VIH,
10
13
Operating Power Supply
Current
(5)
ICC
--
--
--
--
mA
mA
mA
uA
(4)
IIO = 0mA, f = FMAX
CE = VIL and CE2(7) = VIH,
1.0
2.0
0.5
1.0
3.0
5.0
Operating Power Supply
Current
ICC1
IIO = 0mA, f = 1MHz
CE = VIH or CE2(7) = VIL,
IIO = 0mA
Standby Current – TTL
ICCSB
CE≧VCC-0.2V or CE2(7)≦0.2V,
0.2
0.3
(6)
Standby Current – CMOS
ICCSB1
VIN≧VCC-0.2V or VIN≦0.2V
1. Typical characteristics are at TA=25OC and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. ICC (MAX.) is 8mA/11mA at VCC=2.0V/3.0V and TA=70OC.
6. ICCSB1(MAX.) is 2.0uA/3.0uA at VCC=2.0V/3.0V and TA=70OC.
7. 48B BGA ignore CE2 condition.
Revision 1.3
May. 2006
R0201-BS616UV2019
3
BS616UV2019
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
VDR
PARAMETER
VCC for Data Retention
Data Retention Current
TEST CONDITIONS
MIN.
1.5
--
TYP. (1)
MAX.
UNITS
CE≧VCC-0.2V or CE2(4)≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
--
0.1
--
--
1.0
--
V
CE≧VCC-0.2V or CE2(4)≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
(3)
ICCDR
uA
ns
ns
Chip Deselect to Data
Retention Time
tCDR
0
See Retention Waveform
(2)
tR
Operation Recovery Time
tRC
--
--
1. VCC=1.5V, TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
3. ICCDR(Max.) is 0.7uA at TA=70OC.
4. 48B BGA ignore CE2 condition
n LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled)
Data Retention Mode
V
DR≧1.5V
VCC
VCC
VCC
CE
tCDR
tR
CE≧VCC - 0.2V
VIH
VIH
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
DR≧1.5V
VCC
VCC
tCDR
tR
CE2≦0.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
1V/ns
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
Input and Output Timing
Reference Level
0.5Vcc
MAY CHANGE
WILL BE CHANGE
FROM “H” TO “L”
FROM “H” TO “L”
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
CL = 5pF+1TTL
CL = 30pF+1TTL
Output Load
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
VCC
1 TTL
90%
90%
Output
10%
10%
GND
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
DOES NOT
APPLY
(1)
®
¬
®
¬
CL
Rise Time:
1V/ns
Fall Time:
1V/ns
1. Including jig and scope capacitance.
Revision 1.3
R0201-BS616UV2019
4
May.
2006
BS616UV2019
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
CYCLE TIME : 85ns CYCLE TIME : 100ns
(VCC=1.9~3.6V) (VCC=1.9~3.6V)
MIN. TYP. MAX. MIN. TYP. MAX.
JEDEC
PARAMETER
NAME
PARANETER
DESCRIPTION
UNITS
NAME
tAVAX
tAVQX
tELQV1
tELQV2
tBLQV
tGLQV
tELQX1
tELQX2
tBLQX
tGLQX
tEHQZ1
tEHQZ2
tBHQZ
tGHQZ
tAVQX
tRC
tAA
Read Cycle Time
85
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
85
85
85
85
40
--
100
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
100
100
50
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select Access Time
(CE)
tACS1
tACS2
tBA
--
--
Chip Select Access Time
(CE2)
--
--
Data Byte Control Access Time
(LB, UB)
--
--
tOE
Output Enable to Output Valid
Chip Select to Output Low Z
--
--
(CE)
tCLZ1
tCLZ2
tBE
15
15
15
15
15
--
Chip Select to Output Low Z
(CE2) 15
--
--
Data Byte Control to Output Low Z (LB, UB)
Output Enable to Output Low Z
15
15
--
--
--
tOLZ
tCHZ1
tCHZ2
tBDO
tOHZ
tOH
--
--
Chip Select to Output High Z
Chip Select to Output High Z
(CE)
35
35
35
30
--
40
40
40
35
--
(CE2)
--
--
Data Byte Control to Output High Z (LB, UB)
Output Enable to Output High Z
--
--
--
--
Data Hold from Address Change
15
15
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
Revision 1.3
May. 2006
R0201-BS616UV2019
5
BS616UV2019
READ CYCLE 2 (1,3,4)
CE
tACS1
CE2
DOUT
(6)
tACS2
(5, 6)
tCHZ
(5,6)
tCLZ
READ CYCLE 3 (1, 4)
tRC
ADDRESS
OE
tAA
tOH
tOE
tOLZ
tACS1
CE
(5)
tOHZ
CE2
(6)
tACS2
(5,6)
(1,5,6)
tCLZ
tCHZ
tBA
tBE
LB, UB
DOUT
tBDO
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
6. 48B BGA ignore this parameters related to CE2.
Revision 1.3
May. 2006
R0201-BS616UV2019
6
BS616UV2019
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
CYCLE TIME : 85ns CYCLE TIME : 100ns
(VCC=1.9~3.6V) (VCC=1.9~3.6V)
MIN. TYP. MAX. MIN. TYP. MAX.
JEDEC
PARAMETER
NAME
PARANETER
DESCRIPTION
UNITS
NAME
tAVAX
tAVWL
tAVWH
tELWH
tBLWH
tWLWH
tWHAX1
tWHAX2
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
tAS
Write Cycle Time
85
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
100
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Set up Time
tAW
tCW
tBW
tWP
tWR1
tWR2
tWHZ
tDW
tDH
Address Valid to End of Write
Chip Select to End of Write
Data Byte Control to End of Write
85
85
50
40
0
--
100
100
70
50
0
--
--
--
(LB, UB)
--
--
Write Pulse Width
--
--
Write Recovery Time
(CE, WE)
(CE2)
--
--
Write Recovery Time
0
--
0
--
Write to Output High Z
--
35
--
--
40
--
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
35
0
40
0
--
--
tOHZ
tOW
--
35
--
--
40
--
10
10
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
OE
(3)
tWR1
(11)
tCW
(5)
CE
(5,12)
CE2
(11)
tCW
(3)
tWR2
tBW
LB, UB
tAW
(2)
tWP
WE
tAS
(4,10)
tOHZ
DOUT
tDH
tDW
DIN
Revision 1.3
May. 2006
R0201-BS616UV2019
7
BS616UV2019
WRITE CYCLE 2 (1,6)
ADDRESS
tWC
(11)
tCW
(5)
CE
CE2
(5,12)
(5)
tBW
LB, UB
WE
(3)
tAW
tWR
(2)
tWP
tAS
(4,10)
tWHZ
(7)
(8)
tOW
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and CE2 active and WE
low. All signals must be active to initiate a write and any one signal can terminate a write by
going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low and CE2 is high during this period, DQ pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.t CW is measured from the later of CE going low or CE2 going high to the end of write.
12.48B BGA ignore this parameters related to CE2.
Revision 1.3
R0201-BS616UV2019
8
May.
2006
BS616UV2019
n ORDERING INFORMATION
BS616UV2019 X
X
Z Y Y
SPEED
85: 85ns
10: 100ns
PKG MATERIAL
-: Normal
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
D: DICE
A: BGA-48-0608
T: TSOP I-48
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
UNIT
SYMBO
HD
INCH
MM
12°(2X)
12°(2X)
A
0.0433±0.004
0.004±0.002
0.039±0.002
0.009±0.002
1.10±0.10
0.10±0.05
1.00±0.05
0.22±0.05
0.20±0.03
0.10 ~ 0.21
0.10 ~ 0.16
16.40±0.10
11.80±0.10
0.50±0.10
18.00±0.20
0.60±0.15
0.80±0.10
0.1 Max.
A1
A2
b
1
e
4
b1 0.008±0.001
0.004 ~ 0.008
c1 0.004 ~ 0.006
D
E
e
c
b
E
0.645±0.004
0.472±0.004
0.020±0.004
HD 0.708±0.008
L
0.0236±0.006
0.0315±
12°(2x)
2
2
L1
y
θ
Seating
y
0.004 Max.
0°~8°
"A"
0°~8°
D
A2
A1
A
GAUGE PLANE
A
θ
2
2
SEATING PLANE
"A" DETAIL VIEW
A
12°(2x)
L
b
L1
WITH PLATING
c
c
BASE METAL
b1
SECTION A-A
4
1
TSOP I-48 Pin
Revision 1.3
May. 2006
R0201-BS616UV2019
9
BS616UV2019
n PACKAGE DIMENSIONS (continued)
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
D1
VIEW A
48 mini-BGA (6 x 8mm)
Revision 1.3
May. 2006
R0201-BS616UV2019
10
BS616UV2019
n Revision History
Revision No.
History
Draft Date
Remark
1.2
1.3
Add Icc1 characteristic parameter
Jan. 13, 2006
May. 25, 2006
Change I-grade operation temperature range
- from –25OC to –40OC
Revision 1.3
R0201-BS616UV2019
11
May.
2006
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