BS616LV8016DCG55_技术文档

Very Low Power CMOS SRAM

512K X 16 bit

BS616LV8016

Pb-Free and Green package materials are compliant to RoHS

n FEATURES

ŸWide V_CCoperation voltage : 2.4V ~ 5.5V

n DESCRIPTION

The BS616LV8016 is a high performance, very low power CMOS

Static Random Access Memory organized as 524,288 by 16 bits and

operates form a wide range of 2.4V to 5.5V supply voltage.

Advanced CMOS technology and circuit techniques provide both

high speed and low power features with typical CMOS standby

current of 0.8uA at 3.0V/25^OC and maximum access time of 55ns at

3.0V/85^OC.

ŸVery low power consumption :

V_CC= 3.0V

V_CC= 5.0V

Operation current : 31mA (Max.) at 55ns

2mA (Max.) at 1MHz

Standby current : 0.8uA (Typ.) at 25^OC

Operation current : 76mA (Max.) at 55ns

10mA (Max.) at 1MHz

Standby current : 3.5uA (Typ.) at 25^OC

ŸHigh speed access time :

Easy memory expansion is provided by an active LOW chip enable

(CE1), active HIGH chip enable (CE2) and active LOW output

enable (OE) and three-state output drivers.

-55

-70

55ns(Max.) at V_CC=3.0~5.5V

70ns(Max.) at V_CC=2.7~5.5V

ŸAutomatic power down when chip is deselected

ŸEasy expansion with CE2, CE1 and OE options

ŸI/O Configuration x8/x16 selectable by LB and UB pin.

ŸThree state outputs and TTL compatible

The BS616LV8016 has an automatic power down feature, reducing

the power consumption significantly when chip is deselected.

The BS616LV8016 is available in DICE form and 48-ball BGA

package.

ŸFully static operation, no clock, no refresh

ŸData retention supply voltage as low as 1.5V

n POWER CONSUMPTION

POWER DISSIPATION

Operating

STANDBY

PRODUCT

FAMILY

OPERATING

TEMPERATURE

PKG TYPE

(I_CCSB1, Max)

(I_CC, Max)

V_CC=5.0V

10MHz

V_CC=3.0V

10MHz

V_CC=5.0V V_CC=3.0V

1MHz

9mA

f_Max.

1MHz

f_Max.

BS616LV8016DC

BS616LV8016FC

DICE

Commercial

25uA

50uA

4.0uA

8.0uA

39mA

40mA

75mA

1.5mA

19mA

20mA

30mA

+0^OC to +70^OC

BGA-48-0912

Industrial

BS616LV8016FI

10mA

76mA

2mA

31mA

BGA-48-0912

-40^OC to +85^OC

n PIN CONFIGURATIONS

n BLOCK DIAGRAM

1

2

3

4

5

6

A13

A12

A11

A

B

C

D

E

F

LB

OE

A0

A1

A2

CE2

DQ0

DQ2

VCC

VSS

DQ6

DQ7

NC

A10

A9

A8

A7

A6

A5

A4

Address

Input

1024

Memory Array

10

Row

Decoder

Buffer

1024 x 8192

DQ8

DQ9

VSS

UB

A3

A5

A4

A6

CE1

DQ1

DQ3

DQ4

DQ5

WE

DQ10

DQ11

8192

DQ0

Column I/O

16

A17

VSS

A14

A12

A9

A7

Data

Input

Buffer

.

Write Driver

Sense Amp

.

16

.

VCC DQ12

DQ14 DQ13

A16

A15

A13

A10

Data

Output

Buffer

.

512

Column Decoder

DQ15

9

CE2

CE1

WE

OE

UB

G

H

DQ15

A18

NC

A8

Address Input Buffer

Control

A11

LB

A14 A15 A16 A17 A18 A0 A1 A2 A3

V_CC

V_SS

48-ball BGA top view

Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.

R0201-BS616LV8016

Revision 2.3

May. 2006

1

BS616LV8016

n PIN DESCRIPTIONS

Name

Function

These 19 address inputs select one of the 524,288 x 16 bit in the RAM

A0-A18 Address Input

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when

data read form or write to the device. If either chip enable is not active, the device is

deselected and is in standby power mode. The DQ pins will be in the high impedance

state when the device is deselected.

CE1 Chip Enable 1 Input

CE2 Chip Enable 2 Input

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

WE Write Enable Input

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impendence state when OE is inactive.

Lower byte and upper byte data input/output control pins.

OE Output Enable Input

LB and UB Data Byte Control Input

16 bi-directional ports are used to read data from or write data into the RAM.

DQ0-DQ15 Data Input/Output

Ports

V_CC

Power Supply

Ground

V_SS

n TRUTH TABLE

MODE

CE2

DQ0~DQ7 DQ8~DQ15 V_CCCURRENT

CE1

WE

X

OE

X

LB

X

H

L

UB

X

H

X

L

H

X

L

X

L

High Z

D_OUT

High Z

D_OUT

I_CCSB, I_CCSB1

Chip De-selected

(Power Down)

X

I_CCSB, I_CCSB1

X

H

X

I_CCSB, I_CCSB1

H

I_CC

Output Disabled

Read

L

H

X

L

H

L

H

L

High Z

D_OUT

H

L

High Z

D_IN

L

D_IN

Write

X

H

L

X

D_IN

H

D_IN

X

NOTES: H means V_IH; L means V_IL; X means don’t care (Must be V_IHor V_ILstate)

Revision 2.3

R0201-BS616LV8016

2

May.

2006

BS616LV8016

n ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

n OPERATING RANGE

AMBIENT

TEMPERATURE

0^OC to + 70^OC

SYMBOL

V_TERM

T_BIAS

PARAMETER

RATING

-0.5⁽²⁾to 7.0

-40 to +125

-60 to +150

1.0

UNITS

V

RANG

V_CC

Terminal Voltage with

Respect to GND

Commercial

Industrial

2.4V ~ 5.5V

Temperature Under

Bias

^OC

-40^OC to + 85^OC

T_STG

Storage Temperature

Power Dissipation

DC Output Current

^OC

P_T

W

n CAPACITANCE ⁽¹⁾(T_A= 25^OC, f = 1.0MHz)

I_OUT

20

mA

SYMBOL PAMAMETER CONDITIONS MAX. UNITS

Input

Capacitance

1. Stresses greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage to the

device. This is a stress rating only and functional operation of

the device at these or any other conditions above those

indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

C_IN

C_IO

V_IN= 0V

V_I/O= 0V

6

8

pF

Input/Output

Capacitance

1. This parameter is guaranteed and not 100% tested.

2. –2.0V in case of AC pulse width less than 30 ns.

n DC ELECTRICAL CHARACTERISTICS (T_A= -40^OC to +85^OC)

PARAMETER

TEST CONDITIONS

MIN.

2.4

-0.5⁽²⁾

2.2

--

TYP.⁽¹⁾

MAX.

UNITS

V

NAME

V_CC

Power Supply

--

5.5

V_IL

V_IH

I_IL

Input Low Voltage

0.8

V

Input High Voltage

V_CC+0.3⁽³⁾

V

V_IN= 0V to V_CC

,

Input Leakage Current

Output Leakage Current

Output Low Voltage

Output High Voltage

1

uA

V

CE1 = V_IHor CE2 = V_IL

V_I/O= 0V to V_CC,

I_LO

--

CE1 = V_IHor CE2 = V_ILor OE = V_IH

V_OL

V_OH

V_CC= Max, I_OL= 2.0mA

--

0.4

--

V_CC= Min, I_OH= -1.0mA

CE1 = V_ILand CE2 = V_IH,

2.4

--

V

V_CC=3.0V

V_CC=5.0V

V_CC=3.0V

V_CC=5.0V

V_CC=3.0V

V_CC=5.0V

V_CC=3.0V

V_CC=5.0V

31

76

2

Operating Power Supply

Current

(5)

I_CC

mA

uA

(4)

I_DQ= 0mA, f = F_MAX

CE1 = V_ILand CE2 = V_IH,

I_DQ= 0mA, f = 1MHz

Operating Power Supply

Current

I_CC1

--

10

1.0

2.0

8.0

50

CE1 = V_IH, or CE2 = V_IL,

I_DQ= 0mA

I_CCSB

Standby Current – TTL

--

0.8

3.5

CE1≧V_CC-0.2V or CE2≦0.2V,

V_IN≧V_CC-0.2V or V_IN≦0.2V

(6)

I_CCSB1

Standby Current – CMOS

--

1. Typical characteristics are at T_A=25^OC and not 100% tested.

2. Undershoot: -1.0V in case of pulse width less than 20 ns.

3. Overshoot: V_CC+1.0V in case of pulse width less than 20 ns.

4. F_MAX=1/t_RC.

5. I_{CC (MAX.)}is 30mA/75mA at V_CC=3.0V/5.0V and T_A=70^OC.

6. I_CCSB1(MAX.)is 4.0uA/25uA at V_CC=3.0V/5.0V and T_A=70^OC.

Revision 2.3

May. 2006

R0201-BS616LV8016

3

BS616LV8016

n DATA RETENTION CHARACTERISTICS (T_A= -40^OC to +85^OC)

SYMBOL

V_DR

PARAMETER

V_CCfor Data Retention

Data Retention Current

TEST CONDITIONS

MIN.

1.5

--

TYP. ⁽¹⁾

MAX.

UNITS

CE1≧V_CC-0.2V or CE2≦0.2V,

VIN≧V_CC-0.2V or VIN≦0.2V

CE1≧V_CC-0.2V or CE2≦0.2V,

VIN≧V_CC-0.2V or VIN≦0.2V

--

0.4

--

4.0

--

V

(3)

I_CCDR

uA

ns

Chip Deselect to Data

Retention Time

t_CDR

0

See Retention Waveform

(2)

t_R

Operation Recovery Time

t_RC

--

1. V_CC=1.5V, T_A=25^OC and not 100% tested.

2. t_RC= Read Cycle Time.

3. I_CCDR(Max.)is 2.0uA at T_A=70^OC.

n LOW V_CCDATA RETENTION WAVEFORM (1) (CE1 Controlled)

Data Retention Mode

V

_DR≧1.5V

V_CC

t_CDR

t_R

CE1≧V_CC- 0.2V

V_IH

CE1

n LOW V_CCDATA RETENTION WAVEFORM (2) (CE2 Controlled)

Data Retention Mode

V

_DR≧1.5V

V_CC

t_CDR

t_R

CE2≦0.2V

CE2

V_IL

n AC TEST CONDITIONS

n KEY TO SWITCHING WAVEFORMS

(Test Load and Input/Output Reference)

WAVEFORM

INPUTS

OUTPUTS

Input Pulse Levels

Vcc / 0V

1V/ns

MUST BE

STEADY

MUST BE

STEADY

Input Rise and Fall Times

Input and Output Timing

Reference Level

0.5Vcc

MAY CHANGE

WILL BE CHANGE

FROM “H” TO “L”

t_CLZ, t_OLZ, t_CHZ, t_OHZ, t_WHZ

C_L= 5pF+1TTL

C_L= 30pF+1TTL

Output Load

Others

MAY CHANGE

WILL BE CHANGE

FROM “L” TO “H”

ALL INPUT PULSES

DON’T CARE

ANY CHANGE

PERMITTED

CHANGE :

STATE UNKNOW

V_CC

1 TTL

90%

Output

10%

GND

CENTER LINE IS

HIGH INPEDANCE

“OFF” STATE

DOES NOT

APPLY

(1)

®

¬

®

¬

C_L

Rise Time:

1V/ns

Fall Time:

1V/ns

1. Including jig and scope capacitance.

Revision 2.3

R0201-BS616LV8016

4

May.

2006

BS616LV8016

n AC ELECTRICAL CHARACTERISTICS (T_A= -40^OC to +85^OC)

READ CYCLE

CYCLE TIME : 55ns CYCLE TIME : 70ns

(V_CC=3.0~5.5V) (V_CC=2.7~5.5V)

JEDEC

PARAMETER

NAME

PARANETER

DESCRIPTION

UNITS

NAME

MIN. TYP. MAX. MIN. TYP. MAX.

t_AVAX

t_AVQX

t_ELQV

t_BLQV

t_GLQV

t_ELQX

t_BLQX

t_GLQX

t_EHQZ

t_BHQZ

t_GHQZ

t_AVQX

t_RC

t_AA

Read Cycle Time

55

--

55

30

--

70

--

70

35

--

ns

Address Access Time

Chip Select Access Time

Data Byte Control Access Time

(CE1)

(CE2)

t_ACS1

t_ACS2

t_BA

--

(LB, UB)

--

t_OE

Output Enable to Output Valid

Chip Select to Output Low Z

--

(CE1)

(CE2)

t_CLZ1

t_CLZ2

t_BE

10

5

10

5

--

Data Byte Control to Output Low Z (LB, UB)

Output Enable to Output Low Z

--

t_OLZ

t_CHZ1

t_CHZ2

t_BDO

t_OHZ

t_OH

--

Chip Select to Output High Z

(CE1)

(CE2)

--

30

25

--

35

30

--

Data Byte Control to Output High Z (LB, UB)

Output Enable to Output High Z

--

Data Hold from Address Change

10

n SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE 1 ^(1,2,4)

t_RC

ADDRESS

t_AA

t_OH

D_OUT

Revision 2.3

May. 2006

R0201-BS616LV8016

5

BS616LV8016

READ CYCLE 2 ^(1,3,4)

CE1

t_ACS1

CE2

D_OUT

t_ACS2

(5)

t_CHZ

(5)

t_CLZ

READ CYCLE 3 ^{(1, 4)}

ADDRESS

t_RC

t_AA

OE

t_OH

t_OE

t_OLZ

CE1

(5)

t_ACS1

t_OHZ

t_CHZ

(5)

(1,5)

t_CLZ1

CE2

t_ACS2

(5)

(2,5)

t_CLZ2

t_CHZ2

t_BA

t_BE

LB, UB

D_OUT

t_BDO

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = V_ILand CE2= V_IH.

3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.

4. OE = V_IL.

5. Transition is measured ± 500mV from steady state with C_L= 5pF.

The parameter is guaranteed but not 100% tested.

Revision 2.3

R0201-BS616LV8016

6

May.

2006

BS616LV8016

n AC ELECTRICAL CHARACTERISTICS (T_A= -40^OC to +85^OC)

WRITE CYCLE

CYCLE TIME : 55ns CYCLE TIME : 70ns

(V_CC=3.0~5.5V) (V_CC=2.7~5.5V)

MIN. TYP. MAX. MIN. TYP. MAX.

JEDEC

PARAMETER

NAME

PARANETER

DESCRIPTION

UNITS

NAME

t_AVAX

t_AVWL

t_AVWH

t_ELWH

t_BLWH

t_WLWH

t_WHAX

t_WLQZ

t_DVWH

t_WHDX

t_GHQZ

t_WHQX

t_WC

t_AS

Write Cycle Time

55

0

--

70

0

--

ns

Address Set up Time

t_AW

t_CW

t_BW

t_WP

t_WR1

t_WR2

t_WHZ

t_DW

t_DH

Address Valid to End of Write

Chip Select to End of Write

Data Byte Control to End of Write

55

25

30

0

--

70

30

35

0

--

(LB, UB)

--

Write Pulse Width

--

Write Recovery Time

(CE1, WE)

(CE2)

--

Write Recovery Time

0

--

0

--

Write to Output High Z

--

25

--

30

--

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

25

0

30

0

--

t_OHZ

t_OW

--

25

--

30

--

5

n SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE 1 ⁽¹⁾

t_WC

ADDRESS

OE

(3)

t_WR1

(11)

t_CW

(5)

CE1

CE2

(11)

t_CW

(3)

t_WR2

t_BW

LB, UB

t_AW

(2)

t_WP

WE

t_AS

(4,10)

t_OHZ

D_OUT

t_DH

t_DW

D_IN

Revision 2.3

May. 2006

R0201-BS616LV8016

7

BS616LV8016

WRITE CYCLE 2 ^(1,6)

ADDRESS

t_WC

(11)

t_CW

(5)

CE1

CE2

(11)

t_CW

t_BW

(3)

t_WR

(12)

LB, UB

WE

t_AW

(2)

t_WP

t_AS

(4,10)

t_WHZ

(7)

(8)

t_OW

D_OUT

t_DW

t_DH

(8,9)

D_IN

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and

WE low. All signals must be active to initiate a write and any one signal can terminate a

write by going inactive. The data input setup and hold timing should be referenced to the

second transition edge of the signal that terminates the write.

3. t_WRis measured from the earlier of CE1 or WE going high or CE2 going low at the end of

write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite

phase to the outputs must not be applied.

5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low

transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V_IL).

7. D_OUTis the same phase of write data of this write cycle.

8. D_OUTis the read data of next address.

9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the

data input signals of opposite phase to the outputs must not be applied to them.

10.Transition is measured ± 500mV from steady state with C_L= 5pF.

The parameter is guaranteed but not 100% tested.

11.t _CWis measured from the later of CE1 going low or CE2 going high to the end of write.

12.The change of Read/Write cycle must accompany with CE or address toggled.

Revision 2.3

R0201-BS616LV8016

8

May.

2006

BS616LV8016

n ORDERING INFORMATION

BS616LV8016

X

Z Y Y

SPEED

55: 55ns

70: 70ns

PKG MATERIAL

-: Normal

G: Green, RoHS Compliant

P: Pb free, RoHS Compliant

GRADE

C: +0^oC ~ +70^oC

I: -40^oC ~ +85^oC

PACKAGE

D: DICE

F: BGA-48-0912

Note:

BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does

not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result

in significant injury or death, including life-support systems and critical medical instruments.

n PACKAGE DIMENSIONS

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.

3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

SIDE VIEW

D

0.1

N

D

E

D1

E1

e

D1

48

12.0

9.0

5.25

3.75

0.75

3.375

SOLDER BALL 0.35 ±0.05

VIEW A

48 mini-BGA (9mm x 12mm)

Revision 2.3

R0201-BS616LV8016

9

May.

2006

BS616LV8016

n Revision History

Revision No.

2.2

History

Draft Date

Remark

Add Icc1 characteristic parameter

Improve Iccsb1 spec.

Jan. 13, 2006

I-grade from 110uA to 50uA at 5.0V

10uA to 8.0uA at 3.0V

C-grade from 55uA to 25uA at 5.0V

5.0uA to 4.0uA at 3.0V

2.3

Change I-grade operation temperature range

May. 25, 2006

- from –25^OC to –40^OC

Revision 2.3

R0201-BS616LV8016

10

May.

2006


型号：	BS616LV8016DCG55
厂家：	BRILLIANCE SEMICONDUCTOR
描述：	Very Low Power CMOS SRAM 512K X 16 bit 超低功耗CMOS SRAM 512K ×16位静态存储器
文件：	总10页 (文件大小：155K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BS616LV8016DCG55 [BSI]

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