BS616LV4016DC-55 [BSI]
Very Low Power/Voltage CMOS SRAM 256K X 16 bit; 非常低的功率/电压CMOS SRAM 256K ×16位
| 型号： | BS616LV4016DC-55 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power/Voltage CMOS SRAM 256K X 16 bit |
| 文件： | 总10页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
BSI 256K X 16 bit
• Wide Vcc operation voltage : 2.4V ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 25mA (@55ns) operating current
I -grade: 27mA (@55ns) operating current
C-grade: 17mA (@70ns) operating current
I -grade: 18mA (@70ns) operating current
0.45uA (Typ.) CMOS standby current
• High speed access time :
55ns (Max.) at Vcc = 2.7~3.6V / 85oC
70ns (Max.) at Vcc = 2.4~3.6V / 85oC
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
BS616LV4016
• Easy expansion with CE and OE options
FEATURES
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV4016 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.45uA at 3.0V/25oC and maximum access time of 55ns at 2.7V/85oC.
Easy memory expansion is provided by an active LOW chip enable (CE)
,active LOW output enable(OE) and three-state output drivers.
The BS616LV4016 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
-55
-70
The BS616LV4016 is available in DICE form , JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.
• Data retention supply voltage as low as 1.5V
PRODUCT FAMILY
POWER DISSIPATION
SPEED
Operating
STANDBY
(
ns )
OPERATING
PRODUCT FAMILY
Vcc
RANGE
( ICCSB1 , Max )
( I CC , Max )
PKG TYPE
TEMPERATURE
55ns: 2.7~3.6V
70ns: 2.4~3.6V
Vcc =
Vcc = 3.0V
3.0V
55ns
70ns
BS616LV4016DC
BS616LV4016EC
DICE
+0O C to +70O
C
TSOP2-44
BGA-48-0608
DICE
2.4V ~ 3.6V
2.4V ~ 3.6V
55 / 70
55 / 70
25mA
27mA
17mA
6.0uA
8.0uA
BS616LV4016AC
BS616LV4016DI
-40O C to +85OC
TSOP2-44
BGA-48-0608
BS616LV4016EI
BS616LV4016AI
18mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A5
A6
A7
OE
UB
LB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A2
A1
A0
CE
A4
A3
A2
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12
A1
Address
22
2048
A0
A17
A16
BS616LV4016EC
BS616LV4016EI
Input
Row
Memory Array
2048 x 2048
Buffer
A15
A14
A13
A12
Decoder
2048
Data
Input
Buffer
16
16
16
Column I/O
DQ0
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
128
Data
Output
16
Buffer
Column Decoder
DQ15
14
CE
WE
OE
UB
Control
Address Input Buffer
LB
A11 A10 A9 A8 A7
A6 A5
Vcc
Gnd
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.1
R0201-BS616LV4016
1
Jan.
2004
BSI
BS616LV4016
PIN DESCRIPTIONS
Name
Function
A0-A17 Address Input
These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.
CE Chip Enable Input
WE Write Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
CE
H
WE
X
OE
X
LB
X
UB
D0~D7
High Z
High Z
High Z
High Z
Dout
D8~D15
Vcc CURRENT
CCSB , ICCSB1
Not selected
(Power Down)
X
H
H
X
L
High Z
High Z
High Z
High Z
Dout
Dout
High Z
Din
I
X
X
X
H
ICCSB , ICCSB1
L
L
ICC
ICC
ICC
ICC
ICC
ICC
ICC
ICC
X
H
X
H
H
X
Output Disabled
Read
L
H
L
L
L
H
L
L
L
High Z
Dout
H
L
L
Din
Write
X
H
L
L
X
Din
H
Din
X
Revision 1.1
Jan. 2004
R0201-BS616LV4016
2
BSI
BS616LV4016
OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS(1)
AMBIENT
TEMPERATURE
SYMBOL
VTERM
TBIAS
TSTG
PARAMETER
RATING
UNITS
V
RANGE
Vcc
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
Commercial
Industrial
0 O C to +70 O C
2.4V ~ 3.6V
2.4V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +85
-60 to +150
1.0
O C
-40 O C to +85 O C
O C
W
PT
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
IOUT
SYMBOL
PARAMETER CONDITIONS MAX.
UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
CIN
VIN=0V
=0V
6
8
pF
Capacitance
Input/Output
Capacitance
DQ
C
I/O
V
pF
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
PARAMETER
MIN. TYP.(1) MAX.
UNITS
PARAMETER
TEST CONDITIONS
NAME
Guaranteed Input Low
Voltage(2)
--
VIL
Vcc=3.0V -0.3
0.8
V
Guaranteed Input High
Voltage(2)
--
IH
V
V
Vcc=3.0V
Vcc+0.3
2.0
IN
IIL
Input Leakage Current Vcc = Max, V = 0V to Vcc
--
--
--
--
1
1
uA
uA
IH
Vcc = Max, CE = V IH , or OE,= V
Output Leakage Current
ILO
V
I/O = 0V to Vcc
V
V
--
--
--
--
VOL
VOH
Output Low Voltage
Output High Voltage
OL
Vcc=3.0V
Vcc=3.0V
0.4
--
Vcc = Max, I = 2.0mA
Vcc = Min, IOH = -1.0mA
2.4
--
(5)
70ns
55ns
18
27
,IDQ= 0mA,
CE=VIL
F=Fmax(3)
Operating Power
Supply Current
ICC
mA
mA
uA
Vcc=3.0V
ICCSB
IH
DQ
--
CE = V , I = 0mA
--
--
Standby Current-TTL
Vcc=3.0V
Vcc=3.0V
1.0
8
(4)
CE Vcc-0.2V,
≧
Standby Current-CMOS
ICCSB1
0.45
V
IN
Vcc - 0.2V or VIN 0.2V
≦
≧
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
4. IccSB1_max. is 6uA @Vcc=3.0V during 0oC~70oC.
5. Icc_Max. is 25mA(@55ns) / 17mA(@70ns) at Vcc=3.0V/ 0~70oC.
Revision 1.1
R0201-BS616LV4016
3
Jan.
2004
BSI
BS616LV4016
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
(1)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
UNITS
CE
Vcc - 0.2V
Vcc - 0.2V or V
≧
≧
VDR
Vcc for Data Retention
1.5
--
--
V
IN
IN
V
0.2V
0.2V
≦
≦
(3)
CE
Vcc - 0.2V
Vcc - 0.2V or V
≧
≧
ICCDR
Data Retention Current
--
0
0.15
1.7
uA
IN
IN
V
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
TRC
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
3. IccDR(Max.) is 1.2uA at TA=70OC.
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
V
DR ≥ 1.5V
Vcc
Vcc
Vcc
CE
t
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
Revision 1.1
R0201-BS616LV4016
4
Jan.
2004
BSI
BS616LV4016
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
1V/ns
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
Timing Reference Level
0.5Vcc
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
JEDEC
PARAMETER
CYCLE TIME : 70ns
CYCLE TIME : 55ns
(Vcc = 2.7~3.6V)
PARAMETER
(Vcc = 2.4~3.6V)
DESCRIPTION
Read Cycle Time
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
NAME
t
t
55
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
30
30
--
70
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAX
RC
t
t
Address Access Time
AVQV
AA
t
t
Chip Select Access Time
--
--
ELQV
ACS
(1)
t
t
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
(LB,UB)
(LB,UB)
(LB,UB)
--
--
BA
BA
t
t
--
--
GLQV
OE
t
t
10
10
5
10
10
5
E1LQX
CLZ
t
t
--
--
BE
BE
t
t
--
--
GLQX
OLZ
t
t
--
30
30
25
--
35
35
30
EHQZ
CHZ
t
t
--
--
BDO
BDO
t
t
--
--
GHQZ
OHZ
t
t
Data Hold from Address Change
AXOX
OH
10
--
--
10
--
--
ns
NOTE :
1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
Revision 1.1
Jan. 2004
R0201-BS616LV4016
5
BSI
BS616LV4016
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t
ACS
t
BA
LB,UB
(5)
CHZ
t
BDO
t
BE
t
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
t
RC
ADDRESS
OE
t
AA
t
OH
t
OE
t
OLZ
CE
(5)
t
ACS
t
t
OHZ
(1,5)
(5)
CLZ
t
CHZ
t
BA
LB,UB
D OUT
t
BE
t
BDO
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
5. The parameter is guaranteed but not 100% tested.
.
.
Revision 1.1
Jan. 2004
R0201-BS616LV4016
6
BSI
BS616LV4016
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 55ns
(Vcc = 2.7~3.6V)
CYCLE TIME : 70ns
PARAMETER
(Vcc = 2.4~3.6V)
DESCRIPTION
Write Cycle Time
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tBW
55
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tCW
tAS
Chip Select to End of Write
Address Setup Time
--
--
Address Valid to End of Write
Write Pulse Width
55
30
0
--
70
35
0
--
tAW
tWP
tWR
--
--
Write recovery Time
--
--
(CE,WE)
(1)
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
(LB,UB)
25
--
--
30
--
--
tBW
tWHZ
tDW
tDH
tWLQZ
tDVWH
tWHDX
tGHQZ
25
--
30
--
25
0
30
0
--
--
--
25
--
30
tOHZ
tWHOX
tOW
End of Write to Output Active
5
--
--
5
--
--
ns
NOTE :
1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(10)
CW
t
(5)
CE
t
BW
LB,UB
WE
t
AW
(3)
t
WP
(2)
t
AS
(4,11)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 1.1
Jan. 2004
R0201-BS616LV4016
7
BSI
BS616LV4016
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(10)
t
CW
(5)
CE
t
BW
LB,UB
t
WR
t
AW
(3)
t
WP
(2)
WE
t
AS
(4,11)
t
t
OW
(7)
(8)
t
WHZ
D OUT
t
DW
(8,9)
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. TCW is measured from the later of CE going low to the end of write.
11. The parameter is guaranteed but not 100% tested.
Revision 1.1
R0201-BS616LV4016
8
Jan.
2004
BSI
BS616LV4016
ORDERING INFORMATION
BS616LV4016 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
E: TSOP2-44
A: BGA-48-0608
D: DICE
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
TSOP2-44
Revision 1.1
Jan. 2004
R0201-BS616LV4016
9
BSI
BS616LV4016
PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
D1
N
D
E
D1
E1
48
8.0
6.0
5.25
3.75
SOLDER BALL
0.35± 0.05
VIEW A
48 mini-BGA (6 x 8mm)
Revision 1.1
R0201-BS616LV4016
10
Jan.
2004
相关型号：
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