BS616LV2018AI [BSI]
Very Low Power/Voltage CMOS SRAM 128K X 16 bit; 非常低的功率/电压CMOS SRAM 128K ×16位
| 型号： | BS616LV2018AI |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power/Voltage CMOS SRAM 128K X 16 bit |
| 文件： | 总11页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BSI
BS616LV2018
FEATURES
DESCRIPTION
• Very low operation voltage : 2.4 ~ 3.6V
• Very low power consumption :
The BS616LV2018 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
Vcc = 3.0V
C-grade: 16mA (Max.) operating current
I -grade: 20mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616LV2018 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2018 is available in DICE form, JEDEC standard 48-pin
TSOP Type I package and 48-ball BGA package.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
Vcc
PKG TYPE
(I
, Max)
(I , Max)
CC
CCSB1
TEMPERATURE
RANGE
Vcc=
Vcc=3.0V
Vcc=3.0V
3.0V
BS616LV2018DC
BS616LV2018TC
BS616LV2018AC
DICE
0 O C to +70 O
C
70
70
0.7 uA
TSOP1-48
16 mA
BGA-48-0608
2.4V ~3.6V
BS616LV2018DI
DICE
-40 O C to +85 O
C
1.5 uA
20 mA
BS616LV2018TI
BS616LV2018AI
TSOP1-48
BGA-48-0608
BLOCK DIAGRAM
PIN CONFIGURATIONS
A8
A13
A15
1
2
3
4
5
6
Address
20
A16
1024
A14
A
B
C
D
E
F
LB
D8
D9
OE
UB
A0
A3
A1
A4
A2
N.C.
D0
Input
Row
Memory Array
1024 x 2048
A12
A7
A6
A5
A4
Buffer
Decoder
CE
D1
D10
D11
D12
D13
A5
A6
D2
2048
Data
VSS
VCC
N.C.
N.C.
A14
A12
A9
A7
D3
VCC
VSS
16
16
16
Column I/O
Input
DQ0
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
A16
A15
A13
A10
D4
128
Data
D14
D15
N.C.
D5
D6
16
Output
Buffer
Column Decoder
DQ15
G
H
WE
A11
D7
N.C.
A8
14
CE
WE
OE
UB
N.C.
Control
Address Input Buffer
LB
A11 A9 A3 A2 A1
48-ball BGA top view
A0 A10
Vcc
Gnd
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.0
April 2002
R0201-BS616LV2018
1
BSI
BS616LV2018
PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE Chip Enable Input
WE Write Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
CE
H
WE
X
OE
X
LB
UB
DQ0~DQ7
DQ8~DQ15
Vcc CURRENT
Not selected
X
X
High Z
High Z
ICCSB, ICCSB1
(Power Down)
Output Disabled
Read
L
H
H
X
L
H
L
L
H
L
X
L
L
H
L
L
High Z
Dout
High Z
Dout
Din
High Z
Dout
Dout
High Z
Din
ICC
ICC
ICC
ICC
ICC
ICC
ICC
L
L
H
L
L
Write
X
X
Din
Din
X
H
Revision 2.0
April 2002
R0201-BS616LV2018
2
BSI
BS616LV2018
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
SYMBOL
PARAMETER
RATING
UNITS
RANGE
Vcc
TEMPERATURE
Terminal Voltage with
-0.5 to
V
TERM
BIAS
STG
T
V
T
T
P
Respect to GND
Vcc+0.5
Commercial
Industrial
0 O C to +70O
-40 O C to +85O
C
2.4V ~ 3.6V
2.4V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
C
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
PARAMETER
CONDITIONS
MAX. UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
IN
C
IN
V
=0V
6
8
pF
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
1. This parameter is guaranteed and not tested.
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
PARAMETER
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP. (1) MAX.
NAME
Guaranteed Input Low
Vcc=3.0V
Vcc=3.0V
VIL
-0.5
--
0.8
V
Voltage(2)
Guaranteed Input High
Voltage(2)
VIH
IIL
2.0
--
--
--
Vcc+0.2
1
V
Input Leakage Current
Vcc = Max, VIN = 0V to Vcc
Vcc = Max, CE = VIH, or OE = VIH
uA
,
IOL
Output Leakage Current
--
--
1
uA
V
I/O = 0V to Vcc
Vcc=3.0V
Vcc=3.0V
VOL
VOH
Output Low Voltage
Output High Voltage
Vcc = Max, IOL = 2mA
Vcc = Min, IOH = -1mA
--
--
--
0.4
--
V
V
2.4
Operating Power Supply
Current
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
ICC
CE = VIL, IDQ = 0mA, F = Fmax(3)
--
--
--
--
--
16
1
mA
mA
uA
ICCSB
Standby Current-TTL
CE = VIH, IDQ = 0mA
CE Њ Vcc-0.2V,
ICCSB1
Standby Current-CMOS
0.1
0.7
V
IN Њ Vcc - 0.2V or VIN Љ 0.2V
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
CE Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE Њ Vcc - 0.2V
ICCDR
Data Retention Current
--
0
0.05
0.5
uA
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
TRC
O
1. Vcc = 1.5V, TA = + 25 C
2. tRC = Read Cycle Time
Revision 2.0
April 2002
R0201-BS616LV2018
3
BSI
BS616LV2018
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
V
DR ≥ 1.5V
Vcc
Vcc
t
Vcc
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
CE
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
Ω
Ω
1269
1269
5PF
3.3V
3.3V
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
OUTPUT
OUTPUT
FROM L TO H
,
100PF
DON T CARE:
CHANGE :
STATE
INCLUDING
INCLUDING
Ω
Ω
1404
1404
ANY CHANGE
PERMITTED
JIG AND
SCOPE
JIG AND
SCOPE
UNKNOWN
DOES NOT
APPLY
CENTER
FIGURE 1A
FIGURE 1B
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
THEVENIN EQUIVALENT
667
Ω
OUTPUT
1.73V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
BS616LV2018-70
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
UNIT
NAME
tRC
tAVAX
Read Cycle Time
70
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVQV
tELQV
tBA
tAA
Address Access Time
tACS
Chip Select Access Time
(CE)
--
(1)
tBA
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
(LB,UB)
--
tGLQV
tOE
tCLZ
tBE
tOLZ
tCHZ
tBDO
tOHZ
--
t
(CE)
10
10
10
0
E1LQX
t
(LB,UB)
--
BE
t
--
GLQX
t
(CE)
35
35
30
EHQZ
t
(LB,UB)
0
BDO
t
0
GHQZ
tAXOX
tOH
Output Disable to Address Change
10
--
--
ns
NOTE :
1. tBA is 35ns (@speed=70ns) with address toggle. ; .tBA is 70ns (@speed=70ns) without address toggle.
Revision 2.0
April 2002
R0201-BS616LV2018
4
BSI
BS616LV2018
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t
ACS
t
BA
LB,UB
(5)
t
CHZ
t
BE
t
BDO
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
t
RC
ADDRESS
OE
t
AA
t
OH
t
OE
t
OLZ
CE
(5)
(1,5)
(5) t ACS
CLZ
t
OHZ
t
t
CHZ
t
BA
LB,UB
D OUT
t
BE
t
BDO
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
.
.
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.0
April 2002
R0201-BS616LV2018
5
BSI
BS616LV2018
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
WRITE CYCLE
JEDEC
PARAMETER
BS616LV2018-70
UNIT
PARAMETER
DESCRIPTION
MIN. TYP. MAX.
NAME
NAME
t
Write Cycle Time
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tCW
tAS
tAW
tWP
tWR
AVAX
t
Chip Select to End of Write
Address Setup Time
E1LWH
t
--
AVWL
t
Address Valid to End of Write
Write Pulse Width
70
35
0
--
AVWH
t
--
WLWH
t
Write recovery Time
(CE,WE)
(LB,UB)
--
WHAX
(1)
t
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
30
0
--
tBW
BW
t
30
--
tWHZ
tDW
tDH
WLQZ
t
30
0
DVWH
t
--
WHDX
t
0
30
tOHZ
GHQZ
tWHOX
tOW
End of Write to Output Active
5
--
--
ns
NOTE :
1. tBW is 30ns (@speed=70ns) with address toggle. ; tBW is 70ns (@speed=70ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
t
WR
(11)
CW
t
(5)
CE
t
BW
LB,UB
WE
t
AW
(3)
t
WP
(2)
t
AS
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 2.0
April 2002
R0201-BS616LV2018
6
BSI
BS616LV2018
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
CW
t
(5)
CE
t
BW
LB,UB
t
WR
t
AW
(3)
t
WP
(2)
t
DH
WE
t
AS
(4,10)
t
WHZ
(7)
(8)
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
Revision 2.0
April 2002
R0201-BS616LV2018
7
BSI
BS616LV2018
ORDERING INFORMATION
BS616LV2018 X X -- Y Y
SPEED
70: 70ns
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
T: TSOP 1 - 48 PIN
A: BGA - 48 PIN (6x8mm)
D: DICE
Revision 2.0
April 2002
R0201-BS616LV2018
8
BSI
BS616LV2018
PACKAGE DIMENSIONS
UNIT
SYMBOL
HD
INCH
MM
A
0.0433̈́0.004
1.10̈́0.10
0.10̈́0.05
1.00̈́0.05
0.22̈́0.05
0.20̈́0.03
0.10 ~ 0.21
0.10 ~ 0.16
16.40̈́0.10
12.00̈́0.10
0.50̈́0.10
18.00̈́0.20
0.60̈́0.15
0.80̈́0.10
0.1 Max.
C
L
A1 0.004̈́0.002
A2 0.039̈́0.002
1
48
b
0.009̈́0.002
b1 0.008̈́0.001
0.004 ~ 0.008
c1 0.004 ~ 0.006
c
D
E
e
0.645̈́0.004
0.472̈́0.004
0.020̈́0.004
HD 0.708̈́0.008
0.0236̈́0.006
L
24
25
12̓(2x)
L1 0.0315̈́0.004
Seating Plane
y
y
Ӱ
0.004 Max.
0̓~ 8̓
"A"
0̓~ 8̓
D
GAUGE PLANE
A
A
24
25
SEATING PLANE
12̓(2x)
L
b
L1
WITH PLATING
"A" DETAIL VIEW
c
c1
BASE METAL
b1
SECTION A-A
48
1
TSOP1-48PIN
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
A16
NC
VSS
IO15
IO7
IO14
IO6
A8
IO13
IO5
NC
NC
/WE
CE2
NC
/UB
/LB
NC
NC
A7
9
10
IO12
IO4
Pkg Type :
37
VCC
IO11
IO3
13
48TSOP(I)-12x18mm
IO10
IO2
16
17
IO9
IO1
A6
IO8
A5
IO0
A4
/OE
VSS
/CE
A0
A3
27
25
A2
A1
24
Revision 2.0
April 2002
R0201-BS616LV2018
9
BSI
BS616LV2018
PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
D1
VIEW A
48 mini-BGA (6 x 8)
Revision 2.0
April 2002
R0201-BS616LV2018
10
BSI
REVISION HISTORY
BS616LV2018
Revision Description
Date
Note
1.0
2.0
Data Sheet release
Jan. 30, 2001
April,12,2002
Modify some AC parameters
Revision 2.0
April 2002
R0201-BS616LV2018
11
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