TISP61089ASDR-S [BOURNS]
Surge Protection Circuit, PDSO8, ROHS COMPLIANT, PLASTIC, SOP-8;
| 型号： | TISP61089ASDR-S |
| 厂家： | 
BOURNS ELECTRONIC SOLUTIONS |
| 描述： | Surge Protection Circuit, PDSO8, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件： | 总12页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TISP61089D, TISP61089SD, TISP61089AD,
TISP61089ASD, TISP61089P, TISP61089AP
DUAL FORWARD-CONDUCTING P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
TISP61089 Gated Protector Series
2/10 Overshoot Voltage Specified
Overvoltage Protection for Negative Rail SLICs
I
= 100 A, 2/10
Dual Voltage-Tracking Protectors
PP
Element
- ‘61089 for Battery Voltages to ......................................... -75 V
- ‘61089A for Battery Voltages to ..................................... -100 V
- Low Gate Triggering Current ....................................... < 5 mA
- High Holding Current ............................................... > 150 mA
V
8
Diode
SCR
12
Rated for GR-1089-CORE and K.44 Impulses
Impulse Wave Shape
I
PPSM
A
Package Options
- Surface Mount 8-pin Small-Outline
Line Feed-Thru Connection (D)
Shunt Version Connection (SD)
- Through-Hole 8-pin DIP (P)
Voltage
2/10
Current
2/10
120
40
10/700
10/1000
5/310
............................................. UL Recognized Components
10/1000
30
D Package, P Package Top Views and Device Symbol for Feed-Thru Pin-Out
K1
G
K1
K1
G
(Tip)
1
2
3
4
8
7
6
5
K1 (Tip)
(Gate)
A
A
(Ground)
(Ground)
A
A
NC
(Ring) K2
K2 (Ring)
MD6XBD
NC - No internal connection
Terminal typical application names shown in
parenthesis
K2
K1
G
K2
SD6XAEB
D Package Top View and Device Symbol for Shunt (SD) Pin-Out
(Tip) K1
1
2
3
4
8
7
6
5
NC
A
(Ground)
(Ground)
(Gate)
G
NC
A
A
A
(Ring) K2
NC
MD6XBE
NC - No internal connection
Terminal typical application names shown in
parenthesis
K2
SD6XAU
How To Order
Device
Package
Carrier
R†
Order as
Device
Package
Carrier
Order as
TISP61089DR
TISP61089D
TISP61089SDR
TISP61089SD
TISP61089P
R†
TISP61089ADR
TISP61089AD
TISP61089ASDR
TISP61089ASD
TISP61089AP
TISP61089
D (Small-Outline)
TISP61089A
D (Small-Outline)
Tube
R†
Tube
R†
TISP61089S
TISP61089
D (Small-Outline)
P (8-pin DIP)
TISP61089AS
TISP61089A
D (Small-Outline)
P (8-pin DIP)
Tube
Tube
Tube
Tube
† Carrier R is Embossed Tape Reeled
† Carrier R is Embossed Tape Reeled
NOVEMBER 1995 - REVISED AUGUST 2002
Specifications are subject to change without notice.
1
TISP61089 Gated Protector Series
Description
These ‘61089 parts are all dual forward-conducting buffered p-gate thyristor (SCR) overvoltage protectors. They are designed to protect
monolithic SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and
induction. The ‘61089 limits voltages that exceed the SLIC supply rail voltage. The ‘61089 parameters are specified to allow equipment
compliance with Telcordia (formally Bellcore) GR-1089-CORE and ITU-T recommendations K.20, K.21 and K.45.
The SLIC line driver section is typically powered from 0 V (ground) and a negative (battery) voltage. The protector gate is connected to this
negative supply. This references the protection (clipping) voltage to the negative supply voltage. The protection voltage will then track the
negative supply voltage and the overvoltage stress on the SLIC is minimized.
Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially clipped close to the SLIC
negative supply rail value. If sufficient current is available from the overvoltage, then the protector SCR will switch into a low voltage on-state
condition. As the overvoltage subsides the high holding current of ‘61089 SCR avoids d.c. latchup.
The ‘61089 is intended to be used with a series resistance of at least 25 Ω and a suitable overcurrent function for Telcordia compliance. Power
fault conditions require a series overcurrent element which either interrupts or reduces the circuit current before the ‘61089 current rating is
exceeded. For equipment compliant to ITU-T recommendations K.20 or K.21 or K.45 only, the series resistor value is set by the coordination
requirements. For coordination with a 400 V limit GDT, a minimum series resistor value of 10 Ω is recommended.
The ‘61089 buffered gate design reduces the loading on the SLIC supply during overvoltages caused by power cross and induction. The
regular pin-out for surface mount and through-hole packages is a feed through configuration. Connection to the SLIC is made via the ‘61089,
Ring through pins 4 - 5 and Tip through pins 1 - 8. A non-feed-through surface mount (D) package is available. This shunt (SD) version pin-out
does not make duplicate connections to pin 5 and pin 8 which increases package creepage distance from ground of the other connections
from about 0.7 mm to over 3 mm. High voltage ringing SLICs, with battery voltages below -100 V and down to -155 V, can be protected by the
TISP61089B device. Details of this device are in the TISP61089B data sheet.
Absolute Maximum Ratings, -40 °C ≤ T ≤ 85 °C (Unless Otherwise Noted)
J
Rating
Symbol
Value
Unit
61089
-100
-120
Repetitive peak off-state voltage, V = 0
GK
V
V
DRM
‘61089A
61089
-85
Repetitive peak gate-cathode voltage, V = 0
KA
V
V
GKRM
‘61089A
-120
Non-repetitive peak on-state pulse current (see Notes 1 and 2)
10/1000 µs (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4)
5/320 µs (ITU-T K.20, K.21& K.45, K.44 open-circuit voltage wave shape 10/700 µs)
1.2/50 µs (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4)
2/10 µs (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4)
30
40
I
A
PPSM
100
120
Non-repetitive peak on-state current, V
= -75 V, 50 Hz to 60 Hz (see Notes 1 and 2)
GG
0.1 s
11
1 s
4.8
2.7
I
A
TSM
5 s
300 s
900 s
0.95
0.93
Non-repetitive peak gate current, 1/2 µs pulse, cathodes commoned (see Notes 1 and 2)
Operating free-air temperature range
I
+40
A
GSM
T
-40 to +85
-40 to +150
-40 to +150
°C
°C
°C
A
Junction temperature
T
J
Storage temperature range
T
stg
NOTES: 1. Initially the protector must be in thermal equilibrium with -40 °C ≤ T ≤ 85 °C. The surge may be repeated after the device returns
J
to its initial conditions. Gate voltage ranges are -20 V to -75 V for the ‘61089 and -20 V to -100 V for the ‘61089A.
2. The rated current values may be applied either to the Ring to Ground or to the Tip to Ground terminal pairs. Additionally, both
terminal pairs may have their rated current values applied simultaneously (in this case the Ground terminal current will be twice
the rated current value of an individual terminal pair). Above 85 °C, derate linearly to zero at 150 °C lead temperature.
NOVEMBER 1995 - REVISED AUGUST 2002
Specifications are subject to change without notice.
2
TISP61089 Gated Protector Series
Recommended Operating Conditions
Component
Min
100
25
40
8
Typ
Max
Unit
nF
Ω
C
Gate decoupling capacitor
220
G
Series resistor for GR-1089-CORE first-level surge survival
Series resistor for GR-1089-CORE first-level and second-level surge survival
Series resistor for GR-1089-CORE intra-building port surge survival
Series resistor for K.20, K.21 and K.45 coordination with a 400 V primary protector
Ω
R
S
Ω
10
Ω
Electrical Characteristics, T = 25 °C (Unless Otherwise Noted)
J
Parameter
Test Conditions
Min
Typ
Max
-5
Unit
µA
T = 25 °C
J
I
Off-state current
V
= V , V = 0
DRM GK
D
D
T = 85 °C
-50
µA
J
2/10 µs, I = -56 A, R = 45 Ω, V
PP GG
= -48 V, C = 220 nF
-57
-60
-60
-64
S
G
2/10 µs, I = -100 A, R = 50 Ω, V = -48 V, C = 220 nF
PP GG
S
G
V
Breakover voltage
V
(BO)
1.2/50 µs, I = -53 A, R = 47 Ω, V = -48 V, C = 220 nF
PP GG
S
G
1.2/50 µs, I = -96 A, R = 52 Ω, V = -48 V, C = 220 nF
PP GG
S
G
2/10 µs, I = -56 A, R = 45 Ω, V
= -48 V, C = 220 nF
9
PP GG
S
G
Gate-cathode impulse 2/10 µs, I = -100 A, R = 50 Ω, V = -48 V, C = 220 nF
PP GG
12
12
16
S
G
V
V
V
V
GK(BO)
breakover voltage
1.2/50 µs, I = -53 A, R = 47 Ω, V = -48 V, C = 220 nF
PP GG
S
G
1.2/50 µs, I = -96 A, R = 52 Ω, V = -48 V, C = 220 nF
PP GG
S
G
V
Forward voltage
I = 5 A, t = 200 µs
3
F
F
w
2/10 µs, I = 56 A, R = 45 Ω, V
PP
= -48 V, C = 220 nF
6
8
S
GG
G
Peak forward recovery 2/10 µs, I = 100 A, R = 50 Ω, V = -48 V, C = 220 nF
PP GG
S
G
V
FRM
voltage
1.2/50 µs, I = 53 A, R = 47 Ω, V = -48 V, C = 220 nF
PP GG
8
S
G
1.2/50 µs, I = 96 A, R = 52 Ω, V = -48 V, C = 220 nF
PP GG
12
S
G
I
Holding current
I = -1 A, di/dt = 1A/ms, V = -48 V
GG
-150
mA
µA
H
T
T = 25 °C
-5
-50
5
J
I
Gate reverse current
Gate trigger current
V
= V = V , V = 0
GK GKRM KA
GKS
GG
T = 85 °C
µA
J
I
I = -3 A, t
≥ 20 µs, V = -48 V
GG
mA
GT
T
p(g)
p(g)
Gate-cathode trigger
voltage
V
I = -3 A, t
≥ 20 µs, V = -48 V
GG
2.5
V
GT
T
Q
C
Gate switching charge 1.2/50 µs, I = -53 A, R = 47 Ω, V = -48 V, C = 220 nF
PP GG
0.1
µC
pF
pF
GS
KA
S
G
V
= -3 V
100
50
Cathode-anode off-
state capacitance
D
f = 1 MHz, V = 1 V, I = 0, (see Note 3)
d
G
V
= -48 V
D
NOTES: 3. These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured
device terminals are a.c. connected to the guard terminal of the bridge.
Thermal Characteristics
Parameter
Test Conditions
Min
Typ
Max
Unit
T = 25 °C, EIA/JESD51-3
A
D Package
P package
120
RθJA
Junction to free air thermal resistance
PCB, EIA/JESD51-2
°C/W
100
environment, P
TOT
= 1.7 W
NOVEMBER 1995 - REVISED AUGUST 2002
Specifications are subject to change without notice.
3
TISP61089 Gated Protector Series
Parameter Measurement Information
+i
Quadrant I
IPPSM
Forward
Conduction
Characteristic
IFSM (= |ITSM|)
IF
VF
VGK(BO)
VGG
+v
-v
ID
IH
V
(BO)
IT
ITSM
Quadrant III
IPPSM
Switching
Characteristic
-i
PM6XAAC
Figure 1. Voltage-Current Characteristic
Unless Otherwise Noted, All Voltages are Referenced to the Anode
NOVEMBER 1995 - REVISED AUGUST 2002
Specifications are subject to change without notice.
4
TISP61089 Gated Protector Series
Thermal Information
PEAK NON-RECURRING AC
vs
CURRENT DURATION
TI61AFA
20
15
RING AND TIP TERM INALS:
Equal ITSM values applied
simultaneously
GROUND TERM INAL:
Current twice ITSM value
10
8
7
6
EIA /JESD51
Environment and
PCB, TA = 25 °C
5
4
3
VGG = -80 V
VGG = -60 V
2
1.5
1
VGG = -100 V
0.8
0.7
0.6
0.5
0.01
0.1
1
10
100
1000
t — Current Duration — s
Figure 2. Non-repetitive Peak On-State Current against Duration
(Gate Voltage Ranges are -20 V to -75 V for the '61089 and -20 V to -100 V for the '61089A)
NOVEMBER 1995 - REVISED AUGUST 2002
Specifications are subject to change without notice.
5
TISP61089 Gated Protector Series
APPLICATIONS INFORMATION
Gated Protectors
This section covers three topics. First, it is explained why gated protectors are needed. Second, the voltage limiting action of the protector is
described. Third, an example application circuit is described.
Purpose of Gated Protectors
Fixed voltage thyristor overvoltage protectors have been used since the early 1980s to protect monolithic SLICs (Subscriber Line Interface
Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. As the SLIC was usually powered
from a fixed voltage negative supply rail, the limiting voltage of the protector could also be a fixed value. The TISP1072F3 is a typical example
of a fixed voltage SLIC protector.
SLICs have become more sophisticated. To minimize power consumption, some designs automatically adjust the supply voltage, VBAT, to a
value that is just sufficient to drive the required line current. For short lines the supply voltage would be set low, but for long lines, a higher
supply voltage would be generated to drive sufficient line current. The optimum protection for this type of SLIC would be given by a protection
voltage which tracks the SLIC supply voltage. This can be achieved by connecting the protection thyristor gate to the SLIC supply, Figure 3.
This gated (programmable) protection arrangement minimizes the voltage stress on the SLIC, no matter what value of supply voltage.
TIP
WIRE
SLIC
'61089
Th4
RSa
40
600
GENERATOR
SOURCE
RESISTANCE
SWITCHING MODE
POWER SUPPLY
RSb
40
600
Th5
Tx
RING
WIRE
C2
AC
ISLIC
IG
GENERATOR
0 - 600 V rms
C1
220 nF
IBAT
VBAT
D1
AI6XAGB
Figure 3. ‘61089 Buffered Gate Protector
Operation of Gated Protectors
Figures 4 and 5 show how the ’61089 device limits negative and positive overvoltages. Positive overvoltages (Figure 5) are clipped by the
antiparallel diodes in the ’61089 protector and the resulting current is diverted to ground. Negative overvoltages (Figure 4) are initially clipped
close to the SLIC negative supply rail value (VBAT). If sufficient current is available from the overvoltage, then the protector (Th5) will crowbar
into a low voltage on-state condition. As the overvoltage subsides the high holding current of the crowbar prevents d.c. latchup. The
protection voltage will be the sum of the gate supply (VBAT) and the peak gate-cathode voltage (VGK(BO)). The protection voltage will be
increased if there is a long connection between the gate decoupling capacitor, C1, and the gate terminal. During the initial rise of a fast
impulse, the gate current (IG) is the same as the cathode current (IK). Rates of 70 A/µs can cause inductive voltages of 0.7 V in 2.5 cm of
printed wiring track. To minimize this inductive voltage increase of protection voltage, the length of the capacitor to gate terminal tracking
should be minimized. Inductive voltages in the protector cathode wiring will also increase the protection voltage. These voltages can be
minimized by routing the SLIC connection through the protector as shown in Figure 3.
Application Circuit
Figure 6 shows a typical ’61089 part SLIC card protection circuit. The incoming line conductors, Ring (R) and Tip (T), connect to the relay
matrix via the series overcurrent protection. Fusible resistors, fuses and positive temperature coefficient (PTC) thermistors can be used for
overcurrent protection. Resistors will reduce the prospective current from the surge generator for both the ’61089 device and the ring/test
NOVEMBER 1995 - REVISED AUGUST 2002
Specifications are subject to change without notice.
6
TISP61089 Gated Protector Series
APPLICATIONS INFORMATION
Application Circuit (Continued)
protector. The TISP7xxxF3 protector has the same protection voltage for any terminal pair. This protector is used when the ring generator
configuration may be ground or battery-backed. For dedicated ground-backed ringing generators, the TISP3xxxF3 gives better protection as
its inter-conductor protection voltage is twice the conductor to ground value.
Relay contacts 3a and 3b connect the line conductors to the SLIC via the ’61089 protector. The protector gate reference voltage comes from
the SLIC negative supply (VBAT). A 220 nF gate capacitor sources the high gate current pulses caused by fast rising impulses.
SLIC
PROTECTOR
SLIC
PROTECTOR
SLIC
SLIC
IF
Th5
IK
Th5
'61089
'61089
IG
VBAT
VBAT
C1
C1
220 nF
220 nF
AI6XAHC
AI6XAIC
Figure 4. Negative Overvoltage Condition
Figure 5. Positive Overvoltage Condition
OVER-
CURRENT
PROTECTION
RING/TEST
PROTECTION
TEST
RELAY
RING
RELAY
SLIC
RELAY
SLIC
PROTECTOR
SLIC
TIP
WIRE
Th1
S3a
Th4
RSa
S1a
S2a
Th3
RSb
Th5
Th2
RING
WIRE
S3b
TISP
3xxxF3
OR
'61089
S1b
S2b
VBAT
C1
220 nF
7xxxF3
TEST
EQUIP-
MENT
RING
GENERATOR
AI6XAJC
Figure 6. Typical Application Circuit
NOVEMBER 1995 - REVISED AUGUST 2002
Specifications are subject to change without notice.
7
TISP61089 Gated Protector Series
MECHANICAL DATA
Device Symbolization Code
Devices will be coded as below.
Device
Symbolization Code
P61089
TISP61089D
TISP61089SD
TISP61089AD
TISP61089ASD
TISP61089P
TISP61089AP
61089S
61089A
1089AS
TISP61089
61089A
NOVEMBER 1995 - REVISED AUGUST 2002
Specifications are subject to change without notice.
8
TISP61089 Gated Protector Series
MECHANICAL DATA
D008 Plastic Small-outline Package
This small-outline package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will
withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high
humidity conditions. Leads require no additional cleaning or processing when used in soldered assembly.
D008
8-pin Small Outline Microelectronic Standard
Package MS-012, JEDEC Publication 95
4.80 - 5.00
(0.189 - 0.197)
8
7
6
5
5.80 - 6.20
(0.228 - 0.244)
INDEX
3.81 - 4.00
(0.150 - 0.157)
1
3
2
4
4.60 - 5.21
(0.181 - 0.205)
0.25 - 0.50
(0.010 - 0.020)
1.35 - 1.75
(0.053 - 0.069)
7 ° NOM
3 Places
x 45 ° N0M
0.102 - 0.203
(0.004 - 0.008)
4 ° ± 4 °
0.36 - 0.51
(0.014 - 0.020)
8 Places
7 ° NOM
4 Places
0.28 - 0.79
(0.011 - 0.031)
Pin Spacing
1.27
(0.050)
(see Note A)
6 places
0.190 - 0.229
(0.0075 - 0.0090)
0.51 - 1.12
(0.020 - 0.044)
MILLIMETERS
(INCHES)
DIMENSIONS ARE:
MDXXAAE
NOTES: A. Leads are within 0.25 (0.010) radius of true position at maximum material condition.
B. Body dimensions do not include mold flash or protrusion.
C. Mold flash or protrusion shall not exceed 0.15 (0.006).
D. Lead tips to be planar within ±0.051 (0.002).
NOVEMBER 1995 - REVISED AUGUST 2002
Specifications are subject to change without notice.
9
TISP61089 Gated Protector Series
MECHANICAL DATA
D008 Tape DImensions
D008 Package (8-pin Small Outline) Single-Sprocket Tape
1.50 - 1.60
3.90 - 4.10
(.059 - .063)
(.154 - .161)
0.40
1.95 - 2.05
7.90 - 8.10
(.016)
(.077 - .081)
(.311 - .319)
0.8
(.03)
MIN.
5.40 - 5.60
(.213 - .220)
11.70 - 12.30
(.461 - .484)
6.30 - 6.50
(.248 - .256)
1.50
(.059)
ø
MIN.
0 MIN.
Cover
Tape
2.0 - 2.2
(.079 - .087)
Carrier Tape
Embossment
Direction of Feed
MILLIMETERS
(INCHES)
DIMENSIONS ARE:
NOTES: A. Taped devices are supplied on a reel of the following dimensions:-
MDXXATC
330 +0.0/-4.0
(12.99 +0.0/-.157)
Reel diameter:
100 ± 2.0
(3.937 ± .079)
Reel hub diameter:
13.0 ± 0.2
(.512 ± .008)
Reel axial hole:
B. 2500 devices are on a reel.
NOVEMBER 1995 - REVISED AUGUST 2002
Specifications are subject to change without notice.
10
TISP61089 Gated Protector Series
MECHANICAL DATA
P008 Plastic Dual-In-Line Package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will
withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high
humidity conditions The package is intended for insertion in mounting-hole rows on 7.62 (0.300) centers. Once the leads are compressed and
inserted, sufficient tension is provided to secure the package in the board during soldering. Leads require no additional cleaning or processing
when used in soldered assembly.
P008
9.25 - 9.75
(.364 - .384)
8
7
6
5
Index
Notch
6.10 - 6.60
(.240 - .260)
1
2
3
4
1.78
(.070)
4 Places
7.62 - 8.23
(.300 - .324)
MAX.
5.08
(.200)
MAX.
MIN.
Seating
Plane
3.17
(.125)
0.51
MIN.
0.20 - 0.36
(.008 - .014)
(.020)
0.38 - 0.53
(.015 - .021)
8 Places
2.54
TYP.
8.38 - 9.40
(.330 - .370)
(.100)
(see Note A)
6 Places
MILLIMETERS
(INCHES)
DIMENSIONS ARE:
MDXXCF
NOTES: A. Each pin centerline is located within 0.25 (0.010) of its true longitudinal position.
B. Dimensions fall within JEDEC MS001 - R-PDIP-T, 0.300" Dual-In-Line Plastic Family.
C. Details of the previous dot index P008 package style, drawing reference MDXXABA, are given in the earlier publications.
NOVEMBER 1995 - REVISED AUGUST 2002
Specifications are subject to change without notice.
11
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Phone
Fax
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Europe:
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+886-2-25624116
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To obtain technical applications assistance, a quotation, or to place an order, contact a Bourns representative in your area.
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