VCA2615 [BB]
Dual, Variable Gain Amplifier; 双通道，可变增益放大器
| 型号： | VCA2615 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Dual, Variable Gain Amplifier |
| 文件： | 总19页 (文件大小：523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VCA2617
SBOS326 −AUGUST 2005
Dual, Variable Gain Amplifier
FD EATURES
DESCRIPTION
INDEPENDENT CHANNEL CONTROLS:
− Gain Range: 48dB
− Clamping Levels
The VCA2617 is a dual-channel, continuously variable,
voltage-controlled gain amplifier well-suited for a variety of
ultrasound systems as well as applications in proximity
detectors and test equipment. The VCA2617 uses a true
variable-gain amplifier architecture, achieving very good
noise performance at low gains, while not sacrificing high gain
distortion performance.
− Post-Gain: 0, +6dB
D
D
D
D
D
D
D
D
LOW NOISE: 4.1nV//Hz
LOW POWER: 52mW/Channel
BANDWIDTH: 50MHz
Following a linear-in-dB response, the VCA2617 gain can be
varied over a 48dB range with a 0.2V to 2.3V control voltage.
Two separate high-impedance control inputs allow for a
channel independent variation of the gains. Each channel of
the VCA2617 can be configured to provide a gain range of
−10dB to 38dB, or −16dB to 32dB, depending on the gain
select pin (HG). This post-gain feature allows the user to
optimize the output swing of VCA2617 for a variety of
high-speed analog-to-digital converters (ADC). As a means to
improve system overload recovery time, the VCA2617 also
provides an internal clamping circuitry where an externally
applied voltage sets the desired output clamping level.
HARMONIC DISTORTION: −53dBc at 5MHz
CROSSTALK: −61dB at 5MHz
5V SINGLE SUPPLY
POWER-DOWN MODE
SMALL QFN-32 PACKAGE (5x5mm)
AD PPLICATIONS
MEDICAL AND INDUSTRIAL ULTRASOUND
SYSTEMS
The VCA2617 operates on a single +5V supply while
consuming only 52mW per channel. It is available in a small
QFN-32 package (5x5mm).
− Suitable for 10-Bit and 12-Bit Systems
D
D
TEST EQUIPMENT
SONAR
RELATED PRODUCTS
PART NUMBER
DESCRIPTION
VCA2615
Dual, Low-Noise, Variable-Gain Amplifier with
Preamp
Gain
C
Select A
A
EXT
V
A
V
A
CLMP
CNTL
Out A+
In A+
Clamping
Circuitry
V−I
I−V
−
Out A
−
In A
Out B+
In B+
Clamping
Circuitry
V−I
I−V
−
Out B
−
In B
V
B
V
B
CLMP
Gain
CNTL
C
B
EXT
Select B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢃ ꢉꢆꢉ ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑꢊꢍꢋ ꢊꢒ ꢓꢔ ꢎ ꢎ ꢕꢋꢑ ꢐꢒ ꢍꢌ ꢖꢔꢗ ꢘꢊꢓ ꢐꢑꢊ ꢍꢋ ꢙꢐ ꢑꢕꢚ ꢀꢎ ꢍꢙꢔ ꢓꢑꢒ
ꢓ ꢍꢋ ꢌꢍꢎ ꢏ ꢑꢍ ꢒ ꢖꢕ ꢓ ꢊ ꢌꢊ ꢓ ꢐ ꢑꢊ ꢍꢋꢒ ꢖ ꢕꢎ ꢑꢛꢕ ꢑꢕ ꢎ ꢏꢒ ꢍꢌ ꢆꢕꢜ ꢐꢒ ꢇꢋꢒ ꢑꢎ ꢔꢏ ꢕꢋꢑ ꢒ ꢒꢑ ꢐꢋꢙ ꢐꢎ ꢙ ꢝ ꢐꢎ ꢎ ꢐ ꢋꢑꢞꢚ
ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ
Copyright 2005, Texas Instruments Incorporated
www.ti.com
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SBOS326 −AUGUST 2005
(1)
This integrated circuit can be damaged by ESD.
Texas Instruments recommends that all
integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and
installation procedures can cause damage.
ABSOLUTE MAXIMUM RATINGS
Power Supply (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
DD
VCA2617 Analog Input . . . . . . . . . . . . . . . . . −0.3V to (+V + 0.3V)
Logic Input . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to (+V + 0.3V)
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −40°C to +150°C
S
S
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
(1)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
(1)
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
TRANSPORT MEDIA,
QUANTITY
PRODUCT
PACKAGE-LEAD
ORDERING NUMBER
VCA2617RHBT
VCA2617RHBR
Tape and Reel, 250
Tape and Reel, 3000
VCA2617
QFN−32
RHB
−40°C to +85°C
VCA2617
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
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SBOS326 −AUGUST 2005
ELECTRICAL CHARACTERISTICS
All specifications at T = +25°C, V
= 5V, load resistance = 500Ω on each output to ground, differential output (1V ), CA, CB = 3.9µF,
A
DD
PP
single-ended input configuration, f = 5MHz, HG = Low (High-Gain Mode), V
= 2.3V, unless otherwise noted.
IN CNTL
VCA2617
TYP
MIN
MAX
PARAMETER
CONDITIONS
UNIT
VARIABLE GAIN AMPLIFIER
Input Resistance
Single-Ended
300
8
kΩ
pF
Input Capacitance
Maximum Input Voltage
Differential
(1)
Linear Operation ; Each Input
2.0
1.0
4.1
1
V
V
PP
PP
Single-Ended
Input Voltage Noise
Input Current Noise
Noise Figure
Gain = 45dB, R = 0Ω
Independent of Gain
nV/√Hz
pA/√Hz
dB
S
13.3
2.5
50
Input Common-Mode Voltage
Bandwidth
Internal
V
MHz
V
Clipping Voltage Range (V
Clipping Voltage Variation
)
0.25 to 2.6
CLMP
V
= 0.5V, VCA
OUT
= 1.0V
PP
75
80
mV
CLMP
50Ω in Series
Maximum Capacitive Output Loading
Slew Rate
pF
100
6
V/µs
(1)
Maximum Output Signal
V
PP
V
Output Common-Mode Voltage
Output Impedance
2.5
3
at 5MHz, Single-Ended, Either Output
Ω
Output Short-Circuit Current
2nd-Harmonic Distortion
3rd-Harmonic Distortion
Overload Distortion (2nd-Harmonic)
Crosstalk
60
mA
dBc
dBc
dBc
dB
V
V
= 1V , V
PP CNTL
= 1.5V
= 1.5V
−43
−43
−53
−62
−40
−61
1
OUT
OUT
= 1V , V
PP CNTL
Input Signal = 1V , V
PP CNTL
= 2V
Delay Matching
ns
ACCURACY
Gain Slope
V
V
V
V
= 0.4V to 2.0V
22
0.9
dB/V
dB
CNTL
CNTL
CNTL
CNTL
(2)
Gain Error
= 0.4V to 2.0V
= 0.2V to 2.3V
= 0.4V to 2.0V
−2
+2
Gain Range
48
dB
35.5
dB
Gain Range (HG)
HG = 0 (+6dB); VGA High Gain; V
= 0.2V to 2.3V
= 0.2V to 2.3V
−10 to +38
−16 to +32
50
dB
CNTL
HG = 1 (0dB); VGA Low Gain; V
CNTL
dB
Output Offset Voltage, Differential
Channel-to-Channel Gain Matching
mV
dB
V
= 0.4V to 2.0V
0.8
CNTL
GAIN CONTROL INTERFACE (V
)
CNTL
Input Voltage Range
Input Resistance
Response Time
0.2 to 2.3
V
1
MΩ
µs
42dB Gain Change; to 90% Signal Level
0.5
(3), (4)
DIGITAL INPUTS
(HGA, HGB, PD)
V
, High-Level Input Voltage
IH
, Low-Level Input Voltage
2.0
V
V
V
0.8
IL
Input Resistance
Input Capacitance
1
5
MΩ
pF
POWER SUPPLY
Supply Voltage
4.75
5.0
105
22
25
2
5.25
125
V
Power Dissipation
mW
mW
µs
Power-Down
Power-Up Response Time
Power-Down Response Time
µs
THERMAL CHARACTERISTICS
Temperature Range
Ambient, Operating
−40
+85
°C
Thermal Resistance, q
Soldered Pad; Four-Layer PCB with Thermal Vias
36.7
4.0
°C/W
°C/W
JA
q
JC
(1)
(2)
(3)
(4)
2nd, 3rd-harmonic distortion less than or equal to −30dBc.
Referenced to best fit dB-linear curve.
Parameters ensured by design; not production tested.
Do not leave inputs floating; no internal pull-up/pull-down resistors.
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SBOS326 −AUGUST 2005
PIN CONFIGURATION
24
23
22
1
2
3
4
5
6
7
8
VCNTL
CLMPA
HGA
A
INA+
NC
V
VDDR
VCA2617
(Thermal Pad tied to
Ground Potential)
21 NC
20
19 HGB
VB
PD
VCM
GNDR
NC
18
17
V
V
CLMPB
CNTLB
INB+
PIN DESCRIPTIONS
PIN
DESIGNATOR
DESCRIPTION
PIN
17
DESIGNATOR
DESCRIPTION
1
IN +
A
Channel A +Input
V
B
Channel B Gain Control Voltage Input
Channel B Clamp Voltage
CNTL
2
NC
No Internal Connection
18
V
B
CLMP
HGB
PD
3
4
V
R
Reference Supply
19
20
21
22
23
24
25
26
27
Channel B High/Low Output Gain (High = Low Gain)
Power Down (Active High)
DD
VB
Bias Voltage, 0.1µF Bypass Capacitor
Common-mode Voltage, 0.1µF Bypass Capacitor
Internal Reference Ground
No Internal Connection
5
V
NC
No Internal Connection
CM
GNDR
NC
6
HGA
Channel A High/Low Output Gain (High = Low Gain)
Channel A Clamp Voltage
7
V
A
A
CLMP
8
IN +
Channel B+ Input
V
Channel A Gain Control Voltage Input
Channel A+ Output
B
CNTL
9
IN −
B
Channel B− Input
Out +
A
10
11
NC
CB2
CB1
No Internal Connection
Out −
A
Channel A− Output
Channel B, External Coupling Capacitor
GNDA
Channel A Ground
12
13
14
15
16
Channel B, External Coupling Capacitor
Channel B Supply
28
29
30
31
32
V
A
Channel A Supply
DD
V
B
CA1
CA2
NC
Channel A; External Coupling Capacitor
Channel A; External Coupling Capacitor
No Internal Connection
DD
GNDB
Channel B Ground
Out −
Channel B− Output
B
Out +
Channel B+ Output
IN −
Channel A− Input
B
A
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SBOS326 −AUGUST 2005
TYPICAL CHARACTERISTICS
All specifications at T = +25°C, V
DD
= 5V, load resistance = 500Ω on each output to ground, differential output (1V ), CA, CB = 3.9µF,
PP
A
single-ended input configuration, f = 5MHz, HG = Low (High-Gain Mode), V
= 2.3V, unless otherwise noted.
IN
CNTL
GAIN vs VCNTL
GAIN ERROR vs VCNTL
60
55
50
45
40
35
30
25
20
15
10
5
2.0
1.5
1.0
0.5
0
HG = 0
HG = 0
HG = 1
HG = 1
−
−
−
−
0.5
1.0
1.5
2.0
0
−
5
−
−
−
10
15
20
VCNTL (V)
VCNTL (V)
Figure 1
Figure 2
GAIN vs VCNTL vs FREQUENCY
GAIN ERROR vs VCNTL vs FREQUENCY
50
40
30
20
10
0
2.0
1.5
1.0
0.5
0
−
−
−
−
0.5
1.0
1.5
2.0
1MHz
2MHz
5MHz
1MHz
2MHz
5MHz
−
10
20
10MHz
10MHz
−
VCNTL (V)
VCNTL (V)
Figure 3
Figure 4
GAIN vs VCNTL vs TEMPERATURE
GAIN ERROR vs VCNTL vs TEMPERATURE
45
40
35
30
25
20
15
10
5
2.0
1.5
1.0
0.5
0
−
_
40 C
−
_
40 C
_
+25 C
_
+25 C
_
+85 C
−
−
−
−
_
0.5
1.0
1.5
2.0
+85 C
0
−
5
−
−
10
15
VCNTL (V)
VCNTL (V)
Figure 5
Figure 6
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SBOS326 −AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at T = +25°C, V
DD
= 5V, load resistance = 500Ω on each output to ground, differential output (1V ), CA, CB = 3.9µF,
PP
A
single-ended input configuration, f = 5MHz, HG = Low (High-Gain Mode), V
= 2.3V, unless otherwise noted.
IN
CNTL
GAIN MATCHING, CHA to CHB
GAIN MATCHING, CHA to CHB
70
100
VCNTL = 2.0V
VCNTL = 0.4V
90
80
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
Delta Gain (dB)
Delta Gain (dB)
Figure 7
Figure 8
GAIN vs FREQUENCY
GAIN vs FREQUENCY
45
40
µ
3.9 F
HG = 0, VCNTL = 2.3V
40
39
38
37
36
35
34
33
32
31
µ
0.1 F
35
30
25
20
15
10
5
HG = 1, VCNTL = 2.3V
4700pF
µ
0.022 F
HG = 0, VCNTL = 0.7V
0
−
5
HG = 1, VCNTL = 0.7V
10
−
10
0.1
1
10
100
0.1
1
100
Frequency (MHz)
Frequency (MHz)
Figure 10
Figure 9
OUTPUT−REFERRED NOISE vs VCNTL
INPUT−REFERRED NOISE vs VCNTL
1000
100
10
1000
100
10
HG = 1
HG = 0
HG = 0
HG = 1
1
VCNTL (V)
VCNTL (V)
Figure 12
Figure 11
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SBOS326 −AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at T = +25°C, V
DD
= 5V, load resistance = 500Ω on each output to ground, differential output (1V ), CA, CB = 3.9µF,
PP
A
single-ended input configuration, f = 5MHz, HG = Low (High-Gain Mode), V
= 2.3V, unless otherwise noted.
IN
CNTL
INPUT−REFERRED NOISE vs FREQUENCY
(Hi VGA Gain)
NOISE FIGURE vs VCNTL
100
10
HG = 1
HG = 0
10
1
1
10
VCNTL (V)
Frequency (MHz)
Figure 13
Figure 14
DISTORTION vs FREQUENCY
(2nd−Harmonic, VCNTL = 2.3V)
DISTORTION vs FREQUENCY
(3rd−Harmonic, VCNTL = 2.3V)
−
−
−
−
−
−
−
−
−
−
−
50
52
54
56
58
60
62
64
66
68
70
−
50
52
54
56
58
60
62
64
66
68
70
−
−
−
−
−
−
−
−
−
−
HG = 1
HG = 1
HG = 0
HG = 0
1
10
1
10
Frequency (MHz)
Frequency (MHz)
Figure 15
Figure 16
DISTORTION vs VCNTL
(Lo VGA Gain)
DISTORTION vs VCNTL
(Hi VGA Gain)
−
−
−
−
−
−
−
25
30
35
40
45
50
55
60
65
40
45
50
55
60
65
−
−
−
−
−
−
−
−
2nd−Harmonic
2nd−Harmonic
3rd−Harmonic
3rd−Harmonic
VCNTL (V)
VCNTL (V)
Figure 17
Figure 18
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SBOS326 −AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at T = +25°C, V
DD
= 5V, load resistance = 500Ω on each output to ground, differential output (1V ), CA, CB = 3.9µF,
PP
A
single-ended input configuration, f = 5MHz, HG = Low (High-Gain Mode), V
= 2.3V, unless otherwise noted.
IN
CNTL
DISTORTION vs RESISTIVE LOAD
DISTORTION vs VCA OUTPUT
−
40
45
50
55
60
65
70
−
−
−
−
−
−
−
−
−
40
45
50
55
60
65
70
75
80
−
−
−
−
−
−
2nd−Harmonic
3rd−Harmonic
2nd−Harmonic
3rd−Harmonic
Ω
Resistance ( )
VCA Output (VPP
)
Figure 19
Figure 20
CROSSTALK vs VCNTL
CROSSTALK vs VCNTL
−
−
−
−
−
−
−
−
−
−
−
55
57
59
61
63
65
67
69
71
73
75
−
55
57
59
61
63
65
67
69
71
73
75
−
−
−
−
−
−
−
−
−
−
HG = 0
HG = 1
1MHz
2MHz
5MHz
10MHz
VCNTL (V)
VCNTL (V)
Figure 21
Figure 22
TOTAL POWER vs TEMPERATURE
DISTORTION vs TEMPERATURE
−
−
−
−
−
−
80
75
70
65
60
55
105.8
105.7
105.6
105.5
105.4
105.3
105.2
105.1
105.0
104.9
3rd−Harmonic
2nd−Harmonic
−
−
−
−
−
−
−
−
40 30 20 10
0
10 20 30 40 50 60 70 80
40 30 20 10
0
10 20 30 40 50 60 70 80
_
_
Temperature ( C)
Temperature ( C)
Figure 24
Figure 23
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SBOS326 −AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at T = +25°C, V
DD
= 5V, load resistance = 500Ω on each output to ground, differential output (1V ), CA, CB = 3.9µF,
PP
A
single-ended input configuration, f = 5MHz, HG = Low (High-Gain Mode), V
= 2.3V, unless otherwise noted.
IN
CNTL
VCLMP vs VOUT
2ND−HARMONIC DISTORTION
(150mVPP, S/E Input)
−
−
20
24
6.2
5.8
5.4
5.0
4.6
4.2
3.8
3.4
3.0
2.6
2.2
1.8
1.4
1.0
0.6
0.2
−0.2
−28
HG = 0
−
−
−
−
32
36
40
44
HG = 1
−48
0.25
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
0.50
0.75
1.00
VCLMP (V)
VIN (VPP
)
Figure 25
Figure 26
2ND−HARMONIC DISTORTION vs VCNTL
(Differential Input)
DISTORTION vs VOUT
(Differential Input)
−45
−50
−45
−50
−55
−60
−65
−70
−75
−
55
HG = 0
2nd−Harmonic
−60
−65
−70
−75
3rd−Harmonic
HG = 1
VOUT
( )
PP
VCNTL (V)
Figure 27
Figure 28
3RD−HARMONIC DISTORTION vs VCNTL
(Differential Input)
DISTORTION vs RESISTIVE LOAD
(Differential)
−45
−50
−30
−35
−40
−45
−50
−55
−60
−65
−70
HG = 1
2nd−Harmonic
−
55
−60
−65
HG = 0
−
70
3rd−Harmonic
−75
50 100 150 200 250 300 350 400 450 500 550 600 650 700 750
Resistance (Ω)
VCNTL (V)
Figure 30
Figure 29
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SBOS326 −AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at T = +25°C, V
DD
= 5V, load resistance = 500Ω on each output to ground, differential output (1V ), CA, CB = 3.9µF,
PP
A
single-ended input configuration, f = 5MHz, HG = Low (High-Gain Mode), V
= 2.3V, unless otherwise noted.
IN
CNTL
OUTPUT IMPEDANCE vs FREQUENCY
100
GROUP DELAY vs FREQUENCY
25
23
21
19
17
15
10
1
0.1
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
Figure 32
Figure 31
GAIN CONTROL TRANSIENT RESPONSE
2V
0V
1VPP
µ
Time (0.4 s/div)
Figure 33
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Table 1. Gain and Noise Performance of Various
VCA Blocks
THEORY OF OPERATION
The VCA2617 is a dual-channel variable gain amplifier
(VGA) with each channel being independant. The VGA is
a true variable-gain amplifier, achieving lower noise output
at lower gains. The output amplifier has two gains, allowing
for further optimization with different analog-to-digital
converters. Figure 34 shows a simplified block diagram of
a single channel of the dual-channel system. The VGA can
be powered down in order to conserve system power when
necessary.
NOISE nV/√Hz
BLOCK
GAIN (Loss) dB
Buffer
0
0
3.9
2.2
2.2
4.1
90
Attenuator (VCA2619)
Attenuator (VCA2619)
VCA1 (VCA2617)
VCA1 (VCA2617)
VCA1 (VCA2619)
−40
40
0
40
3.9
When the block diagram shown in Figure 34 has a gain of
40dB, the noise referred to the input (RTI) is:
Ǹ
(1)
Total Noise (RTI) + 4.1nVń Hz
VGA
When the block diagram shown in Figure 35 has the
combined gain of 60dB, the noise referred to the input
(RTI) is given by the expression:
Figure 34. Simplified Block Diagram of VCA2617
VGA—OVERVIEW
Total Noise (RTI) +
Ǹ(Buffer Noise)
2
2
2
) (ATTEN Noise) ) (VCA Noise)
Ǹ
+ Ǹ(3.9)
2
2
2
) (2.2) ) (3.9) + 5.9nVń Hz
(2)
The VGA that is used with the VCA2617 is a true
variable-gain amplifier; as the gain is reduced, the noise
contribution from the VGA itself is also reduced. This
design is in contrast with another popular device
architecture (used by the VCA2619), where an effective
VCA characteristic is obtained by a voltage-variable
attenuator succeeded by a fixed-gain amplifier. At the
highest gain, systems with either architecture are
dominated by the noise produced at the input to either the
fixed or variable gain amplifier. At low gains, however, the
noise output is dominated by the contribution from the
VGA. Therefore, the overall system with lower VGA gain
will produce less noise.
Repeating the above measurements for both VCA
configurations when the overall gain is 10dB yields the
following results:
For the VCA with a variable gain amplifier (Figure 34):
Ǹ
Total Noise (RTI) + 90nVń Hz
(3)
For the VCA with a variable attenuation attenuator
(Figure 35):
2
2
2
Total Noise + Ǹ(3.9) ) (2.2) ) (2.0ń0.10)
Ǹ
+ 14nVń Hz
The following example will illustrate this point. Figure 34
shows a block diagram of the variable-gain amplifier;
Figure 35 shows a block diagram of a variable attenuation
attenuator followed by a fixed gain amplifier. For purposes
of this example, let us assume the performance
characteristics shown in Table 1; these values are the
typical performance data of the VCA2617 and the
VCA2619.
(4)
The VGA has a continuously-variable gain range of 48dB
with the ability to select either of two options. The gain of
the VGA can either be varied from −10dB to 38dB, or from
−16dB to 32dB. The VGA output can be programmed to
clip at a predetermined voltage that is selected by the user.
When the user applies a voltage to the VCLMP-pin, the
output will have a peak-to-peak voltage that is given by the
graph shown in Figure 26.
Amplifier
Buffer
ATTENUATOR
Figure 35. Block Diagram of Older VCA Models
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is fixed, will not show diminished noise in this manner.
Refer to Table 2, which shows a comparison between the
noise performance at different gains for the VCA2617 and
the older VCA2619.
VOLTAGE-CONTROLLEDAMPLIFIER (VCA)—
DETAIL
Figure 36 shows a simplified schematic of the VCA. The
VCA2617 is a true voltage-controlled amplifier, with the
gain expressed in dB directly proportional to a control
signal. This architecture compares to the older VCA
products where a voltage-controlled attenuator was
followed by a fixed-gain amplifier. With a variable-gain
amplifier, the output noise diminishes as the gain reduces.
A variable-gain amplifier, where the output amplifier gain
Table 2. Noise vs Gain (R = 0)
G
NOISE RTI (nV/√Hz)
PRODUCT
VCA2617
VCA2617
VCA2619
VCA2619
GAIN (dB)
40
0
4.1
100
5.9
40
0
500
Clipping Program
Circuitry
VDD
HGA/B
R1
Q1
Q5
Q7
Q9
R2
D1
D3
D2
+IN
Q2
Q3
A1
D4
A2
VCM
Q4
Q6
Q8
External
Capacitor
VCNTL
Q10
Q11
Q12
Q14
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
Q24
C1
C2
VCA
Program
Circuitry
C
Q13
Q30
Q15
Q25
Voltage−Controlled
Resistor Network
Control Signal
Q26
Q32
VCM
D5
D7
D6
D8
A4
Q27
A3
R3
Q28
−
IN
R4
Q29
Q31
Q33
Q34
VDD
Clipping Program
Circuitry
VCLMP
Figure 36. Block Diagram of VCA
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The VCA accepts a differential input at the +IN and −IN
terminals. Amplifier A1, along with transistors Q2 and Q3,
forms a voltage follower that buffers the +IN signal to be
able to drive the voltage-controlled resistor. Amplifier A3,
along with transistors Q27 and Q28, plays the same role
as A1. The differential signal applied to the
voltage-controlled resistor network is converted to a
current that flows through transistors Q1 through Q4.
Through the mirror action of transistors Q1/Q5 and Q4/Q6,
a copy of this same current flows through Q5 and Q6.
Assuming that the signal current is less than the
programmed clipping current (that is, the current flowing
through transistors Q7 and Q8), the signal current will then
go through the diode bridge (D1 through D4) and be sent
through either R2 or R1, depending upon the state of Q9.
This signal current multiplied by the feedback resistor
associated with amplifier A2, determines the signal
voltage that is designated −OUT. Operation of the circuitry
associated with A3 and A4 is identical to the operation of
the previously described function to create the signal
+OUT.
balanced configuration is used to keep the second
harmonic component of the distortion low. The common
source connection associated with each group of FET
variable resistors is brought out to an external pin so that
an external capacitor can be used to make an AC
connection. This connection is necessary to achieve an
adequate low-frequency bandwidth because the coupling
capacitor would be too large to include within the
monolithic chip. The value of this variable resistor ranges
in value from 15Ω to 5000Ω to achieve a gain range of
about 48dB. The low-frequency bandwidth is then given by
the formula:
Low Frequency BW + 1ń2pRC
(5)
where:
R is the value of the attenuator.
C is the value of the external coupling capacitor.
For example, if a low-frequency bandwidth of 500kHz was
desired and the value of R was 10Ω, then the value of the
coupling capacitor would be 0.05µF.
A1 and its circuitry form a voltage-to-current converter,
while A2 and its circuitry form a current-to-voltage
converter. This architecture was adapted because it has
excellent signal-handling capability. A1 has been
designed to handle a large voltage signal without
overloading, and the various mirroring devices have also
been sized to handle large currents. Good overload
capability is achieved as both the input and output
amplifier are not required to amplify voltage signals.
Voltage amplification occurs when the input voltage is
converted to a current; this current in turn is converted
back to a voltage as amplifier A2 acts as a transimpedance
amplifier. The overall gain of the output amplifier A2 can be
altered by 6dB by the action of the HG signal. This enables
more optimum performance when the VCA interfaces with
either a 10-bit or 12-bit analog-to-digital converter (ADC).
An external capacitor (C) is required to provide a low
impedance connection to join the two sections of the
resistor network. Capacitor C could be replaced by a
short-circuit. By providing a DC connection, the output
offset will be a function of the gain setting. Typically, the
offset at this point is 10mV; thus, if the gain varies from
1 to 100, the output offset would vary from 10mV to
100mV.
One of the benefits of this method of gain control is that the
output offset is independent of the variable gain of the
output amplifier. The DC gain of the output amplifier is
extremely low; any change in the input voltage is blocked
by the coupling capacitor, and no signal current flows
through the variable resistor. This method also means that
any offset voltage existing in the input is stored across this
coupling capacitor; when the resistor value is changed, the
DC output will not change. Therefore, changes in the
control voltage do not appear in the output signal.
Figure 37 shows the output waveform resulting from a step
change in the control voltage, and Figure 38 shows the
output voltage resulting when the control voltage is a
full-scale ramp.
Channel 1
VCNTL
(2V/div)
Channel 2
Output
VARIABLE GAIN CHARACTERISTICS
(20mV/div)
Transistors Q10, Q12, Q14, Q16, Q18, Q20, Q22, and Q24
form a variable resistor network that is programmed in an
exponential manner to control the gain. Transistors Q11,
Q13, Q15, Q17, Q19, Q21, Q23, and Q25 perform the
same function. These two groups of FET variable resistors
are configured in this manner to balance the capacitive
loading on the total variable-resistor network. This
Time (400ns/div)
Figure 37. Response to Step Change of V
CNTL
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When FETs used as variable resistors are placed in
parallel, the attenuation characteristic that is created
behaves according to this same exponential characteristic
at discrete points as a function of the control voltage.
It does not perfectly obey an ideal exponential
characteristic at other points; however, an 8-section
approximation yields a 1dB error to an ideal curve.
Channel 1
VCNTL
(2V/div)
PROGRAMMABLE CLIPPING
Channel 2
Output
The clipping level of the VCA2617 can be programmed to
a desired output. The programming feature is useful when
matching the clipped level from the output of the VCA to
the full-scale range of a subsequent VCA, in order to
prevent the VCA from generating false spectral signals;
see the circuit diagram shown in Figure 39. The signal
node at the drain junction of Q5 and Q6 is sent to the diode
bridge formed by diode-connected transistors, D1 through
D4. The diode bridge output is determined by the current
that flows through transistors Q7 and Q8. The maximum
current that can then flow into the summing node of A2 is
this same current; consequently, the maximum voltage
output of A2 is this same current multiplied by the feedback
resistor associated with A2. The maximum output voltage
of A2, which would be the clipped output, can then be
controlled by adjusting the current that flows through Q7
and Q8; see the circuit diagram shown in Figure 36. The
circuitry of A1, R1, and Q1 converts the clamp voltage
(VCLMP) to a current that controls equal and opposite
currents flowing through transistors Q5 and Q6.
(20mV/div)
Time (400ns/div)
Figure 38. Response to Ramp Change of V
CNTL
The exponential gain control characteristic is achieved
through a piecewise approximation to a perfectly smooth
exponential curve. Eight FETs, operated as variable
resistors whose value is progressively 1/2 of the value of
the adjacent parallel FET, are turned on progressively, or
their value is lowered to create the exponential gain
characteristic. This characteristic can be shown in the
following way. An exponential such as y = ex increases in
the y dimension by a constant ratio as the x dimension
increases by a constant linear amount. In other words, for
x1 x2
a constant (x1 − x2), the ratio e /e remains the same.
VDD
R1
Q9
Q1
Q5
Q7
HGA/B
R2
From
Buffered
Input
D1
D3
D2
D4
A1
Q2
Clip Adjust
Input
A2
VCM
Output
Amplifier
Q6
Q8
Figure 39. Clipping Level Adjust Circuitry
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When HG = 0, the previously described circuitry is
designed so that the value of the VCLMP signal is equal to
the peak differential signal developed between +VOUT and
−VOUT. When HG = 1, the differential output will be equal
to the clamp voltage. This method of controlled clipping
also achieves fast and clean settling waveforms at the
output of the VCA, as shown in Figure 40 through
Figure 43. The sequence of waveforms demonstrate the
clipping performance during various stages of overload.
In a typical application, the VCA2617 will drive an
anti-aliasing filter, which in turn will drive an ADC. Many
modern ADCs, such as the ADS5270, are well-behaved
with as much as 2x overload. This means that the clipping
level of the VCA should be set to overcome the loss in the
filter such that the clipped input to the ADC is just slightly
over the full-scale input. By setting the clipping level in this
manner, the lowest harmonic distortion level will be
achieved without interfering with the overload capability of
the ADC.
Input
Input
(0.5V/div)
(0.5V/div)
Differential
Output
Differential
Output
(0.5V/div)
(0.5V/div)
Time (200ns/div)
VCNTL = 1.0V
Time (200ns/div)
VCNTL = 1.0V
Figure 42. Overload (1.5V
Input)
Figure 40. Before Overload (630mV
Input)
PP
PP
Input
Input
(2V/div)
(0.5V/div)
Differential
Output
Differential
Output
(1V/div)
(0.5V/div)
Time (200ns/div)
Time (200ns/div)
VCNTL = 1.0V
VCNTL = 1.0V
Figure 43. Extreme Overload (3.8V
Input)
Figure 41. Approaching Overload
(700mV Input)
PP
PP
15
PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2006
PACKAGING INFORMATION
Orderable Device
VCA2617RHBR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RHB
32
32
32
32
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
VCA2617RHBRG4
VCA2617RHBT
QFN
QFN
QFN
RHB
RHB
RHB
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
VCA2617RHBTG4
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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