MSC1212Y4 [BB]
Precision Analog-to-Digital Converter (ADC); 高精度模拟数字转换器（ ADC ）
| 型号： | MSC1212Y4 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Precision Analog-to-Digital Converter (ADC) |
| 文件： | 总69页 (文件大小：1095K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSC1212
®
M
S
C
1
2
1
2
SBAS278A – MARCH 2003 – REVISED DECEMBER 2004
Precision Analog-to-Digital Converter (ADC)
and Digital-to-Analog Converters (DACs)
with 8051 Microcontroller and Flash Memory
Peripheral Features
FEATURES
ANALOG FEATURES
● 34 I/O PINS
● ADDITIONAL 32-BIT ACCUMULATOR
● THREE 16-BIT TIMER/COUNTERS
● SYSTEM TIMERS
● PROGRAMMABLE WATCHDOG TIMER
● FULL-DUPLEX DUAL USARTS
● MASTER/SLAVE SPI™ WITH DMA
● 16-BIT PWM
● 24-BITS NO MISSING CODES
● 22-BITS EFFECTIVE RESOLUTION AT 10Hz
Low Noise: 75nV
● PGA FROM 1 TO 128
● PRECISION ON-CHIP VOLTAGE REFERENCE:
Accuracy: 0.2%
Drift: 5ppm/°C
● POWER MANAGEMENT CONTROL
● INTERNAL CLOCK DIVIDER
● IDLE MODE CURRENT < 200µA
● STOP MODE CURRENT < 100nA
● PROGRAMMABLE BROWNOUT RESET
● PROGRAMMABLE LOW VOLTAGE DETECT
● 21 INTERRUPT SOURCES
● 8 DIFFERENTIAL/SINGLE-ENDED CHANNELS
● ON-CHIP OFFSET/GAIN CALIBRATION
● OFFSET DRIFT: 0.02PPM/°C
● GAIN DRIFT: 0.5PPM/°C
● ON-CHIP TEMPERATURE SENSOR
● SELECTABLE BUFFER INPUT
● BURNOUT DETECT
● QUAD 16-BIT MONOTONIC VOLTAGE DACs:
2 VDACs Can Be Programmed as IDACs
8µs Settling Time
● TWO HARDWARE BREAKPOINTS
GENERAL FEATURES
● PIN-COMPATIBLE WITH MSC1210/11/13/14
● PACKAGE: TQFP-64
● LOW POWER: 4mW
● INDUSTRIAL TEMPERATURE RANGE:
–40°C to +85°C
● POWER SUPPLY: 2.7V to 5.25V
DIGITAL FEATURES
Microcontroller Core
● 8051 COMPATIBLE
● HIGH SPEED CORE:
4 Clocks per Instruction Cycle
● DC TO 30MHz
● SINGLE INSTRUCTION 133ns
● DUAL DATA POINTER
APPLICATIONS
● INDUSTRIAL PROCESS CONTROL
● INSTRUMENTATION
Memory
● UP TO 32kB FLASH DATA MEMORY
● FLASH MEMORY PARTITIONING
● ENDURANCE 1M ERASE/WRITE CYCLES,
100-YEAR DATA RETENTION
● IN-SYSTEM SERIALLY PROGRAMMABLE
● EXTERNAL PROGRAM/DATA MEMORY (64kB)
● 1280 BYTES DATA SRAM
● FLASH MEMORY SECURITY
● 2kB BOOT ROM
● PROGRAMMABLE WAIT STATE CONTROL
● LIQUID/GAS CHROMATOGRAPHY
● BLOOD ANALYSIS
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTS
● WEIGH SCALES
● PRESSURE TRANSDUCERS
● INTELLIGENT SENSORS
● PORTABLE APPLICATIONS
● DAS SYSTEMS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2003-2004, Texas Instruments Incorporated
www.ti.com
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
FLASH
MEMORY
PACKAGE
DESIGNATOR
PACKAGE
MARKING
PRODUCT
PACKAGE-LEAD
MSC1212Y2
MSC1212Y2
4k
4k
TQFP-64
PAG
"
–40°C to +85°C
MSC1212Y2
"
"
"
MSC1212Y3
MSC1212Y3
8k
8k
TQFP-64
PAG
"
–40°C to +85°C
MSC1212Y3
"
"
"
MSC1212Y4
MSC1212Y4
16k
16k
TQFP-64
PAG
"
–40°C to +85°C
MSC1212Y4
"
"
"
MSC1212Y5
MSC1212Y5
32k
32k
TQFP-64
PAG
"
–40°C to +85°C
MSC1212Y5
"
"
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or refer to our web
site at www.ti.com/msc.
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
Analog Inputs
DISCHARGE SENSITIVITY
Input Current ............................................................ 100mA, Momentary
Input Current .............................................................. 10mA, Continuous
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
Input Voltage .............................................AGND – 0.3V to AVDD + 0.3V
Power Supply
DVDD to DGND......................................................................–0.3V to 6V
AVDD to AGND ......................................................................–0.3V to 6V
AGND to DGND .............................................................. –0.3V to +0.3V
V
REF to AGND ....................................................... –0.3V to AVDD + 0.3V
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
Digital Input Voltage to DGND .............................. –0.3V to DVDD + 0.3V
Digital Output Voltage to DGND ........................... –0.3V to DVDD + 0.3V
Maximum Junction Temperature ................................................ +150°C
Operating Temperature Range ...................................... –40°C to +85°C
Storage Temperature Range ....................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................ +235°C
Package Power Dissipation ................................ (TJ Max - TAMBIENT)/θJA
Output Current All Pins ................................................................ 200mA
Output Pin Short Circuit .....................................................................10s
Thermal Resistance, Junction-to-Ambient (θJA) High K (2s2p) 50.9°C/W
Thermal Resistance, Junction-to-Ambient (θJA) Low K (1s) .... 76.2°C/W
Thermal Resistance, Junction-to-Case (θJC) ........................... 12.5°C/W
Digital Outputs
Output Current ......................................................... 100mA, Continuous
I/O Source/Sink Current ............................................................... 100mA
Power Pin Maximum .................................................................... 300mA
NOTE: (1) Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
MSC1212Yx FAMILY FEATURES
FEATURES(1)
MSC1212Y2(2)
MSC1212Y3(2)
MSC1212Y4(2)
MSC1212Y5(2)
Flash Program Memory (Bytes)
Flash Data Memory (Bytes)
Up to 4k
Up to 4k
Up to 8k
Up to 8k
Up to 16k
Up to 16k
Up to 32k
Up to 32k
Internal Scratchpad RAM (Bytes)
Internal MOVX SRAM (Bytes)
Externally Accessible Memory (Bytes)
256
1024
256
1024
256
1024
256
1024
64k Program, 64k Data
64k Program, 64k Data
64k Program, 64k Data
64k Program, 64k Data
NOTES: (1) All peripheral features are the same on all devices; the flash memory size is the only difference. (2) The last digit of the part number (N) represents
the onboard flash size = (2N)kBytes.
MSC1212
2
SBAS278A
www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V,
unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
MSC1212Yx
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN0-AIN7, AINCOM)
Analog Input Range
Buffer OFF
Buffer ON
(In+) – (In–); See Figure 4
Buffer OFF
AGND – 0.1
AGND + 50mV
AVDD + 0.1
AVDD – 1.5
±VREF/PGA
V
V
V
MΩ
nA
Full-Scale Input Voltage Range
Differential Input Impedance
Input Current
7/PGA
0.5
Buffer ON
Bandwidth
Fast Settling Filter
Sinc2 Filter
Sinc3 Filter
–3dB
–3dB
–3dB
0.469 • fDATA
0.318 • fDATA
0.262 • fDATA
Programmable Gain Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
User-Selectable Gain Ranges
Buffer ON
Multiplexer Channel Off, T = +25°C
Sensor Input Open Circuit
1
128
9
0.5
±2
pF
pA
µA
ADC OFFSET DAC
Offset DAC Range
±VREF/(2 • PGA)
V
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
8
Bits
% of Range
ppm/°C
±1.5
1
SYSTEM PERFORMANCE
Resolution
ENOB
24
Bits
Bits
22
Output Noise
See Typical Characteristics
No Missing Codes
Integral Nonlinearity
Offset Error
Offset Drift(1)
Gain Error(2)
Gain Error Drift(1)
System Gain Calibration Range
System Offset Calibration Range
Common-Mode Rejection
Sinc3 Filter
End Point Fit, Differential Input
After Calibration
24
Bits
%FSR
ppm of FS
ppm of FS/°C
%
ppm/°C
% of FS
% of FS
dB
±0.0015
7.5
0.02
0.005
0.5
Before Calibration
After Calibration
Before Calibration
80
–50
100
120
50
At DC
115
130
120
120
100
100
88
fCM = 60Hz, fDATA = 10Hz
fCM = 50Hz, fDATA = 50Hz
fCM = 60Hz, fDATA = 60Hz
dB
dB
dB
dB
dB
dB
Normal Mode Rejection
Power-Supply Rejection
f
f
SIG = 50Hz, fDATA = 50Hz
SIG = 60Hz, fDATA = 60Hz
(3)
At DC, dB = –20log(∆VOUT/∆VDD
)
VOLTAGE REFERENCE INPUTS
Reference Input Range
VREF
VREF Common-Mode Rejection
Input Current(4)
(2)
REF IN+, REF IN–
VREF ≡ (REF IN+) – (REF IN–)
At DC
VREF = 2.5V, ADC Only
For Each DAC, 5V Reference
0.0
0.3
AVDD
AVDD
V
V
dB
µA
µA
2.5
110
10
DAC Reference Current
25
ON-CHIP VOLTAGE REFERENCE
Output Voltage
VREFH = 1 at +25°C, PGA = 1, 2, 4, 8
2.495
2.5
1.25
2.505
V
V
VREFH = 0
Power-Supply Rejection Ratio
Short-Circuit Current Source
Short-Circuit Current Sink
Short-Circuit Duration
65
8
50
dB
mA
µA
Sink or Source
Indefinite
Drift
5
3
8
ppm/°C
Ω
ms
Output Impedance
Startup Time from Power ON
Temperature Sensor
Sourcing 100µA
CREFOUT = 0.1µF
Temperature Sensor Voltage
Temperature Sensor Coefficient
T = +25°C
115
375
mV
µV/°C
VOLTAGE DAC STATIC PERFORMANCE(5)
Resolution
Relative Accuracy
Differential Nonlinearity
Zero Code Error
Full-Scale Error
Gain Error
Zero Code Error Drift
Gain Temperature Coefficient
16
Bits
%
LSB
±0.05
±0.146
±1
+35
All 0s Loaded to DAC Register
All 1s Loaded to DAC Register
+13
0
0
±20
±5
mV
–1.25
–1.25
% of FSR
% of FSR
µV/°C
+1.25
ppm of FSR/°C
MSC1212
SBAS278A
3
www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)
All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V,
unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
MSC1212Yx
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
VOLTAGE DAC OUTPUT CHARACTERISTICS(6)
Output Voltage Range
Output Voltage Settling Time
Slew Rate
AGND
AVDD
V
µs
V/µs
Ω
To ±0.003% FSR, 0200H to FD00H
8
1
7
DC Output Impedance
Short-Circuit Current
All 1s Loaded to DAC Register
Maximum VREF = 2.5V
20
mA
IDAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
Maximum Short-Circuit Current Duration
Compliance Voltage
Relative Accuracy
Zero Code Error
25
Indefinite
AVDD – 1.5
0.185
mA
V
Over Full Range
% of FSR
% of FSR
% of FSR
% of FSR
0.5
–0.4
–0.6
Full-Scale Error
Gain Error
ANALOG POWER-SUPPLY REQUIREMENTS
Analog Power-Supply Voltage
Analog Current
ADC Current
AVDD
Analog OFF, PDAD = 1
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
4.75
5.25
V
IADC + IVREF
IADC
< 1
200
500
240
850
250
250
nA
µA
µA
µA
µA
µA
µA
PGA = 128, Buffer ON
Excluding Load Current External Reference
ADC ON, VDAC OFF
VDAC Current
VREF Supply Current
IVDAC
IVREF
NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AVDD – 1.5V with buffer ON. To calibrate gain,
turn buffer off. (3) ∆VOUT is change in digital result. (4) 9pF switched capacitor at fSAMP clock frequency (see Figure 6). (5) Linearity calculated using a reduced code
range of 512 to 65024; output unloaded. (6) Ensured by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications from TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +1.25V,
unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
MSC1212Yx
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN0-AIN7, AINCOM)
Analog Input Range
Buffer OFF
Buffer ON
(In+) – (In–); See Figure 4
Buffer OFF
AGND – 0.1
AGND + 50mV
AVDD + 0.1
AVDD – 1.5
±VREF/PGA
V
V
V
MΩ
nA
Full-Scale Input Voltage Range
Differential Input Impedance
Input Current
7/PGA
0.5
Buffer ON
Bandwidth
Fast Settling Filter
Sinc2 Filter
Sinc3 Filter
–3dB
–3dB
–3dB
0.469 • fDATA
0.318 • fDATA
0.262 • fDATA
Programmable Gain Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
User-Selectable Gain Ranges
Buffer On
Multiplexer Channel Off, T = +25°C
Sensor Input Open Circuit
1
128
9
0.5
±2
pF
pA
µA
ADC OFFSET DAC
Offset DAC Range
±VREF/(2 • PGA)
V
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
8
Bits
% of Range
ppm/°C
±1.5
1
SYSTEM PERFORMANCE
Resolution
ENOB
24
Bits
Bits
22
Output Noise
See Typical Characteristics
No Missing Codes
Integral Nonlinearity
Offset Error
Offset Drift(1)
Gain Error(2)
Gain Error Drift(1)
System Gain Calibration Range
System Offset Calibration Range
Sinc3 Filter
End Point Fit, Differential Input
After Calibration
24
Bits
%FSR
ppm of FS
ppm of FS/°C
%
ppm/°C
% of FS
% of FS
±0.0015
7.5
0.02
0.005
1.0
Before Calibration
After Calibration
Before Calibration
80
–50
120
50
MSC1212
4
SBAS278A
www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 3V (Cont.)
All specifications from TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, and Bipolar, VREF ≡ (REF IN+) – (REF IN–) = +1.25V,
unless otherwise noted. For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
MSC1212Yx
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE (Cont.)
Common-Mode Rejection
At DC
100
115
130
120
120
100
100
85
dB
dB
dB
dB
dB
dB
dB
f
f
f
f
f
CM = 60Hz, fDATA = 10Hz
CM = 50Hz, fDATA = 50Hz
CM = 60Hz, fDATA = 60Hz
SIG = 50Hz, fDATA = 50Hz
SIG = 60Hz, fDATA = 60Hz
Normal Mode Rejection
Power-Supply Rejection
(3)
At DC, dB = –20log(∆VOUT/∆VDD
)
VOLTAGE REFERENCE INPUTS
Reference Input Range
VREF
VREF Common-Mode Rejection
Input Current(4)
(2)
REF IN+, REF IN–
VREF ≡ (REF IN+) – (REF IN–)
At DC
VREF = 1.25V, ADC Only
For each DAC, 3V Reference
0.0
0.3
AVDD
AVDD
V
V
dB
µA
µA
1.25
110
10
DAC Reference Current
25
ON-CHIP VOLTAGE REFERENCE
Output Voltage
VREFH = 0 at +25°C, PGA = 1, 2, 4, 8
1.245
1.25
1.255
V
Power-Supply Rejection Ratio
Short-Circuit Current Source
Short-Circuit Current Sink
Short-Circuit Duration
65
2.6
50
Indefinite
dB
mA
µA
Sink or Source
Drift
5
3
8
ppm/°C
Ω
ms
Output Impedance
Startup Time from Power ON
Temperature Sensor
Sourcing 100µA
CREFOUT = 0.1µF
Temperature Sensor Voltage
Temperature Sensor Coefficient
T = +25°C
115
375
mV
µV/°C
VOLTAGE DAC STATIC PERFORMANCE(5)
Resolution
Relative Accuracy
Differential Nonlinearity
Zero Code Error
Full-Scale Error
Gain Error
Zero Code Error Drift
Gain Temperature Coefficient
16
Bits
% of FSR
LSB
±0.05
±0.146
±1
+35
Ensured Monotonic by Design
All 0s Loaded to DAC Register
All 1s Loaded to DAC Register
+13
0
0
±20
±5
mV
–1.25
–1.25
% of FSR
% of FSR
µV/°C
±1.25
ppm of FSR/°C
VOLTAGE DAC OUTPUT CHARACTERISTICS(6)
Output Voltage Range
Output Voltage Settling Time
Slew Rate
AGND
AVDD
V
µs
V/µs
Ω
To ±0.003% FSR, 0200H to FD00H
8
1
7
DC Output Impedance
Short-Circuit Current
All 1s Loaded to DAC Register
Maximum VREF = 2.5V
16
mA
IDAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
Maximum Short-Circuit Current Duration
Compliance Voltage
Relative Accuracy
Zero Code Error
25
Indefinite
AVDD – 1.5
0.185
mA
Over Full Range
% of FSR
% of FSR
% of FSR
% of FSR
0.5
–0.4
–0.6
Full-Scale Error
Gain Error
ANALOG POWER-SUPPLY REQUIREMENTS
Analog Power-Supply Voltage
Analog Current
ADC Current
AVDD
Analog OFF, PDAD = 1
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
2.7
3.6
V
IADC + IVREF
IADC
< 1
200
500
240
850
250
250
nA
µA
µA
µA
µA
µA
µA
PGA = 128, Buffer ON
Excluding Load Current External Reference
VDAC Current
VREF Current
IVDAC
IVREF
NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AVDD – 1.5V with buffer ON. To calibrate gain,
turn buffer off. (3) ∆VOUT is change in digital result. (4) 9pF switched capacitor at fSAMP clock frequency (see Figure 6). (5) Linearity calculated using a reduced code
range of 512 to 65024; output unloaded. (6) Ensured by design and characterization, not production tested.
MSC1212
SBAS278A
5
www.ti.com
DIGITAL CHARACTERISTICS: DVDD = 2.7V to 5.25V
All specifications from TMIN to TMAX, unless otherwise specified.
MSC1212Yx
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
DIGITAL POWER-SUPPLY REQUIREMENTS
DVDD (2.7V to 3.6V)
2.7
3.6
V
Digital Power-Supply Current (2.7V to 3.6V)
Normal Mode, fOSC = 1MHz
Normal Mode, fOSC = 8MHz
Stop Mode
1.3
6
100
mA
mA
nA
DVDD (4.75V to 5.25V)
4.75
5.25
V
Digital Power-Supply Current (4.75V to 5.25V)
Normal Mode, fOSC = 1MHz
Normal Mode, fOSC = 8MHz
Stop Mode
2.2
14
100
mA
mA
nA
DIGITAL INPUT/OUTPUT (CMOS)
Logic Level: VIH (except XIN pin)
VIL (except XIN pin)
Ports 0-3, Input Leakage Current, Input Mode
Pins EA, XIN Input Leakage Current
0.6 • DVDD
DGND
–10
DVDD
0.2 • DVDD
+10
V
V
µA
µA
V
V
V
V
VIH = DVDD or VIH = 0V
0
0
V
V
V
V
OL, ALE, PSEN, Ports 0-3, All Output Modes
OL, ALE, PSEN, Ports 0-3, All Output Modes
OH, ALE, PSEN, Ports 0-3, Strong Drive Output
OH, ALE, PSEN, Ports 0-3, Strong Drive Output
IOL = 1mA
IOL = 30mA, 3V (20mA)
IOH = 1mA
DGND
0.4
1.5
DVDD – 0.4 DVDD – 0.1
DVDD
IOH = 30mA, 3V (20mA)
DVDD – 1.5
Ports 0-3 Pull-Up Resistors
Pins ALE, PSEN, Pull-Up Resistors
Pin RST, Pull-Down Resistor
9
9
200
kΩ
kΩ
kΩ
Flash Programming Mode Only
FLASH MEMORY CHARACTERISTICS: DVDD = 2.7V to 5.25V
tUSEC = 1µs, tMSEC = 1ms
MSC1212Yx
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Flash Memory Endurance
100,000
100
10
1,000,000
cycles
Years
ms
Flash Memory Data Retention
Mass and Page Erase Time
Flash Memory Data Retention
Set with FER Value in FTCON
Set with FWR Value in FTCON
30
40
µs
MSC1212
6
SBAS278A
www.ti.com
AC ELECTRICAL CHARACTERISTICS(1)(2): DVDD = 2.7V to 5.25V
2.7V to 3.6V
4.75V to 5.25V
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNITS
System Clock
(3)
fOSC
D
D
D
External Crystal Frequency (fOSC
)
1
0
1
16
16
12
1
1
1
30
30
12
MHz
MHz
MHz
(3)
1/tOSC
External Clock Frequency (fOSC)
(3)
fOSC
External Ceramic Resonator Frequency (fOSC)
Program Memory
tLHLL
A
A
A
A
A
A
A
A
A
A
A
ALE Pulse Width
1.5tCLK – 5
0.5tCLK – 10
0.5tCLK
1.5tCLK – 5
0.5tCLK – 7
0.5tCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVLL
tLLAX
tLLIV
Address Valid to ALE LOW
Address Hold After ALE LOW
ALE LOW to Valid Instruction In
ALE LOW to PSEN LOW
2.5tCLK – 35
2tCLK – 40
2.5tCLK – 25
2tCLK – 30
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
0.5tCLK
0.5tCLK
PSEN Pulse Width
2tCLK – 5
2tCLK – 5
PSEN LOW to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Address to Valid Instruction In
PSEN LOW to Address Float
5
–5
tCLK – 5
3tCLK – 40
0
tCLK
3tCLK – 25
0
Data Memory
tRLRH
B
B
RD Pulse Width (tMCS = 0)(4)
RD Pulse Width (tMCS > 0)(4)
2tCLK – 5
tMCS – 5
2tCLK – 5
tMCS – 5
ns
ns
tWLWH
C
C
WR Pulse Width (tMCS = 0)(4)
Pulse Width (tMCS > 0)(4)
2tCLK – 5
tMCS – 5
2tCLK – 5
tMCS – 5
ns
ns
tRLDV
B
B
RD LOW to Valid Data In (tMCS = 0)(4)
RD LOW to Valid Data In (tMCS > 0)(4)
2tCLK – 40
tMCS – 40
2tCLK – 30
tMCS – 30
ns
ns
tRHDX
tRHDZ
B
Data Hold After Read
–5
–5
ns
B
B
Data Float After Read (tMCS = 0)(4)
Data Float After Read (tMCS > 0)(4)
tCLK
tCLK
ns
ns
2tCLK
2tCLK
tLLDV
tAVDV
tLLWL
tAVWL
B
B
ALE LOW to Valid Data In (tMCS = 0)(4)
ALE LOW to Valid Data In (tMCS > 0)(4)
2.5tCLK – 40
2.5tCLK – 25
ns
ns
tCLK + tMCS – 40
tCLK + tMCS – 25
B
B
Address to Valid Data In (tMCS = 0)(4)
Address to Valid Data In (tMCS > 0)(4)
3tCLK – 40
3tCLK – 25
ns
ns
1.5tCLK + tMCS – 40
1.5tCLK + tMCS – 25
B, C
B, C
ALE LOW to RD or WR LOW (tMCS = 0)(4)
ALE LOW to RD or WR LOW (tMCS > 0)(4)
0.5tCLK – 5
tCLK – 5
0.5tCLK + 5
tCLK + 5
0.5tCLK – 5
tCLK – 5
0.5tCLK + 5
tCLK + 5
ns
ns
B, C
B, C
Address to RD or WR LOW (tMCS = 0)(4)
Address to RD or WR LOW (tMCS > 0)(4)
tCLK – 5
2tCLK – 5
tCLK – 5
2tCLK – 5
ns
ns
tQVWX
tWHQX
tRLAZ
C
C
B
Data Valid to WR Transition
Data Hold After WR
–8
–5
ns
ns
ns
tCLK – 8
tCLK – 5
RD LOW to Address Float
–0.5tCLK – 5
–0.5tCLK – 5
tWHLH
B, C
B, C
RD or WR HIGH to ALE HIGH (tMCS = 0)(4)
RD or WR HIGH to ALE HIGH (tMCS > 0)(4)
–5
tCLK – 5
5
–5
tCLK – 5
5
ns
ns
tCLK + 5
tCLK + 5
External Clock
tHIGH
D
D
D
D
HIGH Time(5)
LOW Time(5)
Rise Time(5)
Fall Time(5)
15
15
10
10
ns
ns
ns
ns
tLOW
tR
5
5
5
5
tF
PSEN
NOTES: (1) Parameters are valid over operating temperature range, unless otherwise specified. (2) Load capacitance for Port 0, ALE, and
= 100pF,
load capacitance for all other outputs = 80pF. (3) tCLK = 1/fOSC = one oscillator clock period for clock divider = 1. (4) tMCS is a time period related to the Stretch
MOVX selection. The following table shows the value of tMCS for each stretch selection. (5) These values are characterized but not 100% production tested.
MD2
MD1
MD0
MOVX DURATION
tMCS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 Machine Cycles
3 Machine Cycles (default)
4 Machine Cycles
5 Machine Cycles
6 Machine Cycles
7 Machine Cycles
8 Machine Cycles
9 Machine Cycles
0
4tCLK
8tCLK
12tCLK
16tCLK
20tCLK
24tCLK
28tCLK
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EXPLANATION OF THE AC SYMBOLS
Each Timing Symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal
or the logical status of that signal. The designators are:
A—Address
R—RD Signal
t—Time
C—Clock
D—Input Data
V—Valid
H—Logic Level HIGH
I—Instruction (program memory contents)
L—Logic Level LOW, or ALE
P—PSEN
W—WR Signal
X—No Longer a Valid Logic Level
Z—Float
Examples: (1) tAVLL = Time for address valid to ALE LOW. (2) tLLPL = Time for
ALE LOW to PSEN LOW.
Q—Output Data
tLHLL
ALE
tPLPH
tAVLL
tLLPL
tLLIV
tPLIV
PSEN
tPXIZ
tLLAX
tPLAZ
tPXIX
INSTR IN
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2
A8-A15
A8-A15
FIGURE A. External Program Memory Read Cycle.
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tAVLL
tRHDZ
tLLAX
tRLDV
tRLAZ
tRHDX
DATA IN
A0-A7
from RI or DPL
PORT 0
A0-A7 from PCL
INSTR IN
tAVWL
tAVDV
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
FIGURE B. External Data Memory Read Cycle.
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ALE
tWHLH
PSEN
tLLWL
tWLWH
WR
tQVWX
tAVLL
tLLAX
tWHQX
tDW
DATA OUT
A0-A7
from RI or DPL
PORT 0
A0-A7 from PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
FIGURE C. External Data Memory Write Cycle.
tHIGH
tr
tf
VIH1
VIH1
0.8V
VIH1
0.8V
VIH1
0.8V
0.8V
tLOW
tOSC
FIGURE D. External Clock Drive CLK.
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RESET AND POWER-ON TIMING
tRW
RST
tRFD
tRRD
PSEN
tRRD
tRFD
ALE
tRS
tRH
EA
NOTE: PSEN and ALE are internally pulled up with ~9kΩ during RST high.
FIGURE E. Reset Timing.
tRW
RST
PSEN
ALE
tRFD
tRRD
tRH
tRS
tRRD
NOTE: PSEN and ALE are internally pulled up with ~9kΩ during RST high.
FIGURE F. Parallel Flash Programming Power-On Timing (EA is ignored).
tRW
RST
tRS
tRRD
tRH
PSEN
ALE
tRRD
tRFD
NOTE: PSEN and ALE are internally pulled up with ~9kΩ during RST high.
FIGURE G. Serial Flash Programming Power-On Timing (EA is ignored).
SYMBOL
PARAMETER
MIN
MAX
UNIT
tRW
tRRD
tRFD
tRS
RST width
2 tOSC
—
—
ns
µs
ns
ns
ns
RST rise to PSEN ALE internal pull high
RST falling to PSEN and ALE start
Input signal to RST falling setup time
RST falling to input signal hold time
5
—
(217 + 512) tOSC
tOSC
—
—
tRH
(217 + 512) tOSC
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PIN CONFIGURATION
Top View
TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
XOUT
1
2
3
4
5
6
7
8
9
48 EA
XIN
P3.0/RxD0
47 P0.6/AD6
46 P0.7/AD7
45 ALE
P3.1/TxD0
P3.2/INT0
44 PSEN/OSCCLK/MODCLK
43 P2.7/A15
42 DVDD
P3.3/INT1/TONE/PWM
P3.4/T0
P3.5/T1
41 DGND
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P3.6/WR
40 P2.6/A14
39 P2.5/A13
38 P2.4/A12
37 P2.3/A11
36 P2.2/A10
35 P2.1/A09
34 P2.0/A08
33 NC
P3.7/RD 10
DVDD 11
DGND 12
RST 13
DVDD 14
DVDD 15
RDAC0 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN DESCRIPTIONS
PIN #
NAME
DESCRIPTION
1
XOUT
The crystal oscillator pin XOUT supports parallel resonant AT cut crystals and ceramic resonators. XOUT serves as the output
of the crystal amplifier.
2
XIN
The crystal oscillator pin XIN supports parallel resonant AT cut crystals and ceramic resonators. XIN can also be an input if
there is an external clock source instead of a crystal.
3-10
P3.0-P3.7
Port 3 is a bidirectional I/O port. The alternate functions for Port 3 are listed below.
Port 3—Alternate Functions:
PORT
ALTERNATE
MODE
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RxD0
TxD0
INT0
Serial Port 0 Input
Serial Port 0 Output
External Interrupt 0
INT1/TONE/PWM External Interrupt 1/TONE/PWM Output
T0
T1
Timer 0 External Input
Timer 1 External Input
WR
RD
External Data Memory Write Strobe
External Data Memory Read Strobe
11, 14, 15, 42, 58
DVDD
DGND
RST
Digital Power Supply
Digital Ground
12, 41, 57
13
16
17
27
18
19
A HIGH on the reset input for two tOSC periods will reset the device.
RDAC0
VDAC0
AGND
RDAC0 Output
VDAC0 Output
Analog Ground
IDAC0/AIN0 IDAC0 Output/Analog Input Channel 0
IDAC1/AIN1 IDAC1 Output/Analog Input Channel 1
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PIN DESCRIPTIONS (Cont.)
PIN #
NAME
DESCRIPTION
20
21
VDAC2/AIN2
VDAC3/AIN3
AIN4
VDAC2 Output/Analog Input Channel 2
VDAC3 Output/Analog Input Channel 3
Analog Input Channel 4
22
23
AIN5
Analog Input Channel 5
24
AIN6, EXTD
AIN7, EXTA
AINCOM
AVDD
Analog Input Channel 6, Low Voltage Detect Input Generates DLVD Interrupt
Analog Input Channel 7, Low Voltage Detect Input Generates ALVD Interrupt
Analog Common for Single-Ended Inputs
Analog Power Supply
25
26
28
29
REF IN–
Voltage Reference Negative Input
30
REFOUT/REF IN+ Voltage Reference Output/ Voltage Reference Positive Input
31
VDAC1
RDAC1
NC
VDAC1 Output
RDAC1 Output
No Connection
32
33
34-40, 43
P2.0-P2.7
Port 2 is a bidirectional I/O port. The alternate functions for Port 2 are listed below.
Port 2—Alternate Functions:
PORT
ALTERNATE MODE
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
A8
A9
Address Bit 8
Address Bit 9
Address Bit 10
Address Bit 11
Address Bit 12
Address Bit 13
Address Bit 14
Address Bit 15
A10
A11
A12
A13
A14
A15
44
PSEN
OSCCLK
MODCLK
Program Store Enable: Connected to optional external memory as a chip enable. PSEN will provide an active low pulse.
In programming mode, PSEN is used as an input along with ALE to define serial or parallel programming mode.
PSEN is held HIGH for parallel programming and tied LOW for serial programming. This pin can also be selected (when not
using external memory) to output the Oscillator clock, Modulator clock, HIGH, or LOW for light loads.
ALE
PSEN
PROGRAM MODE SELECTION DURING RESET
NC
0
NC
NC
0
Normal Operation (User Application mode)
Parallel Programming
Serial Programming
NC
0
0
Reserved
45
ALE
Address Latch Enable: Used for latching the low byte of the address during an access to external memory. ALE is emitted
at a constant rate of 1/2 the oscillator frequency, and can be used for external timing or clocking. One ALE pulse is skipped
during each access to external data memory. In programming mode, ALE is used as an input along with PSEN to define
serial or parallel programming mode. ALE is held HIGH for serial programming and tied LOW for parallel programming. This
pin can also be selected (when not using external memory) to output HIGH or LOW for light loads.
48
EA
External Access Enable: EA must be externally held LOW to enable the device to fetch code from external program memory
locations starting with 0000H.
46, 47, 49-54
P0.0-P0.7
Port 0 is a bidirectional I/O port. The alternate functions for Port 0 are listed below.
Port 0—Alternate Functions:
PORT
ALTERNATE MODE
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Address/Data Bit 0
Address/Data Bit 1
Address/Data Bit 2
Address/Data Bit 3
Address/Data Bit 4
Address/Data Bit 5
Address/Data Bit 6
Address/Data Bit 7
55, 56, 59-64
P1.0-P1.7
Port 1 is a bidirectional I/O port. The alternate functions for Port 1 are listed below.
Port 1—Alternate Functions:
PORT
ALTERNATE MODE
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
T2
T2EX
RxD1
TxD1
INT2/SS
INT3/MOSI
INT4/MISO
INT5/SCK
T2 Input
T2 External Input
Serial Port Input
Serial Port Output
External Interrupt/Slave Select
External Interrupt/Master Out-Slave In
External Interrupt/Master In-Slave Out
External Interrupt/Serial Clock
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TYPICAL CHARACTERISTICS
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer On, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
EFFECTIVE NUMBER OF BITS
EFFECTIVE NUMBER OF BITS vs DATA RATE
vs DECIMATION RATIO
23
22
21
20
19
18
17
16
15
14
13
12
11
10
22
21
20
19
18
17
16
15
14
13
12
PGA8
PGA2
PGA4
PGA1
PGA1
PGA8
PGA32
PGA64
PGA128
PGA32
PGA64
PGA128
PGA16
Sinc3 Filter, Buffer OFF
Sinc3 Filter, Buffer OFF
1
10
100
Data Rate (SPS)
1000
0
500
1000
Decimation Ratio =
1500
fMOD
2000
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
20
19
18
17
16
15
14
13
12
22
21
20
19
18
17
16
15
14
13
12
PGA8
PGA4
PGA2
PGA8
PGA2
PGA4
PGA1
PGA1
PGA32
PGA128
PGA128
PGA16
PGA64
PGA64
PGA32
PGA16
Sinc3 Filter, Buffer ON
AVDD = 3V, Sinc3 Filter,
REF = 1.25V, Buffer OFF
V
0
500
1000
Decimation Ratio =
1500
fMOD
2000
0
500
1000
Decimation Ratio =
1500
2000
fMOD
fDATA
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
20
19
18
17
16
15
14
13
12
22
21
20
19
18
17
16
15
14
13
12
PGA4
PGA2 PGA4
PGA1
PGA8
PGA8
PGA2
PGA1
PGA16 PGA64
PGA32
PGA128
PGA32
PGA128
PGA64
PGA16
Sinc2 Filter
AVDD = 3V, Sinc3 Filter,
VREF = 1.25V, Buffer ON
0
500
1000
Decimation Ratio =
1500
fMOD
2000
0
500
1000
1500
2000
fMOD
Decimation Ratio =
fDATA
fDATA
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer On, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
EFFECTIVE NUMBER OF BITS vs fMOD
FAST SETTLING FILTER
(set with ACLK)
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
25
20
15
10
5
22
21
20
19
18
17
16
15
14
13
12
fMOD = 203kHz
fMOD = 15.6kHz
fMOD = 31.25kHz
fMOD = 110kHz
fMOD = 62.5kHz
Fast Settling Filter
0
1
10
100
1k
10k
100k
0
500
1000
1500
fMOD
2000
Data Rate (SPS)
Decimation Ratio =
fDATA
EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK)
WITH FIXED DECIMATION
NOISE vs INPUT SIGNAL
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
DEC = 2020
DEC = 500
DEC = 50
DEC = 255
DEC = 20
DEC = 10
0
–2.5
–1.5
–0.5
0.5
1.5
2.5
10
100
1k
10k
100k
Data Rate (SPS)
VIN (V)
INTEGRAL NONLINEARITY vs INPUT SIGNAL
VREF = 2.5V
INTEGRAL NONLINEARITY vs INPUT SIGNAL
VREF = AVDD, Buffer OFF
10
8
30
20
6
–40°C
4
10
2
+85°C
0
0
–2
–4
–6
–8
–10
+25°C
–10
–20
–30
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
VIN = –VREF
0
VIN = +VREF
VIN (V)
VIN (V)
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer On, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
INL ERROR vs PGA
ADC INTEGRAL NONLINEARITY vs VREF
100
90
80
70
60
50
40
30
20
10
0
35
30
25
20
15
10
5
VIN = VREF
Buffer OFF
AVDD = 3V
AVDD = 5V
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VREF (V)
1
2
4
8
16
32
64
128
PGA Setting
ADC CURRENT vs PGA
MAXIMUM ANALOG SUPPLY CURRENT
900
800
700
600
500
400
300
200
100
0
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
PGA = 128, ADC ON,
Brownout Detect ON,
All VDACs ON = FFFFH,
VDACs REF = AVDD
+85°C
+25°C
AVDD = 5V, Buffer = ON
Buffer = OFF
–40°C
AVDD = 3V, Buffer = ON
Buffer = OFF
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
1
2
4
8
16
32
64
128
Analog Supply Voltage (V)
PGA Setting
VREFOUT vs LOAD CURRENT
HISTOGRAM OF OUTPUT DATA
4500
4000
3500
3000
2500
2000
1500
1000
500
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
0
0
0.4
0.8
1.2
1.6
2.0
2.4
–2
–1.5
–1
–0.5
0
0.5
1
1.5
2
V
REFOUT Current Load (mA)
ppm of FS
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer On, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
OFFSET DAC: OFFSET vs TEMPERATURE
OFFSET DAC: GAIN vs TEMPERATURE
10
8
1.00006
1.00004
1.00002
1
6
4
2
0
–2
–4
–6
–8
–10
–12
0.99998
0.99996
0.99994
–40
+25
+85
–40
+25
+85
Temperature (°C)
Temperature (°C)
DIGITAL SUPPLY CURRENT vs FREQUENCY
DIGITAL SUPPLY CURRENT vs CLOCK DIVIDER
100
10
1
100
10
1
5V All Periph ON
5V All Periph OFF
5V All Periph ON IDLE
Divider Values
2
4
8
3V All Periph ON
3V All Periph OFF
3V All Periph ON IDLE
16
32
1024
2048
4096
0.1
1
10
100
1000
0.1
1
10
100
Clock Frequency (MHz)
Clock Frequency (MHz)
DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE
NORMALIZED GAIN vs PGA
20
15
10
5
101
100
99
+85°C
–40°C
+25°C
98
97
0
96
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1
2
4
8
16
32
64
128
Supply Voltage (V)
PGA Setting
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer On, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
CMOS DIGITAL OUTPUT
VDAC DIFFERENTIAL NONLINEARITY vs CODE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
5V
Low
Output
0.6
3V
Low
Output
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
5V
3V
0
10
20
30
40
50
60
70
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DAC Code
Output Current (mA)
VDAC SOURCE CURRENT CAPABILITY
VDAC INTEGRAL NONLINEARITY vs CODE
40
20
5.0
DAC = All 1s
4.9
4.8
4.7
4.6
4.5
+85°C
0
+25°C
–20
–40°C
–40
0
2
4
6
8
10
12
14
16
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
DAC Code
ISOURCE (mA)
VDAC SINK CURRENT CAPABILITY
VDAC FULL-SCALE ERROR vs LOAD RESISTOR
1
0
0.6
DAC = All 0s
0.5
0.4
0.3
0.2
0.1
0
–1
–2
–3
–4
–5
0
2
4
6
8
10
12
14
16
0.5
1
10
100
1k
10k
ISINK (mA)
Load Resistor (kΩ)
MSC1212
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer On, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
For VDAC, VREF = AVDD, RLOAD = 10kΩ, and CLOAD = 200pF, unless otherwise noted.
FULL-SCALE SETTLING TIME
FULL-SCALE SETTLING TIME
Scope Trigger (5.0V/div)
Scope Trigger (5.0V/div)
Full-Scale Code Change
0200H to FFFFH
Output Loaded with
10kΩ and 200pF to GND
Large-Signal Output (1.0V/div)
Full-Scale Code Change
FFFFH to 0200H
Output Loaded with
10kΩ and 200pF to GND
Large-Signal Output (1.0V/div)
Time (1µs/div)
Time (1µs/div)
HALF-SCALE SETTLING TIME
HALF-SCALE SETTLING TIME
Scope Trigger (5.0V/div)
Half-Scale Code Change
Scope Trigger (5.0V/div)
4000H to C000H
Output Loaded with
Half-Scale Code Change
10kΩ and 200pF to GND
C000H to 4000H
Output Loaded with
10kΩ and 200pF to GND
Large-Signal Output (1.0V/div)
Large-Signal Output (1.0V/div)
Time (1µs/div)
Time (1µs/div)
MSC1212
18
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The MSC1212Yx allows the user to uniquely configure the
Flash and SRAM memory maps to meet the needs of their
application. The Flash is programmable down to 2.7V using
both serial and parallel programming methods. The Flash
endurance is 100k Erase/Write cycles. In addition, 1280
bytes of RAM are incorporated on-chip.
DESCRIPTION
The MSC1212Yx is a completely integrated family of mixed-
signal devices incorporating a high-resolution delta-sigma
analog-to-digital converter (ADC), quad 16-bit digital-to-ana-
log converters (DACs), 8-channel multiplexer, burnout detect
current sources, selectable buffered input, offset DAC, Pro-
grammable Gain Amplifier (PGA), temperature sensor, volt-
age reference, 8-bit microcontroller, Flash Program Memory,
Flash Data Memory, and Data SRAM, as shown in Figure 1.
The part has separate analog and digital supplies, which can
be independently powered from 2.7V to +5.5V. At +3V opera-
tion, the power dissipation for the part is typically less than
4mW. The MSC1212Yx is packaged in a TQFP-64 package.
On-chip peripherals include an additional 32-bit accumulator, an
SPI compatible serial port with FIFO, dual USARTs, multiple
digital input/output ports, watchdog timer, low-voltage detect,
on-chip power-on reset, 16-bit PWM, breakpoints, brownout
reset, three timer/counters, and a system clock divider.
The MSC1212Yx is designed for high-resolution measurement
applications in smart transmitters, industrial process control,
weigh scales, chromatography, and portable instrumentation.
ENHANCED 8051 CORE
The device accepts low-level differential or single-ended
signals directly from a transducer. The ADC provides 24 bits
of resolution and 24 bits of no-missing-code performance
using a sinc3 filter with a programmable sample rate. The
ADC also has a selectable filter that allows for high-resolu-
tion single-cycle conversion.
All instructions in the MSC1212 family perform exactly the same
functions as they would in a standard 8051. The effect on bits,
flags, and registers is the same. However, the timing is different.
The MSC1212 family utilizes an efficient 8051 core which results
in an improved instruction execution speed of between 1.5 and
3 times faster than the original core for the same external clock
speed (4 clock cycles per instruction versus 12 clock cycles per
instruction, as shown in Figure 2). This translates into an effective
throughput improvement of more than 2.5 times, using the same
code and same external clock speed. Therefore, a device
frequency of 30MHz for the MSC1212Yx actually performs at an
The microcontroller core is 8051 instruction set compatible. The
microcontroller core is an optimized 8051 core which executes up
to three times faster than the standard 8051 core, given the same
clock source. That makes it possible to run the device at a lower
external clock frequency and achieve the same performance at
lower power than the standard 8051 core.
REF IN−(1)
AVDD AGND
REFOUT/REF IN+
DVDD DGND
+AVDD
Timers/
Counters
LVD
VREF
EA
ALE
PSEN
BOR
8-Bit
Offset DAC
WDT
Temperature
Sensor
IDAC0/AIN0
IDAC1/AIN1
VDAC2/AIN2
VDAC3/AIN3
AIN4
Alternate
Functions
ADDR
DATA
PORT0
PORT1
PORT2
PORT3
8
8
8
8
Digital
Filter
Modulator
MUX
BUF
PGA
T2
SPI/EXT
USART2
AIN5
Up to 32K
FLASH
AIN6
ACC
8051
AIN7
V/I
Converter
VDAC0
VDAC1
VDAC2
VDAC3
ADDR
AINCOM
1.2K
SRAM
V/I
USART1
EXT
T0
Converter
IDAC0/
AIN0
T1
SFR
AIN2
PWM
RW
SPI
FIFO
IDAC1/
AIN1
Clock
Generator
RST
AIN3
SYS Clock
Divider
POR
AGND
RDAC0
RDAC1 VDAC0 VDAC1
XIN XOUT
NOTE: (1) REF IN− must be tied to AGND when using internal VREF
.
FIGURE 1. Block Diagram.
CLK
instr_cycle
cpu_cycle
n + 1
n + 2
C1
C2
C3
C4
C1
C2
C3
C4
C1
FIGURE 2. Instruction Cycle Timing.
MSC1212
SBAS278A
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equivalent execution speed of 75MHz compared to the standard
8051 core. This allows the user to run the device at slower
external clock speeds, which reduces system noise and power
consumption but provides greater throughput. This performance
difference can be seen in Figure 3. The timing of software loops
will be faster with the MSC1212. However, the timer/counter
operation of the MSC1212 may be maintained at 12 clocks per
increment or optionally run at 4 clocks per increment.
Furthermore, improvements were made to peripheral features
that off-load processing from the core, and the user, to further
improve efficiency. For instance, the SPI interface uses a FIFO,
which allows the SPI interface to transmit and receive data with
minimum overhead needed from the core. Also, a 32-bit accu-
mulator was added to significantly reduce the processing over-
head for the multiple byte data from the ADC or other sources.
This allows for 24-bit addition and shifting to be accomplished
in a few instruction cycles, compared to hundreds of instruction
cycles through software implementation.
Single-Byte, Single-Cycle
Instruction
Family Device Compatibility
The hardware functionality and pin configuration across the
MSC1212 family is fully compatible. To the user the only differ-
ence between family members is the memory configuration. This
makes migration between family members simple. Code written
for the MSC1212Y2 can be executed directly on an MSC1212Y3,
MSC1212Y4, or MSC1212Y5. This gives the user the ability to
add or subtract software functions and to freely migrate between
family members. Thus, the MSC1212 can become a standard
device used across several application platforms.
ALE
PSEN
AD0-AD7
PORT 2
4 Cycles
CLK
12 Cycles
Family Development Tools
ALE
PSEN
The MSC1212 is fully compatible with the standard 8051
instruction set. This means that the user can develop soft-
ware for the MSC1212 with their existing 8051 development
tools. Additionally, a complete, integrated development envi-
ronment is provided with each demo board, and third-party
developers also provide support.
AD0-AD7
PORT 2
Power-Down Modes
Single-Byte, Single-Cycle
Instruction
The MSC1212 can power several peripherals and put the
CPU into IDLE. This is accomplished by shutting off the
clocks to those sections, as shown in Figure 4.
FIGURE 3. Comparison of MSC1212 Timing to Standard
8051 Timing.
The MSC1212 also provides dual data pointers (DPTRs) to
speed block Data Memory moves.
SYS Clock
Oscillator
STOP
tOSC
Additionally, it can stretch the number of memory cycles to
access external Data Memory from between two and nine
instruction cycles in order to accommodate different speeds of
memory or devices, as shown in Table I. The MSC1212
provides an external memory interface with a 16-bit address
bus (P0 and P2). The 16-bit address bus makes it necessary
to multiplex the low address byte through the P0 port. To
enhance P0 and P2 for high-speed memory access, hardware
configuration control is provided to configure the ports for
external memory/peripheral interface or general-purpose I/O.
SYS Clock
Divider
SCK
SPICON
PWMHI
9A
A3
tCLK
PDCON.0
PWM Clock
PWMLOW
A2
PDCON.4
µs
FTCON
[3:0]
Flash Write
Timing
USEC
(30µs to 40µs)
EF
FB
ms
Flash Erase
Timing
FTCON
MSECH
FD
MSECL
(5ms to 11ms)
[7:4]
EF
FC
milliseconds
interrupt
MSINT
FA
seconds
interrupt
PDCON.1
SECINT
F9
CKCON
(8EH)
MD2:MD0
INSTRUCTION
CYCLES
(for MOVX)
RD or WR
STROBE WIDTH
(SYS CLKs)
RD or WR
STROBE WIDTH
(µs) AT 12MHz
100ms
HMSEC
watchdog
WDTCON
FF
FE
PDCON.2
ADCON2
000
001
010
011
100
101
110
111
2
2
4
8
12
16
20
24
28
0.167
0.333
0.667
1.000
1.333
1.667
2.000
2.333
divide
by 64
ADC Output Rate
ADCON3
ACLK
3 (default)
F6
ADC Power Down
DF
DE
4
5
6
7
8
9
Decimation Ratio
Modulator Clock
PDCON.3
Timers 0/1/2
CPU Clock
USART0/1
IDLE
TABLE I. Memory Cycle Stretching. Stretching of MOVX
timing as defined by MD2, MD1, and MD0 bits in
CKCON register (address 8EH).
FIGURE 4. MSC1212 Timing Chain and Clock Control.
MSC1212
20
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BURNOUT DETECT
OVERVIEW
When the Burnout Detect (BOD) bit is set in the ADC control
configuration register (ADCON0 DCH), two current sources are
enabled. The current source on the positive input channel sources
approximately 2µA of current. The current source on the negative
input channel sinks approximately 2µA. This allows for the
detection of an open circuit (full-scale reading) or short circuit
(small differential reading) on the selected input differential pair.
INPUT MULTIPLEXER
The input multiplexer provides for any combination of differential
inputs to be selected as the input channel, as shown in Figure 5.
If AIN0 is selected as the positive differential input channel, any
other channel can be selected as the negative differential input
channel. With this method, it is possible to have up to eight fully
differential input channels. It is also possible to switch the polarity
of the differential input pair to negate any offset voltages.
INPUT BUFFER
The analog input impedance is always high, regardless of
PGA setting (when the buffer is enabled). With the buffer
enabled, the input voltage range is reduced and the analog
power-supply current is higher. If the limitation of input
voltage range is acceptable, then the buffer is always pre-
ferred.
AIN0
The input impedance of the MSC1212 without the buffer
is 7MΩ/PGA. The buffer is controlled by the state of the BUF
bit in the ADC control register (ADCON0 DCH).
AIN1
AVDD
Burnout Detect
Current Source
AIN2
ANALOG INPUT
When the buffer is not selected, the input impedance of the
analog input changes with ACLK clock frequency (ACLK
F6H) and gain (PGA). The relationship is:
AIN3
In+
1MHz
7MΩ
AIN4
AIN Impedance (Ω) =
•
In–
ACLK Frequency
PGA
where ACLK frequency = fCLK/(ACLK +1).
AIN5
Burnout Detect
Current Sink
Figure 6 shows the basic input structure of the MSC1212.
The sampling frequency varies according to the PGA set-
tings, as shown in Table II.
AIN6
Temperature Sensor
AGND
80 • I
I
AIN7
RSW
(8kΩ typical)
High
Impedance
> 1GΩ
AINCOM
AIN
CINT
9pF Typical
Sampling Frequency = fSAMP
VCM
FIGURE 5. Input Multiplexer Configuration.
FIGURE 6. Analog Input Structure.
In addition, current sources are supplied that will source or
sink current to detect open or short circuits on the pins.
PGA
FULL-SCALE RANGE
SAMPLING FREQUENCY
1
2
±VREF
±VREF/2
fSAMP
fSAMP
4
±VREF/4
fSAMP
TEMPERATURE SENSOR
8
±VREF/8
fSAMP • 2
fSAMP • 4
fSAMP • 8
fSAMP • 16
fSAMP • 16
On-chip diodes provide temperature sensing capability. When
the configuration register for the input MUX is set to all 1s,
the diodes are connected to the input of the ADC. All other
channels are open.
16
32
64
128
±VREF/16
±VREF/32
±VREF/64
±VREF/128
NOTE: fSAMP = ACLK frequency/64.
TABLE II. Sampling Frequency Versus PGA Setting.
MSC1212
SBAS278A
21
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quires a positive full-scale differential input signal. It then
computes a value to nullify gain errors in the system. Each of
these calibrations will take seven tDATA periods to complete.
PGA
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.
Using the PGA can actually improve the effective resolution
of the ADC. For instance, with a PGA of 1 on a ±2.5V full-
scale range, the ADC can resolve to 1.5µV. With a PGA of
128 on a ±19mV full-scale range, the ADC can resolve to
75nV. With a PGA of 1 on a ±2.5V full-scale range, it would
require a 26-bit ADC to resolve 75nV, as shown in Table III.
Calibration should be performed after power on, a change in
temperature, decimation ratio, buffer, or a change of the
PGA. Calibration will remove the effects of the Offset DAC;
therefore, changes to the Offset DAC register must be done
after calibration.
At the completion of calibration, the ADC Interrupt bit goes
HIGH, which indicates the calibration is finished and valid
data is available.
RMS
MEASUREMENT
RESOLUTION ENOB AT PGA = 1
FULL-SCALE
RANGE
(V)
EQUIVALENT
PGA
SETTING
ENOB
AT 10Hz
(nV)
(5V RANGE)
DIGITAL FILTER
1
2
±2.5V
±1.25
21.7
21.5
21.4
21.2
20.8
20.4
20
1468
843
452
259
171
113
74.5
74.5
21.7
22.5
23.4
24.2
24.8
25.4
26
The Digital Filter can use either the Fast Settling, sinc2, or
sinc3 filter, as shown in Figure 7. In addition, the Auto mode
changes the sinc filter after the input channel or PGA is
changed. When switching to a new channel, it will use the
Fast Settling filter, for the next two conversions the first of
which should be discarded. It will then use the sinc2 followed
by the sinc3 filter to improve noise performance. This com-
bines the low-noise advantage of the sinc3 filter with the
quick response of the Fast Settling Time filter. The frequency
response of each filter is shown in Figure 8.
4
±0.625
±0.313
±0.156
±0.0781
±0.039
±0.019
8
16
32
64
128
19
26
TABLE III. ENOB Versus PGA.
OFFSET DAC
The analog input to the PGA can be offset by up to half the
full-scale input range of the PGA by using the ODAC register
(SFR E6H). The ODAC (Offset DAC) register is an 8-bit
value; the MSB is the sign and the seven LSBs provide the
magnitude of the offset. Since the ODAC introduces an
analog (instead of digital) offset to the PGA, using the ODAC
does not reduce the performance of the ADC.
Adjustable Digital Filter
Sinc3
Sinc2
MODULATOR
Modulator
Data Out
The modulator is a single-loop 2nd-order system. The modu-
lator runs at a clock speed (fMOD) that is derived from the CLK
using the value in the Analog Clock register (ACLK). The
data output rate is:
Fast Settling
Data Rate = fMOD/Decimation Ratio
where fMOD = fCLK/(ACLK +1)/64
FILTER SETTLING TIME
FILTER
SETTLING TIME
(Conversion Cycles)
CALIBRATION
Sinc3
Sinc2
Fast
3(1)
2(1)
1(1)
The offset and gain errors in the MSC1212, or the complete
system, can be reduced with calibration. Calibration is con-
trolled through the ADCON1 register (SFR DDH), bits
CAL2:CAL0. Each calibration process takes seven tDATA
periods (data conversion time) to complete. Therefore, it
takes 14 tDATA periods to complete both an offset and gain
calibration.
NOTE: (1) With Synchronized Channel Changes.
AUTO MODE FILTER SELECTION
CONVERSION CYCLE
1
2
3
4+
For system calibration, the appropriate signal must be
applied to the inputs. The system offset command requires a
zero differential input signal. It then computes an offset that will
nullify offset in the system. The system gain command re-
Discard
Fast
Sinc2
Sinc3
FIGURE 7. Filter Step Responses.
MSC1212
22
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If the internal VREF is not used, then VREF should be disabled in
ADCON0.
SINC3 FILTER RESPONSE
(–3dB = 0.262 • fDATA
)
0
–20
If the external voltage reference is selected, it can be used
as either a single-ended input of differential input, for
ratiometric measures. When using an external reference, it is
important to note that the input current will increase for VREF
with higher PGA settings and with a higher modulator fre-
quency. The external voltage reference can be used over the
input range specified in the Electrical Characteristics section.
–40
–60
–80
–100
–120
DAC
0
fD
2fD
3fD
4fD
5fD
The architecture consists of a string DAC followed by an
output buffer amplifier. Figure 9 shows a block diagram of the
DAC architecture.
Frequency (Hz)
SINC2 FILTER RESPONSE
(–3dB = 0.318 • fDATA
)
0
–20
DAC3
DAC2
DAC1
21 AIN3/VDAC3
–40
AIN2/VDAC2
20
–60
VDAC1
31
V/I Converter
–80
AIN1/IDAC1
RDAC1
19
32
Current
Mirror
–100
–120
0
fD
2fD
3fD
4fD
5fD
AVDD
VREF
DAC0
Frequency (Hz)
17 VDAC0
V/I Converter
18
FAST SETTLING FILTER RESPONSE
(–3dB = 0.469 • fDATA
AIN0/IDAC0
)
Current
Mirror
0
–20
RDAC0
16
–40
FIGURE 9. DAC Architecture.
–60
The input coding to the DAC is straight binary, so the ideal
output voltage is given by:
–80
–100
–120
D
VDAC = VREF
•
65536
0
fD
2fD
3fD
4fD
5fD
where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 65535.
Frequency (Hz)
NOTE: fD = Data Output Rate = 1/tDATA
RESISTOR STRING
FIGURE 8. Filter Frequency Responses.
The DAC selects the voltage from a string of resistors from
the reference to AGND. It is essentially a string of resistors,
each of value R. The code loaded into the DAC register
determines at which node on the string the voltage is tapped
off to be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is ensured
monotonic because it is a string of resistors.
VOLTAGE REFERENCE
The MSC1212 can use either an internal or external voltage
reference. The voltage reference selection is controlled via ADC
Control Register 0 (ADCON0, SFR DCH). The default power-up
configuration for the voltage reference is 2.5V internal.
The internal voltage reference can be selected as either 1.25V
or 2.5V. The analog power supply (AVDD) must be within the
specified range for the selected internal voltage reference. The
valid ranges are: VREF = 2.5 internal (AVDD = 3.3V to 5.25V) and
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output which gives an output range of
AGND to AVDD. It is capable of driving a load of 2kΩ in parallel with
1000pF to GND. The source and sink capabilities of the output
amplifier can be seen in the typical curves. The slew rate is 1V/µs
with a full-scale settling time of 8µs with the output unloaded.
VREF = 1.25 internal (AVDD = 2.7V to 5.25V). If the internal VREF
is selected, then AGND must be connected to REF IN–. The
REFOUT/REF IN+ pin should also have a 0.1µF capacitor
connected to AGND as close as possible to the pin.
MSC1212
SBAS278A
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DAC REFERENCE
IDAC
Each DAC can be selected to use the internal REFOUT/REF IN+
voltage or the supply voltage AVDD as the reference for the DAC.
The full range of the voltage DAC is limited according to
Table IV. The full range of the current DAC is limited
according to Table V.
The compliance specification of the IDAC output defines the
maximum output voltage to achieve the expected current.
Refer to Figure 9 for the IDAC structure and to Table V for
the DAC reference selection and code range.
POWER ON RESET
DAC REFERENCE AVDD = 5V
AVDD = 3V
AVDD < 3.0V
The on-chip Power On Reset (POR) circuitry releases the
device from reset at approximately DVDD = 2.0V. The POR
accommodates power-supply ramp rates as slow as
1V/10ms. To ensure proper operation, the power supply
should ramp monotonically. Note that as the device is re-
leased from reset and program execution begins, the device
current consumption may increase, which may result in a
power-supply voltage drop. If the power supply ramps at a
slower rate, is not monotonic, or a Brownout condition occurs
(where the supply does not drop below the 2.0V threshold),
then improper device operation may occur. The on-chip
Brownout Reset may provide benefit in these conditions.
Figure 11 shows a POR circuit.
DACREF = AVDD
DACREF = 2.5V
DACREF = 1.25V
Full Range
Full Range
Not Recommended
Full Range Not Recommended Not Recommended
Full Range
Full Range
Not Recommended
TABLE IV. Voltage DAC Code Range.
DAC REFERENCE AVDD = 5V
AVDD = 3V
AVDD < 3.0V
DACREF = AVDD
DACREF = 2.5V
DACREF = 1.25V
0000-7FFFH
0000-3FFFH
Not Recommended
Full Range Not Recommended Not Recommended
Full Range Full Range Not Recommended
TABLE V. Current DAC Code Range.
DAC LOADING
The DAC can be selected to be turned off with a 1kΩ, 100kΩ,
or open circuit on the DAC outputs.
DVDD
MSC1212
BIPOLAR OPERATION USING THE DAC
0.1µF
10kΩ
The DAC can be used for a bipolar output range, as shown in
Figure 10. The circuit shown will give an output voltage range
of ±VREF. Rail-to-rail operation at the amplifier output is achiev-
able using an OPA703 as the output amplifier.
13
RST
1MΩ
R2
100kΩ
FIGURE 11. Typical Reset Circuit.
+5V
BROWNOUT RESET
R1
100kΩ
The Brownout Reset (BOR) is enabled through Hardware
Configuration Register 1 (HCR1). If the conditions for proper
POR are not met or the device encounters a brownout
condition that does not generate a POR, the BOR can be
used to ensure proper device operation. The BOR will hold
the state of the device when the power supply drops below
the threshold level programmed in HCR1 and then generate
a reset when the supply rises above the threshold level. Note
that as the device is released from reset and program
execution begins, the device current consumption may in-
crease, which can result in a power supply voltage drop,
which may initiate another brownout condition.
DACREF
OPA703
±5V
VREF
VDAC
–5V
FIGURE 10. Bipolar Operation with the DAC.
The output voltage for any input code can be calculated as
follows:
D
R1 +R2
R2
R1
VO = DACREF
•
•
–DACREF •
65536
R1
The BOR level should be chosen to match closely with the
application. That is, with a high external clock frequency, the
BOR level should match the minimum operating voltage
range for the device or improper operation may still occur.
where D represents the input code in decimal (0 to 65535).
With DACREF = 5V, R1 = R2 = 10kΩ:
10 • D
VO
=
– 5V
MEMORY MAP
65536
The MSC1212 contains on-chip SFR, Flash Memory,
Scratchpad RAM Memory, Boot ROM, and SRAM. The SFR
registers are primarily used for control and status. The
standard 8051 features and additional peripheral features of
This is an output voltage range of ±5V with 0000H corre-
sponding to a –5V output and FFFFH corresponding to a +5V
output. Similarly, using VREF = 2.5V, a ±2.5V output voltage
can be achieved.
MSC1212
24
SBAS278A
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the MSC1212 are controlled through the SFR. Reading from
undefined SFR will return zero and writing to undefined SFR
registers is not recommended and will have indeterminate
effects.
The MSC1212 allows the user to partition the Flash Memory
between Program Memory and Data Memory. For instance,
the MSC1212Y5 contains 32kB of Flash Memory on-chip.
Through the HW configuration registers, the user can define
the partition between Program Memory (PM) and Data
Memory (DM), as shown in Tables VI and VII. The MSC1212
family offers four memory configurations.
Flash Memory is used for both Program Memory and Data
Memory. The user has the ability to select the partition size
of Program and Data Memories. The partition size is set
through hardware configuration bits, which are programmed
through either the parallel or serial programming methods.
Both Program and Data Flash Memories are erasable and
writable (programmable) in User Application mode (UAM).
However, only program execution can occur from Program
Memory. As an added precaution, a lock feature can be
activated through the hardware configuration bits, which
disables erase and writes to 4kB of Program Flash Memory
or the entire Program Flash Memory in UAM.
HCR0
MSC1212Y2 MSC1212Y3 MSC1212Y4 MSC1212Y5
DFSEL
PM
DM
PM DM
PM
DM
PM
DM
000
0kB 4kB
0kB 4kB
0kB 4kB
0kB 4kB
0kB 4kB
2kB 2kB
3kB 1kB
4kB 0kB
0kB 8kB
0kB 8kB
0kB 8kB
0kB 8kB
0kB 16kB 0kB 32kB
0kB 16kB 0kB 32kB
0kB 16kB 16kB 16kB
001
010
011
8kB
8kB 24kB 8kB
100
4kB 4kB 12kB 4kB 28kB 4kB
6kB 2kB 14kB 2kB 30kB 2kB
7kB 1kB 15kB 1kB 31kB 1kB
8kB 0kB 16kB 0kB 32kB 0kB
101
110
111 (default)
The MSC1212 includes 1kB of SRAM on-chip. SRAM starts
at address 0 and is accessed through the MOVX instruction.
This SRAM can also be located to start at 8400H and can be
accessed as both Program and Data Memory.
NOTE: When a 0kB program memory configuration is selected program
execution is external.
TABLE VI. MSC1212Y Flash Partitioning.
FLASH MEMORY
HCR0
MSC1212Y2 MSC1212Y3 MSC1212Y4 MSC1212Y5
PM DM PM DM PM DM PM DM
0000 0400- 0000 0400- 0000 0400- 0000 0400-
13FF 23FF 43FF 83FF
0000 0400- 0000 0400- 0000 0400- 0000 0400-
13FF 23FF 43FF 83FF
0000 0400 0000 0400 0000 0400 0000- 0400-
13FF 23FF 43FF 3FFF 43FF
0000 0400- 0000 0400- 0000- 0400- 0000- 0400-
13FF 23FF 1FFF 23FF 5FFF 23FF
DFSEL
The MSC1212 uses a memory addressing scheme that sepa-
rates Program Memory (FLASH/ROM) from Data Memory
(FLASH/RAM). Each area is 64kB beginning at address 0000H
and ending at FFFFH, as shown in Figure 12. The program and
data segments can overlap since they are accessed in different
ways. Program Memory is fetched by the microcontroller auto-
matically. There is one instruction (MOVC) that is used to
explicitly read the program area. This is commonly used to read
lookup tables. The Data Memory area is accessed explicitly
using the MOVX instruction. This instruction provides multiple
ways of specifying the target address. It is used to access the
64kB of Data Memory. The address and data range of devices
with on-chip Program and Data Memory overlap the 64kB
memory space. When on-chip memory is enabled, accessing
memory in the on-chip range will cause the device to access
internal memory. Memory accesses beyond the internal range
will be addressed externally via Ports 0 and 2.
000
001
010
011
100
0000 0400- 0000- 0400- 0000- 0400- 0000- 0400-
13FF 0FFF 13FF 2FFF 13FF 6FFF 13FF
101
0000- 0400- 0000- 0400- 0000- 0400- 0000- 0400-
07FF 0BFF 17FF 0BFF 37FF 0BFF 77FF 0BFF
110
0000- 0400- 0000- 0400- 0000- 0400- 0000- 0400-
0BFF 07FF 1BFF 07FF 3BFF 07FF 7BFF 07FF
111 (default)
0000- 0000 0000- 0000 0000- 0000 0000- 0000
0FFF
1FFF
3FFF
7FFF
NOTE: Program memory accesses above the highest listed address will
access external program memory.
TABLE VII. Flash Memory Partitioning.
Program
Memory
Data
Memory
It is important to note that the Flash Memory is readable and
writable (depending on the MXWS bit in the MWS SFR) by
the user through the MOVX instruction when configured as
either Program or Data Memory. This means that the user
may partition the device for maximum Flash Program Memory
size (no Flash Data Memory) and use Flash Program Memory
as Flash Data Memory. This may lead to undesirable behav-
ior if the PC points to an area of Flash Program Memory that
is being used for data storage. Therefore, it is recommended
to use Flash partitioning when Flash Memory is used for data
storage. Flash partitioning prohibits execution of code from
Data Flash Memory. Additionally, the Program Memory erase/
write can be disabled through hardware configuration bits
(HCR0), while still providing access (read/write/erase) to
Data Flash Memory.
FFFFH
F800H
FFFFH
2k Internal Boot ROM
External
Program
Memory
External
Data
Memory
Mapped to Both
Memory Spaces
(von Neumann)
8800H
8400H
8000H, 32k (Y5)
8800H
8400H, 33k (Y5)
1k RAM or External
External Memory
1k RAM or External
4400H, 17k (Y4)
2400H, 9k (Y3)
4000H, 16k (Y4)
2000H, 8k (Y3)
1400H, 5k (Y2)
0400H, 1k
1000H, 4k (Y2)
0000H, 0k
1k RAM or External
FIGURE 12. Memory Map.
The MSC1212 has two Hardware Configuration registers
(HCR0 and HCR1) that are programmable only during Flash
Memory Programming mode.
MSC1212
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The effect of memory mapping on Program and Data Memory
is straightforward. The Program Memory is decreased in size
from the top of internal Program Memory. Therefore, if the
MSC1212Y5 is partitioned with 31kB of Flash Program
Memory and 1kB of Flash Data Memory, external Program
Memory execution will begin at 7C00H (versus 8000H for
32kB). The Flash Data Memory is added on top of the SRAM
memory. Therefore, access to Data Memory (through MOVX)
will access SRAM for addresses 0000H-03FFH and access
Flash Memory for addresses 0400H-07FFH.
Bit Addressable Locations
In addition to direct register access, some individual bits are
also accessible. These are individually addressable bits in
both the RAM and SFR area. In the Scratchpad RAM area,
registers 20H to 2FH are bit addressable. This provides 128
(16 • 8) individual bits available to software. A bit access is
distinguished from a full-register access by the type of
instruction. In the SFR area, any register location ending in
a 0 or 8 is bit-addressable. Figure 14 shows details of the on-
chip RAM addressing including the locations of individual
RAM bits.
Data Memory
The MSC1212 can address 64kB of Data Memory. Scratchpad
Memory provides 256 bytes in addition to the 64kB of Data
Memory. The MOVX instruction is used to access the Data
SRAM Memory. This includes 1024 bytes of on-chip Data
SRAM Memory. The data bus values do not appear on
Port 0 (during data bus timing) for internal memory access.
FFH
Indirect
RAM
7FH
Direct
RAM
The MSC1212 also has on-chip Flash Data Memory which is
readable and writable (depending on Memory Write Select
register) during normal operation (full VDD range). This memory
is mapped into the external Data Memory space directly
above the SRAM.
2FH
2EH
2DH
2CH
2BH
2AH
29H
28H
27H
26H
25H
24H
23H
22H
21H
7F 7E 7D 7C 7B 7A 79 78
77 76 75 74 73 72 71 70
6F 6E 6D 6C 6B 6A 69 68
67 66 65 64 63 62 61 60
5F 5E 5D 5C 5B 5A 59 58
57 56 55 54 53 52 51 50
4F 4E 4D 4C 4B 4A 49 48
47 46 45 44 43 42 41 40
3F 3E 3D 3C 3B 3A 39 38
37 36 35 34 33 32 31 30
2F 2E 2D 2C 2B 2A 29 28
27 26 25 24 23 22 21 20
1F 1E 1D 1C 1B 1A 19 18
17 16 15 14 13 12 11 10
0F 0E 0D 0C 0B 0A 09 08
07 06 05 04 03 02 01 00
REGISTER MAP
The Register Map is illustrated in Figure 13. It is entirely
separate from the Program and Data Memory areas men-
tioned before. A separate class of instructions is used to
access the registers. There are 256 potential register loca-
tions. In practice, the MSC1212 has 256 bytes of Scratchpad
RAM and up to 128 SFRs. This is possible, since the upper
128 Scratchpad RAM locations can only be accessed indi-
rectly. That is, the contents of a Working Register (described
below) will designate the RAM location. Thus, a direct refer-
ence to one of the upper 128 locations must be an SFR
access. Direct RAM is reached at locations 0 to 7FH (0 to 127).
255
128
FFH
80H
FFH
20H
1FH
Direct
Special Function
Registers
Indirect
RAM
Bank 3
80H
7FH
18H
17H
SFR Registers
Direct
RAM
Bank 2
Bank 1
Bank 0
10H
0FH
0000H
Scratchpad
RAM
08H
07H
FIGURE 13. Register Map.
0000H
MSB
LSB
SFRs are accessed directly between 80H and FFH (128 to
255). The RAM locations between 128 and 255 can be
reached through an indirect reference to those locations.
Scratchpad RAM is available for general-purpose data stor-
age. It is commonly used in place of off-chip RAM when the
total data contents are small. When off-chip RAM is needed,
the Scratchpad area will still provide the fastest general-
purpose access. Within the 256 bytes of RAM, there are
several special-purpose areas.
FIGURE 14. Scratchpad Register Addressing.
MSC1212
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Working Registers
ACCESSING EXTERNAL MEMORY
As part of the lower 128 bytes of RAM, there are four banks
of Working Registers, as shown in Figure 14. The Working
Registers are general-purpose RAM locations that can be
addressed in a special way. They are designated R0 through
R7. Since there are four banks, the currently selected bank will
be used by any instruction using R0-R7. This allows software
to change context by simply switching banks. This is controlled
via the Program Status Word register (PSW; 0D0H) in the SFR
area described below. Registers R0 and R1 also allow their
contents to be used for indirect addressing of the upper 128
bytes of RAM. Thus, an instruction can designate the value
stored in R0 (for example) to address the upper RAM. The 16
bytes immediately above the these registers are bit address-
able. So any of the 128 bits in this area can be directly
accessed using bit addressable instructions.
If external memory is used, P0 and P2 can be configured as
address and data lines. If external memory is not used, P0
and P2 can be configured as general-purpose I/O lines
through the Hardware Configuration Register.
To enable access to external memory bits 0 and 1 of the
HCR1 register must be set to 0. When these bits are enabled
all memory accesses for both internal and external memory
will appear on ports 0 and 2. During the data portion of the
cycle for internal memory, Port 0 will be zero for security
purposes.
Accesses to external memory are of two types: accesses to
external Program Memory and accesses to external Data
Memory. Accesses to external Program Memory use signal
PSEN (program store enable) as the read strobe. Accesses
to external Data Memory use RD or WR (alternate functions
of P3.7 and P3.6) to strobe the memory.
Stack
Another use of the Scratchpad area is for the programmer’s
stack. This area is selected using the Stack Pointer (SP; 81H)
SFR. Whenever a call or interrupt is invoked, the return
address is placed on the Stack. It also is available to the
programmer for variables, etc., since the Stack can be moved
and there is no fixed location within the RAM designated as
Stack. The Stack Pointer will default to 07H on reset. The user
can then move it as needed. A convenient location would be
the upper RAM area (> 7FH) since this is only available
indirectly. The SP will point to the last used value. Therefore,
the next value placed on the Stack is put at SP + 1. Each
PUSH or CALL will increment the SP by the appropriate value.
Each POP or RET will decrement as well.
External Program Memory and external Data Memory may be
combined if desired by applying the RD and PSEN signals to
the inputs of an AND gate and using the output of the gate as
the read strobe to the external Program/Data Memory.
A program fetch from external Program Memory uses a 16-
bit address. Accesses to external Data Memory can use
either a 16-bit address (MOVX @DPTR) or an 8-bit address
(MOVX @RI).
If Port 2 is selected for external memory use (HCR1, bit 0), it can
not be used as a general-purpose I/O. This bit (or Bit 1 of HCR1)
also forces bits P3.6 and P3.7 to be used for WR and RD instead
of I/O. Port 2, P3.6, and P3.7 should all be written to ‘1’.
If an 8-bit address is being used (MOVX @RI), the contents
of the MPAGE (92H) SFR remain at the Port 2 pins through-
out the external memory cycle. This will facilitate paging.
Program Memory
After reset, the CPU begins execution from Program Memory
location 0000H. The selection of where Program Memory ex-
ecution begins is made by tying the EA pin to VDD for internal
In any case, the low byte of the address is time-multiplexed
with the data byte on Port 0. The ADDR/DATA signals use
CMOS drivers in the Port 0, Port 2, WR, and RD output
buffers. Thus, in this application the Port 0 pins are not open-
drain outputs, and do not require external pull-ups for high-
speed access. Signal ALE (Address Latch Enable) should be
used to capture the address byte into an external latch. The
address byte is valid at the negative transition of ALE. Then,
in a write cycle, the data byte to be written appears on Port 0
just before WR is activated, and remains there until after WR
is deactivated. In a read cycle, the incoming byte is accepted
at Port 0 just before the read strobe is deactivated.
access, or DGND for external access. When EA is tied to VDD
,
any PC fetches outside the internal Program Memory address
occur from external memory. If EA is tied to DGND, then all PC
fetches address external memory. The standard internal Pro-
gram Memory size for MSC1212 family members is shown in
Table VIII. Refer to the Accessing External Memory section for
details on using external Program Memory. If enabled the Boot
ROM will appear from address F800H to FFFFH.
STANDARD INTERNAL
PROGRAM MEMORY SIZE (BYTES)
MODEL NUMBER
MSC1212Y5
MSC1212Y4
MSC1212Y3
MSC1212Y2
32k
16k
8k
The function of Port 0 and Port 2 is selected in Hardware
Configuration Register 1. This can only be changed during the
Flash Program mode. There is no conflict in the use of these
registers; they will either be used as general-purpose I/O or for
external memory access. The default state is for Port 0 and Port
2 to be used as general-purpose I/O. If an external memory
access is attempted when they are configured as general-
purpose I/O, the values of Port 0 and Port 2 will not be affected.
4k
TABLE VIII. MSC1212 Maximum Internal Program Memory Sizes.
MSC1212
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External Program Memory is accessed under two conditions:
1) Whenever signal EA is LOW during reset, then all future
accesses are external, or
MSC1212
P2[7]
HOST
PSEL
AddrHi[6:0]
AddrLo[7:0]
Data[7:0]
Cmd[2:0]
Req
Flash
Programmer
2) Whenever the Program Counter (PC) contains a number
that is outside of the internal Program Memory address range,
if the ports are enabled.
P2[6:0]
P1[7:0]
P0[7:0]
P3[7:5]
P3[4]
NC
PSEN
ALE
If Port 0 and Port 2 is selected for external memory, all 8 bits
of Port 0 and Port 2, as well as P3.6 and P3.7, are dedicated
to an output function and may not be used for general-
purpose I/O. During external program fetches, Port 2 outputs
the high byte of the PC.
Ack
P3[3]
Programming Flash Memory
Pass
P3[2]
There are four sections of Flash Memory for programming.
1. 128 configuration bytes.
RST
RST
CLK
2. Reset sector (4kB) (not to be confused with the 2kB Boot
ROM).
XIN
3. Program Memory.
4. Data Memory.
FIGURE 15. Parallel Programming Configuration.
Boot Rom
Memory programming. The actual code for Flash programming
can not execute from Flash. That code must execute from the
Boot ROM or internal (von Neumann) RAM.
There is a 2kB Boot ROM that controls operation during serial
or parallel programming. Additionally, the Boot ROM routines
can be accessed during the user mode if it is enabled. When
enabled, the Boot ROM routines will be located at memory
addresses F800H-FFFFH during user mode. In program mode
the Boot ROM is located in the first 2kB of Program Memory.
INTERRUPTS
The MSC1212 uses a three-priority interrupt system. As
shown in Table IX, each interrupt source has an independent
priority bit, flag, interrupt vector, and enable (except that nine
interrupts share the Auxiliary Interrupt (AI) at the highest
priority). In addition, interrupts can be globally enabled or
disabled. The interrupt structure is compatible with the origi-
nal 8051 family. All of the standard interrupts are available.
Flash Programming Mode
There are two programming modes: parallel and serial. The
programming mode is selected by the state of the ALE and
PSEN signals during power-on reset. Serial programming
mode is selected with PSEN = 0 and ALE = 1. Parallel
programming mode is selected with PSEN = 1 and ALE = 0,
as shown in Figure 15. If they are both HIGH, the MSC1212
will operate in normal user mode. Both signals LOW is a
reserved mode and is not defined. Programming mode is
exited with a power-on reset signal and the normal mode
selected.
HARDWARE CONFIGURATION MEMORY
The 128 configuration bytes can only be written during the
program mode. The bytes are accessed through SFR regis-
ters CADDR (SFR 93H) and CDATA (SFR 94H). Two of the
configuration bytes control Flash partitioning and system
control. If the security bit is set, these bits can not be changed
except with a Mass Erase command that erases all of the
Flash Memory including the 128 configuration bytes.
The MSC1212 is shipped with Flash Memory erased (all 1s).
Parallel programming methods typically involve a third-party
programmer. Serial programming methods typically involve in-
system programming. UAM allows Flash Program and Data
MSC1212
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INTERRUPT
PRIORITY
ENABLE
INTERRUPT/EVENT
ADDR
NUM
PRIORITY
FLAG
CONTROL
DVDD Low Voltage/HW Breakpoint
33H
6
HIGH
0
EDLVB (AIE.0)(1)
EBP (BPCON.0)(1)
EDLVV (AIE.0)(1)
EBP (BPCON.0)(1)
N/A
AVDD Low Voltage
SPI Receive
33H
33H
33H
33H
33H
33H
33H
03H
0BH
13H
1BH
23H
6
6
6
6
6
6
6
0
1
2
3
4
0
0
0
0
0
0
0
1
2
3
4
5
EALV (AIE.1)(1)
ESPIR (AIE.2)(1)
ESPIT (AIE.3)(1)
EMSEC (AIE.4)(1)
EADC (AIE.5)(1)
ESUM (AIE.6)(1)
ESEC (AIE.7)(1)
IE0 (TCON.1)(2)
TF0 (TCON.5)(3)
IE1 (TCON.3)(2)
TF1 (TCON.7)(3)
EALV (AIE.1)(1)
ESPIR (AIE.2)(1)
ESPIT (AIE.3)(1)
EMSEC (AIE.4)(1)
EADC (AIE .5)(1)
ESUM (AIE.6)(1)
ESEC (AIE.7)(1)
EX0 (IE.0)(4)
ET0 (IE.1)(4)
EX1 (IE.2)(4)
ET1 (IE.3)(4)
ES0 (IE.4)(4)
N/A
N/A
SPI Transmit
N/A
Milliseconds Timer
ADC
N/A
N/A
Summation Register
Seconds Timer
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port 0
N/A
N/A
PX0 (IP.0)
PT0 (IP.1)
PX1 (IP.2)
PT1 (IP.3)
PS0 (IP.4)
RI_0 (SCON0.0)
TI_0 (SCON0.1)
Timer 2 Overflow
Serial Port 1
2BH
3BH
5
7
6
7
TF2 (T2CON.7)
ET2 (IE.5)(4)
ES1 (IE.6)(4)
PT2 (IP.5)
PS1 (IP.6)
RI_1 (SCON1.0)
TI_1 (SCON1.1)
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog
43H
4BH
53H
5BH
63H
8
8
9
IE2 (EXIF.4)
IE3 (EXIF.5)
EX2 (EIE.0)(4)
EX3 (EIE.1)(4)
EX4 (EIE.2)(4)
EX5 (EIE.3)(4)
EWDI (EIE.4)(4)
PX2 (IP.0)
PX3 (IP.1)
PX4 (IP.2)
PX5 (IP.3)
PWDI (IP.4)
9
10
11
12
10
11
IE4 (EXIF.6)
IE5 (EXIF.7)
12
WDTI (EICON.3)
LOW
NOTES: (1) These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). (2) If edge triggered, cleared automatically by hardware when the
service routine is vectored to. If level triggered, the flag follows the state of the pin. (3) Cleared automatically by hardware when interrupt vector occurs.
(4) Globally enabled by EA (IE.7).
TABLE IX. Interrupt Summary.
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Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CADDR 7FH
EPMA
PML
RSL
EBR
EWDR
DFSEL2
DFSEL1
DFSEL0
For access to this register during normal operation, refer to the register descriptions for CADDR and CDATA.
EPMA Enable Programming Memory Access (Security Bit).
bit 7
0: After reset in programming modes, Flash Memory can only be accessed in UAM until a mass erase is done.
1: Fully Accessible (default)
PML
Program Memory Lock. (PML has Priority Over RSL)
bit 6
0: Enable all Flash Programming Modes in program mode; can be written in UAM.
1: Enable Read-Only mode for program mode; can’t be written in UAM (default).
RSL
Reset Sector Lock.
bit 5
0: Enable Reset Sector Writing
1: Enable Read-Only mode for Reset Sector (4kB) (default)
EBR
Enable Boot Rom. Boot Rom is 2kB of code located in ROM, not to be confused with the 4kB Boot Sector located
in Flash Memory.
bit 4
0: Disable Internal Boot Rom
1: Enable Internal Boot Rom (default)
EWDR Enable Watchdog Reset.
bit 3
0: Disable Watchdog Reset
1: Enable Watchdog Reset (default)
DFSEL Data Flash Memory Size. (see Table III)
bits 2-0 000: Reserved
001: 32kB, 16kB, 8kB, or 4kB Data Flash Memory
010: 16kB, 8kB, or 4kB Data Flash Memory
011: 8kB or 4kB Data Flash Memory
100: 4kB Data Flash Memory
101: 2kB Data Flash Memory
110: 1kB Data Flash Memory
111: No Data Flash Memory (default)
The reset sector can be used to provide another method of Flash Memory programming. This will allow Program Memory
updates without changing the jumpers for in-circuit code updates or program development. The code in this boot sector would
then provide the monitor and programming routines with the ability to jump into the main Flash code when programming is
finished.
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Hardware Configuration Register 1 (HCR1)
7
6
5
4
3
2
1
0
CADDR 7EH
DBLSEL1
DBLSEL0
ABLSEL1
ABLSEL0
DAB
DDB
EGP0
EGP23
For access to this register during normal operation, refer to the register descriptions for CADDR and CDATA.
DBLSEL Digital Brownout Level Select
bits 7-6 00: 4.5V
01: 4.2V
10: 2.7V
11: 2.5V (default)
ABLSEL Analog Brownout Level Select
bits 5-4 00: 4.5V
01: 4.2V
10: 2.7V
11: 2.5V (default)
DAB
Disable Analog Power-Supply Brownout Detection
0: Enable Analog Brownout Detection
bit 3
1: Disable Analog Brownout Detection (default).
Disable Digital Power-Supply Brownout Detection
0: Enable Digital Brownout Detection
DDB
bit 2
1: Disable Digital Brownout Detection (default)
Enable General-Purpose I/O for Port 0
EGP0
bit 1
0: Port 0 is Used for External Memory, P3.6 and P3.7 Used for WR and RD
1: Port 0 is Used as General-Purpose I/O (default)
.
.
EGP23 Enable General-Purpose I/O for Ports 2 and 3
bit 0
0: Port 2 is Used for External Memory, P3.6 and P3.7 Used for WR and RD
1: Port 2 and Port3 are Used as General-Purpose I/O (default)
Configuration Memory Programming
Certain key functions such as Brownout Reset and Watchdog Timer are controlled by the hardware configuration bits. These
bits are nonvolatile and can only be changed through serial and parallel programming. Other peripheral control and status
functions, such as ADC configuration timer setup and Flash control, are controlled through the SFRs.
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SFR Definitions (Boldface is unique to the MSC1212Yx)
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RESET VALUES
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
P0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
FFH
07H
00H
00H
00H
00H
00H
30H
00H
00H
SP
DPL0
DPH0
DPL1
DPH1
DPS
0
0
0
0
0
0
0
SEL
IDLE
IT0
PCON
TCON
TMOD
SMOD
TF1
0
1
1
GF1
IE1
GF0
IT1
STOP
IE0
TR1
TF0
TR0
|---------------------------Timer 1 --------------------------|
|--------------------------Timer 0 ---------------------------|
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8AH
8BH
8CH
8DH
8EH
8FH
90H
TL0
00H
00H
00H
00H
01H
00H
FFH
TL1
TH0
TH1
CKCON
MWS
P1
0
0
T2M
0
T1M
0
T0M
0
MD2
0
MD1
0
MD0
MXWS
P1.0
T2
0
0
P1.7
P1.6
P1.5
P1.4
P1.3
TXD1
1
P1.2
RXD1
0
P1.1
T2EX
0
INT5/SCK INT4/MISO INT3/MOSI INT2/SS
91H
92H
93H
94H
95H
96H
97H
98H
99H
9AH
9BH
9CH
EXIF
IE5
IE4
IE3
IE2
0
08H
00H
00H
00H
00H
MPAGE
CADDR
CDATA
MCON
BPSEL
0
0
RAMMAP
SCON0
SM0_0
SM1_0
SM2_0
SCK0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00H
00H
00H
00H
00H
SBUF0
SPICON
SPIDATA
SPIRCON
SCK2
SCK1
FIFO
ORDER
MSTR
CPHA
CPOL
RXCNT7
RXFLUSH
TXCNT7
RXCNT6
TXCNT6
RXCNT5
RXCNT4
TXCNT4
RXCNT3
TXCNT3
RXCNT2
RXIRQ2
TXCNT2
TXIRQ2
RXCNT1
RXIRQ1
TXCNT1
TXIRQ1
RXCNT0
RXIRQ0
TXCNT0
TXIRQ0
9DH
SPITCON
TXCNT5
CLK_EN
00H
TXFLUSH
DRV_DLY DRV_EN
9EH
9FH
A0H
A1H
A2H
SPISTART
SPIEND
P2
1
80H
80H
FFH
00H
00H
1
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
PWMCON
PWMLOW
TONELOW
PWMHI
PPOL
PWMSEL
PWM4
TDIV4
SPDSEL
PWM3
TDIV3
TPCNTL2 TPCNTL1 TPCNTL0
PWM7
TDIV7
PWM6
TDIV6
PWM5
TDIV5
PWM13
TDIV13
PWM2
TDIV2
PWM1
TDIV1
PWM9
TDIV9
PWM0
TDIV0
PWM8
TDIV8
A3H
PWM15
TDIV15
PWM14
TDIV14
PWM12
TDIV12
PWM11
TDIV11
PWM10
TDIV10
00H
TONEHI
A4H
A5H
A6H
A7H
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
B0H
PAI
0
0
0
0
PAI3
ESPIT
SPIT
ET1
0
PAI2
ESPIR
SPIR
EX1
0
PAI1
PAI0
EDLVB
DLVD
EX0
00H
00H
00H
00H
00H
AIE
ESEC
SEC
EA
ESUM
SUM
ES1
0
EADC
ADC
ET2
0
EMSEC
MSEC
ES0
0
EALV
ALVD
ET0
AISTAT
IE
BPCON
BPL
BP
PMSEL
EBP
BPH
P0DDRL
P0DDRH
P1DDRL
P1DDRH
P3
P03H
P07H
P13H
P17H
P3.7
P03L
P07L
P13L
P17L
P3.6
P02H
P06H
P12H
P16H
P3.5
P02L
P06L
P12L
P16L
P3.4
T0
P01H
P05H
P11H
P15H
P3.3
P01L
P05L
P11L
P15L
P3.2
P00H
P04H
P10H
P14H
P3.1
P00L
P04L
P10L
P14L
P3.0
00H
00H
00H
00H
FFH
RD
WR
T1
INT1
INT0
P21L
P25L
P31L
P35L
TXD0
P20H
P24H
P30H
P34H
RXD0
P20L
P24L
P30L
P34L
B1H
B2H
B3H
B4H
B5H
B6H
B7H
B8H
B9H
P2DDRL
P2DDRH
P3DDRL
P3DDRH
DACL
P23H
P27H
P33H
P37H
P23L
P27L
P33L
P37L
P22H
P26H
P32H
P36H
P22L
P26L
P32L
P36L
P21H
P25H
P31H
P35H
00H
00H
00H
00H
DACH
DACCON
IP
DSEL7
DSEL6
DSEL5
DSEL4
DSEL3
DSEL2
DSEL1
DSEL0
00H
1
PS1
PT2
PS0
PT1
PX1
PT0
PX0
80H
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ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RESET VALUES
BAH
BBH
BCH
BDH
BEH
BFH
C0H
SCON1
SBUF1
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00H
00H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
EWU
EWUWDT EWUEX1
EWUEX0
DIV0
00H
00H
00H
SYSCLK
0
0
DIVMOD1 DIVMOD0
RCLK TCLK
0
DIV2
DIV1
C8H
C9H
CAH
T2CON
TF2
EXF2
EXEN2
TR2
C/T2
CP/RL2
RCAP2L
RCAP2H
TL2
00H
00H
00H
00H
CBH
CCH
CDH
CEH
CFH
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
F0H
F1H
TH2
PSW
CY
AC
F0
RS1
RS0
OV
F1
P
00H
00H
OCL
LSB
OCM
00H
OCH
MSB
00H
GCL
LSB
24H
GCM
90H
GCH
MSB
67H
ADMUX
EICON
ADRESL
ADRESM
ADRESH
ADCON0
ADCON1
ADCON2
ADCON3
ACC
INP3
INP2
INP1
INP0
INN3
INN2
INN1
INN0
0
01H
SMOD1
1
EAI
AI
WDTI
0
0
40H
LSB
00H
00H
MSB
—
00H
BOD
POL
DR6
0
EVREF
SM1
DR5
0
VREFH
SM0
DR4
0
EBUF
—
PGA2
CAL2
DR2
PGA1
CAL1
DR1
PGA0
CAL0
DR0
38H
—
x000_0000B
1BH
DR7
0
DR3
0
DR10
DR9
DR8
06H
00H
SSCON
SUMR0
SUMR1
SUMR2
SUMR3
ODAC
SSCON1
SSCON0
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
00H
00H
00H
00H
00H
00H
LVDCON
EIE
ALVDIS
ALVD2
ALVD1
ALVD0
DLVDIS
DLVD2
EX4
1
DLVD1
DLVD0
00H
1
1
1
EWDI
EX5
EX3
EX2
E0H
HWPC0
HWPC1
HWVER
Reserved
Reserved
FMCON
FTCON
B
MEMORY SIZE
0000_01xxB
08H
1
00H
00H
02H
A5H
00H
7FH
00H
0
PGERA
FER2
0
FRCM
FER0
0
BUSY
FWR2
1
0
FER3
FER1
FWR3
FWR1
FWR0
PDCON
PASEL
0
0
PDDAC
0
1
PDPWM
PSEN1
PDAD
PDWDT
0
PDST
ALE1
PDSPI
ALE0
F2H
F3H
F4H
F5H
F6H
F7H
PSEN2
PSEN0
ACLK
0
FREQ6
FREQ5
0
FREQ4
0
FREQ3
0
FREQ2
0
FREQ1
0
FREQ0
RSTREQ
PX2
03H
00H
E0H
7FH
7FH
03H
9FH
0FH
63H
00H
SRST
0
0
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH
EIP
1
1
1
PWDI
PX5
PX4
PX3
SECINT
MSINT
USEC
WRT
WRT
0
SECINT6
MSINT6
0
SECINT5
MSINT5
FREQ5
SECINT4
MSINT4
FREQ4
SECINT3
MSINT3
FREQ3
SECINT2
MSINT2
FREQ2
SECINT1
MSINT1
FREQ1
SECINT0
MSINT0
FREQ0
MSECL
MSECH
HMSEC
WDTCON
EWDT
DWDT
RWDT
WDCNT4
WDCNT3
WDCNT2
WDCNT1
WDCNT0
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Port 0 (P0)
7
6
5
4
3
2
1
0
Reset Value
SFR 80H
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
FFH
P0.7-0
bits 7-0
Port 0. This port functions as a multiplexed address/data bus during external memory access, and as a general-
purpose I/O port when external memory access is not needed. During external memory cycles, this port will contain
the LSB of the address when ALE is HIGH, and Data when ALE is LOW. When used as a general-purpose I/O, this
port drive is selected by P0DDRL and P0DDRH (ACH, ADH). Whether Port 0 is used as general-purpose I/O or for
external memory access is determined by the Flash Configuration Register (HCR1.1) (see SFR CADDR 93H).
Stack Pointer (SP)
7
6
5
4
3
2
1
0
Reset Value
07
SFR 81H
SP.7
SP.6
SP.5
SP.4
SP.3
SP.2
SP.1
SP.0
H
SP.7-0
Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented before
bits 7-0
every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07H after reset.
Data Pointer Low 0 (DPL0)
7
6
5
4
3
2
1
0
Reset Value
SFR 82H
DPL0.7
DPL0.6
DPL0.5
DPL0.4
DPL0.3
DPL0.2
DPL0.1
DPL0.0
00H
DPL0.7-0 Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0
bits 7-0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86H).
Data Pointer High 0 (DPH0)
7
6
5
4
3
2
1
0
Reset Value
SFR 83H
DPH0.7
DPH0.6
DPH0.5
DPH0.4
DPH0.3
DPH0.2
DPH0.1
DPH0.0
00H
DPH0.7-0 Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0
bits 7-0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86H).
Data Pointer Low 1 (DPL1)
7
6
5
4
3
2
1
0
Reset Value
SFR 84H
DPL1.7
DPL1.6
DPL1.5
DPL1.4
DPL1.3
DPL1.2
DPL1.1
DPL1.0
00H
DPL1.7-0 Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0)
bits 7-0 (SFR 86H) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.
Data Pointer High 1 (DPH1)
7
6
5
4
3
2
1
0
Reset Value
SFR 85H
DPH1.7
DPH1.6
DPH1.5
DPH1.4
DPH1.3
DPH1.2
DPH1.1
DPH1.0
00H
DPH1.7-0 Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0)
bits 7-0 (SFR 86H) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.
Data Pointer Select (DPS)
7
6
5
4
3
2
1
0
Reset Value
SFR 86H
0
0
0
0
0
0
0
SEL
00H
SEL
Data Pointer Select. This bit selects the active data pointer.
0: Instructions that use the DPTR will use DPL0 and DPH0.
1: Instructions that use the DPTR will use DPL1 and DPH1.
bit 0
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Power Control (PCON)
7
6
5
4
3
2
1
0
Reset Value
SFR 87H
SMOD
0
1
1
GF1
GF0
STOP
IDLE
30H
SMOD
bit 7
Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0.
0: Serial Port 0 baud rate will be a standard baud rate.
1: Serial Port 0 baud rate will be double that defined by baud rate generation equation.
GF1
General-Purpose User Flag 1. This is a general-purpose flag for software control.
bit 3
GF0
General-Purpose User Flag 0. This is a general-purpose flag for software control.
bit 2
STOP
Stop Mode Select. Setting this bit will halt the oscillator and block external clocks. This bit will always read as a 0.
bit 1
Exit with RESET.
IDLE
Idle Mode Select. Setting this bit will freeze the CPU, Timer 0, 1, and 2, and the USARTs; other peripherals remain
bit 0
active. This bit will always be read as a 0. Exit with AI (A6H) and EWU (C6H) interrupts.
Timer/Counter Control (TCON)
7
6
5
4
3
2
1
0
Reset Value
SFR 88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
TF1
bit 7
Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current
mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1
interrupt service routine.
0: No Timer 1 overflow has been detected.
1: Timer 1 has overflowed its maximum count.
TR1
Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer will preserve the
current bit 6 count in TH1, TL1.
0: Timer is halted.
1: Timer is enabled.
TF0
bit 5
Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current
mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0
interrupt service routine.
0: No Timer 0 overflow has been detected.
1: Timer 0 has overflowed its maximum count.
TR0
Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer will preserve the
bit 4
current count in TH0, TL0.
0: Timer is halted.
1: Timer is enabled.
IE1
bit 3
Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this
bit will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this
bit will inversely reflect the state of the INT1 pin.
IT1
Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge or level triggered interrupts.
bit 2
0: INT1 is level triggered.
1: INT1 is edge triggered.
IE0
bit 3
Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this
bit will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this
bit will inversely reflect the state of the INT0 pin.
IT0
Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge- or level-triggered interrupts.
bit 2
0: INT0 is level triggered.
1: INT0 is edge triggered.
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Timer Mode Control (TMOD)
7
6
5
4
3
2
1
0
TIMER 1
TIMER 0
Reset Value
SFR 89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
GATE
Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment.
bit 7
0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1
1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1.
.
C/T
Timer 1 Counter/Timer Select.
bit 6
0: Timer is incremented by internal clocks.
1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88H) is 1.
M1, M0
Timer 1 Mode Select. These bits select the operating mode of Timer 1.
bits 5-4
M1
M0
MODE
0
0
1
1
0
1
0
1
Mode 0: 8-bit counter with 5-bit prescale.
Mode 1: 16 bits.
Mode 2: 8-bit counter with auto reload.
Mode 3: Timer 1 is halted, but holds its count.
GATE
Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment.
bit 3
0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control).
1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control).
C/T
Timer 0 Counter/Timer Select.
bit 2
0: Timer is incremented by internal clocks.
1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88H) is 1.
M1, M0
Timer 0 Mode Select. These bits select the operating mode of Timer 0.
bits 1-0
M1
M0
MODE
0
0
1
1
0
1
0
1
Mode 0: 8-bit counter with 5-bit prescale.
Mode 1: 16 bits.
Mode 2: 8-bit counter with auto reload.
Mode 3: Two 8-bit counters.
Timer 0 LSB (TL0)
7
6
5
4
3
2
1
0
Reset Value
SFR 8AH
TL0.7
TL0.6
TL0.5
TL0.4
TL0.3
TL0.2
TL0.1
TL0.0
00H
TL0.7-0
bits 7-0
Timer 0 LSB. This register contains the least significant byte of Timer 0.
Timer 1 LSB (TL1)
7
6
5
4
3
2
1
0
Reset Value
SFR 8BH
TL1.7
TL1.6
TL1.5
TL1.4
TL1.3
TL1.2
TL1.1
TL1.0
00H
TL1.7-0
bits 7-0
Timer 1 LSB. This register contains the least significant byte of Timer 1.
Timer 0 MSB (TH0)
7
6
5
4
3
2
1
0
Reset Value
SFR 8CH
TH0.7
TH0.6
TH0.5
TH0.4
TH0.3
TH0.2
TH0.1
TH0.0
00H
TH0.7-0
Timer 0 MSB. This register contains the most significant byte of Timer 0.
bits 7-0
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Timer 1 MSB (TH1)
7
6
5
4
3
2
1
0
Reset Value
SFR 8DH
TH1.7
TH1.6
TH1.5
TH1.4
TH1.3
TH1.2
TH1.1
TH1.0
00H
TH1.7-0
Timer 1 MSB. This register contains the most significant byte of Timer 1.
bits 7-0
Clock Control (CKCON)
7
6
5
4
3
2
1
0
Reset Value
SFR 8EH
0
0
T2M
T1M
T0M
MD2
MD1
MD0
01H
T2M
bit 5
Timer 2 Clock Select. This bit controls the division of the system clock that drives Timer 2. This bit has no effect
when the timer is in baud rate generator or clock output modes. Clearing this bit to 0 maintains 8051
compatibility. This bit has no effect on instruction cycle timing.
0: Timer 2 uses a divide by 12 of the crystal frequency.
1: Timer 2 uses a divide by 4 of the crystal frequency.
T1M
bit 4
Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to
0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing.
0: Timer 1 uses a divide by 12 of the crystal frequency.
1: Timer 1 uses a divide by 4 of the crystal frequency.
T0M
bit 3
Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to
0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing.
0: Timer 0 uses a divide by 12 of the crystal frequency.
1: Timer 0 uses a divide by 4 of the crystal frequency.
MD2, MD1, MD0 Stretch MOVX Select 2-0. These bits select the time by which external MOVX cycles are to be stretched.
bits 2-0
This allows slower memory or peripherals to be accessed without using ports or manual software
intervention. The for RD or WR strobe will be stretched by the specified interval, which will be transparent
to the software except for the increased time to execute the MOVX instruction. All internal MOVX
instructions on devices containing MOVX SRAM are performed at the 2 instruction cycle rate.
RD or WR
STROBE WIDTH
(SYS CLKs)
RD or WR
STROBE WIDTH
(µs) AT 12MHz
MD2
MD1
MD0
STRETCH VALUE MOVX DURATION
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
2 Instruction Cycles
3 Instruction Cycles (default)
4 Instruction Cycles
5 Instruction Cycles
6 Instruction Cycles
7 Instruction Cycles
8 Instruction Cycles
9 Instruction Cycles
2
4
8
12
16
20
24
28
0.167
0.333
0.667
1.000
1.333
1.667
2.000
2.333
Memory Write Select (MWS)
7
6
5
4
3
2
1
0
Reset Value
SFR 8FH
0
0
0
0
0
0
0
MXWS
00H
MXWS
MOVX Write Select. This allows writing to the internal Flash program memory.
bit 0
0: No writes are allowed to the internal Flash program memory.
1: Writing is allowed to the internal Flash program memory, unless PML (HCR0) or RSL (HCR0) are on.
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Port 1 (P1)
7
6
5
4
3
2
1
0
Reset Value
SFR 90H
P1.7
INT5/SCK
P1.6
INT4/MISO
P1.5
INT3/MOSI
P1.4
INT2/SS
P1.3
TXD1
P1.2
RXD1
P1.1
T2EX
P1.0
T2
FFH
P1.7-0
bits 7-0
General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have
an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port
1 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. To use the alternate
function, set the appropriate mode in P1DDRL (SFR AEH), P1DDRH (SFR AFH).
INT5/SCK
bit 7
External Interrupt 5.A falling edge on this pin will cause an external interrupt 5 if enabled.
SPI Clock. The master clock for SPI data transfers.
INT4/MISO External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled.
bit 6 Master In Slave Out. For SPI data transfers, this pin receives data for the master and transmits data from the slave.
INT3/MOSI External Interrupt 3. A falling edge on this pin will cause an external interrupt 3 if enabled.
bit 5
Master Out Slave In. For SPI data transfers, this pin transmits master data and receives slave data.
INT2/SS
External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled.
bit 4
Slave Select.
During SPI operation, this pin provides the select signal for the slave device.
TXD1
Serial Port 1 Transmit. This pin transmits the serial Port 1 data in serial port modes 1, 2, 3, and emits the
bit 3
synchronizing clock in serial port mode 0.
RXD1
Serial Port 1 Receive. This pin receives the serial Port 1 data in serial port modes 1, 2, 3, and is a bidirectional
bit 2
data transfer pin in serial port mode 0.
T2EX
bit 1
Timer 2 Capture/Reload Trigger. A 1 to 0 transition on this pin will cause the value in the T2 registers to be
transferred into the capture registers if enabled by EXEN2 (T2CON.3, SFR C8H). When in auto-reload mode, a 1 to 0
transition on this pin will reload the Timer 2 registers with the value in RCAP2L and RCAP2H if enabled by
EXEN2 (T2CON.3, SFR C8H).
T2
Time 2 External Input. A 1 to 0 transition on this pin will cause Timer 2 to increment or decrement depending
bit 0
on the timer configuration.
External Interrupt Flag (EXIF)
7
6
5
4
3
2
1
0
Reset Value
SFR 91H
IE5
IE4
IE3
IE2
1
0
0
0
08H
IE5
External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be
bit 7
cleared manually by software. Setting this bit in software will cause an interrupt if enabled.
IE4
External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared
bit 6
manually by software. Setting this bit in software will cause an interrupt if enabled.
IE3
External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared
bit 5
manually by software. Setting this bit in software will cause an interrupt if enabled.
IE2
External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared
bit 4
manually by software. Setting this bit in software will cause an interrupt if enabled.
Memory Page (MPAGE)
7
6
5
4
3
2
1
0
Reset Value
SFR 92H
00H
MPAGE
bits 7-0
The 8051 uses Port 2 for the upper 8 bits of the external data memory access by MOVX A@RI and MOVX @RI,
A instructions. The MSC1212 uses register MPAGE instead of Port 2. To access external data memory using the
MOVX A@RI and MOVX @RI, A instructions, the user should preload the upper byte of the address into MPAGE (versus
preloading into P2 for the standard 8051).
Configuration Address Register (CADDR) (write only)
7
6
5
4
3
2
1
0
Reset Value
SFR 93H
00H
CADDR
bits 7-0
Configuration Address Register. This register supplies the address for reading bytes in the 128 bytes of Flash Configuration
Memory. CAUTION: If this register is written to while executing from Flash Memory, the CDATA register will be incorrect.
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Configuration Data Register (CDATA)
7
6
5
4
3
2
1
0
Reset Value
SFR 94H
00H
CDATA
Configuration Data Register. This register will contain the data in the 128 bytes of Flash Configuration Memory
bits 7-0
that is located at the last written address in the CADDR register. This is a read-only register.
Memory Control (MCON)
7
6
0
5
0
4
3
2
1
0
Reset Value
SFR 95H
BPSEL
—
—
—
—
RAMMAP
00H
BPSEL
Breakpoint Address Selection
bit 7
Write: Select one of two Breakpoint registers: 0 or 1.
0: Select breakpoint register 0.
1: Select breakpoint register 1.
Read: Provides the Breakpoint register that created the last interrupt: 0 or 1.
RAMMAP Memory Map 1kB extended SRAM.
bit 0 0: Address is: 0000H-03FFH (default) (Data Memory)
1: Address is 8400H-87FFH (Data and Program Memory)
Serial Port 0 Control (SCON0)
7
6
5
4
3
2
1
0
Reset Value
SFR 98H
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00H
SM0-2
bits 7-5
Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit
in addition to the 8 or 9 data bits.
MODE SM0
SM1
SM2 FUNCTION
LENGTH
PERIOD
(1)
0
0
0
0
0
0
0
1
Synchronous
Synchronous
8 bits
8 bits
12 pCLK
(1)
4 pCLK
1(2)
0
1
1
0
x
Asynchronous
Asynchronous
10 bits
11 bits
Timer 1 or 2 Baud Rate Equation
(1)
2
0
64 pCLK (SMOD = 0)
(1)
32 pCLK (SMOD = 1)
(1)
2
1
0
1
Asynchronous with
Multiprocessor Communication
11 bits
64 pCLK (SMOD = 0)
(1)
32 pCLK (SMOD = 1)
3(2)
3(2)
1
1
1
1
0
1
Asynchronous
11 bits
11 bits
Timer 1 or 2 Baud Rate Equation
Timer 1 or 2 Baud Rate Equation
Asynchronous with
Multiprocessor Communication
NOTE: (1) pCLK will be equal to tCLK, except that pCLK will stop for IDLE. (2) For modes 1 and 3, the selection of
Timer 1 or 2 for baud rate is specified via the T2CON (C8H) register.
REN_0
bit 4
Receive Enable. This bit enables/disables the serial Port 0 received shift register.
0: Serial Port 0 reception disabled.
1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0).
TB8_0
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3.
bit 3
RB8_0
9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes
bit 2
2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0.
TI_0
bit 1
Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted
out. In serial port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end
of the last data bit. This bit must be manually cleared by software.
RI_0
bit 0
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In
serial port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample
of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of
RB8_0. This bit must be manually cleared by software.
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Serial Data Buffer 0 (SBUF0)
7
6
5
4
3
2
1
0
Reset Value
SFR 99H
00H
SBUF0
Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and
bits 7-0
receive buffers are separate registers, but both are addressed at this location.
SPI Control (SPICON). Any change resets the SPI interface, counters, and pointers. PDCON controls
which is enabled.
7
6
5
4
3
2
1
0
Reset Value
SFR 9AH
SCK2
SCK1
SCK0
FIFO
ORDER
MSTR
CPHA
CPOL
00H
SCK
SCK Selection. Selection of tCLK divider for generation of SCK in Master mode.
bits 7-5
SCK2
SCK1
SCK0
SCK PERIOD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
tCLK/2
tCLK/4
tCLK/8
tCLK/16
tCLK/32
tCLK/64
t
CLK/128
tCLK/256
FIFO
bit 4
Enable FIFO in on-chip indirect memory.
0: Both transmit and receive are double buffers
1: Circular FIFO used for transmit and receive bytes
ORDER
bit 3
Set Bit Order for Transmit and Receive.
0: Most Significant Bits First
1: Least Significant Bits First
MSTR
bit 2
SPI Master Mode.
0: Slave Mode
1: Master Mode
CPHA
Serial Clock Phase Control.
bit 1
0: Valid data starting from half SCK period before the first edge of SCK
1: Valid data starting from the first edge of SCK
CPOL
bit 0
Serial Clock Polarity.
0: SCK idle at logic LOW
1: SCK idle at logic HIGH
SPI Data Register (SPIDATA)
7
6
5
4
3
2
1
0
Reset Value
SFR 9BH
00H
SPIDATA
SPI Data Register. Data for SPI is read from or written to this location. The SPI transmit and receive buffers
bits 7-0
are separate registers, but both are addressed at this location.
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SPI Receive Control Register (SPIRCON)
7
6
5
4
3
2
1
0
Reset Value
SFR 9CH
RXCNT7
RXCNT6
RXCNT5
RXCNT4
RXCNT3
RXCNT2
RXIRQ2
RXCNT1
RXIRQ1
RXCNT0
RXIRQ0
00H
RXFLUSH
RXCNT
Receive Counter. Read only bits which read the number of bytes in the receive buffer (0 to 128).
bits 7-0
RXFLUSH
bit 7
Flush Receive FIFO. Write only.
0: No Action
1: SPI Receive Buffer Set to Empty
RXIRQ
Read IRQ Level. Write only.
bits 2-0
000
001
010
011
100
101
110
111
Generate IRQ when Receive Count = 1 or more.
Generate IRQ when Receive Count = 2 or more.
Generate IRQ when Receive Count = 4 or more.
Generate IRQ when Receive Count = 8 or more.
Generate IRQ when Receive Count = 16 or more.
Generate IRQ when Receive Count = 32 or more.
Generate IRQ when Receive Count = 64 or more.
Generate IRQ when Receive Count = 128 or more.
SPI Transmit Control Register (SPITCON)
7
6
5
4
3
2
1
0
Reset Value
SFR 9DH
TXCNT7
TXCNT6
TXCNT5
CLK_EN
TXCNT4
TXCNT3
DRV_EN
TXCNT2
TXIRQ2
TXCNT1
TXIRQ1
TXCNT0
TXIRQ0
00H
TXFLUSH
DRV_DLY
TXCNT
Transmit Counter. Read only bits which read the number of bytes in the transmit buffer (0 to 128).
bits 7-0
TXFLUSH
Flush Transmit FIFO. This bit is write only. When set, the SPI transmit pointer is set equal to the FIFO
bit 7
Output pointer. This bit is 0 for a read operation.
CLK_EN
SCK Driver Enable.
bit 5
0: Disable SCK Driver (Master Mode)
1: Enable SCK Driver (Master Mode)
DRV_DLY
bit 4
Drive Delay (refer to DRV_EN bit).
0: Drive Output Immediately
1: Drive Output After Current Byte Transfer
DRV_EN
Drive Enable.
bit 3
DRV_DLY DRV_EN MOSI or MISO OUTPUT CONTROL
0
0
1
1
0
1
0
1
Tristate Immediately
Drive Immediately
Tristate After the Current Byte Transfer
Drive After the Current Byte Transfer
TXIRQ
Transmit IRQ Level. Write only bits.
bits 2-0
000
001
010
011
100
101
110
111
Generate IRQ when Transmit count = 1 or less.
Generate IRQ when Transmit count = 2 or less.
Generate IRQ when Transmit count = 4 or less.
Generate IRQ when Transmit count = 8 or less.
Generate IRQ when Transmit count = 16 or less.
Generate IRQ when Transmit count = 32 or less.
Generate IRQ when Transmit count = 64 or less.
Generate IRQ when Transmit count = 128 or less.
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SPI Buffer Start Address (SPISTART)
7
6
5
4
3
2
1
0
Reset Value
SFR 9EH
1
80H
SPISTART
bits 6-0
SPI FIFO Start Address. Write-only. This specifies the start address of the SPI data buffer. This is a
circular FIFO that is located in the 128 bytes of indirect RAM. The FIFO starts at this address and ends
at the address specified in SPIEND. Must be less than SPIEND. Writing clears SPI transmit and receive counters.
SPITP
bits 6-0
SPI Transmit Pointer. Read-only. This is the FIFO address for SPI transmissions. This is where the next
byte will be written into the SPI FIFO buffer. This pointer increments after each write to the SPI Data register
unless that would make it equal to the SPI Receive pointer.
SPI Buffer End Address (SPIEND)
7
6
5
4
3
2
1
0
Reset Value
SFR 9FH
1
80H
SPIEND
SPI FIFO End Address. Write-only. This specifies the end address of the SPI data FIFO. This is a circular buffer
bits 6-0
that is located in the 128 bytes of indirect RAM. The buffer starts at SPISTART and ends at this address.
SPIRP
SPI Receive Pointer. Read-only. This is the FIFO address for SPI received bytes. This is the location of the next
bits 6-0
byte to be read from the SPI FIFO. This increments with each read from the SPI Data register until the RxCNT is zero.
Port 2 (P2)
7
6
5
4
3
2
1
0
Reset Value
SFR A0H
FFH
P2
bits 7-0
Port 2. This port functions as an address bus during external memory access, and as a general-purpose I/O port.
During external memory cycles, this port will contain the MSB of the address. Whether Port 2 is used as general-
purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.0).
PWM Control (PWMCON)
7
6
5
4
3
2
1
0
Reset Value
SFR A1H
—
—
PPOL
PWMSEL
SPDSEL
TPCNTL.2
TPCNTL.1
TPCNTL.0
00H
PPOL
bit 5
Period Polarity. Specifies the starting level of the PWM pulse.
0: ON Period. PWM Duty register programs the ON period.
1: OFF Period. PWM Duty register programs the OFF period.
PWMSEL PWM Register Select. Select which 16-bit register is accessed by PWMLOW/PWMHIGH.
bit 4
0: Period (must be 0 for TONE mode)
1: Duty
SPDSEL Speed Select.
bit 3 0: 1MHz (the USEC Clock)
1: SYSCLK
TPCNTL Tone Generator/Pulse Width Modulation Control.
bits 2-0
TPCNTL.2
TPCNTL.1
TPCNTL.0
MODE
0
0
0
1
0
0
1
1
0
1
1
1
Disable (default)
PWM
TONE—Square
TONE—Staircase
Tone Low (TONELOW) /PWM Low (PWMLOW)
7
6
5
4
3
2
1
0
Reset Value
SFR A2H
PWM7
PWM6
PWM5
PWM4
TDIV4
PWM3
TDIV3
PWM2
TDIV2
PWM1
TDIV1
PWM0
TDIV0
00H
TDIV7
TDIV6
TDIV5
PWMLOW Pulse Width Modulator Low Bits. These 8 bits are the least significant 8 bits of the PWM register.
bits 7-0
TDIV7-0
Tone Divisor. The low order bits that define the half-time period. For staircase mode the output is high
bits 7-0
impedance for the last 1/4 of this period.
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Tone High (TONEHI)/PWM High (PWMHI)
7
6
5
4
3
2
1
0
Reset Value
SFR A3H
PWM15
TDIV15
PWM14
TDIV14
PWM13
TDIV13
PWM12
TDIV12
PWM11
TDIV11
PWM10
TDIV10
PWM9
TDIV9
PWM8
TDIV8
00H
PWMHI
Pulse Width Modulator High Bits. These 8 bits are the high order bits of the PWM register.
bits 7-0
TDIV15-8
Tone Divisor. The high order bits that define the half time period. For staircase mode, the output is high
bits 7-0
impedance for the last 1/4 of this period.
Pending Auxiliary Interrupt (PAI)
7
6
5
4
3
2
1
0
Reset Value
SFR A5H
0
0
0
0
PAI3
PAI2
PAI1
PAI0
00H
PAI
bits 3-0
Pending Auxiliary Interrupt Register. The results of this register can be used as an index to vector to the appropriate
interrupt routine. All of these interrupts vector through address 0033H.
PAI3
PAI2
PAI1
PAI0
AUXILIARY INTERRUPT STATUS
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
No Pending Auxiliary IRQ
Digital Low Voltage IRQ Pending
Analog Low Voltage IRQ Pending
SPI Receive IRQ Pending
SPI Transmit IRQ Pending
One Millisecond System Timer IRQ Pending
Analog to Digital Conversion IRQ Pending
Accumulator IRQ Pending
One Second System Timer IRQ Pending
Auxiliary Interrupt Enable (AIE)
7
6
5
4
3
2
1
0
Reset Value
SFR A6H
ESEC
ESUM
EADC
EMSEC
ESPIT
ESPIR
EALV
EDLVB
00H
Interrupts are enabled by EICON.4 (SFR D8H). The other interrupts are controlled by the IE and EIE registers.
ESEC
bit 7
Enable Seconds Timer Interrupt (lowest priority auxiliary interrupt).
Write: Set mask bit for this interrupt 0 = masked, 1 = enabled.
Read: Current value of Seconds Timer Interrupt before masking.
ESUM
Enable Summation Interrupt.
bit 6
Write: Set mask bit for this interrupt 0 = masked, 1 = enabled.
Read: Current value of Summation Interrupt before masking.
EADC
Enable ADC Interrupt.
bit 5
Write: Set mask bit for this interrupt 0 = masked, 1 = enabled.
Read: Current value of ADC Interrupt before masking.
EMSEC
Enable Millisecond System Timer Interrupt.
bit 4
Write: Set mask bit for this interrupt 0 = masked, 1 = enabled.
Read: Current value of Millisecond System Timer Interrupt before masking.
ESPIT
Enable SPI Transmit Interrupt.
bit 3
Write: Set mask bit for this interrupt 0 = masked, 1 = enabled.
Read: Current value of SPI Transmit Interrupt before masking.
ESPIR
Enable SPI Receive Interrupt.
bit 2
Write: Set mask bit for this interrupt 0 = masked, 1 = enabled.
Read: Current value of SPI Receive Interrupt before masking.
EALV
Enable Analog Low Voltage Interrupt.
bit 1
Write: Set mask bit for this interrupt 0 = masked, 1 = enabled.
Read: Current value of Analog Low Voltage Interrupt before masking.
EDLVB
bit 0
Enable Digital Low Voltage or Breakpoint Interrupt (highest priority auxiliary interrupt).
Write: Set mask bit for this interrupt 0 = masked, 1 = enabled.
Read: Current value of Digital Low Voltage or Breakpoint Interrupt before masking.
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Auxiliary Interrupt Status Register (AISTAT)
7
6
5
4
3
2
1
0
Reset Value
SFR A7H
SEC
SUM
ADC
MSEC
SPIT
SPIR
ALVD
DLVD
00H
SEC
bit 7
Second System Timer Interrupt Status Flag (lowest priority AI).
0: SEC interrupt inactive or masked.
1: SEC Interrupt active.
SUM
Summation Register Interrupt Status Flag.
bit 6
0: SUM interrupt inactive or masked (if active, it is set inactive by reading the lowest byte of the Summation register).
1: SUM interrupt active.
ADC
ADC Interrupt Status Flag.
bit 5
0: ADC interrupt inactive or masked (If active, it is set inactive by reading the lowest byte of the Data Output Register).
1: ADC interrupt active (If active no new data will be written to the Data Output Register).
MSEC
bit 4
Millisecond System Timer Interrupt Status Flag.
0: MSEC interrupt inactive or masked.
1: MSEC interrupt active.
SPIT
bit 3
SPI Transmit Interrupt Status Flag.
0: SPI transmit interrupt inactive or masked.
1: SPI transmit interrupt active.
SPIR
bit 2
SPI Receive Interrupt Status Flag.
0: SPI receive interrupt inactive or masked.
1: SPI receive interrupt active.
ALVD
bit 1
Analog Low Voltage Detect Interrupt Status Flag.
0: ALVD interrupt inactive or masked.
1: ALVD interrupt active.
DLVD
bit 0
Digital Low Voltage Detect or Breakpoint Interrupt Status Flag (highest priority AI).
0: DLVD interrupt inactive or masked.
1: DLVD interrupt active.
Interrupt Enable (IE)
7
6
5
4
3
2
1
0
Reset Value
SFR A8H
EA
ES1
ET2
ES0
ET1
EX1
ET0
EX0
00H
EA
bit 7
Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6H).
0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register.
1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled.
ES1
bit 6
Enable Serial Port 1 Interrupt. This bit controls the masking of the serial Port 1 interrupt.
0: Disable all serial Port 1 interrupts.
1: Enable interrupt requests generated by the RI_1 (SCON1.0, SFR C0H) or TI_1 (SCON1.1, SFR C0H) flags.
ET2
bit 5
Enable Timer 2 Interrupt. This bit controls the masking of the Timer 2 interrupt.
0: Disable all Timer 2 interrupts.
1: Enable interrupt requests generated by the TF2 flag (T2CON.7, SFR C8H).
ES0
bit 4
Enable Serial port 0 interrupt. This bit controls the masking of the serial Port 0 interrupt.
0: Disable all serial Port 0 interrupts.
1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98H) or TI_0 (SCON0.1, SFR 98H) flags.
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ET1
bit 3
Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt.
0: Disable Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88H).
EX1
bit 2
Enable External Interrupt 1. This bit controls the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 pin.
ET0
bit 1
Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupts.
1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88H).
EX0
bit 0
Enable External Interrupt 0. This bit controls the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 pin.
Breakpoint Control (BPCON)
7
6
5
4
3
2
1
0
Reset Value
SFR A9H
BP
0
0
0
0
0
PMSEL
EBP
00H
Writing to register sets the breakpoint condition specified by MCON, BPL, and BPH.
BP
bit 7
Breakpoint Interrupt. This bit indicates that a break condition has been recognized by a hardware breakpoint register(s).
Read: Status of Breakpoint Interrupt. Will indicate a breakpoint match for any of the breakpoint registers.
Write: 0: No effect.
1: Clear Breakpoint 1 for breakpoint register selected by MCON (SFR 95H).
PMSEL
Program Memory Select. Write this bit to select memory for address breakpoints of register selected in
bit 1
MCON (SFR 95H).
0: Break on address in data memory.
1: Break on address in program memory.
EBP
Enable Breakpoint. This bit enables this breakpoint register. Address of breakpoint register selected by
bit 0
MCON (SFR 95H).
0: Breakpoint disabled.
1: Breakpoint enabled.
Breakpoint Low (BPL) Address for BP Register Selected in MCON (95H)
7
6
5
4
3
2
1
0
Reset Value
SFR AAH
BPL.7
BPL.6
BPL.5
BPL.4
BPL.3
BPL.2
BPL.1
BPL.0
00H
BPL.7-0
Breakpoint Low Address. The low 8 bits of the 16 bit breakpoint address.
bits 7-0
Breakpoint High Address (BPH) Address for BP Register Selected in MCON (95H)
7
6
5
4
3
2
1
0
Reset Value
SFR ABH
BPH.7
BPH.6
BPH.5
BPH.4
BPH.3
BPH.2
BPH.1
BPH.0
00H
BPH.7-0
Breakpoint High Address. The high 8 bits of the 16 bit breakpoint address.
bits 7-0
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Port 0 Data Direction Low Register (P0DDRL)
7
6
5
4
3
2
1
0
Reset Value
SFR ACH
P03H
P03L
P02H
P02L
P01H
P01L
P00H
P00L
00H
P0.3
Port 0 bit 3 control.
bits 7-6
P03H
P03L
0
0
1
1
0
1
0
1
Standard 8051(Pull-Up)
CMOS Output
Open Drain Output
Input
P0.2
Port 0 bit 2 control.
bits 5-4
P02H
P02L
0
0
1
1
0
1
0
1
Standard 8051(Pull-Up)
CMOS Output
Open Drain Output
Input
P0.1
Port 0 bit 1 control.
bits 3-2
P01H
P01L
0
0
1
1
0
1
0
1
Standard 8051(Pull-Up)
CMOS Output
Open Drain Output
Input
P0.0
Port 0 bit 0 control.
bits 1-0
P00H
P00L
0
0
1
1
0
1
0
1
Standard 8051(Pull-Up)
CMOS Output
Open Drain Output
Input
NOTE: Port 0 also controlled by EA and Memory Access Control HCR1.1.
Port 0 Data Direction High Register (P0DDRH)
7
6
5
4
3
2
1
0
Reset Value
SFR ADH
P07H
P07L
P06H
P06L
P05H
P05L
P04H
P04L
00H
P0.7
Port 0 bit 7 control.
bits 7-6
P07H
P07L
0
0
1
1
0
1
0
1
Standard 8051(Pull-Up)
CMOS Output
Open Drain Output
Input
P0.6
Port 0 bit 6 control.
bits 5-4
P06H
P06L
0
0
1
1
0
1
0
1
Standard 8051(Pull-Up)
CMOS Output
Open Drain Output
Input
P0.5
Port 0 bit 5 control.
bits 3-2
P05H
P05L
0
0
1
1
0
1
0
1
Standard 8051(Pull-Up)
CMOS Output
Open Drain Output
Input
P0.4
Port 0 bit 4 control.
bits 1-0
P04H
P04L
0
0
1
1
0
1
0
1
Standard 8051(Pull-Up)
CMOS Output
Open Drain Output
Input
NOTE: Port 0 also controlled by EA and Memory Access Control HCR1.1.
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Port 1 Data Direction Low Register (P1DDRL)
7
6
5
4
3
2
1
0
Reset Value
SFR AEH
P13H
P13L
P12H
P12L
P11H
P11L
P10H
P10L
00H
P1.3
Port 1 bit 3 control.
bits 7-6
P13H
P13L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P1.2
Port 1 bit 2 control.
bits 5-4
P12H
P12L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P1.1
Port 1 bit 1 control.
bits 3-2
P11H
P11L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P1.0
Port 1 bit 0 control.
bits 1-0
P10H
P10L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
Port 1 Data Direction High Register (P1DDRH)
7
6
5
4
3
2
1
0
Reset Value
SFR AFH
P17H
P17L
P16H
P16L
P15H
P15L
P14H
P14L
00H
P1.7
Port 1 bit 7 control.
bits 7-6
P17H
P17L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P1.6
Port 1 bit 6 control.
bits 5-4
P16H
P16L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P1.5
Port 1 bit 5 control.
bits 3-2
P15H
P15L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P1.4
Port 1 bit 4 control.
bits 1-0
P14H
P14L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
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Port 3 (P3)
7
6
5
4
3
2
1
0
Reset Value
SFR B0H
P3.7
RD
P3.6
WR
P3.5
T1
P3.4
T0
P3.3
INT1
P3.2
INT0
P3.1
P3.0
FFH
TXD0
RXD0
P3.7-0
bits 7-0
General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have
an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated
Port 3 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity.
RD
bit 7
External Data Memory Read Strobe. This pin provides an active low read strobe to an external memory device.
If Port 0 or Port 2 is selected for external memory in the HCR1 register, this function will be enabled even if a 1
is not written to this latch bit. When external memory is selected, the settings of P3DRRH are ignored.
WR
bit 6
External Data Memory Write Strobe. This pin provides an active low write strobe to an external memory
device. If Port 0 or Port 2 is selected for external memory in the HCR1 register, this function will be enabled even
if a 1 is not written to this latch bit. When external memory is selected, the settings of P3DRRH are ignored.
T1
bit 5
Timer/Counter 1 External Input. A 1 to 0 transition on this pin will increment Timer 1.
Timer/Counter 0 External Input. A 1 to 0 transition on this pin will increment Timer 0.
External Interrupt 1. A falling edge/low level on this pin will cause an external interrupt 1 if enabled.
External Interrupt 0. A falling edge/low level on this pin will cause an external interrupt 0 if enabled.
T0
bit 4
INT1
bit 3
INT0
bit 2
TXD0
Serial Port 0 Transmit. This pin transmits the serial Port 0 data in serial port modes 1, 2, 3, and emits the
bit 1
synchronizing clock in serial port mode 0.
RXD0
Serial Port 0 Receive. This pin receives the serial Port 0 data in serial port modes 1, 2, 3, and is a bidirectional
bit 0
data transfer pin in serial port mode 0.
Port 2 Data Direction Low Register (P2DDRL)
7
6
5
4
3
2
1
0
Reset Value
SFR B1H
P23H
P23L
P22H
P22L
P21H
P21L
P20H
P20L
00H
P2.3
Port 2 bit 3 control.
bits 7-6
P23H
P23L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P2.2
Port 2 bit 2 control.
bits 5-4
P22H
P22L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P2.1
Port 2 bit 1 control.
bits 3-2
P21H
P21L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P2.0
Port 2 bit 0 control.
bits 1-0
P20H
P20L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
NOTE: Port 2 also controlled by EA and Memory Access Control HCR1.1.
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Port 2 Data Direction High Register (P2DDRH)
7
6
5
4
3
2
1
0
Reset Value
SFR B2H
P27H
P27L
P26H
P26L
P25H
P25L
P24H
P24L
00H
P2.7
Port 2 bit 7 control.
bits 7-6
P27H
P27L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P2.6
Port 2 bit 6 control.
bits 5-4
P26H
P26L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P2.5
Port 2 bit 5 control.
bits 3-2
P25H
P25L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P2.4
Port 2 bit 4 control.
bits 1-0
P24H
P24L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
NOTE: Port 2 also controlled by EA and Memory Access Control HCR1.1.
Port 3 Data Direction Low Register (P3DDRL)
7
6
5
4
3
2
1
0
Reset Value
SFR B3H
P33H
P33L
P32H
P32L
P31H
P31L
P30H
P30L
00H
P3.3
Port 3 bit 3 control.
bits 7-6
P33H
P33L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P3.2
Port 3 bit 2 control.
bits 5-4
P32H
P32L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P3.1
Port 3 bit 1 control.
bits 3-2
P31H
P31L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P3.0
Port 3 bit 0 control.
bits 1-0
P30H
P30L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
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Port 3 Data Direction High Register (P3DDRH)
7
6
5
4
3
2
1
0
Reset Value
SFR B4H
P37H
P37L
P36H
P36L
P35H
P35L
P34H
P34L
00H
P3.7
Port 3 bit 7 control.
bits 7-6
P37H
P37L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
NOTE: Port 3.7 also controlled by EA and Memory Access Control HCR1.1.
P3.6
Port 3 bit 6 control.
bits 5-4
P36H
P36L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
NOTE: Port 3.6 also controlled by EA and Memory Access Control HCR1.1.
P3.5
Port 3 bit 5 control.
bits 3-2
P35H
P35L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
P3.4
Port 3 bit 4 control.
bits 1-0
P34H
P34L
0
0
1
1
0
1
0
1
Standard 8051
CMOS Output
Open Drain Output
Input
DAC Low Byte (DACL)
7
6
5
4
3
2
1
0
Reset Value
SFR B5H
00H
DACL7-0
Least Significant Bit Register for DAC0-3 and DAC Control (0 and 2).
bits 7-0
DAC High Byte (DACH)
7
6
5
4
3
2
1
0
Reset Value
SFR B6H
00H
DACH7-0
Most Significant Byte Register for DAC0-3 and DAC Control (1 and 3).
bits 7-0
DAC Select Register (DACSEL)
7
6
5
4
3
2
1
0
Reset Value
SFR B7H
DSEL7
DSEL6
DSEL5
DSEL4
DSEL3
DSEL2
DSEL1
DSEL0
00H
DSEL7-0
DAC and DAC Control Select. The DACSEL register selects which DAC output register or which DAC control
bits 7-0
register is accessed by the DACL and DACH registers.
DACSEL (B7H)
DACH (B6H)
DACL (B5H)
RESET VALUE
00H
01H
02H
03H
04H
05H
06H
07H
DAC0 (high)
DAC1 (high)
DAC2 (high)
DAC3 (high)
DACCON1
DACCON3
—
DAC0 (low)
DAC1 (low)
DAC2 (low)
DAC3 (low)
DACCON0
DACCON2
LOADCON
—
0000H
0000H
0000H
0000H
6363H
0303H
--00H
—
—
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DAC0 Control Register (DACCON0)
DACSEL = 04H
7
6
5
4
3
2
1
0
Reset Value
SFR B5H
COR0
EOD0
IDAC0DIS
0
0
SELREF0
DOM0_1
DOM0_0
63H
COR0
Current Over Range on DAC0
bit 7
Write: 0 = Clear to release from high-impedance state back to normal mode unless an over-range condition exists.
1 = NOP
Read: 0 = No current over range for DAC0.
1 = COR0 signal after 3ms filter (EOD0 = 1) or raw signal (EOD0 = 0).
EOD0
Enable Over-Current Detection
bit 6
0 = Disable over-current detection.
1 = Enable over-current detection (default).
IDAC0DIS IDAC0 Disable (for DOM0 = 00)
bit 5
0 = IDAC on mode for DAC0.
1 = IDAC off mode for DAC0 (default).
Not Used
bits 4-3
SELREF0 Select the Reference Voltage for DAC0 Voltage Reference.
bit 2 0 = DAC0 VREF = AVDD (default).
1 = DAC0 VREF = internal VREF
.
DOM0_1-0 DAC Output Mode DAC0.
bits 1-0
DOM0
OUTPUT MODE FOR DAC0
00
01
10
11
Normal VDAC output, IDAC controlled by IDAC0DIS bit.
Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off high impedance, IDAC off (default).
DAC1 Control Register (DACCON1)
DACSEL = 04H
7
6
5
4
3
2
1
0
Reset Value
SFR B6H
COR1
EOD1
IDAC1DIS
0
0
SELREF1
DOM1_1
DOM1_0
63H
COR1
Current Over Range on DAC1
bit 7
Write: 0 = Clear to release from high-impedance state back to normal mode unless an over-range condition exists.
1 = NOP
Read: 0 = No current over range for DAC1.
1 = COR1 signal after 3ms filter (EOD1 = 1) or raw signal (EOD1 = 0).
EOD1
Enable Over-Current Detection
bit 6
0 = Disable over-current detection.
1 = Enable over-current detection (default).
IDAC1DIS IDAC1 Disable (for DOM1 = 00)
bit 5
0 = IDAC on mode for DAC1.
1 = IDAC off mode for DAC1 (default).
Not Used
bits 4-3
SELREF1 Select the Reference Voltage for DAC1 Voltage Reference.
bit 2 0 = DAC1 VREF = AVDD (default).
1 = DAC1 VREF = internal VREF
.
DOM1_1-0 DAC Output Mode DAC0.
bits 1-0
DOM1
OUTPUT MODE FOR DAC1
00
01
10
11
Normal VDAC output, IDAC controlled by IDAC1DIS bit.
Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off high impedance, IDAC off (default).
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DAC2 Control Register (DACCON2)
DACSEL = 05H
7
6
5
4
3
2
1
0
Reset Value
SFR B5H
0
0
0
0
0
SELREF2
DOM2_1
DOM2_0
03H
SELREF2 Select the Reference Voltage for DAC2 Voltage Reference.
bit 2 0 = DAC2 VREF = AVDD (default).
1 = DAC2 VREF = internal VREF
.
DOM2_1-0 DAC Output Mode DAC2.
bits 1-0
DOM2
OUTPUT MODE FOR DAC2
00
01
10
11
Normal VDAC output.
Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off high impedance, IDAC off (default).
DAC3 Control Register (DACCON3)
DACSEL = 05H
7
6
5
4
3
2
1
0
Reset Value
SFR B6H
0
0
0
0
0
SELREF3
DOM3_1
DOM3_0
03H
SELREF3 Select the Reference Voltage for DAC3 Voltage Reference.
bit 2 0 = DAC2 VREF = AVDD (default).
1 = DAC2 VREF = internal VREF
.
DOM3_1-0 DAC Output Mode DAC3.
bits 1-0
DOM2
OUTPUT MODE FOR DAC2
00
01
10
11
Normal VDAC output.
Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off high impedance, IDAC off (default).
DAC Load Control Register (LOADCON)
DACSEL = 06H
7
6
5
4
3
2
1
0
Reset Value
SFR B5H
D3LOAD1
D3LOAD0
D2LOAD1
D2LOAD0
D1LOAD1
D1LOAD0
D0LOAD1
D0LOAD0
00H
D3LOAD1-0 DAC Load Options.
bit 7-6
DxLOAD
OUTPUT MODE FOR DACx
D2LOAD1-0
bit 5-4
00
01
10
11
Direct load: write to DACxL directly loads the DAC buffer and the DAC output (write to DACxH does not load DAC output).
Delay load: the values last written to DACxL/DACxH will be transferred to the DAC output on the next MSEC timer tick.
Delay load: the values last written to DACxL/DACxH will be transferred to the DAC output on the next HMSEC timer tick.
Sync load: the values contained in the DACxL/DACxH registers will be transferred to the DAC output immediately after
11B is written to this register.
D1LOAD1-0
bit 3-2
D0LOAD1-0
bit 1-0
Interrupt Priority (IP)
7
6
5
4
3
2
1
0
Reset Value
SFR B8H
1
PS1
PT2
PS0
PT1
PX1
PT0
PX0
80H
PS1
bit 6
Serial Port 1 Interrupt. This bit controls the priority of the serial Port 1 interrupt.
0 = Serial Port 1 priority is determined by the natural priority order.
1 = Serial Port 1 is a high priority interrupt.
PT2
bit 5
Timer 2 Interrupt. This bit controls the priority of the Timer 2 interrupt.
0 = Timer 2 priority is determined by the natural priority order.
1 = Timer 2 priority is a high priority interrupt.
PS0
bit 4
Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt.
0 = Serial Port 0 priority is determined by the natural priority order.
1 = Serial Port 0 is a high priority interrupt.
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PT1
bit 3
Timer 1 Interrupt. This bit controls the priority of the Timer 1 interrupt.
0 = Timer 1 priority is determined by the natural priority order.
1 = Timer 1 priority is a high priority interrupt.
PX1
bit 2
External Interrupt 1. This bit controls the priority of external interrupt 1.
0 = External interrupt 1 priority is determined by the natural priority order.
1 = External interrupt 1 is a high priority interrupt.
PT0
bit 1
Timer 0 Interrupt. This bit controls the priority of the Timer 0 interrupt.
0 = Timer 0 priority is determined by the natural priority order.
1 = Timer 0 priority is a high priority interrupt.
PX0
bit 0
External Interrupt 0. This bit controls the priority of external interrupt 0.
0 = External interrupt 0 priority is determined by the natural priority order.
1 = External interrupt 0 is a high priority interrupt.
Serial Port 1 Control (SCON1)
7
6
5
4
3
2
1
0
Reset Value
SFR C0H
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00H
SM0-2
bits 7-5
Serial Port 1 Mode. These bits control the mode of serial Port 1. Modes 1, 2, and 3 have 1 start and 1 stop bit
in addition to the 8 or 9 data bits.
MODE SM0
SM1
SM2 FUNCTION
LENGTH
PERIOD
(1)
0
0
0
0
0
0
0
1
Synchronous
Synchronous
8 bits
8 bits
12 pCLK
(1)
4 pCLK
1(2)
0
1
1
0
x
Asynchronous
Asynchronous
10 bits
11 bits
Timer 1 or 2 Baud Rate Equation
(1)
2
0
64 pCLK (SMOD = 0)
(1)
32 pCLK (SMOD = 1)
(1)
2
1
0
1
Asynchronous with
Multiprocessor Communication
11 bits
64 pCLK (SMOD = 0)
(1)
32 pCLK (SMOD = 1)
3(2)
3(2)
1
1
1
1
0
1
Asynchronous
11 bits
11 bits
Timer 1 or 2 Baud Rate Equation
Timer 1 or 2 Baud Rate Equation
Asynchronous with
Multiprocessor Communication
NOTE: (1) pCLK will be equal to tCLK, except that pCLK will stop for IDLE. (2) For modes 1 and 3, the selection of
Timer 1 or 2 for baud rate is specified via the SCON register.
REN_1
bit 4
Receive Enable. This bit enables/disables the serial Port 1 received shift register.
0 = Serial Port 1 reception disabled.
1 = Serial Port 1 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0).
TB8_1
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 1 modes 2 and 3.
bit 3
RB8_1
9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 1 modes
bit 2
2 and 3. In serial port mode 1, when SM2_1 = 0, RB8_1 is the state of the stop bit. RB8_1 is not used in mode 0.
TI_1
bit 1
Transmitter Interrupt Flag. This bit indicates that data in the serial Port 1 buffer has been completely shifted
out. In serial port mode 0, TI_1 is set at the end of the 8th data bit. In all other modes, this bit is set at the end
of the last data bit. This bit must be cleared by software to transmit the next byte.
RI_1
bit 0
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 1 buffer. In
serial port mode 0, RI_1 is set at the end of the 8th bit. In serial port mode 1, RI_1 is set after the last sample
of the incoming stop bit subject to the state of SM2_1. In modes 2 and 3, RI_1 is set after the last sample of
RB8_1. This bit must be cleared by software to receive the next byte.
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Serial Data Buffer 1 (SBUF1)
7
6
5
4
3
2
1
0
Reset Value
SFR C1H
00H
SBUF1.7-0 Serial Data Buffer 1. Data for serial Port 1 is read from or written to this location. The serial transmit and receive
bits 7-0 buffers are separate registers, but both are addressed at this location.
Enable Wake Up (EWU) Waking Up from IDLE Mode
7
6
5
4
3
2
1
0
Reset Value
SFR C6H
—
—
—
—
—
EWUWDT
EWUEX1
EWUEX0
00H
Auxialiary interrupts will wake up from IDLE. They are enabled with EAI (EICON.5).
EWUWDT Enable Wake Up Watchdog Timer. Wake using watchdog timer interrupt.
bit 2
0 = Do not wake up on watchdog timer interrupt.
1 = Wake up on watchdog timer interrupt.
EWUEX1
bit 1
Enable Wake Up External 1. Wake using external interrupt source 1.
0 = Do not wake up on external interrupt source 1.
1 = Wake up on external interrupt source 1.
EWUEX0
bit 0
Enable Wake Up External 0. Wake using external interrupt source 0.
0 = Do not wake up on external interrupt source 0.
1 = Wake up on external interrupt source 0.
System Clock Divider Register (SYSCLK)
7
6
5
40
3
2
1
0
Reset Value
SFR C7H
0
0
DIVMOD1
DIVMOD0
0
DIV2
DIV1
DIV0
00H
DIVMOD1-0 Clock Divide Mode
bits 5-4
Write:
DIVMOD
DIVIDE MODE
Normal mode (default, no divide)
Immediate mode: start divide immediately, return to Normal mode on IDLE wakeup condition..
00
01
10
Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is
enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not
enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the
MSINT counter overflows, which follows a wakeup condition.
11
Reserved
Read:
DIVMOD
DIVISION MODE STATUS
00
01
10
11
No divide
Divider is in Immediate mode
Divider is in Delay mode
Reserved
NOTE:
Do not clear the DIVMOD register to exit Immediate
or Delay modes. Exit these modes only through the
appropriate interrupt (the interrupt can be either
normally generated or software generated).
DIV2-0
bit 2-0
Divide Mode
DIV
DIVISOR
000
001
010
011
100
101
110
111
Divide by 2 (default)
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 1024
Divide by 2048
Divide by 4096
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Timer 2 Control (T2CON)
7
6
5
4
3
2
1
0
Reset Value
SFR C8H
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
00H
TF2
Timer 2 Overflow Flag. This flag will be set when Timer 2 overflows from FFFFH. It must be cleared by software.
bit 7
TF2 will only be set if RCLK and TCLK are both cleared to 0. Writing a 1 to TF2 forces a Timer 2 interrupt if enabled.
EXF2
bit 6
Timer 2 External Flag. A negative transition on the T2EX pin (P1.1) will cause this flag to be set based on
the EXEN2 (T2CON.3) bit. If set by a negative transition, this flag must be cleared to 0 by software.
Setting this bit in software will force a timer interrupt if enabled.
RCLK
bit 5
Receive Clock Flag. This bit determines the serial Port 0 timebase when receiving data in serial modes 1 or 3.
0 = Timer 1 overflow is used to determine receiver baud rate for USART0.
1 = Timer 2 overflow is used to determine receiver baud rate for USART0.
Setting this bit will force Timer 2 into baud rate generation mode. The timer will operate from a divide by 2 of
the external clock.
TCLK
bit 4
Transmit Clock Flag. This bit determines the serial Port 0 timebase when transmitting data in serial modes 1 or 3.
0 = Timer 1 overflow is used to determine transmitter baud rate for USART0.
1 = Timer 2 overflow is used to determine transmitter baud rate for USART0.
Setting this bit will force Timer 2 into baud rate generation mode. The timer will operate from a divide by 2 of
the external clock.
EXEN2
bit 3
Timer 2 External Enable. This bit enables the capture/reload function on the T2EX pin if Timer 2 is not
generating baud rates for the serial port.
0 = Timer 2 will ignore all external events at T2EX.
1 = Timer 2 will capture or reload a value if a negative transition is detected on the T2EX pin.
TR2
Timer 1 Run Control. This bit enables/disables the operation of Timer 2. Halting this timer will preserve the
bit 2
current count in TH2, TL2.
0 = Timer 2 is halted.
1 = Timer 2 is enabled.
C/T2
bit 1
Counter/Timer Select. This bit determines whether Timer 2 will function as a timer or counter. Independent of
this bit, Timer 2 runs at 2 clocks per tick when used in baud rate generator mode.
0 = Timer 2 functions as a timer. The speed of Timer 2 is determined by the T2M bit (CKCON.5).
1 = Timer 2 will count negative transitions on the T2 pin (P1.0).
CP/RL2
bit 0
Capture/Reload Select. This bit determines whether the capture or reload function will be used for Timer 2. If
either RCLK or TCLK is set, this bit will not function and the timer will function in an auto-reload mode
following each overflow.
0 = Auto-reloads will occur when Timer 2 overflows or a falling edge is detected on T2EX if EXEN2 = 1.
1 = Timer 2 captures will occur when a falling edge is detected on T2EX if EXEN2 = 1.
Timer 2 Capture LSB (RCAP2L)
7
6
5
4
3
2
1
0
Reset Value
SFR CAH
00H
RCAP2L
Timer 2 Capture LSB. This register is used to capture the TL2 value when Timer 2 is configured in capture
bits 7-0
mode. RCAP2L is also used as the LSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode.
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Timer 2 Capture MSB (RCAP2H)
7
6
5
4
3
2
1
0
Reset Value
SFR CBH
00H
RCAP2H
bits 7-0
Timer 2 Capture MSB. This register is used to capture the TH2 value when Timer 2 is configured in capture
mode. RCAP2H is also used as the MSB of a 16-bit reload value when Timer 2 is configured in auto-reload
mode.
Timer 2 LSB (TL2)
7
6
5
4
3
2
1
0
Reset Value
SFR CCH
00H
TL2
Timer 2 LSB. This register contains the least significant byte of Timer 2.
bits 7-0
Timer 2 MSB (TH2)
7
6
5
4
3
2
1
0
Reset Value
SFR CDH
00H
TH2
Timer 2 MSB. This register contains the most significant byte of Timer 2.
bits 7-0
Program Status Word (PSW)
7
6
5
4
3
2
1
0
Reset Value
SFR D0H
CY
AC
F0
RS1
RS0
OV
F1
P
00H
CY
Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow
bit 7
(during subtraction). Otherwise it is cleared to 0 by all arithmetic operations.
AC
bit 6
Auxiliary Carry Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry into (during addition),
or a borrow (during substraction) from the high order nibble. Otherwise, it is cleared to 0 by all arithmetic
operations.
F0
User Flag 0. This is a bit-addressable, general-purpose flag for software control.
bit 5
RS1, RS0 Register Bank Select 1-0. These bits select which register bank is addressed during register accesses.
bits 4-3
RS1
RS0 REGISTER BANK ADDRESS
0
0
1
1
0
1
0
1
0
1
2
3
00H-07H
08H-0FH
10H-17H
18H-1FH
OV
Overflow Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow
bit 2
(subtraction), or overflow (multiply or divide). Otherwise it is cleared to 0 by all arithmetic operations.
F1
User Flag 1. This is a bit-addressable, general-purpose flag for software control.
bit 1
P
Parity Flag. This bit is set to 1 if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity); and
bit 0
cleared to 0 on even parity.
ADC Offset Calibration Register Low Byte (OCL)
7
6
5
4
3
2
1
0
Reset Value
SFR D1H
00H
OCL
ADC Offset Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the
bits 7-0
ADC offset calibration. A value which is written to this location will set the ADC offset calibration value.
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ADC Offset Calibration Register Middle Byte (OCM)
7
6
5
4
3
2
1
0
Reset Value
SFR D2H
00H
OCM
ADC Offset Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC
bits 7-0
offset calibration. A value which is written to this location will set the ADC offset calibration value.
ADC Offset Calibration Register High Byte (OCH)
7
6
5
4
3
2
1
0
Reset Value
SFR D3H
00H
OCH
ADC Offset Calibration Register High Byte. This is the high byte of the 24-bit word that contains the
bits 7-0
ADC offset calibration. A value which is written to this location will set the ADC offset calibration value.
ADC Gain Calibration Register Low Byte (GCL)
7
6
5
4
3
2
1
0
Reset Value
SFR D4H
5AH
GCL
ADC Gain Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC
bits 7-0
gain calibration. A value which is written to this location will set the ADC gain calibration value.
ADC Gain Calibration Register Middle Byte (GCM)
7
6
5
4
3
2
1
0
Reset Value
SFR D5H
ECH
GCM
ADC Gain Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains
bits 7-0
the ADC gain calibration. A value which is written to this location will set the ADC gain calibration value.
ADC Gain Calibration Register High Byte (GCH)
7
6
5
4
3
2
1
0
Reset Value
SFR D6H
5FH
GCH
ADC Gain Calibration Register High Byte. This is the high byte of the 24-bit word that contains the
bits 7-0
ADC gain calibration. A value which is written to this location will set the ADC gain calibration value.
ADC Multiplexer Register (ADMUX)
7
6
5
4
3
2
1
0
Reset Value
SFR D7H
INP3
INP2
INP1
INP0
INN3
INN2
INN1
INN0
01H
INP3-0
Input Multiplexer Positive Channel. This selects the positive signal input.
bits 7-4
INP3
INP2
INP1
INP0
POSITIVE INPUT
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0 (default)
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AINCOM
Temperature Sensor (Requires ADMUX = FFH)
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INN3-0
Input Multiplexer Negative Channel. This selects the negative signal input.
bits 3-0
INN3
INN2
INN1
INN0
NEGATIVE INPUT
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
AIN1 (default)
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AINCOM
Temperature Sensor (Requires ADMUX = FFH)
Enable Interrupt Control (EICON)
7
6
5
4
3
2
1
0
Reset Value
SFR D8H
SMOD1
1
EAI
AI
WDTI
0
0
0
40H
SMOD1
bit 7
Serial Port 1 Mode. When this bit is set the serial baud rate for Port 1 will be doubled.
0 = Standard baud rate for Port 1 (default).
1 = Double baud rate for Port 1.
EAI
bit 5
Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and
identified by SFR registers PAI (SFR A5H), AIE (SFR A6H), and AISTAT (SFR A7H).
0 = Auxiliary Interrupt disabled (default).
1 = Auxiliary Interrupt enabled.
AI
bit 4
Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine,
after the source of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates
an Auxiliary Interrupt, if enabled.
0 = No Auxiliary Interrupt detected (default).
1 = Auxiliary Interrupt detected.
WDTI
bit 3
Watchdog Timer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine.
Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled.
The Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabled
in HCR0.
0 = No Watchdog Timer Interrupt Detected (default).
1 = Watchdog Timer Interrupt Detected.
ADC Results Register Low Byte (ADRESL)
7
6
5
4
3
2
1
0
Reset Value
SFR D9H
00H
ADRESL
The ADC Results Low Byte. This is the low byte of the 24-bit word that contains the ADC
bits 7-0
Converter Results. Reading from this register clears the ADC interrupt.
ADC Results Register Middle Byte (ADRESM)
7
6
5
4
3
2
1
0
Reset Value
SFR DAH
00H
ADRESM
The ADC Results Middle Byte. This is the middle byte of the 24-bit word that contains the ADC
bits 7-0
Converter Results.
ADC Results Register High Byte (ADRESH)
7
6
5
4
3
2
1
0
Reset Value
SFR DBH
00H
ADRESH
The ADC Results High Byte. This is the high byte of the 24-bit word that contains the ADC
bits 7-0
Converter Results.
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ADC Control Register 0 (ADCON0)
7
6
5
4
3
2
1
0
Reset Value
SFR DCH
—
BOD
EVREF
VREFH
EBUF
PGA2
PGA1
PGA0
30H
BOD
bit 6
Burnout Detect. When enabled this connects a positive current source to the positive channel and a negative
current source to the negative channel. If the channel is open circuit then the ADC results will be full-scale.
0 = Burnout Current Sources Off (default).
1 = Burnout Current Sources On.
EVREF
bit 5
Enable Internal Voltage Reference. If the internal voltage reference is not used, it should be turned off to save
power and reduce noise.
0 = Internal Voltage Reference Off.
1 = Internal Voltage Reference On (default).
VREFH
bit 4
Voltage Reference High Select. The internal voltage reference can be selected to be 2.5V or 1.25V.
0 = REFOUT/REF IN+ is 1.25V.
1 = REFOUT/REF IN+ is 2.5V (default).
EBUF
Enable Buffer. Enable the input buffer to provide higher input impedance but limits the input voltage range and
bit 3
dissipates more power.
0 = Buffer disabled (default).
1 = Buffer enabled.
PGA2-0
Programmable Gain Amplifier. Sets the gain for the PGA from 1 to 128.
bits 2-0
PGA2
PGA1
PGA0
GAIN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 (default)
2
4
8
16
32
64
128
ADC Control Register 1 (ADCON1)
7
6
5
4
3
2
1
0
Reset Value
SFR DDH
—
POL
SM1
SM0
—
CAL2
CAL1
CAL0
x000 0000B
POL
Polarity. Polarity of the ADC result and Summation register.
bit 6
0 = Bipolar.
1 = Unipolar.
POL
ANALOG INPUT
DIGITAL OUTPUT
+FSR
ZERO
–FSR
0x7FFFFF
0x000000
0x800000
0
+FSR
ZERO
–FSR
0xFFFFFF
0x000000
0x000000
1
SM1-0
Settling Mode. Selects the type of filter or auto select which defines the digital filter settling characteristics.
bits 5-4
SM1
SM0
SETTLING MODE
0
0
1
1
0
1
0
1
Auto
Fast Settling Filter
Sinc2 Filter
Sinc3 Filter
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CAL2-0
Calibration Mode Control Bits.
bits 2-0
CAL2 CAL1 CAL0
CALIBRATION MODE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No Calibration (default)
Self Calibration, Offset and Gain
Self Calibration, Offset Only
Self Calibration, Gain Only
System Calibration, Offset Only
System Calibration, Gain Only
Reserved
Reserved
Read Value—000B.
ADC Control Register 2 (ADCON2)
7
6
5
4
3
2
1
0
Reset Value
SFR DEH
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
1BH
DR7-0
Decimation Ratio LSB.
bits 7-0
ADC Control Register 3 (ADCON3)
7
6
5
4
3
2
1
0
Reset Value
SFR DFH
—
—
—
—
—
DR10
DR9
DR8
06H
DR10-8
Decimation Ratio Most Significant 3 Bits. The output data rate = (ACLK + 1)/64/Decimation Ratio.
bits 2-0
Accumulator (A or ACC)
7
6
5
4
3
2
1
0
Reset Value
SFR E0H
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
00H
ACC.7-0
Accumulator. This register serves as the accumulator for arithmetic and logic operations.
bits 7-0
Summation/Shifter Control (SSCON)
7
6
5
4
3
2
1
0
Reset Value
SFR E1H
SSCON1
SSCON0
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
00H
The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register the 32-bit
SUMR3-0 registers will be cleared. The Summation registers will do sign extend if Bipolar is selected in ADCON1.
SSCON1-0 Summation/Shift Control.
bits 7-6
SSCON1 SSCON0
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
DESCRIPTION
0
0
0
1
0
1
0
0
0
0
1
1
0
0
1
x
0
1
0
x
0
0
0
x
0
0
0
0
0
0
0
0
0
Clear Summation Register
CPU Summation on Write to SUMR0
CPU Subtraction on Write to SUMR0
Note (1) Note (1) Note (1) CPU Shift Only
ADC Summation Only
Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) ADC Summation Completes then Shift Completes
Note (1) Note (1) Note (1)
x
x
x
NOTES: (1) Refer to register bit definition.
SCNT2-0
Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the
bits 5-3
SUMR0 register clears the interrupt.
SCNT2 SCNT1 SCNT0
SUMMATION COUNT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
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SHF2-0
Shift Count.
bits 2-0
SHF2
SHF1
SHF0
SHIFT
DIVIDE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
2
4
8
16
32
64
128
256
Summation Register 0 (SUMR0)
7
6
5
4
3
2
1
0
Reset Value
SFR E2H
00H
SUMR0
bits 7-0
Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7.
Write: will cause values in SUMR3-0 to be added to the summation register.
Read: will clear the Summation Count Interrupt.
Summation Register 1 (SUMR1)
7
6
5
4
3
2
1
0
Reset Value
SFR E3H
00H
SUMR1
Summation Register 1. This is the most significant byte of the lowest 16 bits of the summation register or bits 8-15.
bits 7-0
Summation Register 2 (SUMR2)
7
6
5
4
3
2
1
0
Reset Value
SFR E4H
00H
SUMR2
Summation Register 2. This is the most significant byte of the lowest 24 bits of the summation register or bits 16-23.
bits 7-0
Summation Register 3 (SUMR3)
7
6
5
4
3
2
1
0
Reset Value
SFR E5H
00H
SUMR3
Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24-31.
bits 7-0
Offset DAC Register (ODAC)
7
6
5
4
3
2
1
0
Reset Value
SFR E6H
00H
ODAC
bits 7-0
Offset DAC Register. This register will shift the input by up to half of the ADC input range. The least
significant bit is equal to the input voltage range divided by 256. The input range will depend on the setting
of the PGA. The ODAC is a signed magnitude register with bit 7 providing the sign of the offset and bits 6-0
providing the magnitude.
bit 7
Offset DAC Sign bit.
0 = Positive
1 = Negative
−VREF
ODAC[6: 0]
127
•
• (−1)bit 7
bit 6-0
Offset =
2• PGA
NOTE: The offset must be used after calibration or the calibration will nullify the effects.
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Low Voltage Detect Control (LVDCON)
7
6
5
4
3
2
1
0
Reset Value
SFR E7H
ALVDIS
ALVD2
ALVD1
ALVD0
DLVDIS
DLVD2
DLVD1
DLVD0
00H
ALVDIS
Analog Low Voltage Detect Disable.
bit 7
0 = Enable Detection of Low Analog Supply Voltage.
1 = Disable Detection of Low Analog Supply Voltage.
ALVD2-0
Analog Voltage Detection Level.
bits 6-4
ALVD2 ALVD1 ALVD0
VOLTAGE LEVEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AVDD 2.7V (default)
AVDD 3.0V
AVDD 3.3V
AVDD 4.0V
AVDD 4.2V
AVDD 4.5V
AVDD 4.7V
External Voltage AIN7 Compared to 1.2V
DLVDIS
Digital Low Voltage Detect Disable.
bit 3
0 = Enable Detection of Low Digital Supply Voltage.
1 = Disable Detection of Low Digital Supply Voltage.
DLVD2-0
Digital Voltage Detection Level.
bits 2-0
DLVD2 DLVD1 DLVD0
VOLTAGE LEVEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DVDD 2.7V (default)
DVDD 3.0V
DVDD 3.3V
DVDD 4.0V
DVDD 4.2V
DVDD 4.5V
DVDD 4.7V
External Voltage AIN6 Compared to 1.2V
Extended Interrupt Enable (EIE)
7
6
5
4
3
2
1
0
Reset Value
SFR E8H
1
1
1
EWDI
EX5
EX4
EX3
EX2
E0H
EWDI
by
Enable Watchdog Interrupt. This bit enables/disables the Watchdog interrupt. The Watchdog timer is enabled
the WDTCON (SFR FFH) and PDCON (SFR F1H) registers.
bit 4
0 = Disable the Watchdog Interrupt
1 = Enable Interrupt Request Generated by the Watchdog Timer
EX5
bit 3
External Interrupt 5 Enable. This bit enables/disables external interrupt 5.
0 = Disable External Interrupt 5
1 = Enable External Interrupt 5
EX4
bit 2
External Interrupt 4 Enable. This bit enables/disables external interrupt 4.
0 = Disable External Interrupt 4
1 = Enable External Interrupt 4
EX3
bit 1
External Interrupt 3 Enable. This bit enables/disables external interrupt 3.
0 = Disable External Interrupt 3
1 = Enable External Interrupt 3
EX2
bit 0
External Interrupt 2 Enable. This bit enables/disables external interrupt 2.
0 = Disable External Interrupt 2
1 = Enable External Interrupt 2
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Hardware Product Code Register 0 (HWPC0)
7
6
5
4
3
2
1
0
Reset Value
SFR E9H
HWPC0.7
HWPC0.6
HWPC0.5
HWPC0.4
HWPC0.3
1
MEMORY SIZE
0000_001xxB
HWPC0.7-0
Hardware Product Code LSB. Read-only.
MEMORY SIZE
MODEL
FLASH MEMORY
bits 7-0
0
0
1
1
0
1
0
1
MSC1212Y2
MSC1212Y3
MSC1212Y4
MSC1212Y5
4kB
8kB
16kB
32kB
Hardware Product Code Register 1 (HWPC1)
7
6
5
4
3
2
1
0
Reset Value
SFR EAH
1
08H
HWPC1.7-0
Hardware Product Code MSB. Read-only.
bits 7-0
Hardware Version Register (HDWVER)
7
6
5
4
3
2
1
0
Reset Value
SFR EBH
Flash Memory Control (FMCON)
7
6
5
4
3
2
1
0
Reset Value
SFR EEH
0
PGERA
0
FRCM
0
BUSY
1
0
02H
PGERA
bit 6
Page Erase. Available in both user and program modes.
0 = Disable Page Erase Mode
1 = Enable Page Erase Mode
FRCM
bit 4
Frequency Control Mode. The bypass is only used for slow clocks to save power.
0 = Bypass (default)
1 = Use Delay Line. Saves power (recommended).
BUSY
bit 2
Write/Erase BUSY Signal.
0 = Idle or Available
1 = Busy
Flash Memory Timing Control Register (FTCON)
7
6
5
4
3
2
1
0
Reset Value
SFR EFH
FER3
FER2
FER1
FER0
FWR3
FWR2
FWR1
FWR0
A5H
Refer to Flash Timing Characteristics
FER3-0
bits 7-4
Set Erase. Flash Erase Time = (1 + FER) • (MSEC + 1) • tCLK
11ms industrial temperature range.
.
5ms commercial temperature range.
FWR3-0
bits 3-0
Set Write. Flash Write Time = (1 + FWR) • (USEC + 1) • 5 • tCLK
30µs to 40µs.
.
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B Register (B)
7
6
5
4
3
2
1
0
Reset Value
SFR F0H
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
00H
B.7-0
B Register. This register serves as a second accumulator for certain arithmetic operations.
bits 7-0
Power-Down Control Register (PDCON)
7
6
5
4
3
2
1
0
Reset Value
SFR F1H
0
PDDAC
1
PDPWM
PDAD
PDWDT
PDST
PDSPI
7FH
Turning peripheral modules off puts the MSC1212 in the lowest power mode.
PDDAC
bit 6
Pulse Width Module Control.
0 = DACs On
1 = DACs Power Down
PDPWM
bit 4
Pulse Width Module Control.
0 = PWM On
1 = PWM Power Down
PDAD
ADC Control.
bit 3
0 = ADC On
1 = ADC, VREF, Summation registers, and Analog Brownout are powered down. Analog current = 0.
PDWDT
bit 2
Watchdog Timer Control.
0 = Watchdog Timer On
1 = Watchdog Timer Power Down
PDST
bit 1
System Timer Control.
0 = System Timer On
1 = System Timer Power Down
PDSPI
bit 0
SPI System Control.
0 = SPI System On
1 = SPI System Power Down
PSEN/ALE Select (PASEL)
7
6
5
4
3
2
1
0
Reset Value
SFR F2H
0
0
PSEN2
PSEN1
PSEN0
0
ALE1
ALE0
00H
PSEN2-0
PSEN Mode Select.
bits 5-3
PSEN2
PSEN1
PSEN0
0
0
1
1
1
0
1
0
1
1
X
X
X
0
PSEN
CLK
ADC MODCLK
LOW
1
HIGH
ALE1-0
ALE Mode Select.
bits 1-0
ALE1
ALE0
0
1
1
X
0
1
ALE
LOW
HIGH
NOTE: X = don’t care.
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Analog Clock (ACLK)
7
6
5
4
3
2
1
0
Reset Value
SFR F6H
0
FREQ6
FREQ5
FREQ4
FREQ3
FREQ2
FREQ1
FREQ0
03H
FREQ6-0
bits 6-0
Clock Frequency – 1. This value + 1 divides the system clock to create the ADC clock.
ACLK frequency = fCLK/(FREQ + 1)
fMOD = fCLK/(FREQ + 1)/64
Data Rate = fMOD/Decimation
System Reset Register (SRST)
7
6
5
4
3
2
1
0
Reset Value
SFR F7H
0
0
0
0
0
0
0
RSTREQ
00H
RSTREQ
Reset Request. Setting this bit to 1 and then clearing to 0 will generate a system reset.
bit 0
Extended Interrupt Priority (EIP)
7
6
5
4
3
2
1
0
Reset Value
SFR F8H
1
1
1
PWDI
PX5
PX4
PX3
PX2
E0H
PWDI
bit 4
Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt.
0 = The watchdog interrupt is low priority.
1 = The watchdog interrupt is high priority.
PX5
bit 3
External Interrupt 5 Priority. This bit controls the priority of external interrupt 5.
0 = External interrupt 5 is low priority.
1 = External interrupt 5 is high priority.
PX4
bit 2
External Interrupt 4 Priority. This bit controls the priority of external interrupt 4.
0 = External interrupt 4 is low priority.
1 = External interrupt 4 is high priority.
PX3
bit 1
External Interrupt 3 Priority. This bit controls the priority of external interrupt 3.
0 = External interrupt 3 is low priority.
1 = External interrupt 3 is high priority.
PX2
bit 0
External Interrupt 2 Priority. This bit controls the priority of external interrupt 2.
0 = External interrupt 2 is low priority.
1 = External interrupt 2 is high priority.
Seconds Timer Interrupt (SECINT)
7
6
5
4
3
2
1
0
Reset Value
SFR F9H
WRT
SECINT6
SECINT5
SECINT4
SECINT3
SECINT2
SECINT1
SECINT0
7FH
This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then that 1ms timer tick is divided by the register
HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate an interrupt
which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt. This Interrupt can be monitored
in the AIE register.
WRT
bit 7
Write Control. Determines whether to write the value immediately or wait until the current count is finished.
Read = 0.
0 = Delay Write Operation. The SEC value is loaded when the current count expires.
1 = Write Immediately. The counter is loaded once the CPU completes the write operation.
SECINT6-0 Seconds Count. Normal operation would use 100ms as the clock interval.
bits 6-0
Seconds Interrupt = (1 + SEC) • (HMSEC + 1) • (MSEC + 1) • tCLK.
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Milliseconds Interrupt (MSINT)
7
6
5
4
3
2
1
0
Reset Value
SFR FAH
WRT
MSINT6
MSINT5
MSINT4
MSINT3
MSINT2
MSINT1
MSINT0
7FH
The clock used for this timer is the 1ms clock which results from dividing the system clock by the values in registers MSECH:MSECL.
Reading this register will clear the interrupt.
WRT
bit 7
Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0.
0 = Delay Write Operation. The MSINT value is loaded when the current count expires.
1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.
MSINT6-0 Seconds Count. Normal operation would use 1ms as the clock interval.
bits 6-0 MS Interrupt Interval = (1 + MSINT) • (MSEC + 1) • tCLK
One Microsecond Register (USEC)
7
6
5
4
3
2
1
0
Reset Value
SFR FBH
0
0
0
FREQ4
FREQ3
FREQ2
FREQ1
FREQ0
03H
FREQ4-0
Clock Frequency – 1. This value + 1 divides the system clock to create a 1µs Clock.
bits 4-0
USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFH).
One Millisecond Low Register (MSECL)
7
6
5
4
3
2
1
0
Reset Value
SFR FCH
MSECL7
MSECL6
MSECL5
MSECL4
MSECL3
MSECL2
MSECL1
MSECL0
9FH
MSECL7-0 One Millisecond Low. This value in combination with the next register is used to create a 1ms Clock.
bits 7-0 1ms Clock = (MSECH • 256 + MSECL + 1) • tCLK. This clock is used to set Flash erase time. See FTCON (SFR EFH).
One Millisecond High Register (MSECH)
7
6
5
4
3
2
1
0
Reset Value
SFR FDH
MSECH7
MSECH6
MSECH5
MSECH4
MSECH3
MSECH2
MSECH1
MSECH0
0FH
MSECH7-0 One Millisecond High. This value in combination with the previous register is used to create a 1ms clock.
bits 7-0 1ms = (MSECH • 256 + MSECL + 1) • tCLK
.
One Hundred Millisecond Register (HMSEC)
7
6
5
4
3
2
1
0
Reset Value
SFR FEH
HMSEC7
HMSEC6
HMSEC5
HMSEC4
HMSEC3
HMSEC2
HMSEC1
HMSEC0
63H
HMSEC7-0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock.
bits 7-0 100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • tCLK
.
Watchdog Timer Register (WDTCON)
7
6
5
4
3
2
1
0
Reset Value
SFR FFH
EWDT
DWDT
RWDT
WDCNT4
WDCNT3
WDCNT2
WDCNT1
WDCNT0
00H
EWDT
Enable Watchdog (R/W).
bit 7
Write 1/Write 0 sequence sets the Watchdog Enable Counting bit.
DWDT
Disable Watchdog (R/W).
bit 6
Write 1/Write 0 sequence clears the Watchdog Enable Counting bit.
RWDT
Reset Watchdog (R/W).
bit 5
Write 1/Write 0 sequence restarts the Watchdog Counter.
WDCNT4-0
Watchdog Count (R/W).
bits 4-0
Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There
is an uncertainty of 1 count.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Dec-2004
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
Drawing
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
MSC1212Y2PAGR
MSC1212Y2PAGT
MSC1212Y3PAGR
MSC1212Y3PAGT
MSC1212Y4PAGR
MSC1212Y4PAGT
MSC1212Y5PAGR
MSC1212Y5PAGT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
64
64
64
64
64
64
64
64
1500
250
None
None
None
None
None
None
None
None
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
Call TI
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Call TI
1500
250
1500
250
2000
250
CU SNPB
CU SNPB
Level-3-235C-168 HR
Level-3-235C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
M
0,08
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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Copyright 2004, Texas Instruments Incorporated
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