MPC100AU [BB]
Wide Bandwidth 4 x 1 VIDEO MULTIPLEXER; 宽带宽4× 1视频多路复用器
| 型号： | MPC100AU |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Wide Bandwidth 4 x 1 VIDEO MULTIPLEXER |
| 文件： | 总15页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC100
®
MPC100
MPC100
Wide Bandwidth
4 x 1 VIDEO MULTIPLEXER
The MPC100 consists of four identical monolithic inte-
grated open-loop buffer amplifiers, which are con-
nected internally at the output. The unidirectional trans-
mission path consists of bipolar complementary buffers,
which offer extremely high output-to-input isolation.
The MPC100 multiplexer enables one of the four input
channels to connect to the output. The output of the
multiplexer is in a high-impedance state when no chan-
nel is selected. When one channel is selected with a
digital “1” at the corresponding SEL-input, the compo-
nent acts as a buffer with high input impedance and low
output impedance.
FEATURES
● BANDWIDTH: 250MHz (1.4Vp-p)
● LOW INTERCHANNEL CROSSTALK:
≤60dB (30MHz, DIP); ≤70dB (30MHz, SO)
● LOW SWITCHING TRANSIENTS:
+2.5/–1.2mV
● LOW DIFFERENTIAL GAIN/PHASE
ERRORS: 0.05%, 0.01°
● LOW QUIESCENT CURRENT:
One Channel Selected: ±4.6mA
No Channel Selected: ±230µA
The wide bandwidth of over 250MHz at 1.4Vp-p
signal level, high linearity and low distortion, and low
input voltage noise of 4nV/√Hz make this crosspoint
switch suitable for RF and video applications. All
performance is specified with ±5V supply voltage,
which reduces power consumption in comparison with
±15V designs. The multiplexer is available in space-
saving SO-14 and DIP packages. Both are designed
and specified for operation over the industrial tem-
perature range (–40°C to +85°C.)
APPLICATIONS
● VIDEO ROUTING AND MULTIPLEXING
(CROSSPOINTS)
● RADAR SYSTEMS
● DATA ACQUISITION
● INFORMATION TERMINALS
● SATELLITE OR RADIO LINK IF ROUTING
IN1
DB1
DESCRIPTION
IN2
DB2
The MPC100 is a very wide bandwidth 4-to-1 channel
video signal multiplexer which can be used in a wide
variety of applications.
VOUT
IN3
DB3
IN4
DB4
MPC100 is designed for wide-bandwidth systems,
including high-definition television and broadcast
equipment. Although it is primarily used to route
video signals, the harmonic and dynamic attributes of
the MPC100 make it appropriate for other analog
signal routing applications such as radar, communica-
tions, computer graphics, and data acquisition sys-
tems.
SEL1 SEL2 SEL3 SEL4
TRUTH TABLE
SEL1
SEL2
SEL3
SEL4
VOUT
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
HI-Z
IN1
IN2
IN3
IN4
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111
•
Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1991 Burr-Brown Corporation
PDS-1133F
Printed in U.S.A. March, 1995
SPECIFICATIONS
At VCC = ±5V, RL = 10kΩ, RSOURCE = 50Ω, and TA = +25°C, unless otherwise noted.
MPC100AP, AU
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
DC CHARACTERISTICS
INPUT OFFSET VOLTAGE
Initial
vs Temperature
vs Supply (Tracking)
vs Supply (Non-tracking)
vs Supply (Non-tracking)
Initial Matching
RIN = 0, RSOURCE = 0
+10
±30
–80
–50
–50
±3
±30
mV
µV/°C
dB
dB
dB
VCC = ±4.5V to ±5.5V
VCC = +4.5V to +5.5V
VCC = –4.5V to –5.5V
–40
Between the Four Channels
mV
INPUT BIAS CURRENT
Initial
vs Temperature
vs Supply (Tracking)
vs Supply (Non-tracking)
vs Supply (Non-tracking)
+4
20
±380
+1.0
–11.0
±10
µA
nA/°C
nA/V
µA/V
µA/V
VCC = ±4.5V to ±5.5V
VCC = +4.5V to +5.5V
VCC = –4.5V to –5.5V
INPUT IMPEDANCE
Resistance
Capacitance
Channel On
Channel On
Channel Off
0.88
1.0
1.0
MΩ
pF
pF
Capacitance
INPUT NOISE
Voltage Noise Density
Signal-to-Noise Ratio
fB = 20kHz to 10MHz
S/N = 0.7/VN • √5MHz
4.0
98
nV/√Hz
dB
INPUT VOLTAGE RANGE
Gain Error ≤ 10%
±4.2
V
TRANSFER CHARACTERISTICS
Voltage Gain
RL = 1kΩ, VIN = ±2V
RL = 10kΩ, VIN = ±2.8V
0.982
0.992
V/V
V/V
0.98
CHANNEL SELECTION INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
+2.0
0
VCC
+0.8
150
5
V
V
µA
µA
VSEL = 5.0V
VSEL = 0.8V
100
0.002
SWITCHING CHARACTERISTICS
SEL to Channel ON Time
SEL to Channel OFF Time
Switching Transient, Positive
Switching Transient, Negative
VI = –0.3V to +0.7V, f = 5MHz
90% Point of VO = 1Vp-p
10% Point of VO = 1Vp-p
Measured While Switching
Between Two Grounded Channels
0.25
0.25
+2.5
–1.2
µs
µs
mV
mV
OUTPUT
Voltage
VIN = ±3V, RL = 5kΩ
One Channel Selected
No Channel Selected
No Channel Selected
±2.8
±4.5
±2.98
11
900
1.5
V
Ω
MΩ
pF
Resistance
Resistance
Capacitance
POWER SUPPLY
Rated Voltage
Derated Performance
Quiescent Current
±5
V
V
mA
µA
±5.5
±5
±350
One Channel Selected
No Channel Selected
±4.6
±230
TEMPERATURE RANGE
Operating, AP, AU
Storage, AP, AU
–40
–40
+85
+125
°C
°C
Thermal Resistance, θJA
AP, AU
90
°C/W
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
MPC100
SPECIFICATIONS
At VCC = ±5V, RL = 10kΩ, RSOURCE = 50Ω, and TA = +25°C, unless otherwise noted.
MPC100AP, AU
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
AC CHARACTERISTICS
FREQUENCY DOMAIN
LARGE SIGNAL BANDWIDTH (–3dB)
VO = 5.0Vp-p, COUT = 1pF
VO = 2.8Vp-p, COUT = 1pF
VO = 1.4Vp-p, COUT = 1pF
70
140
250
MHz
MHz
MHz
SMALL SIGNAL BANDWIDTH
GROUP DELAY TIME
VO = 0.2Vp-p, COUT = 1pF
450
450
MHz
ps
DIFFERENTIAL GAIN
f = 4.43MHz, VIN = 0.3Vp-p
VDC = 0 to 0.7V
0.05
0.06
%
%
VDC = 0 to 1.4V
DIFFERENTIAL PHASE
f = 4.43MHz, VIN = 0.3Vp-p
VDC = 0 to 0.7V
0.01
0.02
Degrees
Degrees
VDC = 0 to 1.4V
GAIN FLATNESS PEAKING
VO = 0.2Vp-p, DC to 30MHz
VO = 0.2Vp-p, DC to 100MHz
0.04
0.05
dB
dB
HARMONIC DISTORTION
Second Harmonic
Third Harmonic
f = 30MHz, VO = 1.4Vp-p, RL = 1kΩ
–53
–67
dBc
dBc
CROSSTALK
MPC100AP All Hostile
VI = 1.4Vp-p, Figures 4 and 8
f = 5MHz,
–82
–60
–70
–71
–78
–70
–75
–76
dB
dB
dB
dB
dB
dB
dB
dB
f = 30MHz,
f = 5MHz,
f = 30MHz,
f = 5MHz,
f = 30MHz,
f = 5MHz,
f = 30MHz
Off Isolation
MPC100AU All Hostile
Off Isolation
TIME DOMAIN
RISE TIME
VO = 1.4Vp-p, Step 10% to 90%
COUT = 1pF, ROUT = 22Ω
3.3
ns
SLEW RATE
VO = 2Vp-p
COUT = 1pF
COUT = 22pF
COUT = 47pF
650
460
320
V/µs
V/µs
V/µs
®
3
MPC100
CONNECTION DIAGRAM
FUNCTIONAL DESCRIPTION
Top View
DIP/SO-14
IN1-IN4
GND
Four analog input channels
Analog input shielding grounds, connect to system ground
SEL1 - SEL4 Channel selection inputs
DB1
DB2
DB3
IN1
GND
IN2
1
2
3
4
5
6
7
14 SEL1
13 SEL2
12 –VCC
11 VOUT
10 +VCC
VOUT
–VCC
+VCC
Analog output; tracks selected channel
Negative supply voltage; typical –5VDC
Positive supply voltage; typical +5VDC
GND
IN3
ELECTROSTATIC
DISCHARGE SENSITIVITY
GND
IN4
9
8
SEL3
SEL4
DB4
Electrostatic discharge can cause damage ranging from per-
formancedegradationtocompletedevicefailure.Burr-Brown
Corporationrecommendsthatallintegratedcircuitsbehandled
and stored using appropriate ESD protection methods.
MPC100
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published speci-
fications.
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage (±VCC) .............................................................. ±6V
Analog Input Voltage (IN1 through IN4)(1) ................................ ±VCC, ±0.7V
Logic Input Voltage ................................................... –0.6V to +VCC +0.6V
Operating Temperature ..................................................... –40°C to +85°C
Storage Temperature ...................................................... –40°C to +125°C
Output Current .................................................................................. ±6mA
Junction Temperature .................................................................... +175°C
Lead Temperature (soldering, 10s)................................................ +300°C
Digital Input Voltages (SEL1 through SEL4)(1) ........... –0.5V to +VCC +0.7V
NOTE: (1) Inputs are internally diode-clamped to ±VCC
.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER(1)
TEMPERATURE
PRODUCT
RANGE
PACKAGE
MPC100AP
MPC100AU
–40°C to +85°C
–40°C to +85°C
14-Pin Plastic DIP
SO-14 Surface Mount
010
235
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
®
4
MPC100
TYPICAL PERFORMANCE CURVES
At VCC = ±5V, RLOAD = 10kΩ, RSOURCE = 50Ω, and TA = +25°C, unless otherwise noted.
OFFSET VOLTAGE vs TEMPERATURE
5
INPUT BIAS CURRENT vs TEMPERATURE
5
4
4
3
3
2
2
1
1
0
0
–1
–2
–3
–1
–2
–3
–4
–5
–4
–5
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
INPUT IMPEDANCE vs FREQUENCY
OUTPUT IMPEDANCE vs FREQUENCY
1.0M
100
30
100k
10k
10
1k
3
1
100
10k
100k
1M
10M
100M
1G
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
TOTAL QUIESCENT CURRENT vs TEMPERATURE
One Channel Selected
TOTAL QUIESCENT CURRENT vs TEMPERATURE
No Channel Selected
9
8
7
6
5
4
3
2
300
250
200
150
100
50
0
1
0
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
®
5
MPC100
TYPICAL PERFORMANCE CURVES (CONT)
At VCC = ±5V, RLOAD = 10kΩ, RSOURCE = 50Ω, and TA = +25°C, unless otherwise noted.
TRANSFER FUNCTION
INPUT VOLTAGE NOISE SPECTRAL DENSITY
100
10
5
4
3
2
1
0
–1
–2
–3
1
–4
–5
0.1
–5
–4
–3
–2
–1
0
1
2
3
4
5
100
1k
10k
100k
1M
10M
100M
Input Voltage (V)
Frequency (Hz)
SWITCHING ENVELOPE (Video Signal)
SWITCHING TRANSIENTS (Channel To Channel)
12
10
8
5V
SEL1
+0.7V
Without bandwidth
limiting lowpass filter.
6
SEL2
4
5V
2
0V
0
–0.3V
–2
–4
Time (µs)
0
20
40
60
80 100 120 140 160 180 200
Time (ns)
SMALL SIGNAL PULSE RESPONSE
SWITCHING TRANSIENTS (Channel To Channel)
5V
SEL1
36MHz Low pass filter acc.
Eureka Rec. EU95-PG03
in the signal path.
SEL2
0 —
5V
–4
Time (ns)
0
20
40
60
80 100 120 140 160 180 200
Time (ns)
COUT = 1pF, tRISE = tFALL = 2ns
(Generator) VI = 0.2Vp-p
®
6
MPC100
TYPICAL PERFORMANCE CURVES (CONT)
At VCC = ±5VDC, RLOAD = 10kΩ, RSOURCE = 50Ω, and TA = +25°C, unless otherwise noted.
SMALL SIGNAL PULSE RESPONSE
LARGE SIGNAL PULSE RESPONSE
0 —
0 —
Time (ns)
Time (ns)
COUT = 47pF, tRISE = tFALL = 2ns
(Generator) VI = 0.2Vp-p
COUT = 1pF, tRISE = tFALL = 5ns
(Generator) VI = 5Vp-p
LARGE SIGNAL PULSE RESPONSE
2.5
GROUP DELAY TIME vs FREQUENCY
2
1.5
1
0.5
Group Delay Time
0 —
0
ROUT
50Ω
RI
150Ω
–0.5
–1
VI
DUT
Out
VOUT
300mVPO
=
–1.5
–2
–2.5
Time (ns)
1M
10M
100M
500M
COUT = 47pF, tRISE = tFALL = 5ns
Frequency (Hz)
(Generator) VI = 5Vp-p
BANDWIDTH vs COUT WITH RECOMMENDED ROUT
GAIN FLATNESS
0.5
0.4
20
15
0.3
10
5
0.2
0
0.1
1pF
0.2Vp-p
COUT ROUT
f–3dB
–5
0
1p 0Ω 500MHz
–10
–15
–20
–0.1
–0.2
–0.3
10pF
22pF
10p 22Ω 340MHz
22p 15Ω 250MHz
RIN = 150Ω, RO1 = 1kΩ
33p
47p
12Ω 215MHz
10Ω 130MHz
33pF
47pF
COUT = 22pF, ROUT = 15Ω
–25
dB
–0.4
–0.5
1M
10M
100M
1G
300k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
®
7
MPC100
TYPICAL PERFORMANCE CURVES (CONT)
At VCC = ±5V, RLOAD = 10kΩ, RSOURCE = 50Ω, and TA = +25°C, unless otherwise noted.
BANDWIDTH vs RLOAD
BANDWIDTH vs OUTPUT VOLTAGE
20
15
20
15
5Vp-p
2.8Vp-p
1.4Vp-p
10
10
5
5
0
0
0.6Vp-p
0.2Vp-p
–5
–5
–10
–15
–20
–10
–15
–20
C
OUT = 1pF, ROUT = 0Ω
RIN = 150Ω
C
OUT = 22pF, ROUT = 15Ω, VO = 2.8Vp-p
RL = 500Ω = 1kΩ = 10kΩ
–25
dB
–25
dB
300k
1M
10M
100M
1G
300k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
30MHz HARMONIC DISTORTION
BANDWIDTH MATCHING (DB1...DB4)
2.8Vp-p
20
15
10
5
0
–5
–10
–15
–20
–25
dB
COUT = 22pF, ROUT = 15Ω
Frequency (Hz)
OUT = 2.8Vp-p, RL = 1kΩ, COUT = 1pF
V
300k 1M
10M
100M
1G
Frequency (Hz)
30MHz HARMONIC DISTORTION
Frequency (Hz)
VOUT = 2.8Vp-p, RL = 10kΩ, COUT = 1pF
®
8
MPC100
emitter followers applies no feedback, so their low fre-
quency gain is slightly less than unity and somewhat depen-
dent on loading. Unlike devices using MOS bilateral switch-
ing elements, the bipolar complementary buffers form an
unidirectional transmission path and thus provide high out-
put-to-input isolation. Switching stages compatible to TTL
level digital signals are provided for each buffer to select the
input channel. When no channel is selected, the output of the
device is high-impedance and allows the user to wire more
MPC100s together to form switch multi-channel matrices.
APPLICATIONS INFORMATION
The MPC100 operates from ±5V power supplies (±6V
maximum). Do not attempt to operate with larger power
supply voltages or permanent damage may occur. The buffer
outputs are not current-limited or protected. If the output is
shorted to ground, currents up to 18mA could flow. Momen-
tary shorts to ground (a few seconds) should be avoided, but
are unlikely to cause permanent damage.
INPUT PROTECTION
If one channel is selected with a digital “1” at the corre-
sponding SEL-input, the MPC100 acts as a buffer amplifier
with high input impedance and low output impedance. The
truth table on the front page describes the relationship
between the digital inputs (SEL1 to SEL4) and the analog
inputs (IN1 to IN4), and which signal is selected at the
output.
All pins on the MPC100 are internally protected from ESD
by means of a pair of back-to-back reverse-biased diodes to
either power supply as shown in Figure 1. These diodes will
begin to conduct when the input voltage exceeds either
power supply by about 0.7V. This situation can occur with
loss of the amplifier’s power supplies while a signal source
is still present. The diodes can typically withstand a continu-
ous current of 30mA without destruction. To insure long
term reliability, however, diode current should be externally
limited to 10mA or less whenever possible.
The 2-4 address decoder and chip select logic is not
integrated. The selected design increases the flexibility of
address decoding in complex distribution fields, eases
BUS-controlled channel selection, simplifies channel se-
lection monitoring for the user, and lowers transient peaks.
All of these characteristics make the multiplexer, in effect,
a quad switchable high-speed buffer. It requires DC cou-
pling and termination resistors when directly driven from
a low impedance cable. High-current output amplifiers are
recommended when driving low-impedance transmission
lines or inputs.
The internal protection diodes are designed to withstand
2.5kV (using Human Body Model) and will provide ad-
equate ESD protection for most normal handling proce-
dures. However, static damage can cause subtle changes in
amplifier input characteristics without necessarily destroy-
ing the device. In precision buffer amplifiers, this may cause
a noticeable degradation of offset voltage and drift. There-
fore, static protection is strongly recommended when han-
dling the MPC100.
An advanced complementary bipolar process, consisting of
pn-junction isolated high-frequency NPN and PNP transis-
tors, provides wide bandwidth while maintaining low
crosstalk and harmonic distortion. The single chip band-
width of over 250MHz at an output voltage of 1.4Vp-p
allows the design of large crosspoint or distribution fields
in HDTV-quality with an overall system bandwidth of
36MHz. The buffer amplifiers also offer low differential
gain (0.05%) and phase (0.01°) errors. These parameters
are essential for video applications and demonstrate how
well the signal path maintains a constant small-signal gain
and phase for the low-level color subcarrier at 4.43MHz
(PAL) or 3.58MHz (NSTC) as the brightness (luminance)
signal is ramped through its specified range. The bipolar
construction also ensures that the input impedance remains
high and constant between ON and OFF states. The ON/
OFF input capacitance ratio is near unity, and does not vary
with power supply voltage variations. The low output
capacitance of 1.5pF when no channel is selected is a very
important parameter for large distribution fields. Each par-
allel output capacitance is an additional load and reduces
the overall system bandwidth.
Static damage has been well recognized for MOSFET de-
vices, but any semiconductor device deserves protection
from this potentially damaging source. The MPC100 incor-
porates on-chip ESD protection diodes as shown in Figure 1.
This eliminates the need for the user to add external protec-
tion diodes, performance.
ESD Protection diodes
+VCC
internally connected to all pins.
External Pin
Internal Circuitry
–VCC
FIGURE 1. Internal ESD Protection.
DISCUSSION
OF PERFORMANCE
The MPC100 video multiplexer allows the user to connect
any one of four analog input channels (IN1-IN4) to the output
of the component and to switch between channels within
less than 0.5µs. It consists of four identical unity-gain buffer
amplifiers, which are connected together internally at the
output. The open loop buffers consisting of complementary
Bipolar video crosspoint switches are virtually glitch-free
when compared to signal switches using CMOS or DMOS
devices. The MPC100 operates with a fast make-before-
break switching action to keep the output switching tran-
sients small and short. Switching from one channel to
another causes the signal to mix at the output for a short
time, but it interferes only minimally with the input signals.
®
9
MPC100
The transient peaks remain less than +2.5mV and –1.2mV.
Subsequent equipment might interpret large negative output
glitches as synchronization pulses. To remove this problem,
the output must be clamped during the switching dead time.
With the MPC100, the generated output transients are ex-
tremely small and clamping is unnecessary. The switching
time between two channels is less than 0.5µs. This short
time period allows easy switching during the vertical blank-
ing time. The signal envelope during the transition from one
channel to another rises and falls symmetrically and shows
less overshooting or DC settling transients.
• Bypass power supplies very close to the device pins. Use
tantalum chip capacitors (approximately 2.2µF), a parallel
470pF ceramic chip capacitor may be added if desired.
Surface-mount types are recommended due to their low
lead inductance.
• PC board traces for signal and power lines should be wide
to reduce impedance or inductance.
• Make short and low inductance traces. The entire physical
circuit layout should be as small as possible.
• Use a low-impedance ground plane on the component side
to ensure that low-impedance ground is available through-
out the layout. Grounded traces between the input traces
are essential to achieve high interchannel crosstalk rejec-
tion. Refer to the suggested layout shown in Figure 6.
Power consumption is a serious problem when designing
large crosspoint fields with high component density. Most of
the buffers are always in off-state. One important design
goal was to attain low off-state quiescent current when no
channel is selected. The low supply current of ±230µA in
off-state and ±4.6mA when one channel is selected, as well
as the reduced ±5V supply voltage, conserves power, simpli-
fies the power supply design, and results in cooler, more
reliable operation.
• Do not extend the ground plane under high-impedance
nodes sensitive to stray capacitances, such as the buffer’s
input terminals.
• Sockets are not recommended because they add signifi-
cant inductance and parasitic capacitance. If sockets are
required, use zero-profile solderless sockets.
CIRCUIT LAYOUT
• Use low-inductance and surface-mounted components to
achieve the best AC-performance.
The high-frequency performance of the MPC100 can be
greatly affected by the physical layout of the circuit. The
following tips are offered as suggestions, not as absolutes.
Oscillations, ringing, poor bandwidth and settling, higher
crosstalk, and peaking are all typical problems which plague
high-speed components when they are used incorrectly.
• A resistor (100Ω to 200Ω) in series with the input of the
buffers may help to reduce peaking. Place the resistor as
close as possible to the pin.
• Plug-in prototype boards and wire-wrap boards will not
function well. A clean layout using RF techniques is
essential.
SEL1
(14)
IN1
(1)
DB1
GND
(2)
+VCC = +5V
(10)
SEL2
(13)
IN2
(3)
VOUT
(11)
DB2
(12)
–VCC = –5V
SEL3
GND
(4)
(9)
IN3
DB3
DB4
(5)
SEL1
(8)
GND
(6)
IN4
(7)
NOTE: DB = Diamond Buffer
FIGURE 2. Simplified Circuit Diagram.
®
10
MPC100
10
0
150Ω
DB1
DB2
DB3
DB4
IN1
GND
SEL1
SEL2
SEL3
SEL4
0
0
1
0
–10
–20
–30
–40
–50
–60
–70
50Ω
150Ω
IN2
VI
15Ω
180Ω
50Ω
50Ω
50Ω
GND
IN3
BUF601
VO
22pF
VO
VI
Crosstalk = 20log
VI = 1.4Vp-p
MPC100AP
MPC100AU
GND
150Ω
–80
–90
IN3 is connected to GND
IN4
MPC100
1M
10M
100M 300M
Frequency (Hz)
FIGURE 3. Channel Crosstalk—Grounded Input.
10
0
150Ω
DB1
IN1
SEL1
SEL2
SEL3
SEL4
0
0
1
0
–10
–20
–30
–40
–50
–60
–70
GND
MPC100AP
MPC100AU
50Ω
150Ω
200Ω
VI
IN2
DB2
DB3
DB4
15Ω
180Ω
50Ω
50Ω
50Ω
GND
IN3
BUF601
VO
22pF
VO
VI
Crosstalk = 20log
VI = 1.4Vp-p
GND
150Ω
–80
–90
IN3 is connected with 150Ω + 50Ω to GND
IN4
MPC100
1M
10M
100M 300M
Frequency (Hz)
FIGURE 4. Channel Crosstalk—150Ω Input Resistor.
10
0
150Ω
DB1
IN1
SEL1
SEL2
SEL3
SEL4
0
0
0
0
–10
–20
–30
–40
–50
–60
–70
GND
IN2
MPC100AU
50Ω
150Ω
150Ω
VI
DB2
DB3
DB4
180Ω
50Ω
50Ω
50Ω
GND
IN3
BUF601
VO
VO
VI
Crosstalk = 20log
VI = 1.4Vp-p
GND
–80
–90
MPC100AP
100M 300M
150Ω
IN4
1M
10M
MPC100
Frequency (Hz)
FIGURE 5. Off Isolation.
®
11
MPC100
2.2µ
470p
–5V
IN13
75Ω
75Ω
75Ω
75Ω
150Ω
150Ω
150Ω
150Ω
1
14
13
2
3
12
11
10
9
22Ω
4
5
6
7
IN16
8
MPC100
2.2µ
470p
2.2µ
470p
+5V
0.1µF
16
VCC
15
14
13
12
11
10
9
1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A0
A0
A1
A3
CS
2
A1
IN13
3
75Ω
75Ω
75Ω
75Ω
150Ω
150Ω
150Ω
150Ω
A3
1
14
74HC
237
6
CS1
13
2
3
5
4
CS2
+5V
12
11
10
9
22Ω
4
5
6
7
7
LE
GND
IN16
8
MPC100
2.2µ
470p
2.2µ
470p
IN13
75Ω
75Ω
75Ω
75Ω
150Ω
150Ω
150Ω
150Ω
1
14
13
2
3
+5V
0.1µF
12
11
10
9
16
VCC
22Ω
4
5
6
7
15
14
13
12
11
10
9
1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A0
2
A1
3
A2
74HC
237
5
CS2
IN16
6
4
CS1
8
MPC100
7
2.2µ
LE
GND
470p
2.2µ
470p
IN13
75Ω
75Ω
75Ω
75Ω
150Ω
150Ω
150Ω
150Ω
1
14
+5V
13
2
3
2.2µ
12
11
10
9
10n
6
22Ω
150Ω
4
5
6
7
3
2
7
+
75Ω
OPA623
Out
–5V
10n
4
–
220Ω
2.2µ
220Ω
IN16
8
MPC100
2.2µ
470p
+5V
FIGURE 6. Video Distribution Field.
®
12
MPC100
+5V
2.2µ
+5V
0.1µ
470p
10
4
8
5
BUF600
+5V
LE GND CS2
14
13
9
15 Y0
14 Y1
13 Y2
12 Y3
1
2
3
5
A0
A1
In
1
5
180Ω
150Ω
150Ω
150Ω
150Ω
4
8
1
74HC
237
+1
DB1
–5V
A2
CS1
2
3
75Ω
75Ω
8
150Ω
DB2
DB3
DB4
+5V
150Ω
11
4
5
6
7
3
+
7
Out
75Ω
150Ω
75Ω
6
OPA623
R-2R
Ladder
Network
2
4
–
–5V
390Ω
75Ω
75Ω
390 Ω
MPC100
12
2.2µ
CS
0
A1
0
A0
GAIN SEL1
2
0
1
0
0
0
3
0
0
1
0
0
4
0
0
0
1
0
0
1
0
1
X
2
1
1
0
0
0
0
0
0
470p
–5V
0
1
0.5
0.25
0
0
1
1
X
FIGURE 7. Digital Gain Control.
+5V
0.1µ
16
V
4
8
5
+5V
LE GND CS2
CC
15 Y0
14 Y1
13 Y2
12 Y3
1
2
3
5
A0
A1
2.2µ
470p
10
A2
CS1
14
13
9
In1
In2
In3
In4
150Ω
150Ω
150Ω
150Ω
1
DB1
50Ω
50Ω
50Ω
50Ω
2
3
8
DB2
DB3
DB4
12 Bit
10MHz
A/D Converter
+5V
7
150Ω
11
4
5
6
7
3
+
6
Signal
Input
OPA620
2
–
4
–5V
220Ω
220Ω
ADS804
MPC100
12
2.2µ
470p
–5V
FIGURE 8. High Speed Data Acquisition System.
®
13
MPC100
150Ω
150Ω
150Ω
150Ω
1
R
DB1
DB2
DB3
–5V
2.2µ
+5V
2.2µ
2
3
CH1
G
B
470p
10n
6
12
11
10
150Ω
7
4
5
6
7
3
2
+
75Ω
R
OPA623
75Ω
2.2µ
–
4
390Ω
470p
2.2µ
10n
390Ω
+5V
DB4
–5V
MPC100
9
10 13 14
150Ω
150Ω
150Ω
150Ω
1
DB1
DB2
DB3
R
–5V
2.2µ
+5V
2.2µ
2
3
CH2
G
B
470p
10n
12
11
10
150Ω
7
4
5
6
7
3
+
75Ω
6
G
OPA623
75Ω
2
2.2µ
–
4
390Ω
2.2µ
470p
390Ω
10n
+5V
DB4
–5V
5
MPC100
+5V
9
10 13 14
R
16
CS
CS1 VCC
A0
15 Y0
1
2
3
4
A0
A1
CH3
G
B
74HC
237
14 Y1
13 Y2
12 Y3
A1
A9
LE
CS2 GND
75Ω
5
8
9
10 13 14
150Ω
150Ω
150Ω
150Ω
1
DB1
–5V
2.2µ
+5V
2.2µ
2
3
470p
10n
12
11
10
DB2
DB3
150Ω
7
4
5
6
7
3
2
R
+
75Ω
6
B
OPA623
2.2µ
–
4
CH4
G
B
390Ω
2.2µ
10n
470p
390Ω
+5V
DB4
–5V
75Ω
MPC100
FIGURE 9. Distribution Field for High Resolution Graphic Cards, Cameras.
®
14
MPC100
Out
RO1
RO1
RI
150Ω
RB
51Ω
400MHz
Scope
ROUT
50Ω
50Ω
VO
VI
In
DUT
+1
BOUT
RIN
=
RIN =
50Ω
50Ω
50Ω
COUT
DB1 to DB4
BUF601
Pulse
Generator
FIGURE 10. Test Circuit Pulse Response.
MPC100
OPA623
VIN
150Ω
150Ω
75Ω
Generator
Video
Analyzer
4
3
+
–
75Ω
DUT
75Ω
8
RIN
=
75Ω
RIN
=
75Ω
10kΩ
75Ω
390Ω
DB1 to DB4
4.43MHz
390Ω
VDC
FIGURE 11. Test Circuit Differential Gain and Phase.
Out
RO1
RO1
RI
150Ω
RB
51Ω
Spectrum
Analyzer
ROUT
50Ω
50Ω
VO
VI
Generator
In
DUT
+1
BOUT
RIN
=
RIN =
50Ω
50Ω
50Ω
COUT
DB1 to DB4
BUF601
FIGURE 12. Test Circuit Frequency Response.
MPC100
SEL Inputs
MPC100
SEL Inputs
MPC100
SEL Inputs
MPC100
SEL Inputs
MPC100
SEL Inputs
MPC100
SEL Inputs
1
4
3
5
5
6
7
7
1
3
5
7
1
3
5
7
7
1
3
5
7
1
4
3
5
5
6
7
7
1
3
5
7
14 13 12 11
4
5
6
14 13 12 11
14 13 12 11
Parallel Out
HC4094
Parallel Out
HC4094
Parallel Out
HC4094
2
3
2
3
2
3
SER
Out
SER
Out
SER
Out
SER In
D
• • •
3
1
15
3
1
15
3
1
15
Clock
STR
OE
FIGURE 13. Serial Bus-Controlled Distribution Field.
®
15
MPC100
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