ADS1250U [BB]
20-Bit Data Acquisition System ANALOG-TO-DIGITAL CONVERTER; 20位数据采集系统的模拟数字转换器
| 型号： | ADS1250U |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 20-Bit Data Acquisition System ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总20页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ADS1250
ADS1250
For most current data sheet and other product
information, visit www.burr-brown.com
20-Bit Data Acquisition System
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
The ADS1250 is a precision, wide dynamic range,
delta-sigma, analog-to-digital converter with 20-bit
resolution operating from a single +5V supply. The
delta-sigma architecture is used for wide dynamic
range and to guarantee 20 bits of no missing code
performance. An effective resolution of 18 bits (2.8ppm
of rms noise) is achieved for conversion rates up to
25kHz. The dynamic range of the converter is further
increased by providing a low-noise Programmable
Gain Amplifier (PGA) with gain stages of 1, 2, 4, or
8 for low level input signals.
● 20 BITS NO MISSING CODES
● 18 BITS EFFECTIVE RESOLUTION UP TO
25kHz DATA RATE
● LOW NOISE: 2.8ppm at PGA = 1
● DIFFERENTIAL INPUTS
● INL: 0.002% (MAX)
● PROGRAMMABLE FULL SCALE
● I/O CONTROLLED PGA: 1, 2, 4, 8
● EXTERNAL REFERENCE
The ADS1250 is designed for high-resolution mea-
surement applications in cardiac diagnostics, smart
transmitters, industrial process control, weigh scales,
chromatography and portable instrumentation. The
converter includes a flexible synchronous serial inter-
face and offers a three-wire control mode for low-cost
isolation.
APPLICATIONS
● CARDIAC DIAGNOSTICS
● DIRECT THERMOCOUPLE INTERFACE
● BLOOD ANALYSIS
The ADS1250 is a single-channel converter and is
offered in an SOL-16 package.
● INFRARED PYROMETER
● LIQUID/GAS CHROMATOGRAPHY
● PRECISION PROCESS CONTROL
G0
G1
VREF
CLK
+
SCLK
+VIN
4th-Order
∆Σ
Modulator
Digital
Filter
Serial
Output
DRDY
PGA
–VIN
–
DOUT
+VS
AGND
DSYNC
CS
Control
+VD
DGND
ADS1250
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
• Tel: (520) 746-1111
Twx: 910-952-1111
•
Internet: http://www.burr-brown.com/
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
•
©1999 Burr-Brown Corporation
PDS-1520B
Printed in U.S.A. December, 1999
SPECIFICATIONS
All specifications at TMIN to TMAX, VD = VS = +5V, CLK = 9.6MHz, PGA = 1, and VREF = 4.096, unless otherwise specified.
ADS1250U
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Input Voltage Range(1)
Programmable Gain Amplifier
Input Impedance (differential)
Input Capacitance
G = Gain
AGND
1
±VREF/G
V
8
G = Gain
G = Gain
At +25°C
104/G
6 • G
5
kΩ
pF
pA
nA
Input Leakage
50
1
At TMIN to TMAX
DYNAMIC CHARACTERISTICS
Data Rate
Bandwidth
25
kHz
kHz
3dB
5.4
Serial Clock (SCLK)
System Clock Input (CLK)
9.6
9.6
MHz
MHz
ACCURACY
Integral Linearity Error(2)
THD
Noise
±0.0012
97
2.8
±0.0020
% of FSR
1kHz Input; 0.1dB below FS
dB
ppm of FSR, rms
Bits
3.8
Resolution
20
No Missing Codes
Common-Mode Rejection(3)
Gain Error
Offset Error
Gain Sensitivity to VREF
Power Supply Rejection Ratio
20
105
Bits
dB
% of FSR
ppm of FSR
at DC
90
60
1
±200
±100
1:1
78
VREF = 4.096V ±0.1V
dB
PERFORMANCE OVER TEMPERATURE
Offset Drift
Gain Drift
0.25
5.0
ppm/°C
ppm/°C
VOLTAGE REFERENCE
VREF
Load Current
3.996V
4.096
125
4.196
V
µA
DIGITAL INPUT/OUTPUT
Logic Family
Logic Level: VIH
VIL
CMOS
+4.0
–0.3
+4.5
+VD + 0.3
+0.8
V
V
V
V
VOH
VOL
IOH = –500µA
IOL = 500µA
0.4
Data Format
Binary Two’s Complement
POWER SUPPLY REQUIREMENTS
Operation
Quiescent Current, Analog
Quiescent Current, Digital
Operating Power
+4.75
+5
14
1
+5.25
100
VDC
mA
mA
V = +5VDC
V = +5VDC
75
mW
TEMPERATURE RANGE
Operating
Storage
–40
–60
+85
+100
°C
°C
NOTES: (1) In order to achieve the converter’s full-scale range, the input must be fully differential. If the input is single-ended (+VIN or –VIN is fixed), then the
full-scale range is one-half that of the differential range. (2) Applies to full-differential signals. (3) The common-mode rejection test is performed with a 100mV
differential input.
®
ADS1250
2
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Analog Input: Current ................................................ ±100mA, Momentary
±10mA, Continuous
Voltage ....................................... AGND –0.3V to VS + 0.3V
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
V
V
V
S to VD ....................................................................................–0.3V to 6V
S to AGND ............................................................................ –0.3V to 6V
D to DGND ............................................................................ –0.3V to 6V
AGND to DGND ................................................................................ ±0.3V
REF Voltage to AGND ................................................. –0.3V to VS + 0.3V
V
Digital Input Voltage to DGND ..................................... –0.3V to VD + 0.3V
Digital Output Voltage to DGND .................................. –0.3V to VD + 0.3V
Lead Temperature (soldering, 10s) .............................................. +300°C
Power Dissipation (any package) .................................................. 500mW
Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Burr-
BrownCorporationrecommendsthatallintegrated circuitsbe
handled and stored using appropriate ESD protection
methods.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
ADS1250U
"
SOL-16
"
211
"
–40°C to +85°C
ADS1250U
"
ADS1250U
ADS1250U/1K
Rails
Tape and Reel
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “ADS1250U/1K” will get a single 1000-piece Tape and Reel.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
ADS1250
PIN CONFIGURATION
Top View
SOL-16
16
15
14
13
12
11
10
9
+VIN
–VIN
DGND
1
2
3
4
5
6
7
8
G1 (MSB)
G0 (LSB)
AGND
+VS
VREF
CS
ADS1250
DRDY
CLK
DSYNC
+VD
SCLK
DOUT
DGND
PIN DESCRIPTIONS
PIN
NAME
PIN DESCRIPTION
1
2
3
4
5
6
+VIN
–VIN
Analog Input: Positive Input of the Differential Analog Input.
Analog Input: Negative Input of the Differential Analog Input.
Analog Input: Analog Ground.
AGND
+VS
Analog Input: Analog Power Supply Voltage, +5V.
Analog Input: Reference Voltage Input.
VREF
DSYNC
Digital Input: Data Synchronization. A falling edge on this input will reset the modulator count and place the modulator in a hold
state. The modulator is released from the hold state on the rising edge of DSYNC. This can be used to synchronize multiple
ADS1250s.
7
8
9
+VD
Digital Input: Digital Power Supply Voltage, +5V.
Digital Input: Digital Ground.
DGND
DOUT
Digital Output: Serial Data Output. The serial data is clocked out of the serial data output shift register through this pin. The pin
is driven when CS is LOW, and high impedance when CS is HIGH.
10
SCLK
Digital Input: Serial Clock. The serial clock is in the form of a CMOS-compatible clock. The serial clock can operate up to the
device’s system clock frequency. The serial clock can be either a free-running clock or noncontinuous clock, with either type of
clock; the serial data output is gated by CS.
11
12
CLK
Digital Input: Device System Clock. The system clock is in the form of a CMOS-compatible clock.
DRDY
Digital Output: Data Ready. A falling edge on this output indicates that a new output word is available from the ADS1250 data output
register.
13
CS
Digital Input: Chip Select. Active LOW logic input used to enable serial data output from the ADS1250. CS controls the state of
the DOUT pin. If CS is HIGH, DOUT is high impedance; if CS is LOW, DOUT drives the bus. CS can be used in three ways:
(1) If the ADS1250 shares the bus with other devices, CS is used as serial data output enable for communications.
(2) If the ADS1250 shares the bus with other devices and SCLK is a free-running clock, CS is used to gate serial data
out of the device.
(3) If the ADS1250 is the only device on the bus, CS can be tied LOW to always enable serial data output for a
two-wire interface.
Refer to the Serial Communications section of this data sheet for more detail.
Digital Input: Gain Selection Control (LSB).
14
15
16
G0
G1
Digital Input: Gain Selection Control (MSB).
DGND
Digital Input: Digital Ground.
®
ADS1250
4
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VD = VS = +5V, CLK = 9.6MHz, PGA = 1, and VREF = 4.096, unless otherwise specified.
EFFECTIVE RESOLUTION
vs DATA OUTPUT RATE
RMS NOISE vs DATA OUTPUT RATE
20.0
19.0
18.0
17.0
16.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
PGA = 8
PGA = 4
PGA = 1
PGA = 1
PGA = 2
PGA = 2
PGA = 4
PGA = 8
1
10
100
1000
10000
10000
1
10
100
1000
10000
10000
Data Output Rate (Hz)
Data Output Rate (Hz)
RMS NOISE vs TEMPERATURE
PGA = 8
RMS NOISE vs INPUT VOLTAGE (PGA = 1)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
PGA = 4
PGA = 1
PGA = 2
–60
–40
–20
0
20
40
60
80
100
–4.0 –3.0 –2.0 –1.0
0.0
1.0
2.0
3.0
4.0
Temperature (°C)
Differential Analog Input Voltage (V)
INTEGRAL NON-LINEARITY
INTEGRAL NON-LINEARITY vs TEMPERATURE
PGA = 1
vs DATA OUTPUT RATE (PGA = 1)
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
20
15
10
5
PGA = 2
PGA = 8
PGA = 4
40
0
–60
–40
–20
0
20
60
80
100
1
10
100
1000
10000
10000
Temperature (°C)
Data Output Rate (Hz)
®
5
ADS1250
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VD = VS = +5V, CLK = 9.6MHz, PGA = 1, and VREF = 4.096, unless otherwise specified.
OFFSET DRIFT vs TEMPERATURE
GAIN DRIFT vs TEMPERATURE
30
20
400
200
0
PGA = 1
PGA = 4
PGA = 2
10
PGA = 2
PGA = 4
PGA = 8
PGA = 1
PGA = 4
PGA = 1
PGA = 8
0
PGA = 8
PGA = 8
PGA = 4
–10
–20
–30
–200
–400
PGA = 2
–20
PGA = 2
PGA = 1
–60
–40
–20
0
20
40
60
80
100
–60
–40
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
COMMON-MODE REJECTION RATIO
vs FREQUENCY
POWER SUPPLY REJECTION RATIO
vs FREQUENCY
120
115
110
105
100
100
90
80
70
60
PGA = 8
PGA = 1
PGA = 4
PGA = 2
PGA = 2
PGA = 4
PGA = 1
PGA = 8
1
10
100
1000
1
10
100
1k
10k
Frequency (Hz)
Frequency (Hz)
ANALOG CURRENT vs TEMPERATURE
(PGA = 1)
DIGITAL CURRENT vs TEMPERATURE
(PGA = 1)
20.0
18.0
16.0
14.0
12.0
10.0
8.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
6.0
4.0
2.0
0.0
–60
–40
–20
0
20
40
60
80
100
–60
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
®
ADS1250
6
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VD = VS = +5V, CLK = 9.6MHz, PGA = 1, and VREF = 4.096, unless otherwise specified.
TYPICAL FFT ANALYSIS
OF THE 1kHz fS INPUT SIGNAL (PGA = 4)
POWER DISSIPATION vs CLK FREQUENCY
(PGA = 1)
0
–20
100
80
60
40
20
0
–40
–60
–80
–100
–120
–140
–160
–180
–200
0
2500
5000
7500
10000
12500
0.0
2.0
4.0
6.0
8.0
10.0
Frequency (Hz)
CLK Frequency (MHz)
®
7
ADS1250
Additionally, a lower gain setting (G) decreases the sam-
pling capacitor size, which results in a higher analog input
impedance. This can be seen in the following equation:
THEORY OF OPERATION
The ADS1250 is a precision, high dynamic range, 20-bit,
delta-sigma, A/D converter capable of achieving very high-
resolution digital results at high data rates. The analog input
signal is continuously sampled at a rate determined by the
frequency of the system clock (CLK). The sampled analog
input is modulated by the delta-sigma A/D modulator, fol-
lowed by a digital filter value. A programmable gain func-
tion is also incorporated in the delta-sigma modulator with
larger input sampling capacitors for higher gains. A sinc5
digital low-pass filter processes the output of the delta-sigma
modulator and writes the result into the data output register.
The DRDY pin is pulled LOW indicating that new data is
available to be read by the external microcontroller/micro-
processor. As shown in the block diagram, the main func-
tional blocks of the ADS1250 are the programmable gain
amplifier, a fourth-order delta-sigma modulator, a digital
filter, control logic, and a serial interface. Each of these
functional blocks is described below.
9.6 MHz • 104E3
AIN Impedance (Ω) =
CLK • G
With regard to the analog input signal, the overall analog
performance of the device is affected by three items. First,
the input impedance can affect accuracy. If the source
impedance of the input signal is significant, or if there is
passive filtering prior to the ADS1250, a significant portion
of the signal can be lost across this external impedance. The
magnitude of the effect is dependent on the desired system
performance.
Second, the current into or out of the analog inputs must be
limited. Under no conditions should the current into or out
of the analog inputs exceed 10mA.
Third, to prevent aliasing of the input signal, the bandwidth
of the analog input signal must be band limited. The band-
width is a function of the system clock frequency. With a
system clock frequency of 9.6MHz, the data output rate is
25kHz, with a –3dB frequency of 5.4kHz. The –3dB fre-
quency scales with the system clock frequency.
ANALOG INPUT
The ADS1250 contains a fully differential analog input with
programmable gain. The fully differential switched capaci-
tor architecture provides low system noise, common-mode
rejection of 105dB, and excellent power supply rejection.
The selectable gains on the input are 1, 2, 4, or 8, which
gives a bipolar input voltage range from –4.096 to +4.096V,
to –512mV to +512mV, when the reference input voltage
equals +4.096V. The bipolar ranges are with respect to –VIN
and not with respect to GND.
To guarantee the best linearity of the ADS1250, a fully
differential signal is recommended.
PROGRAMMABLE GAIN AMPLIFIER
The PGA gain setting is programmed via the PGA pins on the
ADS1250. Changes in the gain setting (G) of the PGA results
in an increase in the input capacitor size. Therefore, higher
gain settings result in a lower analog input impedance.
Figure 1 shows the basic input structure of the ADS1250.
The analog input impedance is directly related to the sam-
pling frequency of the input capacitor (fMOD), and the gain
setting (G) of the device. The sampling frequency of the
input capacitor is derived from the system clock (CLK).
Therefore, a lower CLK rate decreases the sampling fre-
quency, which results in a higher analog input impedance.
The PGA of the ADS1250 can be set to a gain of 1, 2, 4, or
8, substantially increasing the dynamic range of the converter
and simplifying the interface to the more common transducers
(see Table I).
GAIN SETTING
ANALOG INPUT
DIFFERENTIAL
FSR (V)
SINGLE-ENDED
FSR (V)
G1
G0
GAIN VALUE
RSW
(1kΩ typical • G)
0
0
1
1
0
1
0
1
1
2
4
8
8.192
4.096
2.048
1.024
4.096
2.048
1.024
0.512
Internal
Circuitry
AIN
CINT
Modulator Frequency
(6pF typical • G)
NOTE: Based on a 4.096V reference. The ADS1250 allows common-
mode voltage as long as the absolute input voltage on +VIN or –VIN does
not go below AGND or above +VS.
= fMOD
VCM
TABLE I. Full-Scale Range versus PGA Setting.
FIGURE 1. Analog Input Structure.
®
ADS1250
8
DELTA-SIGMA MODULATOR
Reference voltages higher than 4.096V will increase the
full-scale range, while the absolute internal circuit noise of
the converter remains the same. This will decrease the noise
in terms of ppm of full scale. However, using a higher
reference voltage will also degrade linearity. Therefore, the
use of a higher reference voltage is not recommended.
The modulator clock is generated by dividing the system
clock by 6. With a nominal system clock frequency of
9.6MHz, the modulator clock frequency is 1.6MHz
(9.6MHz / 6). The output from the modulator is oversampled
64 times by the digital filter. Therefore, with 1.6MHz
modulator clock (derived from a 9.6MHz system clock), the
data output rate is 25kHz (1.6MHz / 64). The data output
rate scales directly with the system clock frequency, as
shown in Table II.
Reference voltages lower than 4.096V will decrease the full-
scale range, while the absolute internal circuit noise at the
converter remains the same. This will increase the noise in
terms of ppm of full scale. However, using a lower reference
voltage will not degrade linearity. Therefore, the use of a
lower reference voltage will reduce the effective resolution.
CLK (MHz)
DATA OUTPUT RATE (Hz)
9.600000
7.372800(1)
6.144000(1)
6.000000(1)
4.915200(1)
3.686400(1)
3.072000(1)
2.457600(1)
1.843200(1)
0.921600
0.460800
0.384000
0.192000
0.038400
0.023040
0.019200
0.011520
0.009600
0.007680
0.006400
0.005760
0.004800
0.003840
25,000
19,200
16,000
15,625
12,800
9,600
8,000
6,400
4,800
2,400
1,200
1,000
500
DIGITAL FILTER
The digital filter is a sinc5 and is described by the following
transfer function:
5
π • f • 64
sin
fMOD
H(f) =
π • f
64 •sin
fMOD
or
100
60
5
1– z–64
50
H(z) =
30
64 • 1– z–1
25
(
)
20
16.67
15
The digital filter of the ADS1250 computes the digital result
based on the most recent outputs from the delta-sigma
modulator. At the most basic level, the digital filter can be
thought of as simply averaging the modulator results in a
weighted form and presenting this average as the digital
result. The digital result is calculated from the digital filter
every 64 modulator clock cycles, or 6 • 64 = 384 system
clock cycles (refer to the Delta-Sigma Modulator section).
However, if there is a significant change in the analog input,
five full conversions are needed for the digital filter to settle.
If the analog input change occurs asynchronously to the
DRDY pulse, six conversions are needed for the conversion
to fully settle. Furthermore, the group delay is only 2.5
conversions due to the digital filter's linear phase response.
12.50
10
NOTE: (1) Standard Clock Oscillator.
TABLE II. CLK Rate versus Data Output Rate.
REFERENCE INPUT
Unlike the analog input, the reference input impedance has no
dependency on the PGA gain setting.
Reference input takes an average current of 125µA with a
9.6MHz system clock. This current will be proportional to
the system clock. A buffered reference is needed for
ADS1250. The recommended reference circuit is shown in
Figure 2.
+5V
+5V
0.10µF
7
4.99kΩ
2
To VREF
Pin 5 of
the ADS1250
6
OPA350
10kΩ
3
1
+
10µF
0.1µF
+
10µF
0.10µF
4
LM404-4.1
FIGURE 2. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the ADS1250.
®
9
ADS1250
There is an additional benefit in using a lower data output
rate. It will provide better rejection of signals in the fre-
quency band of interest. For example, with a 50Hz data
output rate, a significant signal at 75Hz may alias back into
the passband at 25Hz. This is due to the fact that rejection at
75Hz may only be 66dB in the stopband (frequencies higher
than the first notch frequency), as shown in Figure 4.
However, setting the data output rate to 10Hz will provide
135dB rejection at 75Hz (see Figure 6). A similar benefit is
gained at frequencies near the data output rate (see Figures
7, 8, 9, and 10). If a slower data output rate does not meet
the system requirements, the analog front end can be de-
signed to provide the needed attenuation to prevent aliasing.
Additionally the data output rate may be increased and
additional digital filtering may be done in the processor or
controller.
The digital output rate, or data rate, scales directly with the
system CLK frequency. This allows the data output rate to
be changed over a very wide range (five orders of magni-
tude) by changing the system CLK frequency. However, it
is important to note that the –3dB point of the filter is 0.216
times the data output rate. Therefore, the data output rate
should allow for sufficient margin to prevent attenuation of
the signal of interest.
Since the conversion result is essentially an average, the data
output rate determines the location of the resulting notches
in the digital filter (see Figure 3). Note that the first notch is
located at the data output rate frequency, and subsequent
notches are located at integer multiples of the data output
rate to allow for rejection of not only the fundamental
frequency, but also harmonic frequencies. In this manner,
the data output rate can be used to set specific notch
frequencies in the digital filter response.
CONTROL LOGIC
For example, if rejection of the power line frequency is
desired, the data output rate can simply be set to the power
line frequency. For 50Hz rejection, the system CLK fre-
quency should be 19.200kHz; this will set the data output
rate to 50Hz (see Table II and Figure 4). For 60Hz rejection,
the system CLK frequency should be 23.040kHz; this will
set the data output rate to 60Hz (see Table II and Figure 5).
If both 50Hz and 60Hz rejection is required, then the system
CLK should be 3.840kHz; this will set the data output rate
to 10Hz and reject both 50Hz and 60Hz (See Table II and
Figure 6).
The control logic is used for communications and control of
the ADS1250.
Power-Up Sequence
Prior to power-up, all digital and analog input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V, however, they should
never exceed +VS or +VD.
Once the ADS1250 powers up, the DRDY line will pulse
LOW on the first conversion. This data will not be valid. The
sixth pulse of DRDY will be valid data from the analog input
signal.
DIGITAL FILTER RESPONSE
0
NORMALIZED DIGITAL FILTER RESPONSE
0
–20
–40
–20
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
0
50
100
150
200
250
300
0
1
2
3
4
5
6
7
8
9
10
Frequency (Hz)
Frequency (Hz)
FIGURE 3. Normalized Digital Filter Response.
FIGURE 4. Digital Filter Response (50Hz).
®
ADS1250
10
DIGITAL FILTER RESPONSE
DIGITAL FILTER RESPONSE
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
0
10
20
30
40
50
60
70
80
90 100
0
50
100
150
200
250
300
Frequency (Hz)
Frequency (Hz)
FIGURE 5. Digital Filter Response (60Hz).
FIGURE 6. Digital Filter Response (10Hz Multiples).
DIGITAL FILTER RESPONSE
0
DIGITAL FILTER RESPONSE
0
–20
–40
–20
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
45
46
47
48
49
50
51
52
53
54
55
45
46
47
48
49
50
51
52
53
54
55
Frequency (Hz)
Frequency (Hz)
FIGURE 7. Expanded Digital Filter Response (50Hz with a
50Hz Notch).
FIGURE 8. Expanded Digital Filter Response (50Hz with a
10Hz Notch).
DIGITAL FILTER RESPONSE
0
DIGITAL FILTER RESPONSE
0
–20
–40
–20
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
55
56
57
58
59
60
61
62
63
64
65
55
56
57
58
59
60
61
62
63
64
65
Frequency (Hz)
Frequency (Hz)
FIGURE 9. Expanded Digital Filter Response (60Hz with a
60Hz Notch).
FIGURE 10. Expanded Digital Filter Response (60Hz with
a 10Hz Notch).
®
11
ADS1250
DSYNC
Therefore, the output data will be synchronized, but only to
within one CLK clock cycle. To ensure exact synchroniza-
tion to the same CLK clock edge, the timing relationship
between the DSYNC and CLK signals must be observed, as
shown in Figure 11 and Table III. Figure 12 shows a simple
circuit which can be used to clock multiple ADS1250s from
one ADS1250, as well as to ensure that an asynchronous
DSYNC signal will exactly synchronize all the converters.
The DSYNC signal can be used is two ways. First, DSYNC
can be used to synchronize multiple converters. This is done
by applying a negative-going pulse on DSYNC. The nega-
tive pulse resets the current modulator count to zero and
places it in a hold state. The modulator is released from the
hold state and synchronization occurs on the rising edge of
DSYNC. DSYNC does not reset the internal data to zero.
Synchronization assumes that each ADS1250 is driven from
the same system clock. If the DSYNC pulse is completely
asynchronous to the master clock, some ADS1250s may
start-up one CLK clock cycle before the others.
The second use of DSYNC is to reset the modulator count
to zero in order to obtain valid data as quickly as possible.
For example, if the analog input signal is changed signifi-
cantly on the ADS1250, the current conversion cycle will be
a mix of the old data and the new data. Five conversions are
needed for the digital filter to settle. Therefore, the sixth
conversion will be valid data. However, if the analog input
signal is changed and then DSYNC is used to reset the
modulator count, the modulator data at the end of the current
conversion cycle will be entirely from the new signal. After
four additional conversion cycles, the output data will be
completely valid. Note that the conversion cycle in which
DSYNC is used will be slightly longer than normal. Its
length will depend on when DSYNC was set.
CLK
t14
t13
DSYNC
FIGURE 11. DSYNC to CLK Timing for Synchronizing
Multiple ADS1250s.
1/2 74AHC74
Asynchronous
DSYNC
Strobe
D
Q
CLK
Q
1/6 74AHC04
DVDD
OSC
DSYNC
CLK
DOUT
SCLK
DVDD
DSYNC
CLK
DOUT
SCLK
DVDD
DSYNC
CLK
DOUT
SCLK
DVDD
DGND
DGND
DGND
ADS1250
ADS1250
ADS1250
DGND
FIGURE 12. Exactly Synchronizing Multiple ADS1250s to an Asynchronous DSYNC Signal.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
t2
t3
t4
t5
t6
t7
t8
DOR Write Time (Using CS)
DRDY LOW Time
6 • CLK
6 • CLK
6 • CLK
6 • CLK
30
ns
ns
ns
ns
ns
ns
ns
DOR Write Time (CS HIGH)
DRDY HIGH Time
Rising Edge of CLK to Falling Edge of DRDY
Falling Edge of DRDY to Falling Edge of CS
30
30
5
Falling Edge of CS to Rising Edge of DRDY
6 • CLK
Falling Edge of CS to Rising Edge of SCLK or
Falling Edge of DRDY to Rising Edge of SCLK if CS is Tied LOW
Falling Edge of CS to DOUT Valid or
ns
t9
Falling Edge of DRDY to DOUT Valid if CS is Tied LOW (Setup Time)
30
ns
ns
ns
ns
ns
ns
t10
t11
t12
t13
t14
Falling Edge of SCLK to DOUT Valid (Hold Time)
Falling Edge of SCLK to Next DOUT Valid (Setup Time)
Rising Edge of CS to DOUT High Impedance
DSYNC Pulse Width
30
30
100
CLK
– 5
2
Falling Edge of CLK to Falling Edge of DSYNC
TABLE III. Digital Timing.
®
ADS1250
12
CS
MSB to LSB in the time defined by t3. The DRDY line
would stay HIGH for the time defined by t4, as shown in
Figure 15.
The CS signal controls the state of DOUT. If CS is HIGH,
DOUT is in a high-impedance state. When CS is LOW,
DOUT drives the bus.
t3
t4
DRDY
DRDY
The DRDY signal is used to indicate that new data has been
loaded into the data output register and is ready to be read.
The operation of DRDY depends on how the CS signal is
used. The specifics of the three communications methods
are described in the Serial Interface section.
MSB
written
to DOR
DOR
write
complete
FIGURE 15. DRDY Pulse (CS HIGH).
In the first case, which is typical for three-wire serial
communications (CS tied LOW), DRDY would normally be
HIGH. The result of the A/D conversion would be written to
the DOR from MSB to LSB in the time defined by t1. The
DRDY line would then pulse LOW for time defined by t2,
as shown in Figure 13.
Reading DRDY during the time shown by t1 and t3 (Figures
13, 14, and 15) will result in invalid data being read. This is
due to the fact that writes to the DOR are not blocked.
Subsequently, a read from DOR during this time will result
in a combination of old and new data.
SERIAL INTERFACE
t1
t2
The ADS1250 includes a simple serial interface which can
be connected to microcontrollers and digital signal proces-
sors in a variety of ways. Communications with the ADS1250
can commence on the first detection of the DRDY pulse
after power up, although data will not be valid until the sixth
conversion.
DRDY
MSB
written
to DOR
DOR
write
complete
It is important to note that the data from the ADS1250 is a 20-
bit result transmitted MSB-first in Binary Two’s Complement
format, as shown in Table IV.
DOUT
FIGURE 13. DRDY Pulse (CS tied LOW).
DIFFERENTIAL VOLTAGE INPUT
DIGITAL OUTPUT (HEX)
In the second case, which is typical for four-wire serial
communications (CS used), DRDY would normally be HIGH.
The result of the A/D conversion would be written to the DOR
from MSB to LSB in the time defined by t1. The DRDY would
go LOW after the DOR write is completed. After taking CS
LOW, the DRDY line would remain LOW for the time
defined by t2, as shown in Figure 14.
+Full Scale
Zero
7FFFFH
00000H
80000H
–Full Scale
TABLE IV. ADS1250 Data Format (Binary Two's Comple-
ment).
The entire 20-bit result can be read out of the device by simply
providing 20 SCLKs during serial communication with the
part. However, the most common method of communicating
with the device is with a standard SSI interface, such as SPI.
This protocol is based on 8-bit or 16-bit data transfers. It is
possible to use a standard 8-bit or 16-bit data transfer with the
ADS1250. For instance, if only 16 bits of data are read, the
internal bit pointer will automatically reset to the MSB of the
DOR on the next DRDY pulse. This will ensure that the next
read from the DOR will begin with the MSB of newly
converted data. If more than 20 bits of data are read, the data
will be 0 padded. Therefore, if 24 bits of data are read from the
ADS1250, the lowest four bits of the 24-bit data transfer are
read as 0s (0 padded).
t1
t2
DRDY
MSB
written
to DOR
DOR
write
complete
CS
DOUT
The only limitation on SCLK is that it cannot be higher than
9.6MHz. Therefore, it is possible to run CLK at a lower
frequency than SCLK. For instance, it is possible to run
CLK at 23.040kHz for a 60Hz notch, and run SCLK at
9.6MHz to achieve high-speed serial communications. Ad-
ditionally, the data must be clocked out before the next
DRDY to ensure valid data, as described in the DRDY
section.
FIGURE 14. DRDY Pulse (using CS).
In the third case, CS is left HIGH, which may be used if data
is only periodically read from the ADS1250. In this case,
DRDY would normally be LOW. DRDY would go HIGH
immediately prior to the MSB being written to the DOR.
The result of the A/D conversion would be written from
®
13
ADS1250
There are three basic methods of receiving data from the
ADS1250. The first two methods involve a four-wire inter-
face and the third method is a three-wire interface.
output register. The processor would provide 20 (or 24)
SCLKs to read the contents of the DOR. The data bits in the
DOR are shifted out on the DOUT pin after the falling edge
of SCLK. If more than 20 bits of data are read, the data is 0
padded. Taking CS HIGH will take DOUT to a high-
impedance state. The timing for the data transfer is shown in
Figure 16 (see Table III). A simple four-wire interface using
this method is shown in Figure 17. The P1.0 output from the
8xC51 is a free-running clock.
Method 1: Four-Wire Interface
The most common method of receiving data is using a
simple four-wire interface (CS, SCLK, DOUT, and DRDY).
The DRDY line will pulse LOW after the DOR is updated.
The processor would then take CS LOW to select the device
for communication. Once CS is taken LOW, the DOUT
would be driven to the level dictated by the MSB of the data
t5
CLK
t6
DRDY
t7
CS
t8
t10
SCLK
1
2
19
20
21
22
23
24
t12
t9
t11
OUT
LSB
OUT
MSB
DOUT
FIGURE 16. Method 1: Four-Wire Interface Using Noncontinuous SCLK.
DVDD
8xC51
+VIN
P1.0 / T2
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
DGND
G1
–VIN
AGND
+VS
G0
AVDD
AGND
DGND
CS
VREF
Circuit
ADS1250
DVDD
VREF
DRDY
CLK
DSYNC
+VD
SCLK
DOUT
DGND
DVDD
P3.0
P3.1
DGND
ALE
P3.2 / INT0
P3.3
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P3.4
P3.5
P3.6
P3.7
C1
C2
XTAL
XTAL2
XTAL1
VSS
DGND
FIGURE 17. Four-Wire Interface to an 8xC51.
®
ADS1250
14
Method 2: Four-Wire Interface
would be driven to the level dictated by the MSB of the data
output register. CS would be held low for 20 (or 24) SCLKs
to read the contents of the DOR. The data bits in the DOR
are shifted out on the DOUT pin after the falling edge of
SCLK. If CS is held low for more than 20 SCLKs, the data
would be 0 padded. Taking CS HIGH will take DOUT to a
high-impedance state. The timing for the data transfer is
shown in Figure 18 (see Table III). A simple four-wire
interface is shown in Figure 19. The P1.0 output from the
8xC51 is a free-running clock.
The second method of receiving data also uses a simple
four-wire interface (CS, SCLK, DOUT, and DRDY). The
main difference from method 1 is that SCLK is a free-
running clock. The DRDY line will pulse LOW for the time
defined by t2 after the DOR is updated. The processor would
then take CS LOW to select the device for communication.
The recommended method of using CS is to take CS LOW
on the falling edge of SCLK. The only timing constraint of
CS is that the setup time (t9) for the data must be met before
the rising edge of SCLK. Once CS is taken LOW, the DOUT
t5
CLK
t6
DRDY
t7
CS
t8
t10
SCLK
1
2
19
20
21
22
23
24
t9
t11
t12
OUT
MSB
OUT
LSB
DOUT
FIGURE 18. Method 2: Four-Wire Interface Using a Free-Running SCLK.
DVDD
8xC51
+VIN
P1.0 / T2
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
DGND
G1
–VIN
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0
P3.1
AGND
+VS
G0
AVDD
AGND
DGND
CS
VREF
Circuit
ADS1250
DVDD
VREF
DRDY
CLK
DSYNC
+VD
SCLK
DOUT
DGND
DVDD
DGND
ALE
P3.2 / INT0
P3.3
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P3.4
P3.5
P3.6
P3.7
C1
C2
XTAL
XTAL2
XTAL1
VSS
DGND
FIGURE 19. Four-Wire Interface to an 8xC51 (Free-Running SCLK).
15
®
ADS1250
Method 3: Three-Wire Interface
than 20 bits of data are read, the data is 0 padded. Since CS
is tied LOW, the bus will be driven to the state of the last bit
that was shifted out of the DOR. The timing for the data
transfer is shown in Figure 20 (see Table III). A simple
three-wire interface using this method is shown in Figure 21.
The P1.0 output from the 8xC51 is a free-running clock.
The third method of receiving data uses a simple three-wire
interface (SCLK, DOUT, and DRDY). The main difference
from method 1 is that CS is tied LOW, therefore, the DOUT
pin is always driving the bus. The DRDY line will pulse
LOW after the DOR is updated. Since CS is tied LOW (the
DOUT pin is enabled for output), the level dictated by the
MSB of the data output register would be driven on the bus.
The processor would provide 20 (or 24) SCLKs to read the
contents of the DOR. The data bits in the DOR are shifted
out on the DOUT pin after the falling edge of SCLK. If more
Figure 22 shows a five-wire interface using DSYNC. The
communication with the ADS1250 is the same as described
in Method 1. Figure 23 shows a full interface using DSYNC,
G1, and G0. The communication with ADS1250 is the same
as described in Method 1.
t5
CLK
t2
DRDY
t8
t10
SCLK
1
2
19
20
21
22
23
24
t9
t11
OUT
OUT
MSB
DOUT
LSB
FIGURE 20. Method 3: Two-Wire Interface (CS tied LOW).
DVDD
8xC51
+VIN
P1.0 / T2
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
DGND
G1
–VIN
AGND
+VS
G0
AVDD
AGND
CS
VREF
Circuit
ADS1250
DGND
DVDD
VREF
DRDY
CLK
DSYNC
+VD
SCLK
DOUT
DGND
DVDD
P3.0
P3.1
DGND
ALE
P3.2 / INT0
P3.3
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P3.4
P3.5
P3.6
P3.7
C1
C2
XTAL
XTAL2
XTAL1
VSS
DGND
FIGURE 21. Three-Wire Interface to an 8xC51 (CS tied LOW).
®
ADS1250
16
DVDD
8xC51
+VIN
P1.0 / T2
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
DGND
G1
–VIN
AGND
+VS
G0
AVDD
AGND
DGND
CS
ADS1250
VREF
Circuit
VREF
DRDY
CLK
DSYNC
+VD
DVDD
SCLK
DOUT
DGND
DVDD
DGND
P3.0
P3.1
ALE
P3.2 / INT0
P3.3
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P3.4
P3.5
P3.6
P3.7
C1
C2
XTAL
XTAL2
XTAL1
VSS
DGND
FIGURE 22. Five-Wire Interface to an 8xC51.
DVDD
8xC51
+VIN
–VIN
P1.0 / T2
P1.1
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
DGND
G1
DGND
AGND
AVDD
P1.2
G0
AGND
+VS
P1.3
CS
ADS1250
VREF
Circuit
VREF
P1.4
DRDY
CLK
DSYNC
+VD
P1.5
DVDD
P1.6
SCLK
DOUT
DGND
P1.7
DVDD
RST
DGND
P3.0
P3.1
ALE
P3.2 / INT0
P3.3
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P3.4
P3.5
P3.6
P3.7
C1
C2
XTAL
XTAL2
XTAL1
VSS
DGND
FIGURE 23. Full Interface to an 8xC51.
®
17
ADS1250
SOFTWARE GAIN
example, shifting the result by 4 bits when the ADS1250 is set
to a gain of 8 results in an effective gain of 128.
The excellent performance, flexibility, and low cost of the
ADS1250 allows the converter to be considered for designs
which would not normally need a 20-bit ADC. For example,
many designs utilize a 12-bit converter and a high gain INA
or PGA for digitizing low amplitude signals. For some of these
applications, the ADS1250 by itself may be a solution. The
digital result of the converter can simply be shifted up by “n”
bits in the main controller, resulting in a gain of “n” times G,
where G is the gain setting. While this type of manipulation of
the output data is obvious, it is easy to miss how much the gain
can be increased in this manner on a 20-bit converter. For
Isolation
The serial interface of the ADS1250 provides for simple
isolation methods. An example of an isolated four-wire
interface is shown in Figure 19. The ISO150 is used to
transmit the digital clocks over the isolation barrier. In
addition, the digital output of the ADS1250 can, in some
cases, drive opto-isolators directly. Note that DOUT is tri-
stated for the majority of the conversion period and the opto-
isolator connection must take this into account.
VDD2
DRDY
DGND
VDD1
+VIN
DGND
G1
CLK
–VIN
VDD2
DGND
VDD1
AGND
VDD2
AGND
+VS
G0
AVDD
AGND
CS
VREF
ADS1250
Circuit
DGND
DGND
VDD1
VREF
DRDY
CLK
SCLK
DSYNC
+VD
DGND
SCLK
DOUT
DGND
DGND
VDD1
DOUT
VDD2
DGND
AGND
FIGURE 24. Isolated Four-Wire Interface.
®
ADS1250
18
should be connected to the analog ground plane as well as all
other analog grounds. DGND should be connected to the
digital ground plane and all digital signals referenced to this
plane. The ADS1250 pinout is such that the converter is
cleanly separated into an analog and digital portion. This
should allow simple layout of the analog and digital sections
of the design. For a single converter system, AGND and
DGND of the ADS1250 should be connected together,
underneath the converter. Do not join the ground planes, but
connect the two with a moderate signal trace. For multiple
converters, connect the two ground planes at one location as
central to all of the converters as possible. In some cases,
experimentation may be required to find the best point to
connect the two planes together. The printed circuit board
can be designed to provide different analog/digital ground
connections via short jumpers. The initial prototype can be
used to establish which connection works best.
LAYOUT
POWER SUPPLIES
The analog supply should be well regulated and low noise.
For designs requiring very high resolution from the ADS1250,
power supply rejection will be a concern. Avoid running
digital lines under the device as they may couple noise onto
the die. The requirements for the digital supply are not as
strict, however, high frequency noise on VD can capacitively
couple into the analog portion of the ADS1250. This noise
can originate from switching power supplies, very fast
microprocessors, or digital signal processors. For either
supply, high frequency noise will alias back into the pass-
band of the digital filter, affecting the conversion result. If
one supply must be used to power the ADS1250, the VS
supply should be used to power VD. This connection can be
made via a 10Ω resistor which, along with the decoupling
capacitors, will provide some filtering between VD and VS.
In some systems, a direct connection can be made. Experi-
mentation may be the best way to determine the appropriate
connection between VS and VD.
DECOUPLING
Good decoupling practices should be used for the ADS1250
and for all components in the design. All decoupling capaci-
tors, but specifically the 0.1µF ceramic capacitors, should be
placed as close as possible to the pin being decoupled. A
1µF to 10µF capacitor, in parallel with a 0.1µF ceramic
capacitor, should be used to decouple VS to AGND. At a
minimum, a 0.1µF ceramic capacitor should be used to
decouple VD to DGND, as well as for the digital supply on
each digital component.
GROUNDING
The analog and digital sections of the design should be
carefully and cleanly partitioned. Each section should have
its own ground plane with no overlap between them. AGND
TYPICAL CONNECTION
16
+VIN
–VIN
1
2
3
4
5
6
7
8
DGND
+
15
14
13
12
11
10
9
G1
∆Σ
Modulator
PGA
–
AGND
G0
+VS
CS
Digital
Filter
10µF
10µF
0.1µF
VREF
DRDY
CLK
SCLK
DOUT
DSYNC
Serial
Output
+VD
0.1µF
DGND
ADS1250
FIGURE 25. Connection Diagram.
®
19
ADS1250
analog inputs of the ADS1250 are at 2.048V, the differential
voltage is 0V. If one input is at 0V and the other is at 4.096V,
the differential voltage magnitude is 4.096V. This is the case
regardless of which input is at 0V and which is at 4.096V.
The analog input differential voltage is given by the follow-
ing equation:
SYSTEM CONSIDERATIONS
The recommendations for power supplies and grounding
will change depending on the requirements and specific
design of the overall system. Achieving 20 bits noise perfor-
mance is a great deal more difficult than achieving 12 bits of
noise performance. In general, a system can be broken up
into four different stages:
+VIN – –VIN
• Analog Processing
A positive digital output is produced whenever the analog
input differential voltage is positive, while a negative digital
output is produced whenever the differential is negative. For
example, with a 4.096V reference and a gain setting of 2, a
positive full-scale output is produced when the analog input
differential is 2.048V. A negative full-scale output is pro-
duced when the differential voltage is –2.048V. In each case,
the actual input voltages must remain within the AGND to
VS range (see Table I).
• Analog Portion of the ADS1250
• Digital Portion of the ADS1250
• Digital Processing
For the simplest system consisting of minimal analog signal
processing (basic filtering and gain), a microcontroller, and
one clock source, high resolution can be achieved by pow-
ering all components by a common power supply. In addi-
tion, all components can share a common ground plane.
Thus, there would be no distinctions between “analog” or
“digital” power and ground. The layout should still include
a power plane, a ground plane, and careful decoupling. In
a more extreme case, the design could include: multiple
ADS1250s; extensive analog signal processing; one or more
microcontrollers, digital signal processors, or microproces-
sors; many different clock sources; and interconnections to
various other systems. High resolution will be very difficult
to achieve for this design. The approach would be to break
the system into as many different parts as possible. For
example, each ADS1250 may have its own “analog” pro-
cessing front end, its own analog power and ground (possi-
bly shared with the analog front end), and its own “digital”
power and ground. The converter’s “digital” power and
ground would be separate from the power and ground for the
system’s processors, RAM, ROM, and “glue” logic.
Actual Analog Input Voltage—The voltage at any one
analog input relative to AGND.
Full-Scale Range (FSR)—As with most A/D converters,
the full-scale range of the ADS1250 is defined as the “input”
which produces the positive full-scale digital output minus
the “input” which produces the negative full-scale digital
output. For example, with a 4.096V reference and a gain
setting of 2, the differential full-scale range is
2.048V – (–2.048V) = 4.096V.
Least Significant Bit (LSB) Weight—This is the theoreti-
cal amount of voltage that the differential voltage at the
analog input would have to change in order to observe a
change in the output data of one least significant bit. It is
computed as follows:
Full−ScaleRange
LSBWeight =
2N
DEFINITION OF TERMS
An attempt has been made to be consistent with the termi-
nology used in this data sheet. In that regard, the definition
of each term is given as follows:
where N is the number of bits in the digital output.
Conversion Cycle—The term conversion cycle, as used
here, refers to the time period between DRDY pulses.
Analog Input Differential Voltage—For an analog signal
that is fully differential, the voltage range can be compared
to that of an instrumentation amplifier. For example, if both
®
ADS1250
20
相关型号：
©2020 ICPDF网 联系我们和版权申明