ADS1202I [BB]
Motor Control Current Shunt 1-Bit, 10MHz, 2nd-Order, Delta-Sigma Modulator; 电机控制电流分流1位， 10MHz的， 2阶Δ-Σ调制器
| 型号： | ADS1202I |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Motor Control Current Shunt 1-Bit, 10MHz, 2nd-Order, Delta-Sigma Modulator |
| 文件： | 总21页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS1202
SBAS275 – DECEMBER 2002
Motor Control Current Shunt
1-Bit, 10MHz, 2nd-Order, Delta-Sigma Modulator
FEATURES
● 16-BIT RESOLUTION
DESCRIPTION
The ADS1202 is a precision, 80dB dynamic range, delta-
sigma (∆∑) modulator operating from a single +5V supply.
The differential inputs are ideal for direct connections to
transducers or low-level signals. With the appropriate digital
filter and modulator rate, the device can be used to achieve
16-bit Analog-to-Digital (A/D) conversion with no missing
codes. Effective resolution of 12 bits can be maintained with
a digital filter bandwidth of 10kHz at a modulator rate of
10MHz. The ADS1202 is designed for use in medium reso-
lution measurement applications including current measure-
ments, smart transmitters, industrial process control, weigh
scales, chromatography, and portable instrumentation. It is
available in a TSSOP-8 package.
● 13-BIT LINEARITY
● RESOLUTION/SPEED TRADE-OFF:
10-Bit Effective Resolution with 20µs Signal
Delay (12-bit with 77µs)
● ±250mV INPUT RANGE WITH SINGLE 5V SUPPLY
● 2% INTERNAL REFERENCE VOLTAGE
● 2% GAIN ERROR
● FLEXIBLE SERIAL INTERFACE WITH FOUR
DIFFERENT MODES
● IMPLEMENTED TWINNED BINARY CODING AS
SPLIT PHASE OR MANCHESTER CODING FOR
ONE LINE INTERFACING
● OPERATING TEMPERATURE RANGE:
–40°C to +85°C
APPLICATIONS
● MOTOR CONTROL
VIN+
MDAT
2nd-Order
● CURRENT MEASUREMENT
● INDUSTRIAL PROCESS CONTROL
● INSTRUMENTATION
∆∑ Modulator
VIN–
MCLK
Interface
Circuit
RC Oscillator
20MHz
VDD
M0
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTS
● WEIGHT SCALES
M1
GND
Reference
Voltage
2.5V
Buffer
● PRESSURE TRANSDUCERS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature (unless otherwise noted)(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Supply Voltage, GND to VDD ................................................. –0.3V to 6V
Analog Input Voltage Range ......................... GND – 0.4V to VDD + 0.3V
Digital Input Voltage Range .......................... GND – 0.3V to VDD + 0.3V
Power Dissipation ............................................................................ 0.25W
Operating Virtual Junction Temperature Range, TJ ........ –40°C to +150°C
Operating Free-Air Temperature Range, TA ....................–40°C to +85°C
Storage Temperature Range, TSTG ................................–65°C to +150°C
Lead Temperature 1.6mm (1/16") from Case for 10s .................. +260°C
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses beyond those listed under the Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond
those indicated under the Recommended Operating Conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
PACKAGE/ORDERING INFORMATION
MAXIMUM
INTEGRAL
LINEARITY
SPECIFIED
PACKAGE
MAXIMUM
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT ERROR (LSB) GAIN ERROR (%) PACKAGE-LEAD DESIGNATOR(1)
ADS1202
ADS1202
12
±2
TSSOP-8
PW
–40°C to +85°C
ADS1202I
ADS1202IPWT
ADS1202IPWR
Tape and Reel, 250
Tape and Reel, 2000
"
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PIN DESCRIPTIONS
PIN CONFIGURATION
PIN
Top View
TSSOP
NUMBER
NAME
DESCRIPTION
Mode Input
1
2
3
4
5
6
7
8
MO
M0
VIN+
VIN–
M1
1
2
3
4
8
7
6
5
VDD
VIN
+
Analog Input: Noninverting Input
Analog Input: Inverting Input
Mode Input
VIN
–
MCLK
MDAT
GND
ADS1202
M1
GND
MDAT
MCLK
VDD
Power Supply Ground
Modulator Data Output
Modulator Clock Input or Output
Power Supply, +5V Nominal
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
NOM
MAX
UNIT
Supply Voltage, VDD
4.75
–250
0
5.0
5.25
+250
5
V
mV
V
Analog Input Voltage, VIN
Operating Common-Mode Signal, VCM
External Clock(1)
8
10
12
MHz
°C
Operating Junction Temperature Range
–40
105
NOTE: (1) With reduced accuracy, minimum clock can go up to 500kHz.
DISSIPATION RATING
EQUIVALENT INPUT CIRCUIT
DERATING
TA < 25°C
POWER
RATING
FACTOR
ABOVE
TA = 70°C
POWER
RATING
TA = 85°C
POWER
RATING
AVDD
BVDD
C(SAMPLE) = 5pF
TA = 25°C(1)
RON = 350Ω
PACKAGE
AIN
DIN
TSSOP-8
483.6mW
3.868mW/°C
309.5mW
251.4mW
NOTE: (1) This is the inverse of the traditional junction-to-ambient thermal
resistance (RθJA). Thermal resistances are not production tested and are for
informational purposes only.
AGND
BGND
Diode Turn on Voltage: 0.35V
Equivalent Analog Input Circuit
Equivalent Digital Input Circuit
ADS1202
2
SBAS275
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ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at –40°C to +85°C, VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
ADS1202IPW
PARAMETER
RESOLUTION
CONDITIONS
MIN
TYP(1)
MAX
UNITS
16
Bits
DC ACCURACY
Integral Nonlinearity
INL
±3
0.005
±12
0.018
±1
±1000
8
LSB
%
LSB
µV
µV/°C
%
ppm/°C
dB
Differential Linearity(1)
Input Offset
Input Offset Drift
Gain Error
Gain Error Drift
Power-Supply Rejection Ratio
DNL
VOS
TCVOS
GERR
TCGERR
PSRR
±300
2
±0.25
20
±2
4.75V < VDD < 5.25V
80
ANALOG INPUT
Full-Scale Range
Operating Common-Mode Signal(2)
Input Capacitance
FSR
+In – (–In)
Common-Mode
Equivalent
±320
5
mV
V
–0.1
3
pF
nA
kΩ
pF
dB
dB
Input Leakage Current
±1
Differential Input Resistance
Differential Input Capacitance
Common-Mode Rejection Ratio(2)
28
5
90
85
CMRR
At DC
VIN = ±1.25Vp-p at 50kHz
INTERNAL VOLTAGE REFERENCE
Reference Voltage
Initial Accuracy
VOUT
Scale to 320mV
Scale to 320mV
2.450
2.5
2.550
±2+-+
V
%
Reference Temperature Drift
PSRR
dVOUT/dT
±20
80
ppm/°C
dB
Startup Time
0.1
ms
INTERNAL CLOCK FOR MODES, 0, 1, AND 2
Clock Frequency
8
10
20
12
24
MHz
MHz
EXTERNAL CLOCK FOR MODE 3
Clock Frequency
16
AC ACCURACY
Signal-to-Noise Ratio + Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range
SINAD
SNR
THD
VIN = ±250mVp-p at 5kHz
VIN = ±250mVp-p at 5kHz
VIN = ±250mVp-p at 5kHz
VIN = ±250mVp-p at 5kHz
70
70.5
–84
84
dB
dB
dB
dB
67
SFDR
DIGITAL INPUT
Logic Family
TTL with Schmitt Trigger
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CJ
2.6
–0.3
VDD + 0.3
0.8
V
V
µA
µA
pF
VI = VDD
VI = GND
0.005
0.005
5
2.5
–2.5
DIGITAL OUTPUT
High-Level Digital Output
VOH
VOL
VDD = 4.5V, IO = –5mA
VDD = 4.5V, IO = –15mA
VDD = 4.5V, IO = 5mA
VDD = 4.5V, IO = 15mA
4.6
3.9
V
V
V
Low-Level Digital Output
0.4
1.1
V
Output Capacitance
Load Capacitance
CO
CL
5
pF
pF
30
POWER SUPPLY
Supply Voltage
Operating Supply Current
VDD
ICC
4.5
5
6
8
30
40
5.5
7.5
9.5
37.5
47.5
V
Mode 0
Mode 3
VDD = 5V, Mode 0
VDD = 5V, Mode 3
mA
mA
mW
mW
Power Dissipation
OPERATING TEMPERATURE
–40
+85
°C
NOTES: (1) All typical values are at TA = +25°C. (2) Ensured by design. (3) Integral nonlinearity is defined as one-half the peak-to-peak deviation of the best fit
line through the transfer curve for VIN+ = –250mV to +250mV, expressed either as the number of LSBs or as a percent of measured input range (500mV). (4) Only
typical information parameter not tested.
ADS1202
3
SBAS275
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TIMING DIAGRAMS
tC1
MCLK
MDAT
tW1
tD1
DIAGRAM 1: Mode 0 Operation.
tC2
MCLK
MDAT
tD2
tD3
tW2
DIAGRAM 2: Mode 1 Operation.
tC1
MCLK
MDAT
tw1
tC3
tw3
1
0
1
1
0
0
DIAGRAM 3: Mode 2 Operation.
ADS1202
4
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TIMING DIAGRAMS (Cont.)
tC4
MCLK
MDAT
tw4
tD4
DIAGRAM 4: Mode 3 Operation.
TIMING CHARACTERISTICS
over recommended operating free-air temperature range –40°C to +85°C, VDD = 5V, and MCLK = 10MHz, unless otherwise noted.
SPEC
DESCRIPTION
MODE
MIN
MAX
UNITS
tC1
tW1
tD1
tC2
tW2
tD2
tD3
tC3
tW3
tC4
tW4
tD4
tR1
tF1
Clock Period
0
0
0
1
1
1
1
2
2
3
3
3
3
3
90
tC1/2 – 5
tC1/4 – 10
180
110
tC1/2 + 5
tC1/4 + 10
220
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock HIGH Time
Data delay after rising edge of clock
Clock Period
Clock HIGH Time
tC2/2 – 5
tC2/4 – 10
tC2/4 – 10
90
tC2/2 + 5
tC2/4 + 10
tC2/4 + 10
110
Data delay after rising edge of clock
Data delay after falling edge of clock
Clock Period
Clock HIGH Time
tC3/2 – 5
45
tC3/2 + 5
55
Clock Period
Clock HIGH Time
10
tC4 – 10
10
Data delay after falling edge of clock
Rise Time of Clock
0
0
10
Fall Time of Clock
0
10
NOTE: All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams 1 thru 4.
ADS1202
5
SBAS275
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TYPICAL CHARACTERISTICS
VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
INTEGRAL NONLINEARITY vs INPUT SIGNAL (Mode 3)
INTEGRAL NONLINEARITY vs INPUT SIGNAL (Mode 0)
2
2
1
0
1
0
25°C
–1
–1
–2
–3
–4
–5
–2
–3
–4
–5
–6
–7
–40°C
25°C
+85°C
+85°C
–40°C
–320 –240 –160 –80
0
80
160
240
320
–320 –240 –160 –80
0
80
160
240
320
100
100
Differential Input Voltage (mV)
Differential Input Voltage (mV)
INTEGRAL NONLINEARITY vs TEMPERATURE
INTEGRAL NONLINEARITY vs TEMPERATURE
7
6
5
4
3
2
1
0
0.010
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
Mode 0
Mode 0
Mode 3
Mode 3
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
OFFSET vs TEMPERATURE
GAIN vs TEMPERATURE
300
200
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
Mode 3
100
0
–100
–200
–300
–400
–500
–600
–700
Mode 3
Mode 0
Mode 0
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
ADS1202
6
SBAS275
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TYPICAL CHARACTERISTICS (Cont.)
VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
RMS NOISE vs INPUT VOLTAGE LEVEL
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
Mode 0
80
70
60
50
40
30
20
10
0
71.0
70.8
70.6
70.4
70.2
70.0
69.8
69.6
69.4
69.2
69.0
Mode 3
–320 –240 –160 –80
0
80
160
240
320
100
100
–40
–20
0
20
40
60
80
100
Differential Input Voltage (mV)
Temperature (°C)
SIGNAL-TO-NOISE + DISTORTION
vs TEMPERATURE
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
71.0
70.6
70.2
69.8
69.4
69.0
16
14
12
10
8
Sinc3 Filter
Mode 3
Sinc2 Filter
Mode 0
6
4
–40
–20
0
20
40
60
80
0
400
800
1200
1600
2000
Temperature (°C)
Decimation Ratio (OSR)
SPURIOUS-FREE DYNAMIC RANGE
AND TOTAL HARMOINIC DISTORTION
vs TEMPERATURE (Mode 3)
SPURIOUS-FREE DYNAMIC RANGE
AND TOTAL HARMOINIC DISTORTION
vs TEMPERATURE (Mode 0)
95
93
91
89
87
85
83
81
79
77
75
–95
95
93
91
89
87
85
83
81
79
77
75
–95
–93
–91
–89
–87
–85
–83
–81
–79
–77
–75
0.5Vp-p
5kHz
–93
–91
–89
–87
–85
–83
–81
–79
–77
–75
SFDR
THD
SFDR
THD
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
Temperature (°C)
Temperature (°C)
ADS1202
7
SBAS275
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TYPICAL CHARACTERISTICS (Cont.)
VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
SPURIOUS-FREE DYNAMIC RANGE
AND TOTAL HARMOINIC DISTORTION
vs INPUT FREQUENCY (Mode 0)
SPURIOUS-FREE DYNAMIC RANGE
AND TOTAL HARMOINIC DISTORTION
vs INPUT FREQUENCY (Mode 3)
110
100
90
–110
–100
–90
–80
–70
–60
–50
110
100
90
–110
–100
–90
–80
–70
–60
–50
SFDR
THD
SFDR
THD
80
80
70
70
OSR = 256
Sinc3 Filter
OSR = 256
Sinc3 Filter
60
60
50
50
1
10
1
10
Input Frequency (kHz)
Input Frequency (kHz)
FREQUENCY SPECTRUM
FREQUENCY SPECTRUM
(4096 Point FFT, fIN = 1kHz, 0.5Vp-p)
(4096 Point FFT, fIN = 5kHz, 0.5Vp-p)
0
0
Mode 0
Mode 0
–20
–40
–20
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
Frequency (kHz)
Frequency (kHz)
COMMON-MODE REJECTION RATIO
vs FREQUENCY
CLOCK FREQUENCY vs TEMPERATURE
10.5
10.2
9.9
100
95
90
85
80
75
70
65
60
55
50
9.6
9.3
9.0
–40
–20
0
20
40
60
80
100
120
1
10
100
Temperature (°C)
Frequency of Power Supply (Hz)
ADS1202
8
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TYPICAL CHARACTERISTICS (Cont.)
VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
POWER-SUPPLY REJECTION RATIO
vs FREQUENCY
HISTOGRAM OF OUTPUT DATA
90
85
80
75
70
65
60
55
50
2000
1800
1600
1400
1200
1000
800
600
400
200
0
100
1k
10k
100k
Frequency of Power Supply (Hz)
ppm of FS
MCLK AND MDAT
TYPICAL SINK CURRENT
POWER-SUPPLY CURRENT vs TEMPERATURE
Mode 0
70
60
50
40
30
20
10
0
10
5.5V
9
8
7
6
5
4
3
2
1
0
5V
Mode 3
4.5V
0
1
2
3
4
5
6
–40
–20
0
20
40
60
80
100
Output Voltage VOL (V)
Temperature (°C)
MCLK AND MDAT
TYPICAL SOURCE CURRENT
80
70
60
50
40
30
20
10
0
5.5V
5V
4.5V
0
1
2
3
4
5
6
Output Voltage VOH (V)
ADS1202
9
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THEORY OF OPERATION
GENERAL DESCRIPTION
The differential analog input of the ADS1202 is implemented
with a switched capacitor circuit. This switched capacitor
circuit implements a 2nd-order modulator stage, which digi-
tizes the input signal into a 1-bit output stream. The sample
clock (MCLK) provides the switched capacitor network and
modulator clock signal for the A/D conversion process, as
well as the output data-framing clock. The clock source can
be internal as well as external. Different frequencies for this
clock allow for a variety of solutions and signal bandwidths
(however, this can only be utilized in mode 3). The analog
input signal is continuously sampled by the modulator and
compared to an internal voltage reference. A digital stream,
which accurately represents the analog input voltage over
time, appears at the output of the converter.
The ADS1202 is a single-channel, 2nd-order, CMOS analog
modulator designed for medium to high resolution conver-
sions from DC to 39kHz with an oversampling ratio (OSR) of
256. The output of the converter (MDAT) provides a stream
of digital ones and zeros. The time average of this serial
output is proportional to the analog input voltage. The com-
bination of an ADS1202 and a Digital Signal Processor
(DSP) that is programmed to implement a digital filter results
in a medium resolution A/D converter system. This system
allows flexibility with the digital filter design and is capable of
A/D conversion results that have a dynamic range that
exceeds 85dB with OSR = 256.
+5V
+5V
DSP
VDDO
M
0.1µF
ADS1202
10nF
M0
VDD
27Ω
SPICLK
VIN
VIN
M1
+
MCLK
MDAT
GND
SPISIMO
VSSO
–
27Ω
0.1µF
0.1µF
FIGURE 1. Connection Diagram for the ADS1202 Delta-Sigma Modulator Including DSP.
ADS1202
10
SBAS275
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the linearity of the device is ensured only when the analog
voltage applied to either input resides within the range defined
by –320mV and +320mV.
ANALOG INPUT STAGE
Analog Input
The input design topology of the ADS1202 is based on a fully
differential switched-capacitor architecture. This input stage
provides the mechanism to achieve low system noise, high
common-mode rejection (90dB), and excellent power-supply
rejection. The input impedance of the analog input is depen-
dant on the input capacitor and modulator clock frequency
(MCLK), which is also the sampling frequency of the modu-
lator. Figure 2 shows the basic input structure of the ADS1202.
The relationship between the input impedance of the ADS1202
and the modulator clock frequency is:
Modulator
The modulator sampling frequency (CLK) can be operated
over a range of a few MHz to 12MHz in mode 3. The
frequency of MCLK can be decreased to adjust for the clock
requirements of the application. The external MCLK must
have double the modulator frequency.
The modulator topology is fundamentally a 2nd-order, charge-
balancing A/D converter, as the one conceptualized in Figure 3.
The analog input voltage and the output of the 1-bit Digital-to-
Analog Converter (DAC) are differentiated, providing an analog
voltage at X2 and X3. The voltage at X2 and X3 are presented
to their individual integrators. The output of these integrators
progress in a negative or positive direction. When the value of
the signal at X4 equals the comparator reference voltage, the
output of the comparator switches from negative to positive, or
positive to negative, depending on its original state. When the
output value of the comparator switches from HIGH to LOW or
vice versa, the 1-bit DAC responds on the next clock pulse by
changing its analog output voltage at X6, causing the integrators
to progress in the opposite direction. The feedback of the
modulator to the front end of the integrators forces the value of
the integrator output to track the average of the input.
1012
AIN Ω =
(
)
(1)
7 • fMCLK(MHz)
The input impedance becomes a consideration in designs
where the source impedance of the input signal is HIGH. In
this case, it is possible for a portion of the signal to be lost
across this external source impedance. The importance of this
effect depends on the desired system performance. There are
two restrictions on the analog input signal to the ADS1202.
Under no conditions should the current into or out of the
analog inputs exceed 10mA. The absolute input voltage range
must stay in the range GND – 0.4V to VDD + 0.3V. If either of
the inputs exceed these limits, the input protection diodes on
the front end of the converter will begin to turn on. In addition,
RSW
350kΩ (typ)
High
Impedance
> 1GΩ
AIN
+
CINT
7pF (typ)
1.5pF
1.5pF
Switching Frequency
= CLK
VCM
CINT
7pF (typ)
RSW
350kΩ (typ)
High
Impedance
> 1GΩ
AIN
–
FIGURE 2. Input Impedance of the ADS1202.
fCLK
X2
X3
X4
X(t)
Integrator 1
Integrator 2
DATA
fS
VREF
Comparator
X6
D/A Converter
FIGURE 3. Block Diagram of the 2nd-Order Modulator.
ADS1202
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DIGITAL OUTPUT
ods can be used to obtain this synchronization. The first
method has the delta-sigma modulator and the filter receive
the clock signal from the master clock. The second method
has the delta-sigma modulator transmit the clock signal
together with the data signal. The third method has the filter
derivate the clock signal from the received waveform itself.
The timing diagram for the ADS1202 data retrieval is shown
in the Timing Diagrams. When an external clock is applied to
MCLK, it is used as a system clock by the ADS1202, as well
as a framing clock for data out (this procedure, however, can
only be utilized in mode 3). The modulator output data, which
is a serial stream, is available on the MDAT pin. Typically,
MDAT is read on the falling edge of MCLK.
An ideal solution is a delta-sigma modulator with a flexible
interface, such as the ADS1202, which can provide flexible
output format on the output lines MCLK and MDAT, thus
covering different modes of operation. The signal type that
can be provided is selected with control signals M0 and M1.
An input differential signal of 0V will ideally produce a stream
of ones and zeros that are HIGH 50% of the time and LOW
50% of the time. A differential input of 256mV will produce a
stream of ones and zeros that are HIGH 80% of the time. A
differential input of –256mV will produce a stream of ones
and zeros that are HIGH 20% of the time. The input voltage
versus the output modulator signal is shown in Figure 4.
FLEXIBLE DELTA-SIGMA INTERFACE
Figure 5 illustrates the flexible interface of the ADS1202
delta-sigma converter. The control signals M0 and M1 are
entered in the decoder that decodes the input code and
selects the desired mode of operation. Five output signals
from the decoder control the RC oscillator, multiplexer MUX1,
multiplexer MUX2, multiplexer MUX3, and multiplexer MUX4.
DIGITAL INTERFACE
INTRODUCTION
The analog signal that is connected to the input of the delta-sigma
modulator is converted using the clock signal (CLK) applied to the
modulator. The result of the conversion, or modulation, is the
output signal DATA from the delta-sigma modulator.
MUX1 is controlled by the decoder signal. When the internal
RC oscillator is used, the control signal from the decoder
enables the RC oscillator. At the same time, MUX1 uses the
INTCLK signal as a source for the output signal from MUX1,
which is entering the code generator. If the external clock is
used, the control signal from the decoder disables the inter-
nal RC oscillator and the control signal from the decoder, and
positions MUX1 so that EXTCLK provides the output signal
from MUX1 as the input in the code generator.
In most applications where direct connection is realized
between delta-sigma modulator and DSP or uC, two stan-
dard signals are provided. The MDAT and MCLK signals
provide the easiest means of connection. If it is required to
reduce the number of connection lines, having two signals is
sometimes not an optimal solution.
MUX2 selects the output clock, OCLK. The control signal
coming from the decoder controls the output clock. Two
signals come from the code generator as a half clock fre-
quency, CLK/2, and as a quarter clock frequency, CLK/4,
and provide MUX2 with the input signal. The control signal
will select two different output modes on the OCLK signal as
half clock or quarter clock.
The receiver, DSP, or other control circuit must sample the
output data signal from the modulator at the precise sampling
instant. To do this, sampling a clock signal at the receiver is
needed in order to synchronize with the clock signal at the
transmitter. The delta-sigma modulator clock signal, receiver,
filter, and clock must be synchronized. Three general meth-
Modulator Output
+FS (Analog Input)
–FS (Analog Input)
Analog Input
FIGURE 4. Analog Input Versus Modulator Output of the ADS1201.
ADS1202
12
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Interface Circuit
M0
M1
Decoder
MUX1
INTCLK
EXTCLK
RC
Oscillator
MUX3
Code
Generator
MUX4
MUX2
CLK/2
CLK/4
MDAT
MCLK
OCLK
CLK
DATA
∆∑
Modulator
AIN
FIGURE 5. Flexible Interface Block Diagram.
The code generator receives the clock signal from MUX1 and
generates the delta-sigma modulator clock (CLK) divided as
half clock (CLK/2) and quarter clock (CLK/4). At the same
time, the continuous data stream (DATA) coming from the
delta-sigma modulator is elaborated by the Code Generator.
Twinned binary coding (also known as split phase or Manches-
ter coding) is implemented and then output from the code
generator to MUX3.
The control signal from the decoder can select two different
modes on MCLK, one as an output of the internal clock signal
and another as the input for the external clock signal.
As a function of two control signals (M0 and M1), the decoder
circuit, using five control signals, will set multiplexers in order
to obtain the desired mode of operation.
DIFFERENT MODES OF OPERATION
MUX3 selects the source of the output bit stream data,
MDAT. The control signal coming from the decoder controls
the input source of MDAT. Two signals are coming in to the
MUX3, one directly from the delta-sigma modulator and the
other from the code generator. The control signal from the
decoder can select two different output modes on the signal
MDAT: bit stream from a delta-sigma modulator or twinned
binary coding of the same signal.
Figure 5 presents mode selectors (input signals M0 and M1)
that enter the flexible interface circuit and decoder that
decodes the input code, and select the desired mode of
operation. With two control lines it is possible to select four
different modes of operation mode 0, mode 1, mode 2, and
mode 3, which are shown in Table I.
MODE DEFINITION
M1
MO
The last control signal from the decoder controls MUX4.
MUX2 selects the input or output clock, the MCLK signal.
The control signal coming from the decoder controls the
direction of the clock. One signal entering MUX4 from MUX2
comes as a clock signal OCLK. Another signal leaves MUX4
and provides an input to MUX1 as an external clock, EXTCLK.
0
1
Internal Clock, Synchronous Data Output
LOW
LOW
LOW
HIGH
Internal Clock, Synchronous Data Output,
Half Output Clock Frequency
2
3
Internal Clock, Manchester Coded Data Output HIGH
External Clock, Synchronous Data Output
LOW
HIGH HIGH
TABLE I. Mode Definition and Description.
ADS1202
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Mode 0
Mode 1
In mode 0 both input signals, M0 and M1, are LOW. The
control signal coming from the decoder enables the internal
RC oscillator that provides the clock signal INTCLK as an
input to MUX1. The control signal coming from the decoder
also positions MUX1 so that the output signal, which is an
input signal for the code generator, is INTCLK. Another
control signal from the decoder circuit positions MUX3 so
that the source for the output signal MDAT is the signal
arriving directly from the delta-sigma modulator, DATA. MUX2
is positioned for the mode controlled by the signal coming
from the decoder so output signal OCLK is CLK/2. The signal
timings for mode 0 operation are presented in Figure 6. In
this mode, DSP or µC read MDAT data on every rising edge
of the MCLK output clock.
In mode 1, the input signal M0 is HIGH and M1 is LOW (see
Table I). The first control signal coming from the decoder
enables the internal RC oscillator that provides clock signal
INTCLK as an input to MUX1. The second control signal
coming from the decoder positions MUX1 so that the output
signal that is the input signal to the code generator is
INTCLK. The output signal from the delta-sigma modulator,
DATA, is also the MDAT signal coming from the modulator
because the control signal from the decoder positions MUX3
for that operation. MUX2 is positioned for the mode con-
trolled by the control signal coming from the decoder with an
OCLK of CLK/2. Output clock signal MCLK comes through
MUX4 from MUX2 as OCLK or CLK/2. The signal timings for
mode 1 operation are presented in Figure 7. In this mode,
DSP or µC read data on every edge, rising and falling, of the
output clock.
CLK
DATA
MCLK
MDAT
FIGURE 6. Signal Timing in Mode 0.
CLK
DATA
MCLK
MDAT
FIGURE 7. Signal Timing in Mode 1.
14
ADS1202
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Mode 2
Mode 3
In mode 2, M0 is low and M1 is HIGH (see Table I). The control
signal coming from the decoder enables the internal RC oscil-
lator that provides the clock signal INTCLK as an input to MUX1.
Another control signal coming from the decoder positions MUX1
so that the output signal that is the input signal to the code
generator is INTCLK. The output signal MDAT comes from the
code generator because the control signal from the decoder
positions MUX3 for that operation. The DATA signal coming
from the delta-sigma modulator enters the code generator,
where it combines with the clock signal, and twinned binary
coding is implemented as split phase or Manchester coding,
providing the output signal for MUX3. The MCLK output clock
is not active, as multiplexers MUX2 and MUX4 are positioned
for this mode controlled by the control signals coming from the
decoder. The signals timings for mode 2 operation are pre-
sented in Figure 8. In this mode, DSP or µC need to derive the
clock signal from the received waveform itself. Different clock
recovery networks can be implemented.
mode 3 is similar to mode 0; the only difference is that an
external clock (EXTCLK) is provided. In mode 3, both input
signals M0 and M1 are HIGH (see Table I). The control
signal coming from the decoder disables the internal RC
oscillator. The input signal EXTCLK provides the clock
signal as an input to MUX1. The control signal coming from
the decoder positions MUX1 so that the output signal that
is the input signal to the code generator is EXTCLK. The
output signal MDAT is the DATA signal coming directly from
the delta-sigma modulator because the control signal from
the decoder positions MUX3 for that operation. The signal
timings for mode 3 operation are presented in Figure 9. In
this mode, DSP or µC read data on every falling edge of the
input clock.
CLK
DATA
MCLK
MDAT
FIGURE 8. Signal Timing in Mode 2.
MCLK
CLK
DATA
MDAT
FIGURE 9. Signal Timing in Mode 3.
ADS1202
15
SBAS275
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The DSP can be directly connected at the output of two
channels of the optocoupler, C28x or C24x. In this configu-
ration, the signals arriving at C28x or C24x are standard
delta-sigma modulator signals and are connected directly to
the SPICLK and SPISIMO pins. Being a delta-sigma con-
verter, there is no need to have word synch on the serial
data, so SPI is ideal for connection. McBSP would work as
well in SPI mode.
APPLICATIONS
Mode 0 operation in a typical application is shown in Figure
10. Measurement of the motor phase current is done via the
shunt resistor. For better performance, both signals are
filtered. R2 and C2 filter noise on the noninverting input
signal, R3 and C3 filter noise on the inverting input signal, and
C4 in combination with R2 and R3 filter the common-mode
input noise. In this configuration, the shunt resistor is con-
nected via three wires with the ADS1202.
When component reduction is necessary, the ADS1202 can
operate in mode 2, as shown in Figure 11. M1 is HIGH and
M0 is LOW. Only the noninverting input signal is filtered.
R2 and C2 filter noise on the input signal. The inverting input
is directly connected to the GND pin, which is simultaneously
connected to the shunt resistor.
The power supply is taken from the upper gate driver power
supply. A decoupling capacitor of 0.1µF is recommended for
filtering the power supply. If better filtering is required, an
additional 1µF to 10µF capacitor can be added.
The control lines M0 and M1 are both LOW while the part is
operating in mode 0. Two output signals, MCLK and MDAT,
are connected directly to the optocoupler. The optocoupler
can be connected to transfer a direct or inverse signal
because the output stage has the capacity to source and sink
the same current. The discharge resistor is not needed in
parallel with optocoupler diodes because the output driver
has the capacity to keep the LED diode out of the charge.
The output signal from the ADS1202 is Manchester coded. In
this case, only one signal is transmitted. For that reason, one
optocoupler channel is used instead of two channels, as in
the previous example of Figure 10. Another advantage of this
configuration is that the DSP will use only one line per
channel instead of two. That permits the use of smaller DSP
packages in the application.
Floating
Power Supply
HV+
Gated
Drive Circuit
R1
C28x
or
C24x
R5
Optocoupler
D1
5.1V
C1
0.1µF
ADS1202
M0 VDD
R4
C4
10nF
R2
27Ω
SPICLK
VIN
VIN
M1
+
MCLK
MDAT
GND
–
SPISIMO
RSENSE
R3
27Ω
C2
0.1µF
C3
0.1µF
Power
Supply
Gated
Drive Circuit
HV–
FIGURE 10. Application Diagram in Mode 0.
ADS1202
16
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Floating
Power Supply
HV+
Gated
Drive Circuit
R1
D1
5.1V
C1
0.1µF
ADS1202
M0 VDD
R4
R2
27Ω
Optocoupler
C28x
or
C24x
VIN
VIN
M1
+
MCLK
MDAT
GND
–
C2
0.1µF
RSENSE
Power
Supply
Gated
Drive Circuit
HV–
FIGURE 11. Application Diagram in Mode 2.
Floating
Power Supply
HV+
C28x
or
Gate Drive
Circuit
C24x
CVDD
C1
0.1µF
ADS1202
VDD
R2
27Ω
M0
SPICLK
MCLK
MDAT
GND
VIN
VIN
M1
+
+
SPISIMO
–
C2
0.1µF
RSENSE
–
DVDD
FIGURE 12. Application Diagram without Galvanical Isolation in Mode 0.
ADS1202
17
SBAS275
www.ti.com
C4
0.1µF
ADS1202
VDD
R1
27Ω
M0
VIN
+
MCLK
MDAT
GND
+
VIN
–
C1
0.1µF
RSENSE
M1
–
C5
0.1µF
ADS1202
VDD
R2
27Ω
M0
VIN
+
MCLK
MDAT
GND
+
VIN
–
C2
0.1µF
RSENSE
M1
–
C28x
or
C24x
CVDD
C6
0.1µF
ADS1202
VDD
R3
27Ω
M0
VIN
SPICLK
SPISIMO
SPISIMO
SPISIMO
DVDD
+
MCLK
MDAT
GND
+
VIN
–
C3
0.1µF
RSENSE
M1
–
CLK
FIGURE 13. Parallel Operation of ADS1202 in Mode 3.
input current. Experimentation may be the best way to
determine the appropriate connection between the ADS1202
and different power supplies.
LAYOUT CONSIDERATIONS
POWER SUPPLIES
The ADS1202 requires only one power supply (VDD). If there
are separate analog and digital power supplies on the board,
a good design approach is to have the ADS1202 connected
to the analog power supply. Another approach to control the
noise is the use of a resistor on the power supply. The
connection can be made between the ADS1202 power-
supply pins via a 10Ω resistor. The combination of this
resistor and the decoupling capacitors between the power-
supply pins on the ADS1202 provide some filtering. The
analog supply that is used must be well regulated and low
noise. For designs requiring higher resolution from the
ADS1202, power-supply rejection will be a concern. The
digital power supply has high-frequency noise that can be
capacitively coupled into the analog portion of the ADS1202.
This noise can originate from switching power supplies,
microprocessors, or digital signal processors. High-frequency
noise will generally be rejected by the external digital filter at
integer multiples of MCLK. Just below and above these
frequencies, noise will alias back into the passband of the
digital filter, affecting the conversion result. Inputs to the
ADS1202, such as VIN+, VIN–, and MCLK should not be
present before the power supply is on. Violating this condi-
tion could cause latch-up. If these signals are present before
the supply is on, series resistors should be used to limit the
GROUNDING
Analog and digital sections of the design must be carefully
and cleanly partitioned. Each section should have its own
ground plane with no overlap between them. Do not join the
ground planes, but connect the two with a moderate signal
trace underneath the converter. For multiple converters,
connect the two ground planes as close as possible to one
central location for all of the converters. In some cases,
experimentation may be required to find the best point to
connect the two planes together.
DECOUPLING
Good decoupling practices must be used for the ADS1202
and for all components in the design. All decoupling capaci-
tors, specifically the 0.1µF ceramic capacitors, must be
placed as close as possible to the pin being decoupled. A
1µF and 10µF capacitor, in parallel with the 0.1µF ceramic
capacitor, must be used to decouple VDD to GND. At least
one 0.1µF ceramic capacitor must be used to decouple VDD
to GND, as well as for the digital supply on each digital
component.
ADS1202
18
SBAS275
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PACKAGE DRAWING
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
ADS1202
19
SBAS275
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
1
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