HSMP-389R-TR2G [AVAGO]
100V, SILICON, PIN DIODE, LEAD FREE PACKAGE-6;型号: | HSMP-389R-TR2G |
厂家: | AVAGO TECHNOLOGIES LIMITED |
描述: | 100V, SILICON, PIN DIODE, LEAD FREE PACKAGE-6 开关 测试 光电二极管 |
文件: | 总13页 (文件大小:286K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HSMP-389x Series, HSMP-489x Series
Surface Mount RF PIN Switch Diodes
Data Sheet
Description/Applications
Features
TheꢀHSMP-389xꢀseriesꢀisꢀoptimizedꢀforꢀswitchingꢀappli- •ꢀ UniqueꢀConfigurationsꢀinꢀSurfaceꢀMountꢀPackages
cationsꢀwhereꢀlowꢀresistanceꢀatꢀlowꢀcurrentꢀandꢀlowꢀca-
ꢀ
ꢀ
ꢀ
–ꢀAddꢀFlexibility
–ꢀSaveꢀBoardꢀSpace
–ꢀReduceꢀCost
pacitanceꢀareꢀrequired.ꢀTheꢀHSMP-489xꢀseriesꢀproductsꢀ
featureꢀ ultraꢀ lowꢀ parasiticꢀ inductance.ꢀTheseꢀ productsꢀ
areꢀ specificallyꢀ designedꢀ forꢀ useꢀ atꢀ frequenciesꢀ whichꢀ
areꢀmuchꢀhigherꢀthanꢀtheꢀupperꢀlimitꢀforꢀconventionalꢀ
PINꢀdiodes.
•ꢀ Switching
ꢀ
–ꢀLowꢀCapacitance
Pin Connections and Package Marking
ꢀ
–ꢀLowꢀResistanceꢀatꢀLowꢀCurrent
•ꢀ LowꢀFailureꢀinꢀTimeꢀ(FIT)ꢀRate[1]
•ꢀ MatchedꢀDiodesꢀforꢀConsistentꢀPerformance
1
2
6
5
4
•ꢀ BetterꢀThermalꢀConductivityꢀforꢀHigherꢀPowerꢀ
Dissipation
•ꢀ Lead-free
Note:
1.ꢀ ForꢀmoreꢀinformationꢀseeꢀtheꢀSurfaceꢀMountꢀPINꢀReliabilityꢀDataꢀ
Sheet.
3
Notes:
1.ꢀ Packageꢀmarkingꢀprovidesꢀorientation,ꢀidentification,ꢀandꢀdateꢀ
code.
2.ꢀ Seeꢀ“ElectricalꢀSpecifications”ꢀforꢀappropriateꢀpackageꢀmarking.
Package Lead Code Identification,
SOT-23/143
Package Lead Code Identification,
SOT-323
Package Lead Code Identification,
SOT-363
(Top View)
(Top View)
(Top View)
UNCONNECTED
TRIO
SERIES
SERIES
DUAL SWITCH
MODEL
SINGLE
SINGLE
6
1
5
4
6
1
5
4
#0
#2
B
C
2
3
2
3
R
L
COMMON
ANODE
COMMON
CATHODE
COMMON
ANODE
COMMON
CATHODE
LOW
INDUCTANCE
SINGLE
SERIES–
SHUNT PAIR
6
1
5
4
6
1
5
4
E
F
#3
#4
2
3
2
3
DUAL ANODE
UNCONNECTED
PAIR
T
U
DUAL ANODE
HIGH
FREQUENCY
SERIES
6
1
5
4
489B
4890
#5
RING
2
3
QUAD
V
3
4
2
1
#7
UNDER DEVELOPMENT
Absolute Maximum Ratings[1] TC = +25°C
Symbol
Ifꢀ
Parameter
Unit
Ampꢀ
Vꢀ
SOT-23/143
1ꢀ
SOT-323/363
ForwardꢀCurrentꢀ(1ꢀµsꢀPulse)ꢀ
PeakꢀInverseꢀVoltageꢀ
JunctionꢀTemperatureꢀ
StorageꢀTemperatureꢀ
ThermalꢀResistance[2]ꢀ
1
100
PIVꢀ
100ꢀ
Tjꢀ
°Cꢀ
150ꢀ
150
Tstgꢀ
θjcꢀ
°Cꢀ
-65ꢀtoꢀ150ꢀ
500ꢀ
-65ꢀtoꢀ150
150
°C/Wꢀ
Notes:
1.ꢀ Operationꢀinꢀexcessꢀofꢀanyꢀoneꢀofꢀtheseꢀconditionsꢀmayꢀresultꢀinꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.
2.ꢀ TCꢀ=ꢀ+25°C,ꢀwhereꢀTCꢀisꢀdefinedꢀtoꢀbeꢀtheꢀtemperatureꢀatꢀtheꢀpackageꢀpinsꢀwhereꢀcontactꢀisꢀmadeꢀtoꢀtheꢀcircuitꢀboard.
ESD WARNING:
Handling Precautions Should Be Taken To Avoid Static Discharge.
2
TestꢀConditionsꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
VRꢀ=ꢀVBRꢀ
Measureꢀ
IRꢀꢀ10ꢀµAꢀ
IFꢀ=ꢀ5ꢀmAꢀ
fꢀ=ꢀ1ꢀMHzꢀ
VRꢀ=ꢀ5 Vꢀ
ꢀ
VRꢀ=ꢀ5ꢀVꢀ
fꢀ=ꢀ1ꢀMHzꢀ
ꢀ
f=500ꢀMHz–
3ꢀGHz
ꢀ
ꢀ
ꢀ
ꢀ
TestꢀConditionsꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
VRꢀ=ꢀV
IFꢀ=ꢀ5ꢀmAꢀ
fꢀ=ꢀ100ꢀMHzꢀ
ꢀ
VRꢀ=ꢀ5ꢀV
fꢀ=ꢀ1ꢀMHz
Electrical Specifications, TC = 25°C, each diode
Package
Minimum
Breakdown
Voltage VBR (V)
Maximum
Series Resistance
RS (ý)
Maximum
Total Capacitance
CT (pF)
Part Number
HSMP-
Marking Lead
Code
Code Configuration
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
3890ꢀ
3892ꢀ
3893ꢀ
3894ꢀ
3895ꢀ
389Bꢀ
389Cꢀ
389Eꢀ
389Fꢀ
389Lꢀ
389Rꢀ
389Tꢀ
389Uꢀ
389Vꢀ
G0[1]ꢀ
G2[1]ꢀ
G3[1]ꢀ
G4[1]ꢀ
G5[1]ꢀ
G0[2]ꢀ
G2[2]ꢀ
G3[2]ꢀ
G4[2]ꢀ
GL[2]ꢀ
S[2]ꢀ
0ꢀ
2ꢀ
3ꢀ
4ꢀ
5ꢀ
Bꢀ
Cꢀ
Eꢀ
Fꢀ
Lꢀ
Rꢀ
Tꢀ
Uꢀ
Vꢀ
Singleꢀ
100ꢀ
2.5ꢀ
0.30
Series
CommonꢀAnode
CommonꢀCathode
UnconnectedꢀPair
Single
Series
CommonꢀAnode
CommonꢀCathode
UnconnectedꢀTrio
DualꢀSwitchꢀMode
LowꢀInductanceꢀSingle
Series-ShuntꢀPair
HighꢀFrequencyꢀSeriesꢀPair
Z[2]ꢀ
GU[2]ꢀ
GV[2]ꢀ
ꢀ
ꢀ
MeasuBrReꢀ ꢀ
IRꢀꢀ10ꢀµAꢀ
Notes:
1.ꢀ Packageꢀmarkingꢀcodeꢀisꢀwhite.
2.ꢀ Packageꢀisꢀlaserꢀmarked.ꢀ
ꢀ
High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes
Minimum
Maximum
Typical
Total
Capacitance
C T (pF)
Maximum
Typical
Total
Inductance
LT (nH)
Part
Number
HSMP-
Package
Marking
Code[1]
Breakdown
Voltage
VBR (V)
Series
Resistance
RS (ý)
Total
Capacitance
CT (pF)
Configuration
ꢀ
ꢀ
489xꢀ
GAꢀ
DualꢀAnodeꢀ
100ꢀ
2.5ꢀ
0.33ꢀ
0.375ꢀ
1.0
ꢀꢀꢀꢀ ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Note:
1.ꢀ SOT-23ꢀpackageꢀmarkingꢀcodeꢀisꢀwhite;ꢀSOT-323ꢀisꢀlaserꢀmarked.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Typical Parameters at TC = 25°C
Part Number
HSMP-
Series Resistance
RS (ý)
Carrier Lifetime
τ (ns)
Total Capacitance
C T (pF)
ꢀ
389xꢀ
3.8ꢀ
200ꢀ
0.20ꢀ@ꢀ5V
ꢀ ꢀ
ꢀꢀꢀꢀ
TestꢀConditionsꢀ
IFꢀ=ꢀ1ꢀmAꢀ
fꢀ=ꢀ100ꢀMHzꢀ
IFꢀ=ꢀ10ꢀmAꢀ
IRꢀ=ꢀ6ꢀmA
ꢀꢀ
ꢀ
3
HSMP-389x Series Typical Performance, TC = 25°C, each diode
100
10
1
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
120
115
110
105
100
95
Diode Mounted as a
Series Attenuator in a
50 Ohm Microstrip and
Tested at 123 MHz
1 MHz
90
1 GHz
4
0.1
0.01
85
0
8
12
16
20
0.1
1
10
100
1
10
30
I
– FORWARD BIAS CURRENT (mA)
V
– REVERSE VOLTAGE (V)
I
– FORWARD BIAS CURRENT (mA)
F
R
F
Figure 3. 2nd Harmonic Input Intercept
Point vs. Forward Bias Current.
Figure 1. Total RF Resistance at 25 C vs.
Forward Bias Current.
Figure 2. Capacitance vs. Reverse
Voltage.
200
160
100
10
1
V
= –2V
R
120
80
V
= –5V
R
0.1
40
0
V
= –10V
R
25 C –50 C
125 C
0.4
0.01
10
15
20
25
30
0
0.2
0.6
0.8
1.0 1.2
FORWARD CURRENT (mA)
V
– FORWARD VOLTAGE (V)
F
Figure 4. Typical Reverse Recovery Time
vs. Reverse Voltage.
Figure 5. Forward Current vs. Forward
Voltage.
Typical Applications for Multiple Diode Products
1
2
1
0
0
2
+V
–V
2
“ON”
“OFF”
3
3
4
2
5
1
6
1
1
3
4
2
5
1
6
0
b1
b2
b3
RF out
RF in
Figure 7. HSMP-389L Unconnected Trio used in a Dual Voltage, High Isolation
Switch.
Figure 6. HSMP-389L used in a SP3T Switch.
4
Typical Applications for Multiple Diode Productsꢀ(continued)
1
+V
0
2
0
+V
“ON”
“OFF”
RF out
1
1
6
1
5
2
4
3
6
1
5
2
4
3
RF out
RF in
2
RF in
Figure 8. HSMP-389L Unconnected Trio used in a Positive Voltage,
High Isolation Switch.
Figure 9. HSMP-389T used in a Low Inductance Shunt
Mounted Switch.
Bias
Xmtr
Ant
λ
4
C
C
Rcvr
Bias
Xmtr
bias
Ant
Bias
λ
4
Rcvr
Antenna
Xmtr
PA
HSMP-389V
λ
4
λ
4
HSMP-389U
LNA
Rcvr
Figure 10. HSMP-389U Series/Shunt Pair used in a 900 MHz
Transmit/Receive Switch.
Figure 11. HSMP-389V Series/Shunt Pair used in a 1.8 GHz
Transmit/Receive Switch.
5
Typical Applications for Multiple Diode Productsꢀ(continued)
RF COMMON
RF COMMON
RF 2
RF 1
RF 1
RF 2
BIAS 1
BIAS 2
BIAS
BIAS
Figure 12. Simple SPDT Switch, Using Only Positive Current.
Figure 13. High Isolation SPDT Switch, Dual Bias.
RF COMMON
RF COMMON
BIAS
RF 1
RF 2
RF 2
RF 1
BIAS
Figure 14. Switch Using Both Positive and Negative Bias Current.
Figure 15. Very High Isolation SPDT Switch, Dual Bias.
6
Typical Applications for HSMP-489x Low Inductance Series
Equivalent Circuit Model
HSMP-389x Chip*
Microstrip Series Connection for HSMP-489x Series
Inꢀ orderꢀ toꢀ takeꢀ fullꢀ advantageꢀ ofꢀ theꢀ lowꢀ inductanceꢀ
ofꢀtheꢀHSMP-489xꢀseriesꢀwhenꢀusingꢀthemꢀinꢀseriesꢀap-
plications,ꢀbothꢀleadꢀ1ꢀandꢀleadꢀ2ꢀshouldꢀbeꢀconnectedꢀ
together,ꢀasꢀshownꢀinꢀFigureꢀ17.
R
R
s
j
0.5 Ω
Cj
3
0.12 pF*
* Measured at -20 V
RT = 0.5 + Rj
CT = CP + Cj
20
1
2
HSMP-489x
Figure 16. Internal Connections.
Rj =
Ω
I0.9
I = Forward Bias Current in mA
* See AN1124 for package models
Co-Planar Waveguide Shunt Connection for HSMP-489x Series
Co-Planarꢀ waveguide,ꢀ withꢀ groundꢀ onꢀ theꢀ topꢀ sideꢀ ofꢀ
theꢀ printedꢀ circuitꢀ board,ꢀ isꢀ shownꢀ inꢀ Figureꢀ 20.ꢀ Sinceꢀ
itꢀeliminatesꢀtheꢀneedꢀforꢀviaꢀholesꢀtoꢀground,ꢀitꢀoffersꢀ
lowerꢀshuntꢀparasiticꢀinductanceꢀandꢀhigherꢀmaximumꢀ
attenuationꢀwhenꢀcomparedꢀtoꢀaꢀmicrostripꢀcircuit.
Figure 17. Circuit Layout.
Microstrip Shunt Connections for HSMP-489x Series
InꢀFigureꢀ18,ꢀtheꢀcenterꢀconductorꢀofꢀtheꢀmicrostripꢀlineꢀ
isꢀinterruptedꢀandꢀleadsꢀ1ꢀandꢀ2ꢀofꢀtheꢀHSMP-489xꢀdiodeꢀ
areꢀplacedꢀacrossꢀtheꢀresultingꢀgap.ꢀThisꢀforcesꢀtheꢀ1.5ꢀ
nHꢀleadꢀinductanceꢀofꢀleadsꢀ1ꢀandꢀ2ꢀtoꢀappearꢀasꢀpartꢀofꢀ
aꢀlowꢀpassꢀfilter,ꢀreducingꢀtheꢀshuntꢀparasiticꢀinductanceꢀ
andꢀincreasingꢀtheꢀmaximumꢀavailableꢀattenuation.ꢀTheꢀ
0.3ꢀnHꢀofꢀshuntꢀinductanceꢀexternalꢀtoꢀtheꢀdiodeꢀisꢀcre-
atedꢀbyꢀtheꢀviaꢀholes,ꢀandꢀisꢀaꢀgoodꢀestimateꢀforꢀ0.032"ꢀ
thickꢀmaterial.
Co-Planar Waveguide
Groundplane
Center Conductor
Groundplane
50 OHM MICROSTRIP LINES
Figure 20. Circuit Layout.
0.3 pF
PAD CONNECTED TO
GROUND BY TWO
VIA HOLES
0.75 nH
Figure 18. Circuit Layout.
1.5 nH
1.5 nH
Figure 21. Equivalent Circuit.
AꢀSPICEꢀmodelꢀisꢀnotꢀavailableꢀforꢀPINꢀdiodesꢀasꢀSPICEꢀ
doesꢀnotꢀprovideꢀforꢀaꢀkeyꢀPINꢀdiodeꢀcharacteristic,ꢀcar-
rierꢀlifetime.
0.3 pF
0.3 nH
0.3 nH
Figure 19. Equivalent Circuit.
7
Assembly Information
0.026
0.075
0.035
0.016
Figure 22. PCB Pad Layout, SOT-363.
(dimensions in inches).
0.026
0.07
0.035
0.016
Figure 23. PCB Pad Layout, SOT-323.
(dimensions in inches).
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
DIMENSIONS IN
Figure 24. PCB Pad Layout, SOT-23.
0.112
2.85
0.079
2
0.033
0.85
0.108
2.75
0.075
1.9
0.041
1.05
0.071
1.8
0.033
0.85
0.047 0.031 0.033
1.2
0.8
0.85
inches
mm
DIMENSIONS IN
Figure 25. PCB Pad Layout, SOT-143.
8
SMT Assembly
Reliableꢀ assemblyꢀ ofꢀ surfaceꢀ mountꢀ componentsꢀ isꢀ aꢀ
complexꢀprocessꢀthatꢀinvolvesꢀmanyꢀmaterial,ꢀprocess,ꢀ
andꢀ equipmentꢀ factors,ꢀ including:ꢀ methodꢀ ofꢀ heatingꢀ
(e.g.,ꢀIRꢀorꢀvaporꢀphaseꢀreflow,ꢀwaveꢀsoldering,ꢀetc.)ꢀcir-
cuitꢀ boardꢀ material,ꢀ conductorꢀ thicknessꢀ andꢀ pattern,ꢀ
typeꢀofꢀsolderꢀalloy,ꢀandꢀtheꢀthermalꢀconductivityꢀandꢀ
thermalꢀmassꢀofꢀcomponents.ꢀComponentsꢀwithꢀaꢀlowꢀ
mass,ꢀsuchꢀasꢀtheꢀSOTꢀpackage,ꢀwillꢀreachꢀsolderꢀreflowꢀ
temperaturesꢀfasterꢀthanꢀthoseꢀwithꢀaꢀgreaterꢀmass.ꢀ
zones.ꢀTheꢀ preheatꢀ zonesꢀ increaseꢀ theꢀ temperatureꢀ ofꢀ
theꢀ boardꢀ andꢀ componentsꢀ toꢀ preventꢀ thermalꢀ shockꢀ
andꢀbeginꢀevaporatingꢀsolventsꢀfromꢀtheꢀsolderꢀpaste.ꢀ
Theꢀreflowꢀzoneꢀbrieflyꢀelevatesꢀtheꢀtemperatureꢀsuffi-
cientlyꢀtoꢀproduceꢀaꢀreflowꢀofꢀtheꢀsolder.ꢀ
Theꢀratesꢀofꢀchangeꢀofꢀtemperatureꢀforꢀtheꢀramp-upꢀandꢀ
cool-downꢀzonesꢀareꢀchosenꢀtoꢀbeꢀlowꢀenoughꢀtoꢀnotꢀ
causeꢀdeformationꢀofꢀtheꢀboardꢀorꢀdamageꢀtoꢀcompo-
nentsꢀdueꢀtoꢀthermalꢀshock.ꢀTheꢀmaximumꢀtemperatureꢀ
inꢀtheꢀreflowꢀzoneꢀ(TMAX)ꢀshouldꢀnotꢀexceedꢀ260°C.ꢀ
AvagoꢀTechnologies’ꢀdiodesꢀhaveꢀbeenꢀqualifiedꢀtoꢀtheꢀ
time-temperatureꢀprofileꢀshownꢀinꢀFigureꢀ26.ꢀThisꢀprofileꢀ
isꢀrepresentativeꢀofꢀanꢀIRꢀreflowꢀtypeꢀofꢀsurfaceꢀmountꢀ
assemblyꢀprocess.
Theseꢀparametersꢀareꢀtypicalꢀforꢀaꢀsurfaceꢀmountꢀassem-
blyꢀprocessꢀforꢀAvagoꢀTechnologiesꢀdiodes.ꢀAsꢀaꢀgeneralꢀ
guideline,ꢀtheꢀcircuitꢀboardꢀandꢀcomponentsꢀshouldꢀbeꢀ
exposedꢀonlyꢀtoꢀtheꢀminimumꢀtemperaturesꢀandꢀtimesꢀ
necessaryꢀtoꢀachieveꢀaꢀuniformꢀreflowꢀofꢀsolder.ꢀ
Afterꢀ rampingꢀ upꢀ fromꢀ roomꢀ temperature,ꢀ theꢀ circuitꢀ
boardꢀ withꢀ componentsꢀ attachedꢀ toꢀ itꢀ (heldꢀ inꢀ placeꢀ
withꢀsolderꢀpaste)ꢀpassesꢀthroughꢀoneꢀorꢀmoreꢀpreheatꢀ
tp
Critical Zone
T L to Tp
Tp
Ramp-up
T L
tL
Ts
max
Ts
min
Ramp-down
ts
Preheat
25
t 25° C to Peak
Time
Figure 26. Surface Mount Assembly Profile.
Lead-Free Reflow Profile Recommendation (IPC/JEDEC J-STD-020C)
Reflow Parameter
Lead-Free Assembly
3°C/ꢀsecondꢀmax
150°C
Averageꢀramp-upꢀrateꢀ(LiquidusꢀTemperatureꢀ(TS(max)ꢀtoꢀPeak)
Preheat
TemperatureꢀMinꢀ(TS(min))
TemperatureꢀMaxꢀ(TS(max)
)
200°C
Timeꢀ(minꢀtoꢀmax)ꢀ(tS)
60-180ꢀseconds
3°C/secondꢀmax
217°C
Ts(max)ꢀtoꢀTLꢀRamp-upꢀRate
Timeꢀmaintainedꢀabove:
Temperatureꢀ(TL)
Timeꢀ(tL)
60-150ꢀseconds
260ꢀ+0/-5°C
PeakꢀTemperatureꢀ(TP)ꢀ
Timeꢀwithinꢀ5ꢀ°CꢀofꢀactualꢀPeakꢀtemperatureꢀ(tP)
Ramp-downꢀRate
20-40ꢀseconds
6°C/secondꢀmax
8ꢀminutesꢀmax
Timeꢀ25ꢀ°CꢀtoꢀPeakꢀTemperature
Noteꢀ1:ꢀAllꢀtemperaturesꢀreferꢀtoꢀtopsideꢀofꢀtheꢀpackage,ꢀmeasuredꢀonꢀtheꢀpackageꢀbodyꢀsurface
9
Package Dimensions
Outline 23 (SOT-23)
Outline SOT-323 (SC-70 3 Lead)
e1
e2
e1
E1
E
XXX
E1
E
XXX
e
L
B
e
C
L
D
DIMENSIONS (mm)
B
D
C
SYMBOL
MIN.
0.80
0.00
0.15
0.08
1.80
1.10
MAX.
1.00
0.10
0.40
0.25
2.25
1.40
A
A1
B
C
D
E1
e
e1
E
DIMENSIONS (mm)
A
SYMBOL
MIN.
0.79
0.000
0.30
0.08
2.73
1.15
0.89
1.78
0.45
2.10
0.45
MAX.
1.20
0.100
0.54
0.20
3.13
1.50
1.02
2.04
0.60
2.70
0.69
A
A1
B
C
D
E1
e
e1
e2
E
A1
A
0.65 typical
1.30 typical
Notes:
A1
1.80
0.26
2.40
0.46
XXX-package marking
Drawings are not to scale
L
Notes:
XXX-package marking
Drawings are not to scale
L
Outline 143 (SOT-143)
Outline SOT-363 (SC-70 6 Lead)
e2
e1
HE
E
B1
L
E
E1
XXX
e
c
D
DIMENSIONS (mm)
L
SYMBOL
E
D
HE
A
A2
A1
e
MIN.
1.15
1.80
1.80
0.80
0.80
0.00
MAX.
1.35
2.25
2.40
1.10
1.00
0.10
B
C
e
A1
A2
A
DIMENSIONS (mm)
D
SYMBOL
MIN.
0.79
0.013
0.36
0.76
0.086
2.80
1.20
0.89
1.78
0.45
2.10
0.45
MAX.
1.097
0.10
0.54
0.92
0.152
3.06
1.40
1.02
2.04
0.60
2.65
0.69
0.650 BCS
A
A1
B
b
c
L
0.15
0.08
0.10
0.30
0.25
0.46
b
A
B1
C
A1
D
E1
e
e1
e2
E
Notes:
XXX-package marking
Drawings are not to scale
L
10
Package Characteristics
LeadꢀMaterialꢀ
Copperꢀ(SOT-323/363);ꢀAlloyꢀ42ꢀ(SOT-23/143)
LeadꢀFinishꢀ
Tinꢀ100%
260°Cꢀforꢀ5ꢀseconds
2ꢀpoundsꢀpull
MaximumꢀSolderingꢀTemperatureꢀ
MinimumꢀLeadꢀStrengthꢀ
TypicalꢀPackageꢀInductanceꢀ
TypicalꢀPackageꢀCapacitanceꢀ
2ꢀnH
0.08ꢀpFꢀ(oppositeꢀleads)
Ordering Information
Specifyꢀpartꢀnumberꢀfollowedꢀbyꢀoption.ꢀForꢀexample:
ꢀ
HSMPꢀꢀ-ꢀꢀ389xꢀꢀ-ꢀꢀxxxꢀ
ꢀ
ꢀ
ꢀ
BulkꢀorꢀTapeꢀandꢀReelꢀOption
PartꢀNumber;ꢀxꢀ=ꢀLeadꢀCode
SurfaceꢀMountꢀPIN
Option Descriptions
-BLKGꢀ=ꢀBulk,ꢀ100ꢀpcs.ꢀperꢀantistaticꢀbag
-TR1Gꢀ=ꢀTapeꢀandꢀReel,ꢀ3000ꢀdevicesꢀperꢀ7"ꢀreel
-TR2Gꢀ=ꢀTapeꢀandꢀReel,ꢀ10,000ꢀdevicesꢀperꢀ13"ꢀreel
TapeꢀandꢀReelingꢀconformsꢀtoꢀElectronicꢀIndustriesꢀRS-481,ꢀ“TapingꢀofꢀSurfaceꢀMountedꢀComponentsꢀforꢀAutomatedꢀ
Placement.”
For Outlines SOT-23, -323
Device Orientation
REEL
TOP VIEW
4 mm
END VIEW
CARRIER
TAPE
8 mm
ABC
ABC
ABC
ABC
USER
FEED
DIRECTION
Note: "AB" represents package marking code.
"C" represents date code.
COVER TAPE
For Outline SOT-143
For Outline SOT-363
TOP VIEW
END VIEW
TOP VIEW
4 mm
END VIEW
4 mm
8 mm
ABC
8 mm
ABC
ABC
ABC
ABC
ABC
ABC
ABC
Note: "AB" represents package marking code.
"C" represents date code.
Note: "AB" represents package marking code.
"C" represents date code.
11
Tape Dimensions and Product Orientation
For Outline SOT-23
P
P
D
2
E
F
P
0
W
D
1
t1
Ko
13.5 MAX
8
MAX
9
MAX
B
A
0
0
DESCRIPTION
SYMBOL
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
A
B
K
P
3.15
±
±
±
±
0.10
0.10
0.10
0.10
0.124
0.109
0.048
0.157
0.039
±
±
±
±
±
0.004
0.004
0.004
0.004
0.002
0
0
0
2.77
1.22
4.00
BOTTOM HOLE DIAMETER
D
1.00 + 0.05
1
0
PERFORATION
CARRIER TAPE
DIAMETER
PITCH
POSITION
D
P
E
1.50 + 0.10
4.00
1.75
0.059 + 0.004
0.157
0.069
±
±
0.10
0.10
±
±
0.004
0.004
WIDTH
THICKNESS
W
t1
8.00+ 0.30–0.10 0.315+ 0.012–0.004
0.229 0.013 0.009 0.0005
±
DISTANCE
BETWEEN
CENTERLINE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
F
3.50
2.00
±
0.05
0.05
0.138
0.079
±
±
0.002
0.002
CAVITY TO PERFORATION
(LENGTH DIRECTION)
P
±
2
For Outline SOT-143
P
D
P2
P0
E
F
W
D1
t1
K
9
°
MAX
9°
MAX
0
A0
B
0
DESCRIPTION
SYMBOL
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
A
B
K
P
3.19
2.80
1.31
4.00
±
±
±
±
0.10
0.10
0.10
0.10
0.126
0.110
0.052
0.157
±
±
±
±
0.004
0.004
0.004
0.004
0
0
0
BOTTOM HOLE DIAMETER
D
1.00 + 0.25
0.039 + 0.010
1
0
PERFORATION
DIAMETER
PITCH
POSITION
D
P
E
1.50 + 0.10
0.059 + 0.004
4.00
1.75
±
±
0.10
0.10
0.157
0.069
±
±
0.004
0.004
CARRIER TAPE
DISTANCE
WIDTH
THICKNESS
W
t1
8.00+ 0.30 –0.10 0.315+ 0.012 –0.004
0.254 0.013 0.0100 0.0005
±
CAVITY TO PERFORATION
(WIDTH DIRECTION)
F
3.50
2.00
±
0.05
0.05
0.138
0.079
±
0.002
0.002
CAVITY TO PERFORATION
(LENGTH DIRECTION)
P
±
±
2
12
Tape Dimensions and Product Orientation
For Outlines SOT-323, -363
P
P
D
2
P
0
E
F
W
C
D
1
t
(CARRIER TAPE THICKNESS)
T (COVER TAPE THICKNESS)
t
1
K
An
An
0
A
B
0
0
DESCRIPTION
SYMBOL
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
A
B
K
P
2.40
2.40
1.20
4.00
±
±
±
±
0.10
0.10
0.10
0.10
0.094
0.094
0.047
0.157
±
±
±
±
0.004
0.004
0.004
0.004
0
0
0
BOTTOM HOLE DIAMETER
D
1.00 + 0.25
0.039 + 0.010
1
0
PERFORATION
DIAMETER
PITCH
POSITION
D
P
E
1.55
4.00
1.75
±
±
±
0.05
0.10
0.10
0.061
0.157
0.069
±
±
±
0.002
0.004
0.004
CARRIER TAPE
COVER TAPE
DISTANCE
WIDTH
THICKNESS
W
8.00
±
0.30
0.315
0.0100
±
±
0.012
0.0008
t
0.254
5.4
0.062
±
0.02
0.10
0.001
0.05
1
WIDTH
TAPE THICKNESS
C
±
0.205 ± 0.004
0.0025 ± 0.00004
T
±
t
CAVITY TO PERFORATION
(WIDTH DIRECTION)
F
3.50
±
0.138
±
0.002
CAVITY TO PERFORATION
(LENGTH DIRECTION)
P
2.00
±
0.05
0.079
±
0.002
2
ANGLE
FOR SOT-323 (SC70-3 LEAD)
FOR SOT-363 (SC70-6 LEAD)
An
8
°
C MAX
10 C MAX
°
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes 5989-0486EN
AV02-0813EN - June 2, 2009
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