HSMP-382X [AVAGO]

Surface Mount RF PIN Switch and Limiter Diodes;
HSMP-382X
型号: HSMP-382X
厂家: AVAGO TECHNOLOGIES LIMITED    AVAGO TECHNOLOGIES LIMITED
描述:

Surface Mount RF PIN Switch and Limiter Diodes

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HSMP-382x, 482x  
Surface Mount RF PIN Switch and Limiter Diodes  
Data Sheet  
Description/Applications  
Features  
The HSMP-382x series is optimized for switching ap-  
plications where ultra-low resistance is required. The  
HSMP-482x diode is ideal for limiting and low induc-  
tance switching applications up to 1.5 GHz.  
Diodes Optimized for:  
Low Current Switching  
Low Distortion Attenuating  
Power Limiting/Circuit Protection  
A SPICE model is not available for PIN diodes as SPICE  
does not provide for a key PIN diode characteristic, carrier  
lifetime.  
Surface Mount SOT-23 and SOT-323 Packages  
Single and Dual Versions  
Tape and Reel Options Available  
Low Failure in Time (FIT) Rate[1]  
Lead-free  
Note:  
1. For more information see the Surface Mount PIN Reliability  
Data Sheet.  
Package Lead Code Identification, SOT-23 (Top View)  
Package Lead Code Identification, SOT-323 (Top View)  
SERIES  
DUAL ANODE  
SINGLE  
#2  
#0  
HSMP-482B  
COMMON  
CATHODE  
COMMON  
ANODE  
#3  
#4  
DUAL ANODE  
HSMP-4820  
Absolute Maximum Ratings[1] TC = +25°C  
Symbol Parameter  
Unit  
Amp  
SOT-23  
1
SOT-323  
If  
Forward Current (1 μs Pulse)  
1
PIV  
Tj  
Peak Inverse Voltage  
Junction Temperature  
Storage Temperature  
V
50  
150  
50  
150  
°C  
Tstg  
°C  
-65 to 150  
-65 to 150  
θjc  
Thermal Resistance[2]  
°C/W  
500  
150  
Notes:  
1. Operation in excess of any one of these conditions may result in permanent damage to the  
device.  
2. TC = +25°C, where TC is defined to be the temperature at the package pins where contact is  
made to the circuit board.  
Electrical Specifications TC = 25°C  
Package  
Marking  
Code  
Minimum  
Breakdown  
Maximum  
Series Resistance  
RS (Ω)  
Maximum  
Total Capacitance  
CT (pF)  
Part Number  
HSMP-  
Lead  
Code  
Configuration  
Single  
Series  
Common Anode  
Common Cathode  
Voltage VBR (V)  
3820  
3822  
3823  
3824  
F0  
F2  
F3  
F4  
0
2
3
4
50  
0.6  
0.8  
Test Conditions  
VR = VBR  
Measure  
IR ≤ 10 μA  
f = 100 MHz  
IF = 10 mA  
f = 1 MHz  
VR = 20 V  
High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes  
Minimum  
Breakdown  
Voltage  
Maximum  
Typical  
Maximum  
Total  
Capacitance  
CT (pF)  
Typical  
Total  
Inductance  
LT (nH)  
Part  
Number  
HSMP-  
Package  
Marking  
Code  
Series  
Resistance  
RS (Ω)  
Total  
Capacitance  
CT (pF)  
Lead  
Code  
Configuration  
VBR (V)  
4820  
482B  
FA  
FA  
A
A
Dual Anode  
Dual Anode  
50  
0.6  
0.75  
1.2  
1.0  
Test Conditions  
VR = VBR  
Measure  
IR ≤ 10 μA  
IF = 10 mA  
f = 1 MHz  
VR = 20 V  
f = 1 MHz  
VR = 0 V  
f = 500 MHz–  
3 GHz  
Typical Parameters at TC = 25°C  
Part Number  
HSMP-  
Series Resistance  
Carrier Lifetime  
τ (ns)  
Reverse Recovery Time  
Trr (ns)  
Total Capacitance  
CT (pF)  
RS (Ω)  
382x  
1.5  
70  
7
0.60 @ 20 V  
Test Conditions  
f = 100 MHz  
IF = 10 mA  
IF = 10 mA  
VR = 10 V  
IF = 20 mA  
90% Recovery  
2
Typical Parameters at TC = 25°C (unless otherwise noted), Single Diode  
100  
100  
10  
1
100  
10  
V
R = 2V  
R = 5V  
V
1
10  
VR = 10V  
0.1  
0.01  
–50C  
0.8  
25C  
0.6  
125C  
0.2 0.4  
1
10  
0.1  
0
1.0 1.2  
20  
FORWARD CURRENT (mA)  
30  
0.01  
0.1  
1
10  
100  
I
– FORWARD BIAS CURRENT (mA)  
F
V
– FORWARD VOLTAGE (mA)  
F
Figure 2. Reverse Recovery Time vs. Forward  
Current for Various Reverse Voltages.  
Figure 1. Forward Current vs. Forward Voltage.  
Figure 3. RF Resistance at 25C vs. Forward Bias  
Current.  
120  
30  
25  
1.4  
1.2  
1.0  
0.8  
0.6  
Diode Mounted as a  
Series Attenuator in a  
50 Ohm Microstrip and  
Tested at 123 MHz  
115  
110  
1.5 GHz  
20  
105  
100  
95  
15  
1.0 GHz  
10  
5
90  
Measured with external  
bias return  
0
85  
0
10  
20  
30  
40  
50  
0
5
10 15 20 25 30 35 40  
CW POWER IN (dBm)  
1
10  
30  
V
– REVERSE VOLTAGE (V)  
I
– FORWARD BIAS CURRENT (mA)  
R
F
Figure 4. Capacitance vs. Reverse Voltage.  
Figure 6. Large Signal Transfer Curve of the  
HSMP-482x Limiter.  
Figure 5. 2nd Harmonic Input Intercept Point vs.  
Forward Bias Current.  
Typical Applications for Multiple Diode Products  
RF COMMON  
RF COMMON  
RF 2  
RF 1  
BIAS  
RF 1  
RF 2  
BIAS 1  
BIAS 2  
BIAS  
Figure 8. High Isolation SPDT Switch, Dual Bias.  
Figure 7. Simple SPDT Switch, Using Only Positive Current.  
3
Typical Applications for Multiple Diode Products, continued  
RF COMMON  
RF COMMON  
BIAS  
RF 1  
RF 2  
RF 2  
RF 1  
BIAS  
Figure 9. Switch Using Both Positive and Negative Bias Current.  
Figure 10. Very High Isolation SPDT Switch, Dual Bias.  
BIAS  
Figure 11. High Isolation SPST Switch (Repeat Cells as Required.  
Figure 12. Power Limiter Using HSMP-3822 Diode Pair.  
See Application Note 1050 for details.  
4
Typical Applications for HSMP-482x Low Inductance  
Series  
1.5 nH  
1.5 nH  
Microstrip Series Connection for HSMP-482x Series  
0.8 pF  
In order to take full advantage of the low inductance  
of the HSMP-482x series when using them in series  
applications, both lead 1 and lead 2 should be connected  
together, as shown in Figure 14.  
0.3 nH  
0.3 nH  
3
Figure 16. Equivalent Circuit.  
1
2
Co-Planar Waveguide Shunt Connection for HSMP-482x Series  
Figure 13. Internal Connections.  
Co-Planar waveguide, with ground on the top side of  
the printed circuit board, is shown in Figure 17. Since  
it eliminates the need for via holes to ground, it offers  
lower shunt parasitic inductance and higher maximum  
attenuation when compared to a microstrip circuit. See  
AN1050 for details.  
Figure 14. Circuit Layout.  
Co-Planar Waveguide  
Groundplane  
Microstrip Shunt Connections for HSMP-482x Series  
Center Conductor  
Groundplane  
In Figure 15, the center conductor of the microstrip line  
is interrupted and leads 1 and 2 of the HSMP-482x diode  
are placed across the resulting gap. This forces the 0.5  
nH lead inductance of leads 1 and 2 to appear as part of  
a low pass filter, reducing the shunt parasitic inductance  
and increasing the maximum available attenuation.  
The 0.3 nH of shunt inductance external to the diode  
is created by the via holes, and is a good estimate for  
0.032" thick material.  
Figure 17. Circuit Layout.  
50 OHM MICROSTRIP LINES  
0.8 pF  
0.75 nH  
Figure 18. Equivalent Circuit.  
PAD CONNECTED TO  
GROUND BY TWO  
VIA HOLES  
Figure 15. Circuit Layout, HSMP-482x Limiter.  
5
Assembly Information  
SOT-323 PCB Footprint  
A recommended PCB pad layout for the miniature SOT-  
323 (SC-70) package is shown in Figure 19 (dimensions  
are in inches). This layout provides ample allowance for  
package placement by automated assembly equipment  
without adding parasitics that could impair the  
performance.  
0.026  
0.079  
0.039  
0.022  
Dimensions in inches  
Figure 19. Recommended PCB Pad Layout  
for Avago’s SC70 3L/SOT-323 Products.  
SOT-23 PCB Footprint  
0.039  
1
0.039  
1
0.079  
2.0  
0.035  
0.9  
0.031  
0.8  
inches  
Dimensions in  
mm  
Figure 20. Recommended PCB Pad Layout  
for Avago’s SOT-23 Products.  
6
SMT Assembly  
Reliable assembly of surface mount components is a  
complex process that involves many material, process,  
and equipment factors, including: method of heating  
(e.g., IR or vapor phase reflow, wave soldering, etc.) circuit  
board material, conductor thickness and pattern, type of  
solder alloy, and the thermal conductivity and thermal  
mass of components. Components with a low mass, such  
as the SOT-323/-23 package, will reach solder reflow  
temperatures faster than those with a greater mass.  
The preheat zones increase the temperature of the  
board and components to prevent thermal shock and  
begin evaporating solvents from the solder paste. The  
reflow zone briefly elevates the temperature sufficiently  
to produce a reflow of the solder.  
The rates of change of temperature for the ramp-up and  
cool-down zones are chosen to be low enough to not  
causedeformationoftheboardordamagetocomponents  
due to thermal shock. The maximum temperature in the  
reflow zone (TMAX) should not exceed 260°C.  
Avago’s diodes have been qualified to the time-  
temperature profile shown in Figure 21. This profile is  
representative of an IR reflow type of surface mount  
assembly process.  
These parameters are typical for a surface mount  
assembly process for Avago diodes. As a general  
guideline, the circuit board and components should be  
exposed only to the minimum temperatures and times  
necessary to achieve a uniform reflow of solder.  
After ramping up from room temperature, the circuit  
board with components attached to it (held in place with  
solder paste) passes through one or more preheat zones.  
tp  
Critical Zone  
Tp  
T
to Tp  
L
Ramp-up  
T
L
tL  
Ts  
max  
Ts  
min  
Ramp-down  
ts  
Preheat  
25  
t 25° C to Peak  
Time  
Figure 21. Surface Mount Assembly Profile.  
Lead-Free Reflow Profile Recommendation (IPC/JEDEC J-STD-020C)  
Reflow Parameter  
Lead-Free Assembly  
3°C/ second max  
150°C  
Average ramp-up rate (Liquidus Temperature (TS(max) to Peak)  
Preheat  
Temperature Min (TS(min))  
Temperature Max (TS(max)  
Time (min to max) (tS)  
)
200°C  
60-180 seconds  
3°C/second max  
217°C  
Ts(max) to TL Ramp-up Rate  
Time maintained above:  
Temperature (TL)  
Time (tL)  
60-150 seconds  
260 +0/-5°C  
Peak Temperature (TP)  
Time within 5 °C of actual Peak temperature (tP)  
Ramp-down Rate  
20-40 seconds  
6°C/second max  
8 minutes max  
Time 25 °C to Peak Temperature  
Note 1: All temperatures refer to topside of the package, measured on the package body surface  
7
Package Dimensions  
Outline 23 (SOT-23)  
Outline SOT-323 (SC-70)  
e1  
e2  
e1  
E1  
E
XXX  
E1  
E
XXX  
e
L
B
D
e
C
L
DIMENSIONS (mm)  
B
D
C
SYMBOL  
MIN.  
0.80  
0.00  
0.15  
0.08  
1.80  
1.10  
MAX.  
1.00  
0.10  
0.40  
0.25  
2.25  
1.40  
A
A1  
B
C
D
E1  
e
e1  
E
DIMENSIONS (mm)  
A
SYMBOL  
MIN.  
0.79  
0.000  
0.30  
0.08  
2.73  
1.15  
0.89  
1.78  
0.45  
2.10  
0.45  
MAX.  
1.20  
0.100  
0.54  
0.20  
3.13  
1.50  
1.02  
2.04  
0.60  
2.70  
0.69  
A
A1  
B
C
D
E1  
e
e1  
e2  
E
A1  
A
0.65 typical  
1.30 typical  
Notes:  
A1  
1.80  
0.26  
2.40  
0.46  
XXX-package marking  
Drawings are not to scale  
L
Notes:  
XXX-package marking  
Drawings are not to scale  
L
Package Characteristics  
Lead Material ....................................................... Copper (SOT-323); Alloy 42 (SOT-23)  
Lead Finish............................................................................ Tin 100% (Lead-free option)  
Maximum Soldering Temperature............................................... 260°C for 5 seconds  
Minimum Lead Strength.............................................................................. 2 pounds pull  
Typical Package Inductance..........................................................................................2 nH  
Typical Package Capacitance................................................. 0.08 pF (opposite leads)  
Ordering Information  
Specify part number followed by option. For example:  
HSMP  
-
382x  
-
XXX  
Bulk or Tape and Reel Option  
Part Number; x = Lead Code  
Surface Mount PIN  
Option Descriptions  
-BLKG = Bulk, 100 pcs. per antistatic bag  
-TR1G = Tape and Reel, 3000 devices per 7" reel  
-TR2G = Tape and Reel, 10,000 devices per 13" reel  
Tape and Reeling conforms to Electronic Industries RS-481,“Taping of Surface  
Mounted Components for Automated Placement.”  
8
Device Orientation  
For Outlines SOT-23/323  
REEL  
TOP VIEW  
4 mm  
END VIEW  
CARRIER  
TAPE  
8 mm  
ABC  
ABC  
ABC  
ABC  
USER  
FEED  
DIRECTION  
Note: "AB" represents package marking code.  
"C" represents date code.  
COVER TAPE  
Tape Dimensions and Product Orientation  
For Outline SOT-23  
P
2
P
D
E
F
P
0
W
D
1
t1  
Ko  
13.5 MAX  
8 MAX  
9 MAX  
B
A
0
0
DESCRIPTION  
SYMBOL  
SIZE (mm)  
SIZE (INCHES)  
CAVITY  
LENGTH  
WIDTH  
DEPTH  
PITCH  
A
B
K
P
D
3.15 0.10  
2.77 0.10  
1.22 0.10  
4.00 0.10  
1.00 + 0.05  
0.124 0.004  
0.109 0.004  
0.048 0.004  
0.157 0.004  
0.039 0.002  
0
0
0
BOTTOM HOLE DIAMETER  
1
PERFORATION  
CARRIER TAPE  
DIAMETER  
PITCH  
POSITION  
D
1.50 + 0.10  
4.00 0.10  
1.75 0.10  
0.059 + 0.004  
0.157 0.004  
0.069 0.004  
P
E
0
WIDTH  
THICKNESS  
W
t1  
8.00+0.30–0.10  
0.229 0.013  
0.315+0.012–0.004  
0.009 0.0005  
DISTANCE  
BETWEEN  
CENTERLINE  
CAVITY TO PERFORATION  
(WIDTH DIRECTION)  
F
3.50 0.05  
2.00 0.05  
0.138 0.002  
0.079 0.002  
CAVITY TO PERFORATION  
(LENGTH DIRECTION)  
P
2
9
Tape Dimensions and Product Orientation  
For Outline SOT-323  
P
P
P
D
2
0
E
F
W
C
D
1
t
(CARRIER TAPE THICKNESS)  
T (COVER TAPE THICKNESS)  
t
1
K
An  
An  
0
A
B
0
0
DESCRIPTION  
SYMBOL  
SIZE (mm)  
SIZE (INCHES)  
CAVITY  
LENGTH  
WIDTH  
DEPTH  
PITCH  
A
B
K
P
D
2.40 0.10  
2.40 0.10  
1.20 0.10  
4.00 0.10  
1.00 + 0.25  
0.094 0.004  
0.094 0.004  
0.047 0.004  
0.157 0.004  
0.039 + 0.010  
0
0
0
BOTTOM HOLE DIAMETER  
1
PERFORATION  
DIAMETER  
PITCH  
POSITION  
D
1.55 0.05  
4.00 0.10  
1.75 0.10  
0.061 0.002  
0.157 0.004  
0.069 0.004  
P
E
0
CARRIER TAPE  
COVER TAPE  
DISTANCE  
WIDTH  
THICKNESS  
W
8.00 0.30  
0.254 0.02  
0.315 0.012  
0.0100 0.0008  
t
1
WIDTH  
TAPE THICKNESS  
C
T
5.4 0.10  
0.062 0.001  
0.205 0.004  
0.0025 0.00004  
t
CAVITY TO PERFORATION  
(WIDTH DIRECTION)  
F
3.50 0.05  
0.138 0.002  
CAVITY TO PERFORATION  
(LENGTH DIRECTION)  
P
2
2.00 0.05  
0.079 0.002  
ANGLE  
FOR SOT-323 (SC70-3 LEAD)  
FOR SOT-363 (SC70-6 LEAD)  
An  
8C MAX  
10C MAX  
For product information and a complete list of distributors, please go to our web site: www.avagotech.com  
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.  
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5989-4026EN  
AV02-1395EN - April 24, 2012  

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