HCPL-786J500 [AVAGO]
1-CH 15-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16, SMT-16;
| 型号： | HCPL-786J500 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 1-CH 15-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16, SMT-16 光电二极管 转换器 |
| 文件： | 总30页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Isolated 15-bit A/D Converter
Technical Data
HCPL-7860/HCPL-786J
HCPL-0870, -7870
Features
• 12-bit Linearity
• Fast 3 µs Over-Range
• Offset Calibration
Detection
• Serial I/O (SPI , QSPI and
Microwire Compatible)
• ± 200 mV Input Range with
Single 5 V Supply
• 1% Internal Reference
Voltage Matching
• 800 ns Conversion Time
(Pre-Trigger Mode 2)
• -40°C to +85°C Operating
Temperature Range
• 15 kV/µs Isolation Transient
Immunity
• Regulatory Approvals; UL,
CSA, VDE
®
®
®
• 5 Conversion Modes for
Resolution/Speed Trade-Off;
12-bit Effective Resolution
with 20 µs Signal Delay
(14-bit with 103 µs)
DIGITAL CURRENT SENSOR
+
+
ISOLATION
BOUNDARY
OUTPUT
DATA
INPUT
CURRENT
ISOLATED
MODULATOR
DIGITAL
INTERFACE IC
Agilent’s Isolated A/D Converter delivers the reliability, small size, superior isolation and over-temperature
performance motor drive designers need to accurately measure current at half the price of
traditional solutions.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
SPI and QSPI are trademarks of Motorola Corp.
Microwire is a trademark of National Semiconductor Inc.
2
Digital Current Sensing
Circuit
shunt resistance, any range of
current can be monitored, from
less than 1 A to more than 100 A.
than 1 µs, the fast over-range
detector for quickly detecting
short circuits, different conversion
modes giving various resolution/
speed trade-offs, offset calibra-
tion mode to eliminate initial
offset from measurements, and
an adjustable threshold detector
for detecting non-short circuit
overload conditions.
As shown in Figure 1, using the
Isolated 2-chip A/D converter to
sense current can be as simple as
connecting a current-sensing
resistor, or shunt, to the input
and reading output data through
the 3-wire serial output interface.
By choosing the appropriate
Even better performance can be
achieved by fully utilizing the
more advanced features of the
Isolated A/D converter, such as
the pre-trigger circuit which can
reduce conversion time to less
NON-ISOLATED
+ 5 V
ISOLATED
+ 5 V
CCLK
CLAT
V
DD
CHAN
+
V
V
V
V
CDAT
MCLK1
MDAT1
MCLK2
MDAT2
GND
SCLK
SDAT
CS
DD1
IN+
IN-
DD2
INPUT
CURRENT
3-WIRE
SERIAL
INTERFACE
MCLK
MDAT
R
SHUNT
0.02
C1
0.1 µF
+
THR1
OVR1
RESET
C2
0.1 µF
GND1 GND2
C3
10 µF
HCPL-7860/
HCPL-786J
HCPL-x870
Figure 1: Typical Application Circuit.
®
Product Overview
Description
rating) converts a low-bandwidth
analog input into a high-speed
one-bit data stream by means of a
that is compatible with SPI ,
®
®
QSPI , and Microwire proto-
cols, allowing direct connection
to a microcontroller. The Digital
Interface IC is available in two
package styles: the HCPL-7870 is
in a 16-pin DIP package and the
HCPL-0870 is in a 300-mil wide
SO-16 surface-mount package.
Features of the Digital Interface
IC include five different conver-
sion modes, three different pre-
trigger modes, offset calibration,
fast over-range detection, and
adjustable threshold detection.
Programmable features are con-
figured via the Serial Configura-
tion port. A second multiplexed
input is available to allow
The HCPL-7860/HCPL-786J
Isolated Modulator and the
HCPL-x870 Digital Interface IC
together form an isolated
programmable two-chip analog-
to-digital converter. The isolated
modulator allows direct
measurement of motor phase
currents in power inverters while
the digital interface IC can be
programmed to optimize the
conversion speed and resolution
trade-off.
∑
sigma-delta ( ∆) oversampling
modulator. This modulation
provides for high noise margins
and excellent immunity against
isolation-mode transients. The
modulator data and on-chip
sampling clock are encoded and
transmitted across the isolation
boundary where they are
recovered and decoded into
separate high-speed clock and
data channels.
The Digital Interface IC converts
the single-bit data stream from
the Isolated Modulator into
fifteen-bit output words and
provides a serial output interface
In operation, the HCPL-7860/
HCPL-786J Isolated Modulator
(optocoupler with 3750 V
RMS
measurements with a second
dielectric withstand voltage
3
isolated modulator without
additional hardware. Because the
two inputs are multiplexed, only
one conversion at a time can be
made and not all features are
available for the second channel.
The available features for both
channels are shown in the table
at right.
HCPL-x870 Digital Interface IC
Feature
Conversion Mode
Channel #1
Channel #2
✓
✓
✓
✓
✓
✓
✓
Offset Calibration
Pre-Trigger Mode
Over-Range Detection
Adjustable Threshold Detection
Functional Diagrams
ISOLATION
BOUNDARY
V
GND2
NC
1
2
3
4
5
6
7
8
16
15
14
CCLK
CLAT
V
DD1
1
2
3
4
5
6
7
8
16
15
DD
CONFIG.
INTER-
FACE
V
IN+
CHAN
CON-
VERSION
INTER-
FACE
V
V
DD1
1
2
3
4
8
7
6
5
DD2
V
V
CDAT
14 SCLK
13 SDAT
IN–
DD2
SIGMA-
DELTA
MOD./
NC
13 MCLK
MCLK1
MDAT1
MCLK2
MDAT2
GND
V
MCLK
MDAT
GND2
IN+
IN–
SIGMA-
DELTA
MOD./
DECODER
CH1
CH2
NC
NC
NC
NC
12
11
CS
DECODE
ENCODER
12
11
V
ENCODE
THRES-
HOLD
DETECT
&
MDAT
THR1
10 NC
10 OVR1
RESET
GND1
SHIELD
RESET
GND1
9
GND2
9
HCPL-7860 Isolated
Modulator
HCPL-786J Isolated
Modulator
HCPL-x870 Digital
Interface IC
Pin Description, Isolated Modulator
Symbol
Description
Symbol
Description
V
V
Supply voltage input (4.5 V to 5.5 V)
Positive input (± 200 mV
recommended)
Negative input
(normally connected to GND1)
Input ground
V
Supply voltage input (4.5 V to 5.5 V)
Clock output (10 MHz typical)
DD1
DD2
MCLK
MDAT
GND2
IN+
V
Serial data output
Output ground
IN–
GND1
4
Pin Description, Digital Interface IC
Symbol
V
DD
Description
Supply voltage (4.5 V to 5.5 V).
Symbol
Description
CCLK Clock input for the Serial Configuration
Interface (SCI). Serial Configuration
data is clocked in on the rising edge
of CCLK.
CHAN Channel select input. The input level on
CHAN determines which channel of
data is used during the next conversion
cycle. An input low selects channel 1,
a high selects channel 2.
CLAT Latch input for the Serial Configuration
Interface (SCI). The last 8 data bits
clocked in on CDAT by CCLK are
latched into the appropriate
configuration register on the rising
edge of CLAT.
SCLK Serial clock input. Serial data is clocked
out of SDAT on the falling edge of SCLK.
CDAT Data input for the Serial Configuration
Interface (SCI). Serial configuration
data is clocked in MSB first.
SDAT Serial data output. SDAT changes from
high impedance to a logic low output
at the start of a conversion cycle.
SDAT then goes high to indicate that
data is ready to be clocked out. SDAT
returns to a high-impedance state after
all data has been clocked out and CS
has been brought high.
MCLK1 Channel 1 Isolated Modulator clock
input. Input Data on MDAT1 is clocked
in on the rising edge of MCLK1.
MDAT1 Channel 1 Isolated Modulator data
input.
CS
Conversion start input. Conversion
begins on the falling edge of CS. CS
should remain low during the entire
conversion cycle and then be brought
high to conclude the cycle.
MCLK2 Channel 2 Isolated Modulator clock
input. Input Data on MDAT2 is clocked
in on the rising edge of MCLK2.
THR1 Continuous, programmable-threshold
detection for channel 1 input data. A
high level output on THR1 indicates
that the magnitude of the channel 1
input signal is beyond a user
programmable threshold level between
160 mV and 310 mV. This signal
continuously monitors channel 1
independent of the channel select
(CHAN) signal.
MDAT2 Channel 2 Isolated Modulator data
input.
OVR1 High speed continuous over-range
detection for channel 1 input data. A
high level output on OVR1 indicates
that the magnitude of the channel 1
input is beyond full-scale. This signal
continuously monitors channel 1
independent of the CHAN signal.
GND
Digital ground.
RESET Master reset input. A logic high input
for at least 100 ns asynchronously
resets all configuration registers to
their default values and zeroes the
Offset Calibration registers.
5
Isolated A/D Converter Performance
Electrical Specifications
Unless otherwise noted, all specifications are at V
= -200 mV to +200 mV and V = 0 V; all Typical
IN-
IN+
specifications are at T = 25°C and V
= V = V = 5 V; all Minimum/Maximum specifications are at
DD2 DD
A
DD1
T = -40°C to +85°C, V
= V = V = 4.5 to 5.5 V.
DD2 DD
A
DD1
Parameter
Symbol
Min. Typ. Max. Units Test Conditions Fig. Note
STATIC CONVERTER CHARACTERISTICS
Resolution
15
bits
LSB
%
LSB
mV
µV/°C
mV/V
mV
1
2
Integral Nonlinearity
INL
3
30
3
4
0.01 0.14
1
Differential Nonlinearity
Uncalibrated Input Offset
Offset Drift vs. Temperature
DNL
3
4
V
-3
0
2
3
10
V
IN+
= 0 V
5
OS
dV /dT
OS
A
Offset drift vs. V
Internal Reference Voltage
dV /dV
DD1
0.12
320
DD1
OS
V
REF
Absolute Reference Voltage
Tolerance
Reference Voltage
Matching
-4
-2
4
2
%
6
%
T = 25°C.
See Note 5
A
V
Drift vs. Temperature dV
/dT
A
/dV
DD1
60
0.2
ppm/°C
%
REF
REF
V
REF
Drift vs. V
dV
DD1
REF
Full Scale Input Range
-V
REF
+V
mV
5
REF
Recommended Input
Voltage Range
-200
+200
DYNAMIC CONVERTER CHARACTERISTICS
(Digital Interface IC is set to Conversion Mode 3.)
Signal-to-Noise Ratio
Total Harmonic Distortion
Signal-to-(Noise
+ Distortion)
SNR
THD
SND
62
73
-67
66
dB
V
= 35 Hz,
2,9
8
IN+
400 mV
(141 mV ) sine
wave.
pk-pk
rms
Effective Number of Bits
Conversion Time
ENOB
10
12
0.8
20
40
20
3.0
10
22
20
bits
µs
6
7
t
t
t
1.1
24
48
24
4.2
Pre-Trigger Mode 2 7,
Pre-Trigger Mode 1
Pre-Trigger Mode 0
C2
C1
C0
14
Signal Delay
t
10
8
9
10
11
12
DSIG
Over-Range Detect Time
Threshold Detect Time
Signal Bandwidth
Isolation Transient
Immunity
t
t
2.0
V
= 0 to 400 mV 12
OVR1
IN+
step waveform
V = 1 kV
ISO
THR1
BW
CMR
18
15
kHz
kV/µs
11
6
Notes:
7. Conversion time is defined as the
time from when the convert start
signal CS is brought low to when
SDAT goes high, indicating that
output data is ready to be clocked
out. This can be as small as a few
cycles of the isolated modulator clock
and is determined by the frequency of
the isolated modulator clock and the
selected Conversion and Pre-Trigger
modes. For determining the true
signal delay characteristics of the A/D
converter for closed-loop phase
tions. The signal delay is determined
by the frequency of the modulator
clock and which Conversion Mode is
selected, and is independent of the
selected Pre-Trigger Mode and,
therefore, conversion time.
1. Resolution is defined as the total
number of output bits. The useable
accuracy of any A/D converter is a
function of its linearity and signal-to-
noise ratio, rather than how many
total bits it has.
2. Integral nonlinearity is defined as
one-half the peak-to-peak deviation
of the best-fit line through the
transfer curve for VIN+ = -200 mV to
+200 mV, expressed either as the
number of LSBs or as a percent of
measured input range (400 mV).
3. Differential nonlinearity is defined as
the deviation of the actual difference
from the ideal difference between
midpoints of successive output
codes, expressed in LSBs.
4. Data sheet value is the average
magnitude of the difference in offset
voltage from TA = 25°C to TA = 85°C,
expressed in microvolts per °C.
Three standard deviation from typical
value is less than 6 µV/°C.
5. Beyond the full-scale input range the
output is either all zeroes or all ones.
6. The effective number of bits (or
effective resolution) is defined by the
equation ENOB = (SNR-1.76)/6.02
and represents the resolution of an
ideal, quantization-noise limited A/D
converter with the same SNR.
9. The minimum and maximum over-
range detection time is determined by
the frequency of the channel 1 iso-
lated modulator clock.
10. The minimum and maximum thresh-
old detection time is determined by
the user-defined configuration of the
adjustable threshold detection circuit
and the frequency of the channel 1
isolated modulator clock. See the
Applications Information section for
further detail. The specified times
apply for the default configuration.
11. The signal bandwidth is the frequency
at which the magnitude of the output
signal has decreased 3 dB below its
low-frequency value. The signal
margin calculations, the signal delay
specification should be used.
8. Signal delay is defined as the effec-
tive delay of the input signal through
the Isolated A/D converter. It can be
measured by applying a -200 mV to
± 200 mV step at the input of modu-
lator and adjusting the relative delay
of the convert start signal CS so that
the output of the converter is at mid-
scale. The signal delay is the elapsed
time from when the step signal is
applied at the input to when output
data is ready at the end of the conver-
sion cycle. The signal delay is the
most important specification for
determining the true signal delay
characteristics of the A/D converter
and should be used for determining
phase margins in closed-loop applica-
bandwidth is determined by the fre-
quency of the modulator clock and
the selected Conversion Mode.
12. The isolation transient immunity (also
known as Common-Mode Rejection)
specifies the minimum rate-of-rise of
an isolation-mode signal applied
across the isolation boundary beyond
which the modulator clock or data
signals are corrupted.
7
0.02
68
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
0.018
0.016
0.014
0.012
0.01
DD1
DD1
DD1
DD1
DD1
DD1
67
66
65
64
63
6
5
4
3
2
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
DD1
DD1
DD1
0.008
0.006
62
61
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE – °C
TEMPERATURE – °C
TEMPERATURE – °C
Figure 4. INL (%) vs. Temperature.
Figure 2. SNR vs. Temperature.
Figure 3. INL (Bits) vs. Temperature.
7
150
100
50
0.8
0.6
0.4
0.2
0
200
180
160
140
120
100
80
PRE-TRIGGER
MODE 0
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
DD1
DD1
DD1
PRE-TRIGGER
MODE 1
PRE-TRIGGER
MODE 2
0
-50
-100
-150
60
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
DD1
DD1
DD1
40
-0.2
-0.4
20
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
1
2
3
4
5
TEMPERATURE – °C
TEMPERATURE – °C
CONVERSION MODE #
Figure 5. Offset Change vs.
Temperature.
Figure 6. V
Change vs.
Figure 7. Conversion Time vs.
Conversion Mode.
REF
Temperature.
14
80
100
90
80
70
60
50
40
30
75
70
65
60
55
13
12
11
10
20
10
0
9
8
50
45
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
CONVERSION MODE #
CONVERSION MODE #
CONVERSION MODE #
Figure 8. Effective Resolution vs.
Conversion Mode.
Figure 9. SNR vs. Conversion Mode.
Figure 10. Signal Delay vs.
Conversion Mode.
100
90
80
70
60
50
40
30
V
(200 mV/DIV.)
IN+
OVR1 (200 mV/DIV.)
THR1
(2 V/DIV.)
20
10
0
1
2
3
4
5
2 µs/DIV.
CONVERSION MODE #
Figure 11. Signal Bandwidth vs.
Conversion Mode.
Figure 12. Over-Range and Threshold
Detect Times.
8
Isolated Modulator
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-7860#XXX
No Option = Standard DIP Package, 50 per tube.
300 = Gull Wing Surface Mount Option, 50 per tube.
500 = Tape and Reel Packaging Option, 1000 per reel.
HCPL-786J#XXX
No Option = 16-Lead Surface Mount Package, 45 per tube.
500 = Tape and Reel Packaging Option, 850 per reel.
Option data sheets available. Contact Agilent sales representative or authorized distributor.
Package Outline Drawings
8-pin DIP Package
9.80 ± 0.25
(0.386 ± 0.010)
8
1
7
6
5
4
REFERENCE VOLTAGE
MATCHING SUFFIX*
TYPE NUMBER
0.18 (0.007)
0.33 (0.013)
6.10 (0.240)
6.60 (0.260)
DATE CODE
A 7860X
YYWW
7.36 (0.290)
7.88 (0.310)
5° TYP.
2
3
PIN ONE
1.78 (0.070) MAX.
1.19 (0.047) MAX.
4.70 (0.185) MAX.
PIN DIAGRAM
1
2
V
V
V
8
7
DD1
IN+
DD2
PIN ONE
0.51 (0.020) MIN.
MCLK
MDAT
2.92 (0.115) MIN.
V
3
4
6
5
IN–
0.76 (0.030)
1.24 (0.049)
0.65 (0.025) MAX.
GND1 GND2
2.28 (0.090)
2.80 (0.110)
DIMENSIONS IN MILLIMETERS AND (INCHES).
*ALL UNITS WITHIN EACH HCPL-7860 STANDARD PACKAGING INCREMENT (EITHER 50 PER TUBE OR 1000 PER REEL)
HAVE A COMMON MARKING SUFFIX TO REPRESENT AN ABSOLUTE REFERENCE VOLTAGE TOLERANCE OF ± 1%.
AN ABSOLUTE REFERENCE VOLTAGE TOLERANCE OF ± 4% IS GUARANTEED BETWEEN STANDARD PACKAGING
INCREMENTS.
9
8-pin DIP Gull Wing Surface Mount Option 300
PIN LOCATION (FOR REFERENCE ONLY)
9.80 ± 0.25
(0.386 ± 0.010)
1.02 (0.040)
1.19 (0.047)
7
6
5
8
1
4.83
(0.190)
TYP.
6.350 ± 0.25
(0.250 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
2
3
4
MOLDED
0.380 (0.015)
0.635 (0.025)
1.19 (0.047)
1.78 (0.070)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
0.255 (0.075)
0.010 (0.003)
4.19
MAX.
(0.165)
0.635 ± 0.25
(0.025 ± 0.010)
1.080 ± 0.320
(0.043 ± 0.013)
0.51 ± 0.130
(0.020 ± 0.005)
12° NOM.
2.540
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01
xx.xxx = 0.005
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
16-Lead Surface Mount
0.457
(0.018)
1.270
(0.050)
16 15 14 13 12 11 10
9
TYPE NUMBER
DATE CODE
A 786J
YYWW
7.493 ± 0.254
(0.295 ± 0.010)
1
2
3
4
5
6
7
8
10.312 ± 0.254
(0.406 ± 0.10)
ALL LEADS
TO BE
COPLANAR
± 0.002
8.986 ± 0.254
(0.345 ± 0.010)
9°
3.505 ± 0.127
(0.138 ± 0.005)
0–8°
0.457
(0.018)
0.203 ± 0.076
(0.008 ± 0.003)
STANDOFF
0.025 MIN.
10.160 ± 0.254
(0.408 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES).
NOTE: Initial and continued variation in the color of the HCPL-786J's white mold compound is normal
and does not affect device performance or reliability.
10
Package Characteristics
Unless otherwise noted, all specifications are at T = +25°C.
A
Parameter
Input-Output Momentary
Withstand Voltage
Symbol Min. Typ. Max. Units
Test Conditions
RH ≤ 50%, t = 1 min.
Note
14,15
V
3750
V
rms
ISO
(See note ** below)
Resistance (Input - Output)
12
13
R
10
10
10
Ω
V
I-O
= 500 Vdc
15
I-O
11
T = 100°C
A
Capacitance
C
I-O
0.7
pF
f = 1 MHz
(Input - Output)
Input IC Junction-to-Case
Thermal Resistance
Output IC Junction-to-Case
Thermal Resistance
θ
96
°C/W Thermocouple located at
jci
center underside of
package
θ
114
°C/W
jco
** The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Agilent Application
Note 1074, Optocoupler Input-Output Endurance Voltage.
Maximum Solder Reflow Thermal Profile
260
240
∆T = 145°C, 1°C/SEC
220
∆T = 115°C, 0.3°C/SEC
200
180
160
140
120
100
80
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
Regulatory Information
The HCPL-7860/HCPL-786J (isolated modulator) has been approved by the following organizations:
UL
VDE
CSA
Recognized under UL 1577,
Component Recognition
Program, File E55361.
Approved under VDE 0884/06.92
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
with VIORM = 848 VPEAK
.
11
VDE 0884 Insulation Characteristics
Description
Symbol
Characteristic
Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V
I - IV
I - III
I - II
rms
for rated mains voltage ≤ 450 V
rms
for rated mains voltage ≤ 600 V
rms
Climatic Classification
40/85/21
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
2
891
V
V
IORM
PEAK
PEAK
V
IORM
x 1.875 = V , 100% Production Test with t = 1
V
PR
167
1336
6000
V
V
V
PR
m
sec, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
V
IORM
x 1.5 = V , Type and Sample Test, t = 60 sec,
V
PR
PR
m
PEAK
PEAK
Partial Discharge < 5 pC
Highest Allowable Overvoltage
(Transient Overvoltage t = 10 sec)
V
IOTM
ini
Safety-Limiting Values–Maximum Values Allowed in the
Event of a Failure, also see Figure 13.
Case Temperature
T
175
80
250
°C
mW
mW
S
Input Power
Output Power
I
P
S, INPUT
S, OUTPUT
9
Insulation Resistance at T , V = 500 V
R
≥ 10
Ω
SI IO
S
*Refer to the optocoupler section of the Optoelectronics Designer's Catalog, under Product Safety Regulations section, (VDE 0884)
for a detailed description of Method a and Method b partial discharge test profiles.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
300
250
P
P
, OUTPUT
, INPUT
Si
200
150
100
Si
MAX. OPERATING
TEMP. IS 100 °C
50
0
0
50
100
150
200
T
– TEMPERATURE – °C
A
Figure 13. Dependence of Safety-
Limiting Values on Temperature.
12
Insulation and Safety Related Specifications
Parameter
Symbol Value Units
Conditions
Minimum External Air Gap
(Clearance)
Minimum External Tracking
(Creepage)
Minimum Internal Plastic Gap
(Internal Clearance)
L(I01)
7.4
*[8.3]
8.0
*[8.3]
mm
mm
mm
Measured from input terminals to output
terminals, shortest distance through air.
Measured from input terminals to output
terminals, shortest distance path along body
Insulation thickness between emitter and
detector; also known as distance through
insulation.
L(I02)
0.5
Tracking Resistance
(Comparative Tracking Index)
Isolation Group
CTI
175
IIIa
Volts DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
*Values in bracket are for HCPL-786J.
Absolute Maximum Ratings
Parameter
Storage Temperature
Ambient Operating Temperature
Supply Voltages
Steady-State Input Voltage
Two Second Transient Input Voltage
Output Voltages
Lead Solder Temperature
Solder Reflow Temperature Profile
Symbol
Min.
-55
-40
0
-2.0
-6.0
-0.5
Max.
125
+85
5.5
Units
°C
°C
Volts
Volts
Note
T
S
T
A
V
, V
DD1 DD2
V
, V
V
+ 0.5
16
17
IN+ IN-
DD1
MCLK, MDAT
V
+0.5
Volts
DD2
260°C for 10 sec., 1.6 mm below seating plane
See Maximum Solder Reflow Thermal Profile section
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Supply Voltages
Symbol
Min.
-40
4.5
Max.
+85
5.5
Units
°C
Note
T
A
V
, V
DD1 DD2
V
Input Voltage
V
, V
-200
+200
mV
16
IN+ IN-
13
Electrical Specifications, Isolated Modulator
Unless otherwise noted, all specifications are at V
= 0 V and V = 0 V, all Typical specifications are at
IN+
IN-
T = 25°C and V
= V
= 5 V, and all Minimum and Maximum specifications apply over the following
A
DD1
DD2
ranges: T = -40°C to +85°C, V
= 4.5 to 5.5 V and V
= 4.5 to 5.5 V.
A
DD1
DD2
Parameter
Symbol Min. Typ. Max. Units
Test Conditions
Fig. Note
Average Input Bias Current
Average Input Resistance
Input DC Common-Mode
Rejection Ratio
I
R
-0.8
450
60
µA
kΩ
dB
14
18
IN
IN
CMRR
19
IN
Output Logic High Voltage
Output Logic Low Voltage
Output Short Circuit Current
Input Supply Current
Output Supply Current
Output Clock Frequency
Data Hold Time
V
3.9
8.2
4.9
0.1
30
10
V
V
mA
mA
mA
I
I
V
= -100 µA
= 1.6 mA
= V or GND2
DD2
= -350 mV
OH
OUT
OUT
V
0.6
OL
|I
I
I
|
20
21
OSC
DD1
DD2
CLK
OUT
15
15
V
15
16
17
IN+
to +350 mV
10
f
10 13.2 MHz
15 ns
t
HDDAT
Notes:
14. In accordance with UL1577, for devices with minimum V
specified at 3750 V , each isolated modulator (optocoupler) is
rms
ISO
proof-tested by applying an insulation test voltage greater than 4500 Vrms for one second (leakage current detection limit
I - < 5 µa). This test is performed before the Method b, 100% production test for partial discharge shown in VDE 0884
I O
Insulation Characteristics Table.
15. This is a two-terminal measurement: pins 1-4 are shorted together and pins 5-8 are shorted together.
16. If V (pin 3) is brought above V
- 2 V with respect to GND1 an internal optical-coupling test mode may be activated. This test
IN-
DD1
mode is not intended for customer use.
17. Agilent recommends the use of non-chlorinated solder fluxes.
18. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown.
19. CMRR is defined as the ratio of the gain for differential inputs applied between V
and V to the gain for common-mode
IN
IN+
IN-
inputs applied to both V
and V with respect to input ground GND1.
IN+
IN-
20. Short-circuit current is the amount of output current generated when either output is shorted to V
conditions is not recommended.
or GND2. Use under these
DD2
21. Data hold time is amount of time that the data output MDAT will stay stable following the rising edge of output clock MCLK.
14
1
10.5
-40 °C
25 °C
85 °C
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
10.0
9.5
9.0
8.5
8.0
-6
-4
-2
0
2
4
6
-400
-200
0
200
400
V
– V
V
– mV
IN
IN
Figure 14. I vs. V
.
IN
Figure 15. I
vs. V .
DD1 IN
IN
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
10.0
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
DD1
DD1
DD1
9.8
9.6
9.4
9.2
9.0
-40 °C
25 °C
85 °C
8.8
8.6
-400
-200
0
200
400
-40
-15
10
35
60
85
V
– mV
TEMPERATURE – °C
IN
Figure 17. Clock Frequency vs. Temperature.
Figure 16. I
vs. V .
IN
DD2
15
Digital Interface IC
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example
HCPL-7870
Standard 16-pin DIP package, 25 per tube.
HCPL-0870#XXX
No Option = Standard 16-pin SO package, 47 per tube.
500 = Tape and Reel Packaging Option, 1000 per reel.
Option data sheets available. Contact Agilent sales representative or authorized distributor.
Package Outline Drawings
Standard 16-pin DIP Package
16
15
14
13
12
11
10
9
TYPE NUMBER
DATE CODE
R 0.030 x 0.030 DP
A 7870
YYWW
1
2
3
4
5
6
7
8
0.310 ± 0.010
(OUTER TO OUTER)
0.754
0.258
7°
7°
0.060
0.060
0.150 ± 0.010
0.130
0.260
0.130 ± 0.010
0.010 ± 0.002
0.018 ± 0.003
0.100 ± 0.010
0.310/0.380
(CENTER TO CENTER)
0.060
DIMENSIONS IN INCHES.
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = ± 0.01
xx.xxx = ± 0.002
16
Standard 16-pin SO Package
1.27 (0.050)
x 0.075 (0.003)
DEPTH
(2x) EJECTOR PIN
SHINY SURFACE
TOP VIEW
BOTTOM VIEW
PIN NO. 1 IDENTIFIER
1.27 (0.050) x 0.075 (0.003) DEPTH
SHINY SURFACE
1.90
(0.075)
1.90
(0.075)
0.33 x 45°
(0.013 x 45°)
16 15 14 13 12 11 10
9
10.00–10.65
(0.394–0.419)
(TIP TO TIP)
7.544 ± 0.05
(0.297 ± 0.002)
A 0870
YYWW
XX
TH
1.27
(0.050)
1
2
3
4
5
6
7
8
1.27 (0.050)
SIDE VIEW
END VIEW
R 0.18 (R 0.007)
ALL CORNERS
AND EDGES
1.27 BSC
(0.050 BSC) (0.013–0.020)
0.33–0.51
1.016 ± 0.025
(0.040 ± 0.001)
0.10–0.30
(0.004–0.0118)
7°
PARTING
LINE
2.286
(0.090)
0.01 (0.004)
A
SEATING PLANE
0.23–0.32
(0.0091–0.0125)
10.21 ± 0.10
(0.402 ± 0.002)
2.386–2.586
(0.094–0.1018)
1.016 REF.
(0.040)
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES
(UNLESS OTHERWISE SPECIFIED): xx.xx = ± 0.010
xx.xxx = ± 0.002
0° – 8°
DETAIL A
0.40 – 1.27
(0.016 – 0.050)
17
Maximum Solder Reflow Thermal Profile
260
240
∆T = 145°C, 1°C/SEC
220
200
180
160
140
120
100
80
∆T = 115°C, 0.3°C/SEC
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
Absolute Maximum Ratings
Parameter
Storage Temperature
Ambient Operating Temperature
Supply Voltage
Symbol
Min.
-55
-40
0
Max.
Units
Note
T
+125
+85
5.5
°C
°C
V
S
T
A
V
DD
Input Voltage
Output Voltage
All Inputs
All Outputs
-0.5
-0.5
V
V
DD
+ 0.5
+ 0.5
V
V
DD
Lead Solder Temperature
Solder Reflow Temperature Profile
260°C for 10 seconds, 1.6 mm below seating plane
17
See Reflow Thermal Profile
Note:
17. HP recommends the use of non-chlorinated solder fluxes.
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Supply Voltage
Symbol
Min.
-40
4.5
0
Max.
+85
5.5
Units
°C
V
Note
T
A
V
DD
Input Voltage
All Inputs
V
DD
V
18
Electrical Specifications, Digital Interface IC
Unless otherwise noted, all Typical specifications are at T = 25°C and V = 5 V, and all Minimum and
A
DD
Maximum specifications apply over the following ranges: T = -40°C to +85°C and V = 4.5 to 5.5 V.
A
DD
Parameter
Supply Current
DC Input Current
Input Logic Low Voltage
Input Logic High Voltage
Output Logic Low Voltage
Output Logic High Voltage
Clock Frequency (CCLK,
MCLK and SCLK)
Symbol
Min. Typ. Max. Units Test Conditions Fig. Note
I
20
0.001
35
10
0.8
mA
µA
V
f
= 10 MHz
DD
CLK
I
IN
V
IL
V
2.0
4.3
V
V
V
MHz
IH
V
0.15
5.0
0.4
20
I
I
= 4 mA
= -400 µA
OL
OUT
OUT
V
OH
f
CLK
Clock Period (CCLK,
MCLK and SCLK)
Clock High Level Pulse
Width (CCLK, MCLK
and SCLK)
t
50
20
ns
ns
18,
19
PER
t
PWH
Clock Low Level Pulse
Width (CCLK, MCLK
and SCLK)
Setup Time from DAT to
Rising Edge of CLK
(CDAT, CCLK, MDAT
and MCLK)
t
20
10
PWL
t
18
SUCLK
DAT Hold Time after
Rising Edge of CLK
(CDAT, CCLK, MDAT
and MCLK)
t
10
HDCLK
Setup Time from Falling
Edge of CLAT to First
Rising Edge of CCLK
Setup Time from Last
Rising Edge of CCLK
to Rising Edge of CLAT
t
20
20
SUCL1
SUCL2
t
Delay Time from Falling
Edge of SCLK to SDAT
t
15
19
DSDAT
Setup Time from Data
Ready to First Falling
Edge of SCLK
t
200
SUS
Setup Time from CHAN
to falling edge of CS
t
20
SUCHS
Reset High Level Pulse
Width
t
100
PWR
19
t
t
SUCL2
SUCL1
CLAT
CDAT
CCLK
B7
B6
B5
B4
B3
B2
B1
B0
t
HDCLK
t
SUCLK
t
PWH
t
PER
t
PWL
Figure 18. Serial Configuration Interface Timing.
CHAN
t
SUCHS
CS
SDAT
B14 B13 B12 B11 B10
B1
15
B0
t
DSDAT
3
t
PWH
5
1
2
4
6
16
SCLK
t
PER
t
PWL
t
SUS
t
C
Figure 19. Conversion Timing.
20
The primary functions of the
HCPL-x870 Digital Interface IC
are to derive a multi-bit output
signal by averaging the single-bit
modulator data, as well as to
provide a direct microcontroller
interface. The effective resolution
of the multi-bit output signal is a
function of the length of time
(measured in modulator clock
cycles) over which the average is
taken; averaging over longer
periods of time results in higher
resolution. The Digital Interface
IC can be configured for five
conversion modes which have
different combinations of speed
and resolution to achieve the
desired level of performance.
effective sampling time or reduce
conversion time to less than 1 µs,
a fast over-range detection circuit
that rapidly indicates when the
magnitude of the input signal is
beyond full-scale, an adjustable
threshold detection circuit that
indicates when the magnitude of
the input signal is above a user-
adjustable threshold level, an
offset calibration circuit, and a
second multiplexed input that
allows a second Isolated
Applications
Information
Product Description
The HCPL-7860/HCPL-786J
Isolated Modulator (optocoupler)
uses sigma-delta modulation to
convert an analog input signal
into a high-speed (10 MHz)
single-bit digital data stream; the
time average of the modulator’s
single-bit data is directly
proportional to the input signal.
The isolated modulator’s other
main function is to provide
galvanic isolation between the
analog input and the digital
output. An internal voltage
reference determines the full-
scale analog input range of the
modulator (approximately
± 320 mV); an input range of
± 200 mV is recommended to
achieve optimal performance.
Modulator to be used with a
single Digital Interface IC.
The digital output format of the
Isolated A/D Converter is 15 bits
of unsigned binary data. The
input full-scale range and code
assignment is shown in Table 1
below. Although the output con-
tains 15 bits of data, the effective
resolution is lower and is deter-
mined by selected conversion
mode as shown in Table 2 below.
Other functions of the HCPL-
x870 Digital Interface IC include
a Phase Locked Loop based pre-
trigger circuit that can either give
more precise control of the
Table 1. Input Full-Scale Range and Code Assignment.
Analog Input
Full Scale Range
Minimum Step Size
+Full Scale
Voltage Input
640 mV
Digital Output
32768 LSBs
20 µV
+320 mV
0 mV
1 LSB
111111111111111
100000000000000
000000000000000
Zero
-Full Scale
-320 mV
Table 2. Isolated A/D Converter Typical Performance Characteristics.
Conversion Time (µs)
Pre-Trigger Mode
Signal-to-
Noise Ratio
(dB)
Effective
Resolution
(bits)
Signal
Bandwidth
(kHz)
Signal
Delay
(µs)
103
52
20
11
6
Conversion
Mode
0
1
103
52
20
11
6
2
1
2
3
4
5
83
79
73
66
53
13.5
12.8
11.9
10.7
8.5
206
104
40
21
11
3.4
6.9
22
45
90
0.8
Note: Bold italic type indicates Default values.
21
impedance state after a few
cycles of the Isolated Modulator’s
clock.
sion cycle. A logic low level
Digital Interface
Timing
selects channel one, a high level
selects channel 2. CHAN should
not be changed during a conver-
sion cycle. The state of the CHAN
signal has no effect on the
behavior of either the over-range
detection circuit (OVR1) or the
adjustable threshold detection
circuit (THR1). Both OVR1 and
THR1 continuously monitor
channel 1 independent of the
CHAN signal. CHAN also does not
affect the behavior of the pre-
trigger circuit, which is tied to
the conversion timing of channel
1, as explained in the Digital
Interface Configuration section.
Power Up/Reset
At power up, the digital interface
IC should be reset either
manually, by bringing the RESET
pin (pin 9) high for at least
100 ns, or automatically by
connecting a 10 µF capacitor
The amount of time between the
falling edge of CS and the rising
edge of SDAT depends on which
conversion and pre-trigger modes
are selected; it can be as low as
0.7 µs when using pre-trigger
mode 2, as explained in the
Digital Interface Configuration
section.
between the RESET pin and V
DD
(pin 16). The RESET pin operates
asynchronously and places the IC
in its default configuration, as
specified in the Digital Interface
Configuration section.
Serial Configuration
Timing
The HCPL-x870 Digital Interface
IC is programmed using the
Serial Configuration Interface
(SCI) which consists of the clock
(CCLK), data (CDAT), and
Conversion Timing
Figure 19 illustrates the timing
for one complete conversion
cycle. A conversion cycle is
Digital Interface
Configuration
Configuration Registers
The Digital Interface IC contains
four 6-bit configuration registers
that control its behavior. The two
LSBs of any byte clocked into the
serial configuration port (CDAT,
CCLK, CLAT) are used as address
bits to determine which register
the data will be loaded into.
initiated on the falling edge of the
convert start signal (CS); CS
should be held low during the
entire conversion cycle. When CS
is brought low, the serial output
data line (SDAT) changes from a
high-impedance to the low state,
indicating that the converter is
busy. A rising edge on SDAT
indicates that data is ready to be
clocked out. The output data is
clocked out on the negative edges
of the serial clock pulses (SCLK),
MSB first. A total of 16 pulses is
needed to clock out all of the data.
After the last clock pulse, CS
should be brought high again,
causing SDAT to return to a high-
impedance state, completing the
conversion cycle. If the external
circuit uses the positive edges of
SCLK to clock in the data, then a
total of sixteen bits is clocked in,
the first bit is always high
enable/latch (CLAT) signals.
Figure 18 illustrates the timing
for the serial configuration inter-
face. To send a byte of configura-
tion data to the HCPL-x870, first
bring CLAT low. Then clock in
the eight bits of the configuration
byte (MSB first) using CDAT and
the rising edge of CCLK. After the
last bit has been clocked in,
bringing CLAT high again will
latch the data into the appropri-
ate configuration register inside
the interface IC. If more than
eight bits are clocked in before
CLAT is brought high, only the
last eight bits will be used. Refer
to the Digital Interface Configura-
tion section to determine appro-
priate configuration data. If the
default configuration of the
Registers 0 and 1 (with address
bits 00 and 01) specify the
conversion and offset calibration
modes of channels 1 and 2,
register 2 (address bits 10)
specifies the behavior of the
adjustable threshold circuit, and
register 3 (address bits 11)
specifies which pre-trigger mode
to use for channel 1. These
registers are illustrated in Table 3
below, with default values
digital interface IC is acceptable,
then CCLK, CDIN and CLAT may
indicated in bold italic type. Note
that there are several reserved
bits which should always be set
low and that the configuration
registers should not be changed
during a conversion cycle.
be connected to either V or
DD
(indicating that data is ready)
followed by 15 data bits. If fewer
than 16 cycles of SCLK are input
before CS is brought high, the
conversion cycle will terminate
and SDAT will go to the high-
GND.
Channel Select Timing
The channel select signal (CHAN)
determines which input channel
will be used for the next conver-
22
Table 3. Register Configuration.
Configuration Data Bits
Address Bits
Register
Bit 7
High
High
Bit 6
Bit 5
Bit 4
Low
Low
Bit 3
Channel 1
Offset Cal
Bit 2
Reserved
Bit 1
Low
Low
Bit 0
Channel 1 Conversion Mode
0
High
Low
Low
Channel 2
Offset Cal
Low
Reserved
Low
Channel 2 Conversion Mode
1
High
Threshold
Detection Time
Low
Low
Low
High
Threshold Level
2
3
High
Pre-Trigger Mode
Low
Low
Low
Low
Low
Low
Low
Low
High
High
Low
Reserved
Low
Low
Low
High
Note: Bold italic type indicates default values. Reserved bits should be set low.
Conversion Mode
a summary of how performance
changes as a function of conver-
sion mode setting. Combinations
of data bits not specified in Table
4 below are not recommended.
determine the conversion mode
for the appropriate channel. The
bit settings for choosing a partic-
ular conversion mode are shown
in Table 4 below. See Table 2 for
The conversion mode determines
the speed/resolution trade-off for
the Isolated A/D converter. The
four MSBs of registers 0 and 1
Table 4. Conversion Mode Configuration.
Configuration Data Bits
Conversion
Mode
Bit 7
Low
Low
High
High
High
Bit 6
High
Low
Bit 5
Low
High
High
Low
High
Bit 4
High
High
Low
Low
Low
1
2
3
4
5
High
High
Low
Note: Bold italic type indicates default values.
23
Pre-Trigger Mode
periodic. If the signal is not
ately following the convert start
command. The weighting func-
tion increases for half of the con-
version cycle and then decreases
back to zero, at which time the
data ready signal is given,
completing the conversion cycle.
The analog signal is effectively
sampled at the peak of the
periodic and pre-trigger mode 1
or 2 is selected, then the pre-
trigger circuit will not function
properly.
The pre-trigger mode refers to
the operation of a PLL-based
circuit that affects the sampling
behavior and conversion time of
the A/D converter when channel 1
is selected. The PLL pre-trigger
circuit has two modes of opera-
tion; the first mode allows more
precise control of the time at
which the analog input voltage is
effectively sampled, while the
second mode essentially
eliminates the time between when
the external convert start
command is given and when out-
put data is available (reducing it
to less than 1 µs). A brief
An important distinction should
be made concerning the differ-
ence between conversion time
and signal delay. As can be seen
in Figure 20, the amount of time
from the peak of the weighting
function (when the input signal is
being sampled) to when output
data is ready is the same for all
three modes. This is the actual
delay of the analog signal through
the A/D converter and is indepen-
dent of the “conversion time,”
which is simply the time between
the convert start signal and the
data ready signal. Because signal
delay is the true measure of how
much phase shift the A/D
weighting function, half-way
through the conversion cycle.
This is the default mode.
If the convert start signal is
periodic (i.e., at a fixed fre-
quency) and the PLL pre-trigger
circuit is enabled (pre-trigger
modes 1 or 2), either the peak of
the weighting function or the end
of the conversion cycle can be
aligned to the external convert
start command, as shown in
Figure 20. The Digital Interface
IC can therefore synchronize the
conversion cycle so that either
the beginning, the middle, or the
end of the conversion is aligned
with the external convert start
command, depending on whether
pre-trigger mode 0, 1, or 2 is
selected, respectively. The only
requirement is that the convert
start signal for channel 1 be
description of how the A/D con-
verter works with the pre-trigger
circuit disabled will help explain
how the pre-trigger circuit affects
operation when it is enabled.
converter adds to the signal, it
should be used when making
calculations of phase margin and
loop stability in feedback
With the pre-trigger circuit is
disabled (pre-trigger mode 0),
Figure 20 illustrates the relation-
ship between the convert start
command, the weighting function
used to average the modulator
data, and the data ready signal.
The weighted averaging of the
modulator data begins immedi-
systems.
There are different reasons for
using each of the pre-trigger
modes. If the signal is not
WEIGHTING
FUNCTION
CONVERT START – CS
DATA READY – SDAT
A) PRE-TRIGGER MODE 0
B) PRE-TRIGGER MODE 1
C) PRE-TRIGGER MODE 2
Figure 20. Pre-Trigger Modes 0, 1, and 2.
24
periodic, then the pre-trigger
circuit should be disabled by
selecting pre-trigger mode 0. If
the most time-accurate sampling
of the input signal is desired,
then mode 1 should be selected.
If the shortest possible conver-
sion time is desired, then mode 2
should be selected.
The pre-trigger circuit functions
only with channel 1; the circuit
ignores any convert start signals
while channel 2 is selected with
the CHAN input. This allows
conversions on channel 2 to be
performed between conversions
on channel 1 without affecting
the operation of the pre-trigger
circuit. As long as the convert
start signals are periodic while
channel 1 is selected, then the
pre-trigger circuit will function
properly.
The three different pre-trigger
modes are selected using bits 6
and 7 of register 3, as shown in
Table 5 below.
Table 5. Pre-Trigger Mode Configuration.
Configuration Data Bits
Pre-Trigger Mode
Bit 7
Low
Low
Bit 6
Low
High
0
1
2
High
Don’t Care
Note: Bold italic type indicates default values.
Offset Calibration
the selected channel (register
0 for channel 1, register 1 for
channel 2). Bit 3 of the
configuration byte should be
set high to enable offset
calibration mode and bits 4
through 7 should be set to
select conversion mode 1 to
achieve the highest resolution
measurement of the offset.
5. Send another configuration
byte to the appropriate regis-
ter for the selected channel,
setting bit 3 low to disable
calibration mode and setting
bits 4 through 7 to select the
desired conversion mode for
subsequent conversions on
that channel.
The offset calibration circuit can
be used to separately calibrate
the offsets of both channels 1 and
2. The offset calibration circuit
contains a separate offset register
for each channel. After an offset
calibration sequence, the offset
registers will contain a value
equal to the measured offset,
which will then be subtracted
from all subsequent conversions.
A hardware reset (bringing the
RESET pin high for at least
100 ns) is required to reset the
offset calibration registers to
zero.
To calibrate both channels,
perform the above sequence for
each channel. The offset
calibration sequence can be
performed as often as needed.
The table below summarizes how
to turn the offset calibration
mode on or off using bit 3 of
configuration registers 0 and 1.
4. Perform one complete conver-
sion cycle by bringing CS low
until SDAT goes high, indicat-
ing completion of the conver-
sion cycle. Because bit 3 of the
configuration has been set
high, the uncalibrated output
data from the conversion will
be stored in the appropriate
offset calibration register and
will be subtracted from all
subsequent conversions on
that channel. If multiple
The following sequence is
recommended for performing an
offset calibration:
1. Select the appropriate channel
using the CHAN pin (low =
channel 1, high = channel 2).
2. Force zero volts at the input of
the selected isolated
modulator.
3. Send a configuration data byte
to the appropriate register for
Table 6. Offset Calibration
Configuration.
Configuration
Data Bits
Offset
Calibration
conversion cycles are
performed while the offset
calibration mode is enabled,
the uncalibrated data from the
last conversion cycle will be
stored in the offset calibration
register.
Mode
Off
On
Bit 3
Low
High
Note: Bold italic type indicates default
values.
25
Adjustable Threshold
Detection
are programmable using bits 2
through 7 of configuration
register 2, as shown in Tables 7
and 8 below.
Over-Range Detection
The over-range detection circuit
allows fast detection of when the
magnitude of the input signal on
channel 1 is near or beyond full
scale, causing the OVR1 output to
go high. This circuit can be very
useful in current-sensing applica-
tions for quickly detecting when a
short-circuit occurs. The over-
range detection circuit works by
detecting when the modulator
output data has not changed state
for at least 25 clock cycles in a
row, indicating that the input
signal is near or beyond full-
scale, positive or negative.
The adjustable threshold detector
causes the THR1 output to go
high when the magnitude of the
input signal on channel 1 exceeds
a user-defined threshold level.
The threshold level can be set to
one of 16 different values
As with the over-range detector,
the adjustable threshold detector
continuously monitors channel 1
independent of which channel is
selected with the CHAN signal.
This allows continuous monitor-
ing of channel 1 for faults while
converting Channel 2.
between approximately 160 mV
and 310 mV. The adjustable
threshold detector uses a smaller
version of the main conversion
circuit in combination with a
digital comparator to detect when
the magnitude of the input signal
on channel 1 is beyond the
defined threshold level. As with
the main conversion circuit, there
is a trade-off between speed and
resolution with the threshold
detector; selecting faster detec-
tion times exhibit more noise as
the signal passes through the
threshold, while slower detection
times offer lower noise. Both the
detection time and threshold level
Table 7. Threshold
Detection Configuration.
Typical response time to over-
range signals is less than 3 µs.
Configuration
Threshold
Data Bits
Detection
Time
2 - 6 µs
Bit 7
Low
Bit 6
Low
The over-range circuit actually
begins to indicate an over-range
condition when the magnitude of
the input signal exceeds approxi-
mately 250 mV; it starts to
generate periodic short pulses on
OVR1 which get longer and more
frequent as the input signal
approaches full scale. The OVR1
output stays high continuously
when the input is beyond full
scale.
3 - 10 µs
5 - 20 µs
10 - 35 µs
Low
High
High
High
Low
High
Note: Bold italic type indicates default
values.
Table 8. Threshold Level Configuration.
Configuration Data Bits
Threshold Level
± 160 mV
± 170 mV
± 180 mV
± 190 mV
± 200 mV
± 210 mV
± 220 mV
± 230 mV
± 240 mV
± 250 mV
± 260 mV
± 270 mV
± 280 mV
± 290 mV
± 300 mV
± 310 mV
Bit 5
Low
Low
Bit 4
Low
Low
Bit 3
Low
Low
Bit 2
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
The over-range detection circuit
continuously monitors channel 1
independent of which channel is
selected with the CHAN signal.
This allows continuous monitor-
ing of channel 1 for faults while
converting an input signal on
channel 2.
High
High
Low
Low
High
Low
High
Low
High
High
High
Note: Bold italic type indicates default values.
26
Analog Interfacing
drive circuit. If a dedicated
supply is required, in many cases
it is possible to add an additional
winding on an existing trans-
former. Otherwise, some sort of
simple isolated supply can be
used, such as a line powered
transformer or a high-frequency
DC-DC converter.
capacitor (C2) is also recom-
mended at the input due to the
switched-capacitor nature of the
input circuit. The input bypass
capacitor also forms part of the
anti-aliasing filter, which is
recommended to prevent high-
frequency noise from aliasing
down to lower frequencies and
interfering with the input signal.
Power Supplies and
Bypassing
The recommended application
circuit is shown in Figure 21. A
floating power supply (which in
many applications could be the
same supply that is used to drive
the high-side power transistor) is
regulated to 5 V using a simple
zener diode (D1); the value of
resistor R1 should be chosen to
supply sufficient current from the
existing floating supply. The
voltage from the current sensing
resistor or shunt (Rsense) is
applied to the input of the HCPL-
7860 (U2) through an RC anti-
aliasing filter (R2 and C2). And
finally, the output clock and data
of the isolated modulator are
connected to the digital interface
IC. Although the application
circuit is relatively simple, a few
recommendations should be
followed to ensure optimal
An inexpensive 78L05 three-
terminal regulator can also be
used to reduce the floating supply
voltage to 5 V. To help attenuate
high-frequency power supply
noise or ripple, a resistor or
inductor can be used in series
with the input of the regulator to
form a low-pass filter with the
regulator’s input bypass
PC Board Layout
The design of the printed circuit
board (PCB) should follow good
layout practices, such as keeping
bypass capacitors close to the
supply pins, keeping output
signals away from input signals,
the use of ground and power
planes, etc. In addition, the layout
of the PCB can also affect the
isolation transient immunity
(CMR) of the isolated modulator,
due primarily to stray capacitive
coupling between the input and
the output circuits. To obtain
optimal CMR performance, the
layout of the PC board should
minimize any stray coupling by
maintaining the maximum
capacitor.
As shown in Figure 21, 0.1 µF
bypass capacitors (C1 and C3)
should be located as close as
possible to the input and output
power-supply pins of the isolated
modulator (U2). The bypass
capacitors are required because
of the high-speed digital nature of
the signals inside the isolated
modulator. A 0.01 µF bypass
performance.
The power supply for the isolated
modulator is most often obtained
from the same supply used to
power the power transistor gate
possible distance between the
input and output sides of the
circuit and ensuring
FLOATING
POSITIVE
SUPPLY
+ 5 V
HV+
GATE DRIVE
CIRCUIT
R1
CCLK
CLAT
V
DD
C1
D1
5.1 V
CHAN
SCLK
SDAT
CS
0.1 µF
V
V
V
V
CDAT
MCLK1
MDAT1
MCLK2
MDAT2
GND
DD1
IN+
IN-
DD2
R2 39 Ω
MCLK
MDAT
MOTOR
+
-
THR1
OVR1
RESET
C3
0.1 µF
GND1 GND2
C2
0.01 µF
R
SENSE
HCPL-7860/
HCPL-786J
TO
CONTROL
CIRCUIT
HCPL-X870
HV-
Figure 21. Recommended Application Circuit.
27
that any ground or power plane
on the PC board does not pass
directly below or extend much
wider than the body of the
isolated modulator.
maximum value of the shunt is
determined by the current being
measured and the maximum
recommended input voltage of
the isolated modulator. The
maximum shunt resistance can be
calculated by taking the maxi-
mum recommended input voltage
and dividing by the peak current
that the shunt should see during
normal operation. For example, if
a motor will have a maximum
RMS current of 10 A and can
experience up to 50% overloads
during normal operation, then the
peak current is 21.1 A
temperature coefficient (tempco)
of the shunt can introduce
nonlinearity due to the signal
dependent temperature rise of the
shunt. The effect increases as the
shunt-to-ambient thermal
resistance increases. This effect
can be minimized either by
reducing the thermal resistance
of the shunt or by using a shunt
with a lower tempco. Lowering
the thermal resistance can be
accomplished by repositioning
the shunt on the PC board, by
using larger PC board traces to
carry away more heat, or by
using a heat sink.
Shunt Resistors
The current-sensing shunt
resistor should have low
resistance (to minimize power
dissipation), low inductance (to
minimize di/dt induced voltage
spikes which could adversely
affect operation), and reasonable
tolerance (to maintain overall
circuit accuracy). Choosing a
particular value for the shunt is
usually a compromise between
minimizing power dissipation and
maximizing accuracy. Smaller
shunt resistances decrease power
dissipation, while larger shunt
resistances can improve circuit
accuracy by utilizing the full
input range of the isolated
modulator.
(=10x1.414x1.5). Assuming a
maximum input voltage of
200 mV, the maximum value of
shunt resistance in this case
would be about 10 mΩ.
For a two-terminal shunt, as the
value of shunt resistance
decreases, the resistance of the
leads becomes a significant
percentage of the total shunt
resistance. This has two primary
effects on shunt accuracy. First,
the effective resistance of the
shunt can become dependent on
factors such as how long the
leads are, how they are bent, how
far they are inserted into the
board, and how far solder wicks
up the lead during assembly
(these issues will be discussed in
more detail shortly). Second, the
leads are typically made from a
material such as copper, which
has a much higher tempco than
the material from which the
resistive element itself is made,
resulting in a higher tempco for
the shunt overall.
The maximum average power
dissipation in the shunt can also
be easily calculated by multiply-
ing the shunt resistance times the
square of the maximum RMS
current, which is about 1 W in
the previous example.
The first step in selecting a shunt
is determining how much current
the shunt will be sensing. The
graph in Figure 22 shows the
RMS current in each phase of a
three-phase induction motor as a
function of average motor output
power (in horsepower, hp) and
motor drive supply voltage. The
If the power dissipation in the
shunt is too high, the resistance
of the shunt can be decreased
below the maximum value to
decrease power dissipation. The
minimum value of the shunt is
limited by precision and accuracy
requirements of the design. As
the shunt value is reduced, the
output voltage across the shunt is
also reduced, which means that
the offset and noise, which are
fixed, become a larger percentage
of the signal amplitude. The
selected value of the shunt will
fall somewhere between the
40
440
35
30
25
20
15
380
220
120
Both of these effects are elimi-
nated when a four-terminal shunt
is used. A four-terminal shunt has
two additional terminals that are
Kelvin-connected directly across
the resistive element itself; these
two terminals are used to monitor
the voltage across the resistive
element while the other two
10
5
minimum and maximum values,
depending on the particular
requirements of a specific design.
0
0
5
10 15
20 25
30 35
MOTOR PHASE CURRENT – A (rms)
When sensing currents large
enough to cause significant
heating of the shunt, the
Figure 22. Motor Output Horsepower
vs. Motor Phase Current and Supply
Voltage.
terminals are used to carry the
load current. Because of the
Kelvin connection, any voltage
28
drops across the leads carrying
the load current should have no
impact on the measured voltage.
a tightly twisted pair of wires can
accomplish the same thing.
This allows a single pair of wires
or PC board traces to connect the
isolated modulator circuit to the
shunt resistor. By referencing the
input circuit to the negative side
of the sense resistor, any load
current induced noise transients
on the shunt are seen as a
Also, multiple layers of the PC
board can be used to increase
current carrying capacity.
Numerous plated-through vias
should surround each non-Kelvin
terminal of the shunt to help
Several four-terminal shunts from
Isotek (Isabellenhütte) suitable
for sensing currents in motor
drives up to 71 Arms (71 hp or
53 kW) are shown in Table 9; the
maximum current and motor
power range for each of the PBV-
series shunts are indicated. For
shunt resistances from 50 mΩ
down to 10 mΩ, the maximum
current is limited by the input
voltage range of the isolated
modulator. For the 5 mΩ and
2 mΩ shunts, a heat sink may be
required due to the increased
power dissipation at higher
currents.
common-mode signal and will not
distribute the current between the interfere with the current-sense
layers of the PC board. The PC
board should use 2 or 4 oz.
copper for the layers, resulting in
a current carrying capacity in
excess of 20 A. Making the
current carrying traces on the PC
board fairly large can also
improve the shunt’s power
dissipation capability by acting as
a heat sink. Liberal use of vias
where the load current enters and
exits the PC board is also
signal. This is important because
the large load currents flowing
through the motor drive, along
with the parasitic inductances
inherent in the wiring of the
circuit, can generate both noise
spikes and offsets that are
relatively large compared to the
small voltages that are being
measured across the current
shunt.
When laying out a PC board for
the shunts, a couple of points
should be kept in mind. The
recommended.
If the same power supply is used
both for the gate drive circuit and
for the current sensing circuit, it
is very important that the connec-
tion from GND1 of the isolated
modulator to the sense resistor
be the only return path for
Shunt Connections
Kelvin connections to the shunt
should be brought together under
the body of the shunt and then
run very close to each other to
the input of the isolated modula-
tor; this minimizes the loop area
of the connection and reduces the
possibility of stray magnetic
fields from interfering with the
measured signal. If the shunt is
not located on the same PC board
as the isolated modulator circuit,
The recommended method for
connecting the isolated modula-
tor to the shunt resistor is shown
in Figure 21. VIN+ (pin 2 of the
HPCL-7860/HCPL-786J) is
connected to the positive
terminal of the shunt resistor,
while VIN- (pin 3) is shorted to
GND1 with the power-supply
return path functioning as the
sense line to the negative
supply current to the gate drive
power supply in order to
eliminate potential ground loop
problems. The only direct con-
nection between the isolated
modulator circuit and the gate
drive circuit should be the
positive power supply line.
terminal of the current shunt.
Table 9. Isotek (Isabellenhütte) Four-Terminal Shunt Summary.
Shunt
Resistance
Maximum
RMS Current
Motor Power Range
120 V -440 V
Tol.
%
ac
ac
Shunt Resistor
Part Number
mΩ
50
20
10
5
A
3
7
hp
kW
PBV-R050-0.5
PBV-R020-0.5
PBV-R010-0.5
PBV-R005-0.5
PBV-R002-0.5
0.5
0.5
0.5
0.5
0.5
0.8-3
2-7
0.6-2
1.4-5
14
25 [28]
39 [71]
4-14
3-10
7-25 [8-28]
11-39 [19-71]
5-19 [6-21]
8-29 [14-53]
2
Note: Values in brackets are with a heatsink for the shunt.
29
Voltage Sensing
In some applications, however,
supply currents flowing through
the power-supply return path may
cause offset or noise problems. In
this case, better performance
may be obtained by connecting
The 39 Ω resistor in series with
the input lead (R2) forms a low-
pass anti-aliasing filter with the
0.01 µF input bypass capacitor
(C2) with a 400 kHz bandwidth.
The resistor performs another
important function as well; it
dampens any ringing which might
be present in the circuit formed
by the shunt, the input bypass
capacitor, and the inductance of
wires or traces connecting the
two. Undamped ringing of the
input circuit near the input
The HCPL-7860/HCPL-786J
Isolated Modulator can also be
used to isolate signals with
amplitudes larger than its
recommended input range with
the use of a resistive voltage
divider at its input. The only
restrictions are that the
VIN+ and VIN- directly across the
shunt resistor with two conduc-
tors, and connecting GND1 to the
shunt resistor with a third
conductor for the power-supply
return path, as shown in Figure
23. When connected this way,
both input pins should be
bypassed. To minimize electro-
magnetic interference of the
sense signal, all of the conductors
(whether two or three are used)
connecting the isolated modula-
tor to the sense resistor should be
either twisted pair wire or closely
spaced traces on a PC board.
impedance of the divider be
relatively small (less than 1 kΩ)
so that the input resistance
(280 kΩ) and input bias current
(1 µA) do not affect the accuracy
of the measurement. An input
bypass capacitor is still required,
although the 39 Ω series damping
resistor is not (the resistance of
the voltage divider provides the
same function). The low-pass
filter formed by the divider
resistance and the input bypass
capacitor may limit the achievable
bandwidth. To obtain higher
bandwidth, the input bypass
capacitor (C2) can be reduced,
but it should not be reduced
much below 1000 pF to maintain
adequate input bypassing of the
isolated modulator.
sampling frequency can alias into
the baseband producing what
might appear to be noise at the
output of the device.
FLOATING
POSITIVE
SUPPLY
HV+
GATE DRIVE
CIRCUIT
R1
D1
5.1 V
C1
0.1 µF
R2a 39 Ω
V
V
V
V
DD2
DD1
IN+
IN-
R2b 39 Ω
MCLK
MDAT
MOTOR
+
-
GND1 GND2
C2a
C2b
R
SENSE
0.01 µF 0.01 µF
HCPL-7860/
HCPL-786J
HV-
Figure 23. Schematic for Three Conductor Shunt Connection.
www.agilent.com/semiconductors
For product information and a complete list of
distributors, please go to our web site.
For technical assistance call:
Americas/Canada: +1 (800) 235-0312 or
(408) 654-8675
Europe: +49 (0) 6441 92460
China: 10800 650 0017
Hong Kong: (+65) 6271 2451
India, Australia, New Zealand: (+65) 6271 2394
Japan: (+81 3) 3335-8152(Domestic/Interna-
tional), or 0120-61-1280(Domestic Only)
Korea: (+65) 6271 2194
Malaysia, Singapore: (+65) 6271 2054
Taiwan: (+65) 6271 2654
Data subject to change.
Copyright © 2003 Agilent Technologies, Inc.
Obsoletes 5988-6490EN
February 10, 2003
5988-8714EN
相关型号：
©2020 ICPDF网 联系我们和版权申明