HCPL-0708-500E [AVAGO]
1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 15Mbps, ROHS COMPLIANT, SURFACE MOUNT, SOP-8;
| 型号： | HCPL-0708-500E |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 15Mbps, ROHS COMPLIANT, SURFACE MOUNT, SOP-8 输出元件 光电 |
| 文件： | 总12页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-0708
High Speed CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Available in SO-8 package, the HCPL-0708 optocoupler
utilizes the latest CMOS IC technology to achieve out-
standing performance with very low power consump-
tion. Basic building blocks of the HCPL-0708 are a high
speed LED and a CMOS detector IC. The detector incor-
• +5 V CMOS compatibility
• 15 ns typical pulse width distortion
• 30 ns max. pulse width distortion
• 40 ns max. propagation delay skew
porates an integrated photodiode, a high-speed trans- • High speed: 15 MBd
impedance amplifier, and a voltage comparator with an
output driver.
• 60 ns max. propagation delay
• 10 kV/µs minimum common mode rejection
• –40 to 100°C temperature range
Functional Diagram
• Safety and regulatory approvals pending
– UL recognized
3750 V rms for 1 min. per UL 1577 for HCPL-0708
– CSA component acceptance Notice #5
– IEC/EN/DIN EN 60747-5-2
NC
1
2
8
7
V
DD
approved for HCPL-0708 Option 060
ANODE
NC
3
4
6
5
CATHODE
NC
V
O
Applications
• Scan drive in PDP
GND
• Digital field bus isolation: DeviceNet, SDS, Profibus
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
TRUTH TABLE
LED
V
, OUTPUT
O
OFF
ON
H
L
*A 0.1 µF bypass capacitor must be
connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
HCPL-0708 is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part
Number
RoHS
non RoHS
Surface
Mount
Gull
Wing
Tape
UL 5000 Vrms/
IEC/EN/DIN
Compliant Compliant Package
& Reel 1 Minute rating EN 60747-5-2 Quantity
-000E
no option SO-8
X
X
X
100 per tube
HCPL-0708 -500E
-560E
#500
-
X
X
1500 per reel
1500 per reel
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example1:
HCPL-0708-500E to order product of Small Outline SO-8 package in Tape and Reel packaging and RoHS compliant.
Example 2:
HCPL-0708 to order product of Small Outline SO-8 package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’
ꢀ
Package Outline Drawing
LAND PATTERN RECOMMENDATION
8
7
2
6
5
4
5.994 0.203
(0.236 0.008ꢀ
XXXV
YWW
3.937 0.127
(0.155 0.005ꢀ
TYPE NUMBER
(LAST 3 DIGITSꢀ
7.49 (0.295ꢀ
DATE CODE
1
3
PIN ONE
1.9 (0.075ꢀ
0.406 0.076
(0.016 0.003ꢀ
1.270
(0.050ꢀ
BSC
0.64 (0.025ꢀ
0.432
(0.017ꢀ
*
7°
5.080 0.127
45° X
(0.200 0.005ꢀ
3.175 0.127
(0.125 0.005ꢀ
0 ~ 7°
0.228 0.025
(0.009 0.001ꢀ
1.524
(0.060ꢀ
0.203 0.102
(0.008 0.004ꢀ
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASHꢀ
5.207 0.254 (0.205 0.010ꢀ
*
0.305
(0.012ꢀ
MIN.
DIMENSIONS IN MILLIMETERS (INCHESꢀ.
LEAD COPLANARITY = 0.10 mm (0.004 INCHESꢀ MAX.
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 milsꢀ MAX.
ꢁ
Solder Reflow Thermal Profile
300
PREHEATING RATE 3°C + 1°Cꢁ–0.5°CꢁSEC.
REFLOW HEATING RATE 2.5°C 0.5°CꢁSEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
100
0
2.5°C 0.5°CꢁSEC.
SOLDERING
TIME
30
160°C
150°C
140°C
200°C
SEC.
30
SEC.
3°C + 1°Cꢁ–0.5°C
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
50
100
150
200
250
TIME (SECONDSꢀ
Note: Non-halide flux should be used.
Recommended Pb-Free IR Profile
TIMEWITHIN 5 °C of ACTUAL
PEAKTEMPERATURE
t
p
20-40 SEC.
260 +0ꢁ-5 °C
T
T
p
217 °C
L
RAMP-UP
3 °CꢁSEC. MAX.
150 - 200 °C
RAMP-DOWN
6 °CꢁSEC. MAX.
T
smax
T
smin
t
s
t
L
60 to 150 SEC.
PREHEAT
60 to 180 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 200 °C, T = 150 °C
T
smax
smin
Note: Non-halide flux should be used.
Regulatory Information
The HCPL-0708 has been approved by the following organizations:
UL
Recognized under UL 1577, component recognition program, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5, File CA88324.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884Teil 2):2003-01 (Option 060 only)
ꢂ
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air
Gap (Clearance)
L(I01)
4.9
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External
Tracking (Creepage)
L(I02)
CTI
4.8
mm
mm
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic
Gap (Internal Clearance)
0.08
Insulation thickness between emitter and
detector; also known as distance through
insulation.
Tracking Resistance
(Comparative Tracking Index)
≥175
IIIa
Volts
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
the surface of a printed circuit board between the solder
fillets of the input and output leads must be considered.
There are recommended techniques such as grooves
and ribs which may be used on a printed circuit board to
achieve desired creepage and clearances. Creepage and
clearance distances will also change depending on fac-
tors such as pollution degree and insulation level.
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These
dimensions are needed as a starting point for the equip-
ment designer when determining the circuit insulation
requirements. However, once mounted on a printed
circuit board, minimum creepage and clearance require-
ments must be met as specified for individual equipment
standards. For creepage, the shortest distance path along
ꢃ
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060)
Description
Symbol
HCPL-0708 Option 060
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms
for rated mains voltage ≤300 V rms
I-IV
I-III
for rated mains voltage ≤450 V rms
Climatic Classification
55/85/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b†
V
560
V peak
V peak
IORM
VPR
1050
VIORM x 1.875 = VPR, 100% Production
Test with tm = 1 sec, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a†
VPR
840
V peak
V peak
VIORM x 1.5 = VPR, Type and Sample Test,
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage†
VIOTM
4000
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Thermal Derating curve, Figure 11.)
Case Temperature
Input Current
Output Power
TS
150
150
600
°C
mA
mW
IS,INPUT
PS,OUTPUT
Insulation Resistance at TS, V10 = 500 V
RIO
≥109
Ω
†Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations sec-
tion IEC/EN/DIN EN 60747-5-2, for a detailed description.
Absolute Maximum Ratings
Parameter
Symbol
TS
Min.
–55
–40
0
Max.
Units
°C
Figure
Storage Temperature
125
Ambient Operating Temperature[1]
Supply Voltages
TA
+100
°C
VDD
VO
6
Volts
Volts
mA
mA
Output Voltage
–0.5
VDD2 +0.5
Average Output Current
Average Forward Input Current
Lead Solder Temperature
Solder Reflow Temperature Profile
IO
2
IF
20
260°C for 10 sec., 1.6 mm below seating plane
See Solder Reflow Temperature Profile Section
Recommended Operating Conditions
Parameter
Symbol
Min.
–40
4.5
Max.
+100
5.5
Units
°C
Figure
Ambient Operating Temperature
Supply Voltages
TA
VDD
IF
V
Input Current (ON)
10
16
mA
1, 2
ꢄ
Electrical Specifications
Over recommended temperature (T = –40°C to +100°C) and 4.5 V ≤ V ≤ 5.5 V.
A
DD
All typical specifications are at T = 25°C, V = +5 V.
A
DD
Parameter
Symbol
VF
Min.
1.3
5
Typ.
Max.
Units
Test Conditions
IF = 12 mA
IR = 10 µA
Fig. Notes
Input Forward Voltage
1.5
1.8
V
V
1
Input Reverse
BVR
Breakdown Voltage
Logic High Output
Voltage
VOH
4.0
4.8
V
V
IF = 0, IO = –20 µA
Logic Low Output
Voltage
VOL
0.01
0.1
IF = 12 mA, IO = 20 µA
Input Threshold Current
ITH
8.2
mA
mA
IOL = 20 µA
IF = 12 mA
2
4
Logic Low Output
Supply Current
IDDL
6.0
4.5
14.0
Logic High Output
Supply Current
IDDH
11.0
mA
IF = 0
3
Switching Specifications
Over recommended temperature (T = –40°C to +100°C) and 4.5 V ≤ V ≤ 5.5 V.
A
DD
All typical specifications are at T = 25°C, V = +5 V.
A
DD
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Notes
Propagation Delay Time
to Logic Low Output
tPHL
20
35
60
ns
IF = 12 mA, CL = 15 pF
CMOS Signal Levels
5
1
Propagation Delay Time
to Logic High Output
tPLH
13
21
14
60
ns
IF = 12 mA, CL = 15 pF
CMOS Signal Levels
5
1
Pulse Width
PW
100
0
ns
ns
Pulse Width Distortion
|PWD|
30
40
IF = 12 mA, CL = 15 pF
CMOS Signal Levels
2
3
2
3
Propagation Delay Skew
tPSK
ns
IF = 12 mA, CL = 15 pF
CMOS Signal Levels
Output Rise Time
(10 - 90%)
tR
20
25
15
ns
IF = 12 mA, CL = 15 pF
CMOS Signal Levels
Output Fall Time
(90 - 10%)
tF
ns
IF = 12 mA, CL = 15 pF
CMOS Signal Levels
Common Mode
Transient Immunity at
Logic High Output
|CMH|
10
10
kV/µs
VCM = 1000 V, TA = 25°C,
IF = 0 mA
4
5
4
5
Common Mode
Transient Immunity at
Logic Low Output
|CML|
15
kV/µs
VCM = 1000 V, TA = 25°C,
IF = 12 mA
ꢅ
Package Characteristics
All Typicals at T = 25°C.
A
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Input-Output Insulation
II-O
1
µA
45% RH, t = 5 s
V
I-O = 3 kV dc,
TA = 25°C
Input-Output Momentary
Withstand Voltage
VISO
3750
Vrms
RH ≤ 50%, t = 1 min.,
TA = 25°C
Input-Output Resistance
Input-Output Capacitance
Notes:
RI-O
CI-O
1012
0.6
Ω
VI-O = 500 V dc
pF
f = 1 MHz, TA = 25°C
1. t
propagation delay is measured from the 50% level on the risiing edge of the input pulse to the 2.5 V level of the falling edge of the V
PHL
O
signal. t
propagation delay is measured from the 50% level on the falling edge of the input pulse to the 2.5 V level of the rising edge of the
PLH
V
O
signal.
2. PWD is defined as |t
- t |.
PHL PLH
3. t is equal to the magnitude of the worst case difference in t
and/or t
that will be seen between units at any given temperature within
PSK
PHL
PLH
the recommended operating conditions.
4. CM is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
H
5. CM is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
L
ꢆ
8
7
6
5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1000
100
10
V
= 5.0 V
DD
V
= 5.0 V
DD
= 20 µA
I
OL
I
F
T
= 25°C
A
+
V
F
–
1.0
0.1
4
3
2
0.01
0.001
-40
0
25
85
100
-40
0
25
85
100
1.1
1.2
1.3
1.4
1.5
1.6
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
V
– FORWARD VOLTAGE – V
F
Figure 1. Typical input diode forward characteristic.
Figure 2. Typical input threshold current vs.
temperature.
Figure 3. Typical logic high O/P supply current vs.
temperature.
8.0
50
V
= 5.0 V
V
= 5.0 V
DD
DD
= 25 °C
45
40
35
30
25
20
15
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
T
A
T
phl
T
plh
PWD
10
5
0
-40
0
25
85
100
5
I
6
7
8
9
10 11 12 13 14
T
– TEMPERATURE – °C
– PULSE INPUT CURRENT – mA
A
F
Figure 4. Typical logic low O/P supply current vs.
temperature.
Figure 5. Typical switching speed vs. pulse input
current.
ꢇ
Application Information
Bypassing and PC Board Layout
As shown in Figure 6, the only external component re-
quired for proper operation is the bypass capacitor. Ca-
pacitor values should be between 0.01 µF and 0.1 µF. For
each capacitor, the total lead length between both ends
of the capacitor and the power-supply pins should not
exceed 20 mm. Figure 7 illustrates the recommended
printed circuit board layout for the HPCL-0708.
The HCPL-0708 optocoupler is extremely easy to use. No
external interface circuitry is required because the HCPL-
0708 uses high-speed CMOS IC technology allowing
CMOS logic to be connected directly to the inputs and
outputs.
8
7
6
5
V
V
1
2
3
4
DD
O
C
I
F
NC
GND
C1, C2 = 0.01 µF TO 0.1 µF
Figure 6. Recommended printed circuit board layout.
V
V
DD
O
I
F
C2
GND
C1, C2 = 0.01 µF TO 0.1 µF
Figure 7. Recommended printed circuit board layout.
Propagation Delay, Pulse-Width Distortion and Propagation
Delay Skew
to high. Similarly, the propagation delay from high to
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a sys-
low (t ) is the amount of time required for the input
PHL
signal to propagate to the output, causing the output to
change from high to low. See Figure8.
tem. The propagation delay from low to high (t ) is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low
PLH
12 mA
0 mA
INPUT
I
50%
F
t
t
PHL
PLH
V
OH
2.5 V CMOS
OUTPUT
90%
90%
V
10%
10%
O
V
OL
Figure 8.
10
Propagation delay skew is defined as the difference be-
tween the minimum and maximum propagation delays,
Pulse-width distortion (PWD) is the difference between
and t and often determines the maximum data
t
PHL
PLH
either t
or t , for any given group of optocouplers
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typical-
ly, PWD on the order of 20 - 30% of the minimum pulse
width is tolerable; the exact figure depends on the par-
ticular application.
PLH
PHL
which are operating under the same conditions (i.e., the
same drive current, supply voltage, output load, and op-
erating temperature). As illustrated in Figure 9, if the in-
puts of a group of optocouplers are switched either ON
or OFF at the same time, t
is the difference between
PSK
the shortest propagation delay, either t
or t , and
PLH
PHL
Propagation delay skew, t , is an important parameter
PSK
the longest propagation delay, either t
or t
.
PLH
PHL
to consider in parallel data applications where synchro-
nization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of opto-
couplers, differences in propagation delays will cause the
data to arrive at the outputs of the optocouplers at differ-
ent times. If this difference in propagation delay is large
enough it will determine the maximum rate at which
parallel data can be sent through the optocouplers.
As mentioned earlier, t
can determine the maximum
PSK
parallel data transmission rate. Figure 10 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the opto-
couplers. The figure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked off of the rising edge of
the clock.
I
F
50%
DATA
INPUTS
CLOCK
2.5 V,
CMOS
V
O
t
PSK
I
50%
F
DATA
OUTPUTS
t
PSK
2.5 V,
CMOS
CLOCK
V
O
t
PSK
Figure 9. Propagation delay skew waveform.
Figure 10. Parallel data transmission example.
throughoptocouplersinaparallelapplicationistwicet
.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an op-
tocoupler. Figure10 shows that there will be uncertainty
in both the data and clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived. From these consider-
ations,theabsoluteminimumpulsewidththatcanbesent
PSK
A cautious design should use a slightly longer pulse
width to ensure that any additional uncertainty in the
rest of the circuit does not cause a problem.
The HCPL-0708 optocouplers offer the advantage of
guaranteed specifications for propagation delays, pulse-
width distortion, and propagation delay skew over the
recommended temperature and power supply ranges.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV02-0877EN
AV02-0877EN January 8, 2008
1ꢀ
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