ACPM-7881-TR1 [AVAGO]
No regulated voltages required;
| 型号： | ACPM-7881-TR1 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | No regulated voltages required 射频 微波 |
| 文件： | 总12页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPM - 7881
W-CDMA Power Amplifer
Data Sheet
Features
Description
•ꢀ Operatingꢀfrequency:ꢀ1920ꢀ-ꢀ1980ꢀMHzꢀ
•ꢀ 28.5ꢀdBmꢀLinearꢀOutputꢀPowerꢀ@ꢀ3.5V
•ꢀ HighꢀEfficiencyꢀ46%ꢀPAE
TheꢀACPM-7881ꢀisꢀaꢀhighꢀperformanceꢀW-CDMAꢀpowerꢀ
amplifierꢀmoduleꢀofferedꢀinꢀaꢀ4x4x1.1mmꢀpackage.ꢀꢀDe-
signedꢀaroundꢀAvagoꢀTechnologies’ꢀGaAsꢀEnhancementꢀ
ModeꢀpHEMTꢀprocess,ꢀtheꢀACPM-7881ꢀoffersꢀpremiumꢀ
powerꢀaddedꢀefficiencyꢀandꢀlinearityꢀinꢀaꢀveryꢀsmallꢀformꢀ
factor.ꢀꢀTheꢀPAꢀisꢀfullyꢀmatchedꢀtoꢀ50ꢀOhmsꢀonꢀtheꢀinputꢀ
andꢀoutput.
•ꢀ Singleꢀbias,ꢀlowꢀquiescentꢀcurrentꢀ(50mA)
•ꢀ Internalꢀ50ꢀohmꢀmatchingꢀnetworksꢀforꢀbothꢀRFꢀinputꢀ
&ꢀoutput
TheꢀamplifierꢀhasꢀexcellentꢀACLRꢀandꢀefficiencyꢀperfor-
manceꢀatꢀmaxꢀPout,ꢀ28.5dBm,ꢀandꢀlowꢀquiescentꢀcurrentꢀ
(50mA)ꢀwithꢀaꢀsingleꢀbiasꢀcontrolꢀvoltage,ꢀVctrlꢀ=ꢀ2.0V.ꢀꢀNoꢀ
regulatedꢀvoltagesꢀareꢀrequiredꢀtoꢀsetꢀtheꢀbias,ꢀVdd2ꢀcanꢀ
beꢀconnectedꢀdirectlyꢀtoꢀtheꢀbattery.
•ꢀ Noꢀregulatedꢀvoltagesꢀrequired
•ꢀ 3.2ꢀ-ꢀ4.5ꢀVꢀlinearꢀoperation
•ꢀ 4.0ꢀxꢀ4.0mmꢀSMTꢀPackage
•ꢀ Lowꢀpackageꢀprofile,ꢀ1.1mm
DesignedꢀinꢀaꢀsurfaceꢀmountꢀRFꢀpackage,ꢀtheꢀACPM-7881ꢀ
isꢀveryꢀcostꢀandꢀsizeꢀcompetitive.ꢀ
Applications
•ꢀ W-CDMAꢀHandsets
•ꢀ DataꢀCards
•ꢀ PDAs
Functional Block Diagram
Vdd1
(1)
Vddꢀ
(10)
RF in
(ꢁ)
Output
Match
RF out
(ꢄ)
Bias Control
MMIC
Module
Vctrl
(ꢃ)
Vddꢁ
(ꢂ)
Gnd
(ꢀ,ꢅ,ꢆ,ꢇ)
Package Diagram
Vddꢀ (Pin 10)
GND
Vdd1 (Pin 1)
RFin
Agilent
ACPM-ꢆꢄꢄ1
MLYWWDD
XXXX
RFout
GND
N/C (GND)
Vctrl
GND (Pin ꢅ)
Vddꢁ (Pin ꢂ)
ꢃmm sq
Bottom View
1.1ꢆꢂmm
max
Pin Description Table
Pin Number
Pin Label
Description
Function
st
nd
1
2
Vdd1
RFin
Supplyꢀbias
RFꢀinput
1 ꢀandꢀ2 ꢀstagesꢀdrainꢀbias,ꢀnominallyꢀ3.5V
W-CDMAꢀsignalꢀinput,ꢀinternallyꢀgroundedꢀthroughꢀ
inductor.ꢀꢀExternalꢀDCꢀblockꢀneededꢀifꢀDCꢀvoltageꢀ
presentꢀonꢀinputꢀtrace.
3
4
5
N/C
Noꢀinternalꢀconnection
Controlꢀvoltage
Supplyꢀbias
RecommendꢀgroundꢀconnectionꢀonꢀPCB
Outputꢀlevelꢀcontrol,ꢀnominallyꢀ2V
Vctrl
Vdd2
Biasꢀcircuitꢀsupply,ꢀ>ꢀ2.5V;ꢀnominallyꢀ2.85V.ꢀ
Doesꢀnotꢀrequireꢀaꢀregulatedꢀinputꢀandꢀcanꢀbeꢀ
connectedꢀdirectlyꢀtoꢀtheꢀbattery,ꢀifꢀdesired.
6
Gnd
Ground
7
Gnd
Ground
8
RFout
Gnd
RFꢀoutput
Ground
W-CDMAꢀsignal,ꢀrequiresꢀexternalꢀDCꢀblock
9
rd
10
Vdd3
Supplyꢀbias
3 ꢀstageꢀdrainꢀbias,ꢀnominallyꢀ3.5V
Package Dimensions
Marking Notes :
4.00 0.0ꢀ755
Rowꢀ3:ꢀꢀ
0.1055
2.0055
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
MLꢀ=ꢀManufacturingꢀLocationꢀ
ꢀ
ꢀ
(PMꢀ=ꢀAvagoꢀTechnologiesꢀ
Malaysia)ꢀ
0.1055
0.6055
Yꢀ=ꢀYearꢀ
WWꢀ=ꢀWorkꢀWeekꢀ
DDꢀ=ꢀDateꢀCode
3.8055
4.00 0.0ꢀ755
0.4055
0.4755
0.6055
0.7055
Rowꢀ4:ꢀꢀ
ꢀ
ꢀ
XXXXꢀ=ꢀTraceꢀCodeꢀ
(AvagoꢀTechnologiesꢀinternalꢀreference)
0.4055
0.7055
ꢀ
ꢀ
Viewed down through top of package
ꢁ
Maximum Ratings Table
Parameter
Min.
Max.
Supplyꢀvoltage,ꢀVdd1ꢀandꢀVdd3
Supplyꢀvoltage,ꢀVdd2
Analogꢀcontrolꢀvoltage
RFꢀinputꢀpower
5.0ꢀV
-1ꢀV
-1ꢀV
5.0ꢀV
3.0ꢀV
+5ꢀdBm
+90ꢀ°C
12:1
Operatingꢀcaseꢀtemperature
LoadꢀVSWR
Storageꢀtemperatureꢀ(caseꢀtemperature)
-30ꢀ°C
+100ꢀ°C
Notes:
1.ꢀ Operationꢀofꢀthisꢀdeviceꢀinꢀexcessꢀofꢀanyꢀofꢀtheseꢀlimitsꢀmayꢀcauseꢀpermanentꢀdamage.
2.ꢀ AvoidꢀelectrostaticꢀdischargeꢀonꢀI/Oꢀpins
Recommended Operating Conditions
Parameter
Min.
1.0ꢀV
2.6ꢀV
1.9ꢀV
-20ꢀ°C
Typ.
Max.
4.5ꢀV
4.5ꢀV
2.1ꢀV
+85ꢀ°C
Supplyꢀvoltage,ꢀVdd1ꢀandꢀVdd3
Supplyꢀvoltage,ꢀVdd2
Controlꢀvoltage
3.5ꢀV
2.85ꢀV
2.0ꢀV
Caseꢀtemperature
ꢀ
Electrical Characteristics
UnlessꢀOtherwiseꢀSpecified:ꢀꢀf=1920-1980MHz,ꢀVdd1=Vdd3=3.5V,ꢀVdd2=2.85V,ꢀVctrl=2.0V,ꢀPout=28.5dBm,ꢀTa=25°C,ꢀ
Zin/Zoutꢀ=ꢀ50Ω
Parameter
Min.
Typ.
20
Max.
50
Units
uA
LeakageꢀCurrent,ꢀIdd1,2,3;ꢀꢀVctrl=0ꢀV,ꢀRFꢀOffꢀꢀ
ControlꢀCurrent,ꢀIctrl;ꢀVctrl=2.0ꢀV
BiasꢀCurrent,ꢀIdd2;ꢀVctrl=2ꢀV,ꢀVdd2=2.85ꢀV
QuiescentꢀCurrent,ꢀIdd1,3;ꢀRFꢀOffꢀꢀꢀꢀVctrl=2.0ꢀV
75
110
6
145
10
uA
mA
mA
50
80
At Pout=28.5dBm
SupplyꢀcurrentꢀIdd1+Idd3
PAEꢀincludingꢀVdd1,2,3
Gain
435
46
490
mA
41
%
26.5
29
31.5
dB
InputꢀVSWR
1.1
2.0:1
-
ACLR
ꢀ
5MHzꢀoffset
10MHzꢀoffset
-42
-54
-50
-60
-140
-38
-48
-40
-45
-138
dBc/3.84MHz
dBc/3.84MHz
dBc/1MHz
dBc/1MHz
dBm/Hz
2ndꢀHarmonic
3rdꢀHarmonic
NoiseꢀPowerꢀinꢀReceiveꢀband,ꢀ2110ꢀtoꢀ2170MHz
Poutꢀ=ꢀ-50dBmꢀtoꢀ28.5dBm
NoiseꢀFigure
2.1
7.5
3.1
4.1
-60
dB
Stability,ꢀnoꢀspuriousꢀunderꢀconditions:
VSWR=4:1,ꢀallꢀphases
dBc
3<Vdd<4.5,ꢀ-50ꢀdBmꢀtoꢀ28.5ꢀdBm
At Pout=16dBm
SupplyꢀcurrentꢀIdd1+Idd3
PAEꢀincludingꢀVdd1,2,3
Gain
120
9.0
29
145
mA
%
dB
ACLR
ꢀ
5MHzꢀoffset
-42
-55
-38
-48
dBc/3.84MHz
dBc/3.84MHz
10MHzꢀoffset
PA Operation/Shutdown Logic: DC signals
Vctrl
Vdd2
OperationalꢀMode
Shutdown
ꢀ2.0Vꢀtyp
<ꢀ0.2V
2.6ꢀ~ꢀ3.5Vꢀ(ꢀ2.85Vꢀtyp)
0ꢀ~ꢀ4.5ꢀV
ꢃ
Performance Graphs
UnlessꢀOtherwiseꢀSpecified:ꢀꢀf=1920-1980MHz,ꢀVdd1=Vdd3=3.5V,ꢀVdd2=2.85V,ꢀVctrl=2.0V,ꢀꢀ
Pout=28.5dBm,ꢀTa=25°C,ꢀZin/Zoutꢀ=ꢀ50Ω
Data measured at 1920MHz
60
70
40
30
20
10
0
600
700
400
300
200
100
0
-20
-27
-30
-37
-40
-47
-70
-77
-60
-10 -7
0
7
10 17 20 27 30
Pout (dB5)
-10 -7
0
7
10 17 20 27 30
Pout (dB5)
-10 -7
0
7
10 17 20 27 30
Pout (dB5)
Figure 1. PAE vs Pout
Figure 2. Total Idd vs Pout
Figure 3. ACLR1 vs Pout
-20
-27
-30
-37
-40
-47
-70
-77
-60
-67
-ꢀ0
30
29
28
2ꢀ
26
27
24
23
22
21
20
-27 -20 -17 -10 -7
0
7
10 17 20 27 30
-10 -7
0
7
10 17 20 27 30
Pout (dB5)
Pout (dB5)
Figure 4. ACLR2 vs Pout
Figure 5. Gain vs Pout
Data measured at 1950MHz
-20
-27
-30
-37
-40
-47
-70
-77
-60
60
600
700
400
300
200
100
0
70
40
30
20
10
0
-10 -7
0
7
10 17 20 27 30
Pout (dB5)
-10 -7
0
7
10 17 20 27 30
-10 -7
0
7
10 17 20 27 30
Pout (dB5)
Pout (dB5)
Figure 7. Total Idd vs Pout
Figure 6. PAE vs Pout
Figure 8. ACLR1 vs Pout
ꢂ
-20
-27
-30
-37
-40
-47
-70
-77
-60
-67
-ꢀ0
30
29
28
2ꢀ
26
27
24
23
22
21
20
-10 -7
0
7
10 17 20 27 30
-27 -20 -17 -10 -7
0
7
10 17 20 27 30
Pout (dB5)
Pout (dB5)
Figure 9. ACLR2 vs Pout
Figure 10. Gain vs Pout
Data measured at 1980MHz
-20
-27
-30
-37
-40
-47
-70
-77
-60
600
700
400
300
200
100
0
60
70
40
30
20
10
0
-10 -7
0
7
10 17 20 27 30
-10 -7
0
7
10 17 20 27 30
-10 -7
0
7
10 17 20 27 30
Pout (dB5)
Pout (dB5)
Pout (dB5)
Figure 11. PAE vs Pout
Figure 12. Total Idd vs Pout
Figure 13. ACLR1 vs Pout
-20
-27
-30
-37
-40
-47
-70
-77
-60
-67
-ꢀ0
30
29
28
2ꢀ
26
27
24
23
22
21
20
-10 -7
0
7
10 17 20 27 30
Pout (dB5)
-27 -20 -17 -10 -7
0
7
10 17 20 27 30
Pout (dB5)
Figure 14. ACLR2 vs Pout
Figure 15. Gain vs Pout
ꢅ
3
performedꢀ
Moisture Sensitivity Classification: Class 3
PreconditioningperJESD22-A113-DClass was
onꢀallꢀdevicesꢀpriorꢀtoꢀreliabilityꢀtesting.
ESD Sensitivity Level
HumanꢀBodyꢀModelꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
(EIA/JESD22-A114B):ꢀClassꢀ1Aꢀ(250Vmin,ꢀlessꢀthanꢀ500V)ꢀ
ACPM-7881ꢀisꢀaꢀmoistureꢀsensitiveꢀcomponent.ꢀIt’sꢀim-
portantꢀthatꢀtheꢀpartsꢀareꢀhandledꢀunderꢀprecautionꢀandꢀ
aꢀproperꢀmanner.ꢀTheꢀhandling,ꢀbakingꢀandꢀout-of-packꢀ
storageꢀconditionsꢀofꢀtheꢀmoistureꢀsensitiveꢀcomponentsꢀ
areꢀdescribedꢀinꢀIPC/JEDCꢀS-STD-033A.ꢀAvagoꢀTechnolo-
giesꢀrecommendsꢀutilizingꢀtheꢀstandardꢀprecautionsꢀlistedꢀ
below.ꢀ
MachineꢀModelꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
(EIA/JESD22-A115A):ꢀClassꢀAꢀ(50Vmin,ꢀlessꢀthanꢀ200V)
Notes:
ESDꢀSensitivityꢀlevelꢀforꢀHumanꢀBodyꢀModelꢀandꢀMachineꢀModelꢀ
necessitateꢀtheꢀfollowing
handlingꢀprecautions:
1.ꢀ EnsureꢀFaradayꢀcageꢀorꢀconductiveꢀshieldꢀbagꢀisꢀusedꢀduringꢀtrans-
portationꢀprocesses.
2.ꢀ IfꢀtheꢀstaticꢀchargeꢀatꢀSMTꢀassembleꢀstationꢀisꢀaboveꢀtheꢀdeviceꢀ
sensitivityꢀlevel,ꢀplaceꢀanꢀionizerꢀnearꢀtoꢀtheꢀdeviceꢀforꢀchargeꢀneu-
tralizationꢀpurposes.
1.ꢀ CalculatedꢀShelfꢀLifeꢀinꢀSealedꢀBag:ꢀ12ꢀmonthsꢀatꢀ<ꢀ40°Cꢀ
andꢀ<ꢀ90%ꢀRelativeꢀHumidityꢀ(RH)
2.ꢀ PeakꢀPackageꢀBodyꢀTemperature:ꢀ250°C
3.ꢀ Personalꢀgroundingꢀmustꢀbeꢀwornꢀatꢀallꢀtimesꢀwhenꢀhandlingꢀtheꢀ
devices.
3.ꢀ Afterꢀbagꢀisꢀopened,ꢀdevicesꢀthatꢀwillꢀbeꢀsubjectedꢀtoꢀ
reflowꢀsolderꢀofꢀotherꢀhighꢀtemperatureꢀprocessꢀmustꢀ
be:
a.ꢀ Mountedꢀwithinꢀ168ꢀhoursꢀofꢀfactoryꢀconditionꢀ≤ꢀ
30°Cꢀ/ꢀ60%ꢀRH
b.ꢀ Storedꢀatꢀ<10%ꢀRHꢀifꢀnotꢀused
4.ꢀ Devicesꢀrequireꢀbaking,ꢀbeforeꢀmountingꢀif:
a.ꢀ Humidityꢀindicatorꢀcardꢀisꢀ>ꢀ10%ꢀwhenꢀreadꢀatꢀ23ꢀ
ꢀ 5°Cꢀ immediatelyꢀ afterꢀ moistureꢀ barrierꢀ bagꢀ isꢀ
opened.
b.ꢀ Itemsꢀ3aꢀorꢀ3bꢀisꢀnotꢀmet
5.ꢀ Ifꢀbakingꢀisꢀrequired,ꢀpleaseꢀreferꢀtoꢀJ-STD-033ꢀstandardꢀ
forꢀ lowꢀ temperatureꢀ (40°C)ꢀ bakingꢀ requirementꢀ inꢀ
Tape/Reelꢀform.
Tape Dimensions and Orientation
4.00 ±�0.10[2]
1.ꢀ7 ±�0.10
2.00 ±�0.07[1]
0.30 ±�0.07
∅1.77 ±�0.07
7.70 ±�0.07[3]
12.00 ±�0.30
C
4.38 ±�0.10
1.80 ±�0.10
L
4.38 ±�0.10
∅1�.70 (MIN)
�
4.38 ±�0.10
8.00 ±�0.10
Notes:
1. Measured from centerline of sprocket hole to centerline of pocket
ꢁ. Cumulative tolerance of 10 sprocket holes is ± 0.ꢁ mm
ꢀ. All dimensions in millimeters unless otherwise stated.
Agilent
ACPM-ꢀ881
MLYWWDD
XXXX
ꢆ
Reel Dimensions and Orientation
BACK VIEW
Shading indicates
thru slots
18.4 5ax.
+0.4
-0.2
1ꢀ8
70 5in.
27
5in wide (ref)
Slot for carrier
tape insertion
for attach5ent
to reel hub
+2.0
12.4
-0.0
(2 places 180° apart)
REEL
FRONT VIEW
CARRIER
TAPE
USER
FEED
DIRECTION
COVER TAPE
Notes:
1. Reel shall be labeled with the following information (as a minimum).
a. manufacturers name or symbol
b. Agilent Technologies part number
c. purchase order number
d. date code
1.7 5in.
13.0±�0.2
21.0±�0.8
e. quantity of units
ꢁ. A certificate of compliance shall be issued and accompany each shipment of product.
ꢀ. Reel must not be made with or contain ozone depleting materials.
ꢃ. All dimensions in millimeters (mm).
Order Information
Part Number
No. of
Devices
Container
ACPM-7881-BLK 100
ACPM-7881-TR1 1000
Bulk
7”ꢀTapeꢀandꢀReel
ꢄ
Suggested Board Implementation
Cꢂ (10,000pF)
C1 (ꢃꢆ00pF)
Cꢃ (ꢀꢀpF)
Cꢀ (ꢀꢀpF)
GND
Cꢁ (ꢃꢆ00pF)
Notes:
1.ꢀ Allꢀdecouplingꢀcapacitorsꢀshouldꢀbeꢀplacedꢀasꢀcloseꢀtoꢀtheꢀpowerꢀmoduleꢀasꢀpossible.
2.ꢀ RFinꢀ(Pinꢀ2)ꢀhasꢀaꢀgroundedꢀinductorꢀinsideꢀpackageꢀasꢀaꢀmatchingꢀelement.ꢀꢀAnꢀexternalꢀseriesꢀcapacitorꢀisꢀneededꢀifꢀaꢀDCꢀvoltageꢀisꢀpresent.
3.ꢀ Anꢀadditionalꢀbatteryꢀbypassꢀcapacitorꢀshouldꢀbeꢀplacedꢀonꢀbiasꢀlineꢀbeforeꢀtheꢀbatteryꢀterminal,ꢀbutꢀdoesꢀnotꢀneedꢀtoꢀbeꢀimmediatelyꢀadjacentꢀ
toꢀtheꢀPAꢀmodule.ꢀꢀTheꢀbypassꢀcapacitorꢀshouldꢀbeꢀaꢀlargeꢀvalue,ꢀnominallyꢀbetweenꢀ2.2uFꢀandꢀ4.7uF.
4.ꢀ TraceꢀimpedanceꢀonꢀRFꢀlinesꢀshouldꢀbeꢀ50Ω.
ꢇ
Solder Reflow Profile
Suggested Lead Free Reflow Profile For SnAgCu Solder Paste
Peak = ꢁꢂ0 ꢂ˚C
ꢁꢂ0
ꢁ00
Theꢀmostꢀcommonlyꢀusedꢀsolderꢀreflowꢀmethodꢀisꢀaccom-
plishedꢀinꢀaꢀbeltꢀfurnaceꢀusingꢀconvectionꢀheatꢀtransfer.ꢀ
Thisꢀprofileꢀisꢀdesignedꢀtoꢀensureꢀreliableꢀfinishedꢀjoints.ꢀ
However,ꢀtheꢀprofileꢀindicatedꢀꢀwillꢀvaryꢀamongꢀdifferentꢀ
solderꢀpastesꢀfromꢀdifferentꢀmanufacturersꢀandꢀisꢀshownꢀ
hereꢀforꢀreferenceꢀonly.
Melting point = ꢁ1ꢄ˚C
1ꢂ0
100
Otherꢀfactorsꢀthatꢀcanꢀaffectꢀtheꢀprofileꢀincludeꢀtheꢀdensityꢀ
andꢀtypesꢀofꢀcomponentsꢀonꢀtheꢀboard,ꢀtypeꢀofꢀsolderꢀ
usedꢀandꢀtypeꢀofꢀboardꢀorꢀsubstrateꢀmaterialꢀbeingꢀused.ꢀ
Theꢀ profileꢀ showsꢀ theꢀ actualꢀ temperatureꢀ thatꢀ shouldꢀ
occurꢀonꢀtheꢀsurfaceꢀofꢀaꢀtestꢀboardꢀatꢀorꢀnearꢀtheꢀcentralꢀ
ofꢀtheꢀsolderꢀjoint.ꢀꢀForꢀthisꢀtypeꢀofꢀreflowꢀsoldering,ꢀtheꢀ
circuitꢀboardꢀandꢀsolderꢀjointsꢀareꢀfirstꢀtoꢀgetꢀheatedꢀup.ꢀ
Theꢀcomponentsꢀonꢀtheꢀboardꢀareꢀthenꢀheatedꢀbyꢀcon-
duction.ꢀTheꢀcircuitꢀboard,ꢀbecauseꢀitꢀhasꢀaꢀlargeꢀsurfaceꢀ
area,ꢀabsorbsꢀthermalꢀenergyꢀefficientlyꢀandꢀdistributesꢀ
thisꢀheatꢀtoꢀtheꢀcomponents.ꢀ
ꢂ0
Cooling
Preheat
Ramp ꢁ
Reflow
Ramp 1
1ꢂ0
ꢁ00
100
ꢂ0
ꢁꢂ0
0
Seconds
Lead Free Reflow Profile General Guidelines
i. Ramp 1
Rampꢀtoꢀ100°C.ꢀMaximumꢀslopeꢀforꢀthisꢀzoneꢀisꢀlimitedꢀtoꢀ
2°C/sec.ꢀFasterꢀheatingꢀwithꢀrampꢀhigherꢀthanꢀ2°Cꢀmayꢀ
resultꢀinꢀexcessiveꢀsolderꢀballingꢀandꢀslump.ꢀꢀ
Reflowꢀtemperatureꢀprofilesꢀdesignedꢀforꢀtin/leadꢀalloysꢀ
willꢀneedꢀtoꢀbeꢀrevisedꢀaccordinglyꢀtoꢀcaterꢀforꢀtheꢀmelt-
ingꢀpointꢀofꢀtheꢀleadꢀfreeꢀsolderꢀbeingꢀ34°Cꢀ(54°F)ꢀhigherꢀ
thanꢀthatꢀofꢀtin/leadꢀeutecticꢀorꢀnear-eutecticꢀalloys.ꢀInꢀ
addition,ꢀtheꢀsurfaceꢀtensionꢀofꢀmoltenꢀleadꢀfreeꢀsolderꢀ
alloysꢀisꢀsignificantlyꢀhigherꢀthanꢀtheꢀsurfaceꢀtensionꢀforꢀ
tin/leadꢀalloysꢀandꢀthisꢀcanꢀreduceꢀtheꢀspreadꢀofꢀleadꢀfreeꢀ
solderꢀduringꢀreflow.
ii. Preheat
Preheatꢀsettingꢀshouldꢀrangeꢀfromꢀ100ꢀtoꢀ150°Cꢀoverꢀaꢀpe-
riodꢀofꢀ60ꢀtoꢀ120ꢀsecondsꢀdependingꢀonꢀtheꢀcharacteristicsꢀ
ofꢀtheꢀPCBꢀcomponentsꢀandꢀtheꢀthermalꢀcharacteristicsꢀ
ofꢀtheꢀoven.ꢀIfꢀpossible,ꢀdoꢀnotꢀprolongꢀpreheatꢀasꢀitꢀwillꢀ
causeꢀexcessiveꢀoxidationꢀtoꢀoccurꢀtoꢀtheꢀsolderꢀpowderꢀ
surface.ꢀ
iii. Ramp 2
Theꢀtimeꢀinꢀthisꢀzoneꢀshouldꢀbeꢀkeptꢀbelowꢀ35ꢀsecondsꢀtoꢀ
reduceꢀtheꢀriskꢀofꢀfluxꢀexhaustion.Theꢀrampꢀupꢀrateꢀshouldꢀ
beꢀ2°C/secꢀfromꢀ150°Cꢀtoꢀre-flowꢀatꢀ217°C.ꢀItꢀisꢀimportantꢀ
thatꢀtheꢀfluxꢀmediumꢀretainsꢀitsꢀactivityꢀduringꢀthisꢀphaseꢀ
toꢀensureꢀtheꢀcompleteꢀcoalescenceꢀofꢀtheꢀsolderꢀparticlesꢀ
duringꢀre-flow.ꢀꢀ
iv. Reflow
Theꢀ peakꢀ reflowꢀ temperatureꢀ isꢀ calculatedꢀ byꢀ addingꢀ
~32°Cꢀtoꢀtheꢀmeltingꢀpointꢀofꢀtheꢀalloy.ꢀꢀLeadꢀfreeꢀsolderꢀ
pasteꢀmeltsꢀatꢀ218°Cꢀandꢀpeakꢀreflowꢀtemperatureꢀisꢀ218°Cꢀ
+ꢀ32°Cꢀꢀ=ꢀ250°Cꢀ( 5°C).ꢀNoteꢀthatꢀtotalꢀtimeꢀoverꢀ218°Cꢀ
isꢀcriticalꢀandꢀshouldꢀtypicallyꢀbeꢀ60ꢀ–ꢀ150ꢀseconds.ꢀThisꢀ
periodꢀdeterminesꢀtheꢀappearanceꢀofꢀtheꢀsolderꢀjoints.ꢀ
Excessiveꢀtimeꢀaboveꢀreflowꢀmayꢀcauseꢀaꢀdullꢀfinishꢀandꢀ
charredꢀofꢀfluxꢀresidues.ꢀꢀInsufficientꢀtimeꢀaboveꢀreflowꢀ
mayꢀleadꢀtoꢀpoorꢀwettingꢀandꢀimproperlyꢀfusedꢀ(cloudy)ꢀ
fluxꢀresidues.
v. Cooling
Maximumꢀslopeꢀforꢀcoolingꢀisꢀlimitedꢀtoꢀ3°C/sec.ꢀꢀMoreꢀ
rapidꢀcoolingꢀmayꢀcauseꢀsolderꢀjointsꢀcrackꢀwhileꢀcoolingꢀ
atꢀaꢀslowerꢀrateꢀwillꢀincreaseꢀtheꢀlikelihoodꢀofꢀaꢀcrystallineꢀ
appearanceꢀonꢀtheꢀsolderꢀjointsꢀ(dullꢀfinish).
10
PCB Design Guidelines
ꢁ.1
0.ꢀꢆꢂ
TheꢀrecommendedꢀACPM-7881ꢀPCBꢀlandꢀpatternꢀisꢀshownꢀ
inꢀFigureꢀ16.ꢀTheꢀsubstrateꢀisꢀcoatedꢀwithꢀsolderꢀmaskꢀbe-
tweenꢀtheꢀI/Oꢀandꢀconductiveꢀpaddleꢀtoꢀprotectꢀtheꢀgoldꢀ
padsꢀfromꢀshortꢀcircuitꢀthatꢀisꢀcausedꢀbyꢀsolderꢀbleedingꢀ
/ꢀbridging.
Stencil Design Guidelines
Aꢀproperlyꢀdesignedꢀsolderꢀscreenꢀorꢀstencilꢀisꢀrequiredꢀtoꢀ
ensureꢀoptimumꢀamountꢀofꢀsolderꢀpasteꢀisꢀdepositedꢀontoꢀ
theꢀPCBꢀpads.
Theꢀrecommendedꢀstencilꢀlayoutꢀisꢀshownꢀinꢀ
Figureꢀ17.Theꢀstencilꢀhasꢀaꢀsolderꢀpasteꢀdepositionꢀopeningꢀ
0.ꢀꢆꢂ
Figure 16. PCB land pattern (di5ensions in 55)
0.ꢂꢂ
thatꢀisꢀapproximatelyꢀ80%ꢀofꢀtheꢀPCBꢀpad.ꢀReducingꢀtheꢀ
stencilꢀopeningꢀcanꢀpotentiallyꢀgenerateꢀmoreꢀvoids.ꢀOnꢀ
theꢀotherꢀhand,ꢀstencilꢀopeningsꢀlargerꢀthanꢀ100%ꢀwillꢀleadꢀ
toꢀexcessiveꢀsolderꢀpasteꢀsmearꢀorꢀbridgingꢀacrossꢀtheꢀI/Oꢀ
padsꢀorꢀconductiveꢀpaddleꢀtoꢀadjacentꢀI/Oꢀpads.ꢀConsider-
ingꢀtheꢀfactꢀthatꢀsolderꢀpasteꢀthicknessꢀwillꢀdirectlyꢀaffectꢀ
theꢀqualityꢀofꢀtheꢀsolderꢀjoint,ꢀaꢀgoodꢀchoiceꢀisꢀtoꢀuseꢀlaserꢀ
cutꢀstencilꢀcomposedꢀofꢀ0.100mmꢀ(4ꢀmils)ꢀorꢀ0.127mmꢀ(5ꢀ
mils)ꢀthickꢀstainlessꢀsteelꢀwhichꢀisꢀcapableꢀofꢀproducingꢀ
theꢀrequiredꢀfineꢀstencilꢀoutline.ꢀTheꢀcombinedꢀPCBꢀandꢀ
stencilꢀlayoutꢀisꢀshownꢀinꢀFigureꢀ18.
1.ꢅꢄ
0.ꢅꢃ
0.ꢃꢃ
0.ꢅꢃ
Figure 1ꢀ. Stencil outline drawing (di5ensions in 55)
ꢁ.1
0.ꢂꢂ
1.ꢅꢄ
Stencil
Opening
0.ꢃꢃ
Figure 18. Co5bined PCB and stencil layouts (di5ensions in 55)
11
ACPM-7881
package
is
Sn63
(63%
Sn,
37%
Pb).
It
isaeutecticꢀ
Solder Paste Recommendation
TheꢀACPM-7881ꢀpackageꢀisꢀaꢀleadꢀfreeꢀpackageꢀthatꢀwasꢀ
provenꢀtoꢀpassꢀMSL3ꢀwhenꢀreflowedꢀunderꢀleadꢀfreeꢀsolderꢀ
reflowꢀprofile.ꢀTheꢀrecommendedꢀleadꢀfreeꢀsolderꢀforꢀSMTꢀ
reflowꢀisꢀSn-Ag-Cuꢀ(95.5%Tin,ꢀ3.8%ꢀSilver,ꢀ0.7%ꢀCopper)ꢀorꢀ
otherꢀsimilarꢀSn-Ag-Cuꢀsolders.ꢀThisꢀleadꢀfreeꢀsolderꢀpasteꢀ
hasꢀaꢀmeltingꢀpointꢀofꢀ218°Cꢀ(423°F),ꢀtheꢀternaryꢀeutecticꢀ
ofꢀSn-Ag-Cuꢀsystem,ꢀgivingꢀitꢀtheꢀadvantageꢀofꢀbeingꢀtheꢀ
lowest
low
during
meltingꢀlead
enoughtoprotect
solderreflowoperations
free
alternative.
damaging
provided
This
theꢀinternal
the
temperatureꢀisstillꢀ
from
circuitryꢀ
timeꢀ
exposure
atꢀpeakꢀreflowꢀtemperaturesꢀisꢀnotꢀtooꢀexcessive.
Inꢀcertainꢀsituations,ꢀtheꢀdesignerꢀmayꢀuseꢀleadedꢀsolderꢀ
pasteꢀforꢀreflow.ꢀTheꢀrecommendedꢀsolderꢀforꢀmountingꢀ
compoundꢀwithꢀaꢀtypicalꢀmeltingꢀpointꢀofꢀ183°C.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved.
5989-1894EN - April 6, 2006
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