ACPL-072L-XXXE [AVAGO]
Logic IC Output Optocoupler, 1-Element;
| 型号： | ACPL-072L-XXXE |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | Logic IC Output Optocoupler, 1-Element |
| 文件： | 总10页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-772L and ACPL-072L
3.3V/5V High Speed CMOS Optocoupler
Data Sheet
Description
Features
•ꢀ Dualꢀvoltageꢀoperationꢀ(3.3Vꢀandꢀ5V)ꢀ
theꢀ ACPL-772Lꢀ orꢀ ACPL-072Lꢀ optocouplersꢀ utilizeꢀ theꢀ •ꢀ Allowꢀlevelꢀshiftingꢀfunctionalityꢀ
Availableꢀinꢀeitherꢀanꢀ8-pinꢀDIPꢀorꢀSO-8ꢀstyleꢀrespectively,ꢀ
latestꢀCMOSꢀICꢀtechnologyꢀtoꢀachieveꢀoutstandingꢀspeedꢀ
performanceꢀ ofꢀ minimumꢀ 25MBdꢀ dataꢀ rateꢀ andꢀ 6nsꢀ
maximumꢀpulseꢀwidthꢀdistortion.
•ꢀ SupportꢀhighꢀSpeedꢀdatarateꢀofꢀ25ꢀMBdꢀ
•ꢀ WideꢀTemperatureꢀoperationꢀ
•ꢀ CMOSꢀoutputꢀandꢀbufferꢀinputꢀ
BasicꢀbuildingꢀblocksꢀofꢀthisꢀfamilyꢀofꢀproductsꢀareꢀaꢀCMOSꢀ
LEDꢀdriverꢀIC,ꢀaꢀhighꢀspeedꢀLEDꢀandꢀaꢀCMOSꢀdetectorꢀIC.ꢀAꢀ
CMOSꢀlogicꢀinputꢀsignalꢀcontrolsꢀtheꢀLEDꢀdriverꢀIC,ꢀwhichꢀ
suppliesꢀcurrentꢀtoꢀtheꢀLED.ꢀTheꢀdetectorꢀICꢀincorporatesꢀ
anꢀintegratedꢀphotodiode,ꢀaꢀhighꢀspeedꢀtransimpedanceꢀ
amplifier,ꢀandꢀaꢀvoltageꢀcomparatorꢀwithꢀanꢀoutputꢀdriver.
•ꢀ CompatibleꢀwithꢀCMOSꢀandꢀTTLꢀlogicꢀlevel
•ꢀ Lowerꢀpowerꢀconsumptionꢀwithꢀ3.3Vꢀsupply
•ꢀ Goodꢀ ACꢀ performanceꢀ withꢀ lowerꢀ pulseꢀ widthꢀ
distortion
•ꢀ Lead-freeꢀoptionꢀavailable
Specifications
Functional Diagram
•ꢀ 3.3Vꢀandꢀ5VꢀCMOSꢀCompatibility
•ꢀ HighꢀSpeed:ꢀDCꢀtoꢀ25ꢀMBd
•ꢀ 6nsꢀmax.ꢀPulseꢀWidthꢀDistortionꢀ
•ꢀ 40ꢀnsꢀmax.ꢀProp.ꢀDelayꢀ
**V
DD1
1
2
8
7
V
**
DD2
V
NC*
I
•ꢀ 20ꢀnsꢀmax.ꢀꢀProp.ꢀDelayꢀSkew
•ꢀ 10ꢀkV/msꢀmin.ꢀCommonꢀModeꢀRejection
•ꢀ -40ꢀ°Cꢀꢀtoꢀ105ꢀ°CꢀTemperatureꢀRange
•ꢀ SafetyꢀandꢀRegulatoryꢀApprovalsꢀPendingꢀꢀ
ULꢀRecognised
I
O
3
4
6
5
NC*
V
O
LED1
GND
GND
2
1
SHIELD
-ꢀ 5000V ꢀforꢀ1ꢀmin.ꢀperꢀUL1577ꢀforꢀACPL-772Lꢀꢀ
rms
forꢀoptionꢀ020
*ꢀ Pinꢀ3ꢀisꢀtheꢀanodeꢀofꢀtheꢀinternalꢀLEDꢀandꢀmustꢀbeꢀleftꢀunconnectedꢀ
forꢀ guaranteedꢀ datasheetꢀ performance.ꢀ Pinꢀ 7ꢀ isꢀ notꢀ connectedꢀ
internally.
**ꢀ Aꢀ0.1uFꢀbypassꢀcapacitorꢀmustꢀbeꢀconnectedꢀbetweenꢀpinsꢀ1ꢀandꢀ4,ꢀ
andꢀ5ꢀandꢀ8.
-ꢀ 3750V ꢀforꢀ1ꢀmin.ꢀperꢀUL1577ꢀforꢀACPL-072Lꢀ
rms
CSAꢀComponentꢀAcceptanceꢀNoticeꢀ#5ꢀ
IEC/EN/DINꢀENꢀ60747-5-2ꢀ
–ꢀ V
–ꢀ V
ꢀ=ꢀ630ꢀV
ꢀ=ꢀ560ꢀV
ꢀforꢀACPL-772LꢀOptionꢀ060
ꢀforꢀACPL-072LꢀOptionꢀ060
IORM
peak
ꢀ
TRUTH TABLE (POSITIVE LOGIC)
IORM
peak
Applications
VI, INPUT
LED1
OFF
ON
VO, OUTPUT
•ꢀ DigitalꢀFieldbusꢀIsolation:ꢀCC-Link,ꢀDeviceNet,ꢀProfibus,ꢀ
SDS
•ꢀ MultiplexedꢀDataꢀTransmission
•ꢀ GeneralꢀInstrumentꢀandꢀDataꢀAcquisition
•ꢀ ComputerꢀPeripheralꢀinterface
H
L
H
L
•ꢀ MicroprocessorꢀSystemꢀInterface
CAUTION:ꢀItꢀisꢀadvisedꢀthatꢀnormalꢀstaticꢀprecautionsꢀbeꢀtakenꢀinꢀhandlingꢀandꢀassemblyꢀ
ofꢀthisꢀcomponentꢀtoꢀpreventꢀdamageꢀand/orꢀdegradation,ꢀwhichꢀmayꢀbeꢀinducedꢀbyꢀESD.
ꢀ
Package Dimensions
ACPL-772L 8-Pin DIP Package
9.65 ꢀ.ꢁ5
(ꢀ.38ꢀ ꢀ.ꢀ0ꢀꢂ
7.6ꢁ ꢀ.ꢁ5
(ꢀ.3ꢀꢀ ꢀ.ꢀ0ꢀꢂ
OPTION ꢀ6ꢀ CODE*
DATE CODE
TYPE NUMBER
8
0
7
6
5
6.35 ꢀ.ꢁ5
(ꢀ.ꢁ5ꢀ ꢀ.ꢀ0ꢀꢂ
A XXXXV
YYWW
ꢁ
3
4
0.78 (ꢀ.ꢀ7ꢀꢂ MAX.
0.09 (ꢀ.ꢀ47ꢂ MAX.
+ ꢀ.ꢀ76
- ꢀ.ꢀ50
ꢀ.ꢁ54
5˚ TYP.
+ ꢀ.ꢀꢀ3ꢂ
- ꢀ.ꢀꢀꢁꢂ
(ꢀ.ꢀ0ꢀ
3.56 ꢀ.03
(ꢀ.04ꢀ ꢀ.ꢀꢀ5ꢂ
4.7ꢀ (ꢀ.085ꢂ MAX.
ꢀ.50 (ꢀ.ꢀꢁꢀꢂ MIN.
ꢁ.9ꢁ (ꢀ.005ꢂ MIN.
DIMENSIONS IN MILLIMETERS AND (INCHESꢂ.
*OPTION 3ꢀꢀ AND 5ꢀꢀ NOT MARKED.
0.ꢀ8ꢀ ꢀ.3ꢁꢀ
ꢀ.65 (ꢀ.ꢀꢁ5ꢂ MAX.
(ꢀ.ꢀ43 ꢀ.ꢀ03ꢂ
NOTE: FLOATING LEAD PROTRUSION IS ꢀ.ꢁ5 mm (0ꢀ milsꢂ MAX.
ꢁ.54 ꢀ.ꢁ5
(ꢀ.0ꢀꢀ ꢀ.ꢀ0ꢀꢂ
ACPL-772L Package with Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
9.65 ꢀ.ꢁ5
(ꢀ.38ꢀ ꢀ.ꢀ0ꢀꢂ
0.ꢀ06 (ꢀ.ꢀ4ꢀꢂ
0ꢀ.9 (ꢀ.43ꢀꢂ
ꢁ.ꢀ (ꢀ.ꢀ8ꢀꢂ
6
5
8
0
7
6.35ꢀ ꢀ.ꢁ5
(ꢀ.ꢁ5ꢀ ꢀ.ꢀ0ꢀꢂ
ꢁ
3
4
0.ꢁ7 (ꢀ.ꢀ5ꢀꢂ
9.65 ꢀ.ꢁ5
(ꢀ.38ꢀ ꢀ.ꢀ0ꢀꢂ
0.78ꢀ
(ꢀ.ꢀ7ꢀꢂ
MAX.
0.09
(ꢀ.ꢀ47ꢂ
MAX.
7.6ꢁ ꢀ.ꢁ5
(ꢀ.3ꢀꢀ ꢀ.ꢀ0ꢀꢂ
+ ꢀ.ꢀ76
- ꢀ.ꢀ50
ꢀ.ꢁ54
3.56 ꢀ.03
(ꢀ.04ꢀ ꢀ.ꢀꢀ5ꢂ
+ ꢀ.ꢀꢀ3ꢂ
- ꢀ.ꢀꢀꢁꢂ
(ꢀ.ꢀ0ꢀ
0.ꢀ8ꢀ ꢀ.3ꢁꢀ
(ꢀ.ꢀ43 ꢀ.ꢀ03ꢂ
ꢀ.635 ꢀ.ꢁ5
(ꢀ.ꢀꢁ5 ꢀ.ꢀ0ꢀꢂ
0ꢁ ˚ NOM.
ꢀ.635 ꢀ.03ꢀ
(ꢀ.ꢀꢁ5 ꢀ.ꢀꢀ5ꢂ
ꢁ.54
(ꢀ.0ꢀꢀꢂ
BSC
DIMENSIONS IN MILLIMETERS (INCHESꢂ.
LEAD COPLANARITY = ꢀ.0ꢀ mm (ꢀ.ꢀꢀ4 INCHESꢂ.
NOTE: FLOATING LEAD PROTRUSION IS ꢀ.ꢁ5 mm (0ꢀ milsꢂ MAX.
ꢁ
ACPL-072L Small Outline SO-8 Package
LAND PATTERN RECOMMENDATION
8
7
6
5
5.994 ꢀ.ꢁꢀ3
(ꢀ.ꢁ36 ꢀ.ꢀꢀ8ꢂ
XXXV
YWW
3.937 ꢀ.0ꢁ7
(ꢀ.055 ꢀ.ꢀꢀ5ꢂ
TYPE NUMBER
7.49 (ꢀ.ꢁ95ꢂ
(LAST 3 DIGITSꢂ
DATE CODE
0
ꢁ
3
4
PIN ONE
0.9 (ꢀ.ꢀ75ꢂ
ꢀ.4ꢀ6 ꢀ.ꢀ76
(ꢀ.ꢀ06 ꢀ.ꢀꢀ3ꢂ
0.ꢁ7ꢀ
(ꢀ.ꢀ5ꢀꢂ
BSC
ꢀ.64 (ꢀ.ꢀꢁ5ꢂ
ꢀ.43ꢁ
(ꢀ.ꢀ07ꢂ
*
7˚
5.ꢀ8ꢀ ꢀ.0ꢁ7
(ꢀ.ꢁꢀꢀ ꢀ.ꢀꢀ5ꢂ
45 ˚ X
3.075 ꢀ.0ꢁ7
(ꢀ.0ꢁ5 ꢀ.ꢀꢀ5ꢂ
ꢀ ~ 7 ˚
ꢀ.ꢁꢁ8 ꢀ.ꢀꢁ5
(ꢀ.ꢀꢀ9 ꢀ.ꢀꢀ0ꢂ
0.5ꢁ4
(ꢀ.ꢀ6ꢀꢂ
ꢀ.ꢁꢀ3 ꢀ.0ꢀꢁ
(ꢀ.ꢀꢀ8 ꢀ.ꢀꢀ4ꢂ
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASHꢂ
5.ꢁꢀ7 ꢀ.ꢁ54 (ꢀ.ꢁꢀ5 ꢀ.ꢀ0ꢀꢂ
*
ꢀ.3ꢀ5
(ꢀ.ꢀ0ꢁꢂ
MIN.
DIMENSIONS IN MILLIMETERS (INCHESꢂ.
LEAD COPLANARITY = ꢀ.0ꢀ mm (ꢀ.ꢀꢀ4 INCHESꢂ MAX.
OPTION NUMBER 5ꢀꢀ NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS ꢀ.05 mm (6 milsꢂ MAX.
Device Selection Guide
8-PinꢀDIPꢀ
(300ꢀMil)
SmallꢀOutlineꢀꢀ
SO-8
ACPL-772L
ACPL-072L
Ordering Information
SpecifyꢀPartꢀNumberꢀfollowedꢀbyꢀOptionꢀNumberꢀ(ifꢀdesired)
Example:
ACPL-x72L-XXX
020ꢀ=ꢀUL1577ꢀ(ACPL-772Lꢀonly)
060ꢀ=ꢀIEC/EN/DINꢀENꢀ60747-5-2
300ꢀ=ꢀGullꢀWingꢀSurfaceꢀMountꢀOptionꢀ(ACPL-772Lꢀonly)
500ꢀ=ꢀTapeꢀandꢀReelꢀPackagingꢀOption
XXXE=ꢀLeadꢀFreeꢀOption
NoꢀOptionꢀandꢀOptionꢀ300ꢀcontainꢀ50ꢀunitsꢀ(ACPL-772L),ꢀ100ꢀunitsꢀ(ACPL-072L)ꢀperꢀtube.
Optionꢀ500ꢀcontainsꢀ1000ꢀunitsꢀ(ACPL-772L),ꢀ1500ꢀunitsꢀ(ACPL-072L)ꢀperꢀreel.
Optionꢀdataꢀsheetsꢀavailable.ꢀPleaseꢀcontactꢀsalesꢀrepresentativeꢀorꢀauthorizedꢀdistributor.
3
Solder Reflow Temperature Profile
3ꢀꢀ
PREHEATING RATE 3˚C + 0 ˚C/- ꢀ.5 ˚C/SEC.
REFLOW HEATING RATE ꢁ.5˚C ꢀ.5 ˚C/SEC.
PEAK
TEMP.
ꢁ45˚C
PEAK
TEMP.
ꢁ4ꢀ˚C
PEAK
TEMP.
ꢁ3ꢀ˚C
ꢁꢀꢀ
0ꢀꢀ
ꢁ.5˚ C ꢀ.5˚C/SEC.
SOLDERING
TIME
ꢁꢀꢀ˚C
3ꢀ
06ꢀ ˚C
05ꢀ ˚C
04ꢀ ˚C
SEC.
3ꢀ
SEC.
3˚C + 0 ˚C/- ꢀ.5 ˚C
PREHEATING TIME
05ꢀ ˚C, 9ꢀ + 3ꢀ SEC.
5ꢀ SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
ꢀ
ꢀ
5ꢀ
0ꢀꢀ
05ꢀ
TIME (SECONDSꢂ
ꢁꢀꢀ
ꢁ5ꢀ
Note:ꢀUseꢀofꢀnon-chlorineꢀactivatedꢀfluxesꢀisꢀhighlyꢀrecommended.
Recommended Pb-Free IR Profile
TIMEWITHIN 5 ˚C of ACTUAL
PEAKTEMPERATURE
t
p
ꢁꢀ-4ꢀ SEC.
ꢁ6ꢀ +ꢀ/-5
˚
C
T
T
p
L
ꢁ07 ˚C
RAMP-UP
˚C/SEC. MAX.
RAMP-DOWN
3
6 ˚C/SEC. MAX.
05ꢀ - ꢁꢀꢀ ˚C
T
smax
T
smin
t
s
t
L
6ꢀ to 05ꢀ SEC.
PREHEAT
6ꢀto08ꢀSEC.
ꢁ5
t ꢁ5 ˚C to PEAK
TIME
NO TES:
THE TIME FROM ꢁ5
= ꢁꢀꢀ C, T
˚
C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 05ꢀ
smin
T
˚
˚C
smax
Note:ꢀUseꢀofꢀnon-chlorineꢀactivatedꢀfluxesꢀisꢀhighlyꢀrecommended.
Regulatory Information
TheꢀACPL-772LꢀandꢀACPL-072Lꢀareꢀpendingꢀapprovalꢀfromꢀtheꢀfollowingꢀorganizations:
IEC/EN/DIN EN 60747-5-2ꢀ
Approvedꢀunder:ꢀ
IECꢀ60747-5-2:1997ꢀ+ꢀA1:2002ꢀ
ENꢀ60747-5-2:2001ꢀ+ꢀA1:2002ꢀ
DINꢀENꢀ60747-5-2ꢀ(VDEꢀ0884ꢀTeilꢀ2):2003-01.ꢀ
(optionꢀ060ꢀonly)
ULꢀ
ApprovedꢀunderꢀULꢀ1577,ꢀcomponentꢀrecognitionꢀprogramꢀup,ꢀFileꢀE55361.
CSAꢀ
ApprovedꢀunderꢀCSAꢀComponentꢀAcceptanceꢀNoticeꢀ#5,ꢀFileꢀCAꢀ88324.
ꢂ
Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
ACPL-772L
Option 060
ACPL-072L
Option 060 Units
Description
Symbol
Installation classification per DIN VDE 0ꢀꢀ0/ꢀ.89, Table ꢀ
for rated mains voltage ≤ ꢀ50 Vrms
I – IV
I – IV
I – III
I – IV
I – III
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ ꢂ50 Vrms
Climatic Classification
55/ꢀ00/ꢁꢀ
55/ꢀ00/ꢁꢀ
ꢁ
Pollution Degree (DIN VDE 0ꢀꢀ0/ꢀ.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b**
ꢁ
V
V
630
ꢀꢀ8ꢀ
560
V
peak
IORM
ꢀ050
V
peak
PR
V
IORM
x ꢀ.875=V , ꢀ00% Production Test with t =ꢀ sec, Partial discharge < 5 pC
PR m
Input to Output Test Voltage, Method a**
x ꢀ.5=V , Type and Sample Test, t =60 sec, Partial discharge < 5 pC
V
V
9ꢂ5
8ꢂ0
V
peak
PR
V
IORM
PR
m
Highest Allowable Overvoltage (Transient Overvoltage t = ꢀ0 sec)
6000
ꢂ000
V
peak
ini
IOTM
Safety-limiting values – maximum values allowed in the event of a failure, also see Figure ꢁ.
Case Temperature
Input Current
Output Power
T
ꢀ75
ꢁ30
600
ꢀ50
ꢀ50
600
°C
mA
mW
S
I
S, INPUT
P
S, OUTPUT
W
Insulation Resistance at T , V = 500 V
R
IO
>ꢀ09
>ꢀ09
S
IO
*ꢀ Isolationꢀcharacteristicsꢀareꢀguaranteedꢀonlyꢀwithinꢀtheꢀsafetyꢀmaximumꢀratingsꢀwhichꢀmustꢀbeꢀensuredꢀbyꢀprotectiveꢀcircuitsꢀinꢀapplication.ꢀ
SurfaceꢀmountꢀclassificationꢀisꢀclassꢀAꢀinꢀaccordanceꢀwithꢀCECCOO802.
**ꢀ ReferꢀtoꢀtheꢀoptocouplerꢀsectionꢀofꢀtheꢀIsolationꢀandꢀControlꢀComponentsꢀDesigner’sꢀCatalog,ꢀunderꢀProductꢀSafetyꢀRegulationsꢀsectionꢀIEC/EN/
DINꢀENꢀ60747-5-2,ꢀforꢀaꢀdetailedꢀdescriptionꢀofꢀMethodꢀaꢀandꢀMethodꢀbꢀpartialꢀdischargeꢀtestꢀprofiles.
Note:ꢀTheseꢀoptocouplersꢀareꢀsuitableꢀforꢀ“safeꢀelectricalꢀisolation”ꢀonlyꢀwithinꢀtheꢀsafetyꢀlimitꢀdata.ꢀꢀMaintenanceꢀofꢀtheꢀsafetyꢀdataꢀshallꢀbeꢀensuredꢀ
byꢀmeansꢀofꢀprotectiveꢀcircuits.
Note:ꢀTheꢀsurfaceꢀmountꢀclassificationꢀisꢀClassꢀAꢀinꢀaccordanceꢀwithꢀCECCꢀ00802.
Table 2. Insulation and Safety Related Specifications
Value
Parameter
Symbol ACPL-772L ACPL-072L
Units
Conditions
Minimum External Air Gap (Clearance)
L(ꢀ0ꢀ)
7.ꢀ
ꢂ.9
mm
Measured from input terminals to output termi-
nals, shortest distance through air.
Minimum External Tracking (Creepage)
L(ꢀ0ꢁ)
7.ꢂ
ꢂ.8
mm
mm
Measured from input terminals to output termi-
nals, shortest distance path along body.
Minimum Internal Plastic Gap (Internal Clearance)
0.08
0.08
Through insulation distance conductor to conduc-
tor, usually the straight line distance thickness
between the emitter and detector.
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
>ꢀ75
IIIa
>ꢀ75
IIIa
V
DIN IEC ꢀꢀꢁ/VDE 0303 Part ꢀ
Material Group (DIN VDE 0ꢀꢀ0, ꢀ/89, Table ꢀ)
All Avago Technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting
point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage
and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed
circuit board between the solder fillets of the input and output leads must be considered.
There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage
and clearance distances will also change depending on factors such as pollution degree and insulation level.
5
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Min.
–55
–ꢂ0
0
Max.
+ꢀꢁ5
+ꢀ05
6.0
Units
°C
Storage Temperature
T
S
[ꢀ]
Ambient Operating Temperature
T
A
°C
Supply Voltages
Input Voltage
Output Voltage
V
V
V
, V
Volts
Volts
Volts
DDꢀ DDꢁ
–0.5
–0.5
V
DDꢀ
DDꢁ
+0.5
+0.5
I
V
O
Average Output Current
ACPL-07ꢁL
ACPL-77ꢁL
I
I
5
ꢀ0
mA
mA
O
O
Lead Solder Temperature
ꢁ60°C for ꢀ0 sec., ꢀ.6 mm below seating plane
Please See Solder Reflow Temperature Profile Section
Solder Reflow Temperature Profile
Table 4. Recommended Operating Conditions
Parameter
Symbol
Min.
–ꢂ0
3.0
Max.
+ꢀ05
3.6
Units
°C
V
Ambient Operating Temperature
Supply Voltages ( 3.3V operation)
Supply Voltages ( 5V operation)
Logic High Input Voltage
Logic Low Input Voltage
T
A
V
V
V
V
, V
DDꢀ DDꢁ
, V
DDꢀ DDꢁ
ꢂ.5
5.5
V
ꢁ.0
V
DDꢀ
V
IH
IL
0.0
0.8
ꢀ.0
V
Input Signal Rise and Fall Times
t , t
r f
ms
Table 5. Electrical Specifications
Testꢀconditionsꢀthatꢀareꢀnotꢀspecifiedꢀcanꢀbeꢀanywhereꢀwithinꢀtheꢀrecommendedꢀoperatingꢀrange.ꢀꢀ
Theꢀ followingꢀ specificationsꢀ coverꢀ theꢀ followingꢀ powerꢀ supplyꢀ combinations:ꢀ ꢀ (4.5V≤V ≤5.5V,ꢀ 4.5V≤V ≤5.5V),ꢀ
DD1
DD2
(3V≤V ≤3.6V,ꢀ3V≤V ≤3.6V),ꢀ(4.5V≤V ≤5.5V,ꢀ3V≤V ≤3.6V)ꢀandꢀ(3V≤V ≤3.6V,ꢀ4.5V≤V ≤5.5V).
DD1
DD2
DD1
DD2
DD1
DD2
AllꢀtypicalꢀspecificationsꢀareꢀatꢀT =+25°Cꢀ,ꢀV ꢀ=ꢀV ꢀ=ꢀ+3.3V.ꢀ
A
DD1
DD2
Parameter
Symbol
Min.
Typ.
8.8
ꢀ.ꢂ
ꢂ.3
ꢂ.5
Max. Units
Test Conditions
V = 0 V
[ꢁ]
Logic Low Input Supply Current
I
I
I
I
I
ꢀ5
5
mA
mA
mA
mA
mA
V
DDꢀL
DDꢀH
DDꢁL
DDꢁH
I
I
[ꢁ]
Logic High Input Supply Current
Output Supply Current
V = V
I DDꢀ
ꢀ0
ꢀ0
ꢀ0
Input Current
–ꢀ0
ꢁ.9
Logic High Output Voltage
V
OH
3.3
ꢁ.9
0
I = –ꢁ0 mA, V = V
O I IH
ꢀ.9
V
I = –ꢂ mA, V = V
O I IH
Logic Low Output Voltage
V
OL
0.ꢀ
ꢀ.0
V
I = ꢁ0 mA, V = V
O I IL
0.35
V
I = ꢂ mA, V = V
O I IL
6
Table 6. Switching Specifications
Testꢀconditionsꢀthatꢀareꢀnotꢀspecifiedꢀcanꢀbeꢀanywhereꢀwithinꢀtheꢀrecommendedꢀoperatingꢀrange.
Theꢀ followingꢀ specificationsꢀ coverꢀ theꢀ followingꢀ powerꢀ supplyꢀ combinations:ꢀ ꢀ (4.5V≤V ≤5.5V,ꢀ 4.5V≤V ≤5.5V),ꢀ
DD1
DD2
(3V≤V ≤3.6V,ꢀ3V≤V ≤3.6V),ꢀ(4.5V≤V ≤5.5V,ꢀ3V≤V ≤3.6V)ꢀandꢀ(3V≤V ≤3.6V,ꢀ4.5V≤V ≤5.5V).
DD1
DD2
DD1
DD2
DD1
DD2
AllꢀtypicalꢀspecificationsꢀareꢀatꢀT =+25°C,ꢀV ꢀ=ꢀV ꢀ=ꢀ+3.3V.
A
DD1
DD2
Parameter
Propogation Delay Time to Logic Low Output
Symbol
Min.
Typ.
ꢁ3.5
ꢁ5.5
Max.
Units
ns
Test Conditions
[3]
[3]
t
PHL
t
PLH
t
PW
ꢂ0
ꢂ0
C = ꢀ5 pF, CMOS Signal Levels
L
Propogation Delay Time to Logic High Output
ns
C = ꢀ5 pF, CMOS Signal Levels
L
[ꢂ]
Pulse Width
ꢂ0
ns
C = ꢀ5 pF, CMOS Signal Levels
L
[5]
Maximum Data Rate
ꢁ5
6
MBd
ns
C = ꢀ5 pF, CMOS Signal Levels
L
[6]
Pulse Width Distortion | t - t
|
|PWD |
ꢁ
C = ꢀ5 pF, CMOS Signal Levels
L
PHL PLH
[7]
Propagation Delay Skew
t
PSK
ꢁ0
ns
C = ꢀ5 pF, CMOS Signal Levels
L
Output Rise Time (ꢀ0% – 90%)
Output Fall Time (90% - ꢀ0%)
t
t
9
ns
C = ꢀ5 pF, CMOS Signal Levels
L
R
8
ns
C = ꢀ5 pF, CMOS Signal Levels
L
F
[8]
Common Mode Transient Immunity at Logic High Output
| CM |
ꢀ0
ꢀ0
ꢁ0
kV/ms V = ꢀ000 V, T = ꢁ5°C,
CM A
H
V = V , V > 0.8 V
DDꢀ
I
DDꢀ
O
[8]
Common Mode Transient Immunity at Logic Low Output
| CM |
ꢁ0
kV/ms V = ꢀ000 V, T = ꢁ5°C,
CM A
L
V = 0 V, V < 0.8 V
I
O
Table 7. Package Characteristics
AllꢀtypicalꢀspecificationsꢀareꢀatꢀT ꢀ=ꢀ25°C.
A
Parameters
Symbol Min. Typ.
Max. Units Test Conditions
V rms RH ≤ 50%, t = ꢀ min, T = ꢁ5°C
Input-Output Momentary
With-stand Voltage
07ꢁL
77ꢁL
V
ISO
3750
3750
5000
A
[7,8,9]
77ꢁL with
0ꢁ0 option
[9]
ꢀꢁ
W
pF
pF
Input-Output Resistance
R
C
C
ꢀ0
V
= 500 V dc
I-O
I-O
I-O
I
Input-Output Capacitance
0.6
f = ꢀ MHz
[ꢀꢁ]
Input Capacitance
3.0
Input IC Junction-to-Case
Thermal Resistance
77ꢁL
07ꢁL
77ꢁL
07ꢁL
qjci
ꢀꢂ5
ꢀ60
ꢀꢂ0
ꢀ35
°C/W Thermocouple located at center underside of package
Output IC Junction-to-Case
Thermal Resistance
qjco
°C/W
Package Power Dissipation
P
PD
ꢀ50
mW
Notes:
1.ꢀ AbsoluteꢀMaximumꢀambientꢀoperatingꢀtemperatureꢀmeansꢀtheꢀdeviceꢀwillꢀnotꢀbeꢀdamagedꢀifꢀoperatedꢀunderꢀtheseꢀconditions.ꢀItꢀdoesꢀnotꢀ
guaranteeꢀfunctionality.
2.ꢀ TheꢀLEDꢀisꢀONꢀwhenꢀV ꢀisꢀlowꢀandꢀOFFꢀwhenꢀV ꢀisꢀhigh.
I
I
3.ꢀ t ꢀpropagationꢀdelayꢀisꢀmeasuredꢀfromꢀtheꢀ50%ꢀlevelꢀonꢀtheꢀfallingꢀedgeꢀofꢀtheꢀV ꢀsignalꢀtoꢀtheꢀ50%ꢀlevelꢀofꢀtheꢀfallingꢀedgeꢀofꢀtheꢀV ꢀsignal.ꢀt ꢀ
PHL
I
O
PLH
propagationꢀdelayꢀisꢀmeasuredꢀfromꢀtheꢀ50%ꢀlevelꢀonꢀtheꢀrisingꢀedgeꢀofꢀtheꢀV ꢀsignalꢀtoꢀtheꢀ50%ꢀlevelꢀofꢀtheꢀrisingꢀedgeꢀofꢀtheꢀV ꢀsignal.
I
O
4.ꢀ Theꢀminimumꢀpulseꢀwidthꢀisꢀtheꢀshortestꢀpulseꢀwidthꢀatꢀwhichꢀtheꢀspecifiedꢀpulseꢀwidthꢀdistortionꢀisꢀguaranteed.
5.ꢀ Theꢀmaximumꢀdataꢀrateꢀisꢀtheꢀfastestꢀdataꢀrateꢀatꢀwhichꢀtheꢀspecifiedꢀpulseꢀwidthꢀdistortionꢀisꢀguaranteed.
6.ꢀ PWDꢀisꢀdefinedꢀasꢀ|t ꢀ-ꢀt |.ꢀ%PWDꢀ(percentꢀpulseꢀwidthꢀdistortion)ꢀisꢀequalꢀtoꢀtheꢀPWDꢀdividedꢀbyꢀpulseꢀwidth.
PHL PLH
7.ꢀ t ꢀisꢀequalꢀtoꢀtheꢀmagnitudeꢀofꢀtheꢀworstꢀcaseꢀdifferenceꢀinꢀt ꢀand/orꢀt ꢀthatꢀwillꢀbeꢀseenꢀbetweenꢀunitsꢀatꢀanyꢀgivenꢀtemperatureꢀwithinꢀtheꢀ
PSK
PHL
PLH
recommendedꢀoperatingꢀconditions.
8.ꢀ CM ꢀisꢀtheꢀmaximumꢀcommonꢀmodeꢀvoltageꢀslewꢀrateꢀthatꢀcanꢀbeꢀsustainedꢀwhileꢀmaintainingꢀV ꢀ>ꢀ0.8ꢀV .ꢀCMLꢀisꢀtheꢀmaximumꢀcommonꢀ
H
O
DD2
modeꢀvoltageꢀslewꢀrateꢀthatꢀcanꢀbeꢀsustainedꢀwhileꢀmaintainingꢀV ꢀ<ꢀ0.8ꢀV.ꢀTheꢀcommonꢀmodeꢀvoltageꢀslewꢀratesꢀapplyꢀtoꢀbothꢀrisingꢀandꢀfallingꢀ
O
commonꢀmodeꢀvoltageꢀedges.
9.ꢀꢀ Deviceꢀconsideredꢀaꢀtwo-terminalꢀdevice:ꢀpinsꢀ1,ꢀ2,ꢀ3,ꢀandꢀ4ꢀshortedꢀtogetherꢀandꢀpinsꢀ5,ꢀ6,ꢀ7,ꢀandꢀ8ꢀshortedꢀtogether.
7
10.ꢀInꢀaccordanceꢀwithꢀUL1577,ꢀeachꢀACPL-072Lꢀisꢀproofꢀtestedꢀbyꢀapplyingꢀanꢀinsulationꢀtestꢀvoltageꢀ≥ꢀ4500ꢀV ꢀforꢀ1ꢀsecondꢀ(leakageꢀdetectionꢀ
RMS
currentꢀlimit,ꢀI ꢀ≤ꢀ5ꢀmA).ꢀEachꢀACPL-772Lꢀisꢀproofꢀtestedꢀbyꢀapplyingꢀanꢀinsulationꢀtestꢀvoltageꢀ≥ꢀ4500ꢀV ꢀforꢀ1ꢀsecondꢀ(leakageꢀdetectionꢀcurrentꢀ
I-O
RMS
limit,ꢀI ꢀ≤ꢀ5ꢀmA).
I-O
11.ꢀTheꢀInput-OutputꢀMomentaryꢀWithstandꢀVoltageꢀisꢀaꢀdielectricꢀvoltageꢀratingꢀthatꢀshouldꢀnotꢀbeꢀinterpretedꢀasꢀanꢀinput-outputꢀcontinuousꢀ
voltageꢀrating.ꢀForꢀtheꢀcontinuousꢀvoltageꢀratingꢀrefersꢀtoꢀyourꢀequipmentꢀlevelꢀsafetyꢀspecificationꢀorꢀAvagoꢀTechnologiesꢀApplicationꢀNoteꢀ1074ꢀ
entitledꢀ“OptocouplerꢀInput-OutputꢀEnduranceꢀVoltage.”
12.ꢀC ꢀisꢀtheꢀcapacitanceꢀmeasuredꢀatꢀpinꢀ2ꢀ(V ).
I
I
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
31
29
27
25
23
21
19
17
15
PWD
Tplh
Tphl
-20
0
20
40
60
80
100
-20
0
20
40
TAꢀ(oC)
60
80 100
o
TAꢀ( C)
Figure 1. Typical propagation delays vs temperature
Figure 2. Typical pulse width distortion vs temperature
32
30
28
26
24
12
11
10
9
8
7
6
Tplh
Tphl
22
RiseꢀTime
FallꢀTime
5
4
20
15
25
35
45
55
-20
0
20
40
60
80
100
CLꢀ(pF)
TAꢀ(oC)
Figure 4. Typical propagation delays vs load capacitance
Figure 3. Typical rise and fall time vs temperature
6
5
Surface Mount SO-8 Product
1,000
Standard 8-pin DIP Product
PWD
4
1000
800
600
400
200
0
Isꢀ(mA)
Isꢀ(mA)
800
600
400
200
0
Psꢀ(mW)
3
2
1
0
Psꢀ(mW)
0
25
50
75 100 125 150 175
15
25
35
CL ꢀ(pF)
45
55
0
25 50 75 100 125 150 175
TAꢀ-ꢀCaseꢀTemperatureꢀ-ꢀ˚C
T
A
ꢀ-ꢀCaseꢀTemperatureꢀ-ꢀC
Figure 6. Thermal derating curve, dependence of safety limiting value
with case temperature per IEC/EN/DIN EN 60747-5-2
Figure 5. Typical pulse width distortion vs load capacitance
8
Application Information
Propagation Delay, Pulse-Width Distortion and Propaga-
tion Delay Skew
Bypassing and PC Board Layout
Propagationꢀ Delayꢀ isꢀ aꢀ figureꢀ ofꢀ meritꢀ whichꢀ describesꢀ
howꢀquicklyꢀaꢀlogicꢀsignalꢀpropagatesꢀthroughꢀaꢀsystem.ꢀ
Theꢀ ACPL-x72Lꢀ optocouplersꢀ areꢀ extremelyꢀ easyꢀ toꢀ use.ꢀ
NoꢀexternalꢀinterfaceꢀcircuitryꢀisꢀrequiredꢀbecauseꢀACPl-
x72Lꢀ usesꢀ highꢀ speedꢀ CMOSꢀ ICꢀ technologyꢀ allowingꢀ
CMOSꢀ logicꢀ toꢀ beꢀ connectedꢀ directlyꢀ toꢀ theꢀ inputsꢀ andꢀ
outputs.
Theꢀ propagationꢀ delayꢀ fromꢀ aꢀ lowꢀ toꢀ highꢀ (t )ꢀ isꢀ theꢀ
PLH
amountꢀofꢀtimeꢀrequiredꢀforꢀanꢀinputꢀsignalꢀtoꢀpropagateꢀ
toꢀtheꢀoutput,ꢀcausingꢀtheꢀoutputꢀtoꢀchangeꢀfromꢀlowꢀtoꢀ
high.ꢀꢀSimilarly,ꢀtheꢀpropagationꢀdelayꢀfromꢀhighꢀtoꢀlowꢀ
(t )ꢀisꢀtheꢀamountꢀofꢀtimeꢀrequiredꢀforꢀtheꢀinputꢀsignalꢀ
PHL
Asꢀ shownꢀ inꢀ Figureꢀ 7,ꢀ theꢀ onlyꢀ externalꢀ componentsꢀ
requiredꢀforꢀproperꢀoperationꢀareꢀtwoꢀbypassꢀcapacitors.ꢀ
Capacitorꢀ valuesꢀ shouldꢀ beꢀ betweenꢀ 0.01mFꢀ andꢀ 0.1mF.ꢀ
Forꢀ eachꢀ capacitor,ꢀ theꢀ totalꢀ leadꢀ lengthꢀ betweenꢀ bothꢀ
endsꢀofꢀtheꢀcapacitorꢀandꢀpowerꢀsupplyꢀpinsꢀshouldꢀnotꢀ
exceedꢀ 20mm.ꢀ Figureꢀ 8ꢀ illustratesꢀ theꢀ recommendedꢀ
printedꢀcircuitꢀboardꢀlayoutꢀforꢀACPL-x72L.
toꢀpropagateꢀtoꢀtheꢀoutput,ꢀcausingꢀtheꢀoutputꢀtoꢀchangeꢀ
fromꢀhighꢀtoꢀlow.ꢀꢀPleaseꢀseeꢀFigureꢀ9.
INPUT
5 V CMOS
0 V
V
50%
I
t
t
PHL
PLH
V
OH
2.5 V CMOS
OUTPUT
90%
90%
V
V
10%
10%
O
8
7
6
5
V
DD1
1
2
3
4
DD2
V
OL
C1
C2
V
I
NC
Figure 9. Signal plot shows how propagation delay is defined
Pulse-widthꢀ distortionꢀ (PWD)ꢀ isꢀ theꢀ differenceꢀ betweenꢀ
NC
V
O
GND
GND
1
2
t
ꢀ andꢀ t ꢀ andꢀ oftenꢀ determinesꢀ theꢀ maximumꢀ dataꢀ
PLH
PHL
rateꢀ capabilityꢀ ofꢀ aꢀ transmissionꢀ system.ꢀ ꢀ PWDꢀ canꢀ beꢀ
expressedꢀinꢀpercentꢀbyꢀdividingꢀtheꢀPWDꢀ(inꢀns)ꢀbyꢀtheꢀ
minimumꢀpulseꢀwidthꢀ(inꢀns)ꢀbeingꢀtransmitted.ꢀꢀTypically,ꢀ
PWDꢀ onꢀ theꢀ orderꢀ ofꢀ 20-30%ꢀ ofꢀ theꢀ minimumꢀ pulseꢀ
widthꢀ isꢀ tolerable.ꢀTheꢀ PWDꢀ specificationꢀ forꢀ ACPL-x72Lꢀ
isꢀ 6nsꢀ (15%)ꢀ maximumꢀ acrossꢀ recommendedꢀ operatingꢀ
conditions.
C1, C2 = 0.01 µF TO 0.1 µF
Figure 7. Recommended Circuit Diagram
V
DD1
V
DD2
V
I
C1
C2
V
O
GND
GND
1
2
C1, C2 = 0.01 µF TO 0.1 µF
Figure 8. Recommended Printed Circuit Board Layout
9
Propagationꢀdelayꢀskew,ꢀt ,ꢀisꢀanꢀimportantꢀparameterꢀ Asꢀ mentionedꢀ earlier,ꢀ t ꢀ canꢀ determineꢀ theꢀ maximumꢀ
PSK
PSK
toꢀ considerꢀ inꢀ parallelꢀ dataꢀ applicationsꢀ whereꢀ parallelꢀ dataꢀ transmissionꢀ rate.ꢀ Figureꢀ 11ꢀ isꢀ theꢀ timingꢀ
synchronizationꢀ ofꢀ signalsꢀ onꢀ parallelꢀ dataꢀ linesꢀ isꢀ aꢀ diagramꢀ ofꢀ aꢀ typicalꢀ parallelꢀ dataꢀ applicationꢀ withꢀ
concern.ꢀꢀIfꢀtheꢀparallelꢀdataꢀisꢀsentꢀthroughꢀaꢀgroupꢀofꢀ bothꢀ theꢀ clockꢀ andꢀ dataꢀ linesꢀ beingꢀ sentꢀ throughꢀ theꢀ
optocouplers,ꢀdifferencesꢀinꢀpropagationꢀdelaysꢀwillꢀcauseꢀ optocouplers.ꢀTheꢀfigureꢀshowsꢀdataꢀandꢀclockꢀsignalsꢀatꢀ
theꢀdataꢀtoꢀarriveꢀatꢀtheꢀoutputsꢀofꢀtheꢀoptocouplersꢀatꢀ theꢀinputsꢀandꢀoutputsꢀofꢀtheꢀoptocouplers.ꢀInꢀthisꢀcaseꢀ
differentꢀ times.ꢀ ꢀ Ifꢀ thisꢀ differenceꢀ inꢀ propagationꢀ delayꢀ theꢀdataꢀisꢀassumesꢀtoꢀbeꢀclockedꢀoffꢀofꢀtheꢀrisingꢀedgeꢀofꢀ
isꢀ largeꢀ enoughꢀ itꢀ willꢀ determineꢀ theꢀ maximumꢀ rateꢀ atꢀ theꢀclock.
whichꢀparallelꢀdataꢀcanꢀbeꢀsentꢀthroughꢀtheꢀoptocouplers.
DATA
Propagationꢀ delayꢀ skewꢀ isꢀ definedꢀ asꢀ theꢀ differenceꢀ
INPUTS
betweenꢀtheꢀminimumꢀandꢀmaximumꢀpropagationꢀdelays,ꢀ
eitherꢀt ꢀorꢀt ꢀforꢀanyꢀgivenꢀgroupꢀofꢀoptocouoplersꢀ
PLH
PHL
CLOCK
whichꢀareꢀoperatingꢀunderꢀtheꢀsameꢀconditionsꢀ(i.e.,ꢀtheꢀ
sameꢀ driveꢀ current,ꢀ supplyꢀ voltage,ꢀ outputꢀ load,ꢀ andꢀ
operatingꢀtemperature).ꢀAsꢀillustratedꢀinꢀFigureꢀ10,ꢀifꢀtheꢀ
inputsꢀofꢀaꢀgroupꢀofꢀoptocouplersꢀareꢀswitchedꢀeitherꢀONꢀ
DATA
orꢀOFFꢀatꢀtheꢀsameꢀtime,ꢀt ꢀisꢀtheꢀdifferenceꢀbetweenꢀ
PSK
theꢀshortestꢀpropagationꢀdelay,ꢀeitherꢀt ꢀorꢀt ꢀandꢀtheꢀ
PLH
PHL
OUTPUTS
CLOCK
t
PSK
longestꢀpropagationꢀdelay,ꢀeitherꢀt ꢀandꢀt
.
PLH
PHL
V
I
50%
t
PSK
Figure 11. Parallel data transmission example.
2.5 V,
CMOS
V
O
Propagationꢀ delayꢀ skewꢀ representsꢀ theꢀ uncertaintyꢀ
ofꢀ whereꢀ anꢀ edgeꢀ mightꢀ beꢀ afterꢀ beingꢀ sentꢀ throughꢀ
anꢀ optocoupler.ꢀ Figureꢀ 11ꢀ showsꢀ thatꢀ thereꢀ willꢀ beꢀ
uncertaintyꢀ inꢀ bothꢀ theꢀ dataꢀ andꢀ clockꢀ lines.ꢀ ꢀ Itꢀ isꢀ
importantꢀthatꢀtheseꢀtwoꢀareasꢀofꢀuncertaintyꢀnotꢀoverlap,ꢀ
otherwiseꢀ theꢀ clockꢀ signalꢀ mightꢀ arriveꢀ beforeꢀ allꢀ theꢀ
dataꢀ outputsꢀ haveꢀ settled,ꢀ orꢀ someꢀ ofꢀ theꢀ dataꢀ outputsꢀ
mayꢀstartꢀtoꢀchangeꢀbeforeꢀtheꢀclockꢀsignalꢀhasꢀarrived.ꢀ
Fromꢀtheseꢀconsiderations,ꢀtheꢀabsoluteꢀminimumꢀpulseꢀ
widthꢀthatꢀcanꢀbeꢀsentꢀthroughꢀoptocouplersꢀinꢀaꢀparallelꢀ
t
PSK
V
50%
I
2.5 V,
CMOS
V
O
applicationꢀisꢀtwiceꢀt .ꢀAꢀcautiousꢀdesignꢀshouldꢀuseꢀaꢀ
PSK
slightlyꢀlongerꢀpulseꢀwidthꢀtoꢀensureꢀthatꢀanyꢀadditionalꢀ
uncertaintyꢀ inꢀ theꢀ restꢀ ofꢀ theꢀ circuitꢀ doesꢀ notꢀ causeꢀ aꢀ
problem.
Figure 10. Propagation delay skew waveform
Theꢀ ACPL-x72Lꢀ optocouplerꢀ offersꢀ theꢀ advantageꢀ ofꢀ
guaranteedꢀspecificationsꢀforꢀpropagationꢀdelays,ꢀpulse-
widthꢀ distortion,ꢀ andꢀ propagationꢀ delayꢀ skewꢀ overꢀ theꢀ
recommendedꢀtemperatureꢀandꢀpowerꢀsupplyꢀranges.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © ꢁ006 Avago Technologies Limited. All rights reserved.
AV0ꢀ-0ꢂ6ꢁEN - October ꢀ7, ꢁ006
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