U3741BM-P2FL中文资料_数据手册_规格书

Features

• Minimal External Circuitry Requirements, No RF Components on the PC Board Except

Matching to the Receiver Antenna

• High Sensitivity, Especially at Low Data Rates

• Sensitivity Reduction Possible Even While Receiving

• Fully Integrated VCO

• Low Power Consumption Due to Configurable Self Polling with a Programmable Time

Frame Check

• Supply Voltage 4.5 V to 5.5 V

• Operating Temperature Range -40°C to 105°C

• Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Printed Antenna on PCB

• Low-cost Solution Due to High Integration Level

• ESD Protection According to MIL-STD 883 (4KV HBM) Except Pin POUT (2KV HBM)

• High Image Frequency Suppression due to 1 MHz IF in Conjunction with a SAW

Front-end Filter

UHF ASK

Receiver IC

– Up to 40 dB is Thereby Achievable with Newer SAWs.

• Programmable Output Port for Sensitivity Selection or for Controlling External

Periphery

• Communication to the Microcontroller Possible via a Single, Bi-directional Data Line

• Power Management (Polling) is also Possible by Means of a Separate Pin via the

Microcontroller

U3741BM

• 2 Different IF Bandwidth Versions are Available (300 kHz and 600 kHz)

Description

The U3741BM is a multi-chip PLL receiver device supplied in an SO20 package. It has

been specially developed for the demands of RF low-cost data transmission systems

with low data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in

Manchester or Bi-phase code. The receiver is well suited to operate with Atmel's PLL

RF transmitter U2741B. Its main applications are in the areas of telemetering, security

technology and keyless-entry systems. It can be used in the frequency receiving

range of f₀= 300 MHz to 450 MHz for ASK or FSK data transmission. All the state-

ments made below refer to 433.92-MHz and 315-MHz applications.

Rev. 4662B–RKE–10/04

System Block Diagram

UHF ASK/FSK

Remote control receiver

Remote control transmitter

1 Li cell

U2741B

U3741BM

1...3

Demod

Control

XTO

µC

Encoder

ATARx9x

PLL

Antenna

Keys

XTO

VCO

PLL

Power

amp.

LNA

VCO

Block Diagram

V_S

50 kΩ

FSK/ASK

CDEM

FSK/ASK-

Demodulator

and data filter

DEMOD_OUT

DATA

RSSI

Limiter out

AVCC

ENABLE

TEST

SENS

Sensitivity

reduction

Polling circuit

and

IF Amp

control logic

POUT

MODE

DVCC

AGND

DGND

4^thOrder

FE

CLK

Standby logic

LPF

3 MHz

MIXVCC

LNAGND

LFGND

LFVCC

IF Amp

VCO

XTO

LF

LPF

3 MHz

f

LNA_IN

LNA

÷ 64

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U3741BM

4662B–RKE–10/04

U3741BM

Pin Configuration

Figure 1. Pinning SO20

SENS

FSK/ASK

CDEM

1

2

3

4

5

6

7

8

9

20 DATA

19 ENABLE

18 TEST

17 POUT

16 MODE

15 DVCC

14 XTO

AVCC

AGND

DGND

MIXVCC

LNAGND

LNA_IN

13 LFGND

12 LF

NC 10

11 LFVCC

Pin Description

Symbol

SENS

FSK/ASK

CDEM

AVCC

AGND

DGND

MIXVCC

LNAGND

LNA_IN

NC

Function

1

Sensitivity-control resistor

Selecting FSK/ASK. Low: FSK, High: ASK

Lower cut-off frequency data filter

Analog power supply

Analog ground

2

3

4

5

6

Digital ground

7

Power supply mixer

High-frequency ground LNA and mixer

RF input

8

9

10

11

12

13

14

15

16

17

18

Not connected

LFVCC

LF

Power supply VCO

Loop filter

LFGND

XTO

Ground VCO

Crystal oscillator

DVCC

MODE

POUT

TEST

Digital power supply

Selecting 433.92 MHz/315 MHz. Low: 4.90625 MHz (USA). High: 6.76438 (Europe)

Programmable output port

Test pin, during operation at GND

Enables the polling mode

19

20

ENABLE

DATA

Low: polling mode off (sleep mode)

H: polling mode on (active mode)

Data output/configuration input

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4662B–RKE–10/04

RF Front End

The RF front end of the receiver is a heterodyne configuration that converts the input

signal into a 1-MHz IF signal. According to the block diagram, the front end consists of

an LNA (low noise amplifier), LO (local oscillator), a mixer and RF amplifier.

The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO

(crystal oscillator) generates the reference frequency f_XTO. The VCO (voltage-controlled

oscillator) generates the drive voltage frequency f_LOfor the mixer. f_LOis dependent on

the voltage at pin LF. f_LOis divided by a factor of 64. The divided frequency is compared

to f_XTOby the phase frequency detector. The current output of the phase frequency

detector is connected to a passive loop filter and thereby generates the control voltage

V_LFfor the VCO. By means of that configuration, V_LFis controlled in a way that f_LO/64 is

equal to f_XTO. If f_LOis determined, f_XTOcan be calculated using the following formula:

f_LO

f_XTO= -------

64

The XTO is a one-pin oscillator that operates at the series resonance of the quartz crys-

tal. According to Figure 2, the crystal should be connected to GND via a capacitor CL.

The value of that capacitor is recommended by the crystal supplier. The value of CL

should be optimized for the individual board layout to achieve the exact value of f_XTOand

hereby of f_LO. When designing the system in terms of receiving bandwidth, the accuracy

of the crystal and XTO must be considered.

Figure 2. PLL Peripherals

V_S

DVCC

C_L

XTO

LFGND

R1 = 820 Ω

C9 = 4.7 nF

C10 = 1 nF

LF

R1

C9

V_S

C10

LFVCC

The passive loop filter connected to pin LF is designed for a loop bandwidth of

B_Loop= 100 kHz. This value for B_Loopexhibits the best possible noise performance of the

LO. Figure 2 shows the appropriate loop filter components to achieve the desired loop

bandwidth. If the filter components are changed for any reason, please note that the

maximum capacitive load at pin LF is limited. If the capacitive load is exceeded, a bit

check may no longer be possible since f_LOcannot settle in time before the bit check

starts to evaluate the incoming data stream. Therefore, self polling also does not work in

that case.

f_LOis determined by the RF input frequency f_RFand the IF frequency f_IFusing the follow-

ing formula:

f_LO= f_RF– f_IF

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U3741BM

4662B–RKE–10/04

U3741BM

To determine f_LO, the construction of the IF filter must be considered at this point. The

nominal IF frequency is f_IF= 1 MHz. To achieve a good accuracy of the filter’s corner fre-

quencies, the filter is tuned by the crystal frequency f_XTO. This means that there is a

fixed relation between f_IFand f_LOthat depends on the logic level at pin mode. This is

described by the following formulas:

f_LO

MODE = 0 (USA) f_IF= ---------

314

f_LO

MODE = 0 (Europe) f_IF= -----------------

432.92

The relation is designed to achieve the nominal IF frequency of f_IF= 1 MHz for most

applications. For applications where f_RF= 315 MHz, the MODE must be set to ‘0’. In the

case of f_RF= 433.92 MHz, the MODE must be set to ‘1’. For other RF frequencies, f_IFis

not equal to 1 MHz. f_IFis then dependent on the logical level at pin MODE and on f_RF.

Table 1 summarizes the different conditions.

The RF input either from an antenna or from a generator must be transformed to the RF

input pin LNA_IN. The input impedance of that pin is provided in the electrical parame-

ters. The parasitic board inductances and capacitances also influence the input

matching. The RF receiver U3741BM exhibits its highest sensitivity at the best sig-

nal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the

transformation network.

A good practice when designing the network is to start with power matching. From that

starting point, the values of the components can be varied to some extent to achieve the

best sensitivity.

If a SAW is implemented into the input network, a mirror frequency suppression of

∆P_Ref= 40 dB can be achieved. There are SAWs available that exhibit a notch at

∆f = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The

selectivity of the receiver is also improved by using a SAW. In typical automotive appli-

cations, a SAW is used.

Figure 3 on page 6 shows a typical input matching network for f_RF= 315 MHz and

f_RF= 433.92 MHz using a SAW. Figure 4 on page 6 illustrates an input matching to 50 Ω

without a SAW. The input matching networks shown in Figure 4 are the reference net-

works for the parameters given in the “Electrical Characteristics”.

Table 1. Calculation of LO and IF Frequency

Conditions

Local Oscillator Frequency

f_LO= 314 MHz

Intermediate Frequency

f_IF= 1 MHz

f_RF= 315 MHz, MODE = 0

f_RF= 433.92 MHz, MODE = 1

f_LO= 432.92 MHz

f_IF= 1 MHz

f_LO

f_IF= ---------

314

f_RF

f_LO= -------------------

300 MHz < f_RF< 365 MHz, MODE = 0

365 MHz < f_RF< 450 MHz, MODE = 1

1

1 + ---------

314

f_RF

f_LO

f_IF= -----------------

432.92

f_LO= ---------------------------

1

1 + -----------------

432.92

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4662B–RKE–10/04

Figure 3. Input Matching Network with SAW Filter

8

9

8

LNAGND

U3741BM

L

C3

9

L

LNA_IN

25n

47p

25n

22p

C16

C17

8.2p

C17

22p

C16

100p

L3

TOKO LL2012

F47NJ

TOKO LL2012

27NJ

f_RF= 433.92 MHz

f_RF= 315 MHz

47n

27n

L2

TOKO LL2012

F82NJ

TOKO LL2012

RF_IN

F33NJ

5

1

2

1

2

B3555

B3551

OUT

IN

OUT

33n

6

82n

6

C2

OUT_GND

IN_GND

C2

CASE_GND

3, 4 7, 8

CASE_GND

3, 4 7, 8

8.2p

10p

Figure 4. Input Matching Network without SAW Filter

f_RF= 315 MHz

f_RF= 433.92 MHz

8

LNAGND

U3741BM

9

LNA_IN

25n

33p

LNA_IN

25n

15p

RF_IN

RF

IN

3.3p

100p

3.3p

100p

39n

TOKO LL2012

F39NJ

22n

TOKO LL2012

F22NJ

Please note that for all coupling conditions (see Figure 3 and Figure 4), the bond wire

inductivity of the LNA ground is compensated. C3 forms a series resonance circuit

together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its

value is not critical but must be large enough not to detune the series resonance circuit.

For cost reduction, this inductor can be easily printed on the PCB. This configuration

improves the sensitivity of the receiver by about 1 dB to 2 dB.

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U3741BM

4662B–RKE–10/04

U3741BM

Analog Signal Processing

IF Amplifier

The signals coming from the RF front end are filtered by the fully integrated 4th-order IF

filter. The IF center frequency is f_IF= 1 MHz for applications where f_RF= 315 MHz or

f_RF= 433.92 MHz is used. For other RF input frequencies, refer to Table 1 to determine

the center frequency.

The U3741BM is available with 2 different IF bandwidths. U3741BM-M2, the version

with B_IF= 300 kHz, is well suited for ASK systems where Atmel’s PLL transmitter

U2741B is used. The receiver U3741BM-M3 employs an IF bandwidth of B_IF= 600 kHz.

This version can be used together with the U2741B in FSK and ASK mode. If used in

ASK applications, it allows higher tolerances for the receiver and PLL transmitter crys-

tals. SAW transmitters exhibit much higher transmit frequency tolerances compared to

PLL transmitters. Generally, it is necessary to use B_IF= 600 kHz together with such

transmitters.

RSSI Amplifier

The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is

fed into the demodulator. The dynamic range of this amplifier is DR_RSSI= 60 dB. If the

RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK

mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is

defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage

due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input

signal is about 60 dB higher compared to the RF input signal at full sensitivity.

In FSK mode, the S/N ratio is not affected by the dynamic range of the RSSI amplifier.

The output voltage of the RSSI amplifier is internally compared to a threshold voltage

VTh_red. VTh_red is determined by the value of the external resistor R_Sense. R_Senseis

connected between pin Sense and GND or VS. The output of the comparator is fed into

the digital control logic. By this means it is possible to operate the receiver at lower

sensitivity.

If R_Senseis connected to VS, the receiver operates at a lower sensitivity. The reduced

sensitivity is defined by the value of R_Sense, the maximum sensitivity by the sig-

nal-to-noise ratio of the LNA input. The reduced sensitivity is dependent on the signal

strength at the output of the RSSI amplifier.

Since different RF input networks may exhibit slightly different values for the LNA gain,

the sensitivity values given in the electrical characteristics refer to a specific input

matching. This matching is illustrated in Figure 4 on page 6 and exhibits the best possi-

ble sensitivity.

R_Sensecan be connected to VS or GND via a microcontroller or by the digital output port

POUT of the U3741BM receiver IC. The receiver can be switched from full sensitivity to

reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake

up if the RF input signal does not exceed the selected sensitivity. If the receiver is

already active, the data stream at pin DATA will disappear when the input signal is lower

than defined by the reduced sensitivity. Instead of the data stream, the pattern accord-

ing to Figure 5 is issued at pin DATA to indicate that the receiver is still active.

Figure 5. Steady L State Limited DATA Output Pattern

DATA

t_min2

t_{DATA_L_max}

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4662B–RKE–10/04

FSK/ASK Demodulator

and Data Filter

The signal coming from the RSSI amplifier is converted into the raw data signal by the

ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK.

Logic 'L' sets the demodulator to FSK, Logic 'H' sets it into ASK mode.

In ASK mode an automatic threshold control circuit (ATC) is employed to set the detec-

tion reference voltage to a value where a good signal-to-noise ratio is achieved. This

circuit also implies the effective suppression of any kind of in-band noise signals or com-

peting transmitters. If the S/N ratio exceeds 10 dB, the data signal can be detected

properly.

The FSK demodulator is intended to be used for an FSK deviation of ∆f ≥ 20 kHz. Lower

values may be used but the sensitivity of the receiver is reduced in that condition. The

minimum usable deviation is dependent on the selected baud rate. In FSK mode, only

BR_Range0 and BR_Range1 are available. In FSK mode, the data signal can be

detected if the S/N Ratio exceeds 2 dB.

The output signal of the demodulator is filtered by the data filter before it is fed into the

digital signal processing circuit. The data filter improves the S/N ratio as its bandpass

can be adopted to the characteristics of the data signal. The data filter consists of a

1st-order high-pass and a 1st-order low-pass filter.

The high-pass filter cut-off frequency is defined by an external capacitor connected to

pin CDEM. The cut-off frequency of the high-pass filter is defined by the following for-

mula:

1

f_{cu_DF}= ------------------------------------------------------------

2 × π × 30 kΩ× CDEM

In self-polling mode, the data filter must settle very rapidly to achieve a low current con-

sumption. Therefore, CDEM cannot be increased to very high values if self polling is

used. On the other hand, CDEM must be large enough to meet the data filter require-

ments according to the data signal. Recommended values for CDEM are given in the

“Electrical Characteristics” on page 23. The values are slightly different for ASK and

FSK mode.

The cut-off frequency of the low-pass filter is defined by the selected baud rate range

(BR_Range). BR_Range is defined in the OPMODE register (refer to section “Configu-

ration of the Receiver” on page 17). BR_Range must be set in accordance to the used

baud rate.

The U3741BM is designed to operate with data coding where the DC level of the data

signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation

schemes are used, the DC level should always remain within the range of

VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 1.5 dB

in that condition.

Each BR_Range is also defined by a minimum and a maximum edge-to-edge time

(tee_sig). These limits are defined in the “Electrical Characteristics” on page 23. They

should not be exceeded to maintain full sensitivity of the receiver.

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U3741BM

4662B–RKE–10/04

U3741BM

Receiving

Characteristics

The RF receiver U3741BM can be operated with and without a SAW front-end filter. In a

typical automotive application, a SAW filter is used to achieve better selectivity. The

selectivity with and without a SAW front end-filter is illustrated in Figure 6. This example

relates to ASK mode and the 300-kHz bandwidth version of the U3741BM. FSK mode

and the 600-kHz version of the receiver exhibit similar behavior. Note that the mirror fre-

quency is reduced by 40 dB. The plots are printed relative to the maximum sensitivity. If

a SAW filter is used, an insertion loss of about 4 dB must be considered.

When designing the system in terms of receiving bandwidth, the LO deviation must be

considered as it also determines the IF center frequency. The total LO deviation is cal-

culated to be the sum of the deviation of the crystal and the XTO deviation of the

U3741BM. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of

the U3741BM is an additional deviation due to the XTO circuit. This deviation is speci-

fied to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in

that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in

ASK mode but not in FSK mode.

Figure 6. Receiving Frequency Response

0.0

-10.0

-20.0

without SAW

-30.0

-40.0

-50.0

-60.0

-70.0

-80.0

with SAW

-90.0

-100.0

-6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0

1.0 2.0 3.0 4.0 5.0 6.0

df (MHz)

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4662B–RKE–10/04

Polling Circuit and Control Logic

The receiver is designed to consume less than 1 mA while being sensitive to signals

from a corresponding transmitter. This is achieved via the polling circuit. This circuit

enables the signal path periodically for a short time. During this time the bit check logic

verifies the presence of a valid transmitter signal. Only if a valid signal is detected the

receiver remains active and transfers the data to the connected microcontroller. If there

is no valid signal present, the receiver is in sleep mode most of the time resulting in low

current consumption. This condition is called polling mode. A connected microcontroller

is disabled during that time.

All relevant parameters of the polling logic can be configured by the connected micro-

controller. This flexibility enables the user to meet the specifications in terms of current

consumption, system response time, data rate etc.

Regarding the number of connection wires to the microcontroller, the receiver is very

flexible. It can be either operated by a single bi-directional line to save ports to the con-

nected microcontroller, it can be operated by up to three uni-directional ports.

Basic Clock Cycle of the The complete timing of the digital circuitry and the analog filtering is derived from one

clock. According to Figure 7, this clock cycle T_Clkis derived from the crystal oscillator

Digital Circuitry

(XTO) in combination with a divider. The division factor is controlled by the logical state

at pin MODE. According to section “RF Front End” on page 4, the frequency of the crys-

tal oscillator (f_XTO) is defined by the RF input signal (f_RFin) which also defines the

operating frequency of the local oscillator (f_LO).

Figure 7. Generation of the Basic Clock Cycle

T_Clk

MODE

Divider

:14/:10

L : USA (:10)

H: Europe (:14)

16

f_XTO

DVCC

15

XTO

14

XTO

Pin MODE can now be set in accordance with the desired clock cycle T_Clk. T_Clkcontrols

the following application-relevant parameters:

•

Timing of the polling circuit including bit check

Timing of analog and digital signal processing

Timing of register programming

Frequency of the reset marker

F filter center frequency (f_IF0

)

Most applications are dominated by two transmission frequencies: f_Send= 315 MHz is

mainly used in the USA, f_Send= 433.92 MHz in Europe. In order to ease the usage of all

T_Clk-dependent parameters, the electrical characteristics display three conditions for

each parameter.

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U3741BM

4662B–RKE–10/04

U3741BM

•

USA Applications

(f_XTO= 4.90625 MHz, MODE = L, T_Clk= 2.0383 µs)

Europe Applications

(f_XTO= 6.76438 MHz, MODE = H, T_Clk= 2.0697 µs)

Other applications

(T_Clkis dependent on f_XTOand on the logical state of pin MODE. The electrical

characteristic is given as a function of T_Clk).

The clock cycle of some function blocks depends on the selected baud rate range

(BR_Range) which is defined in the OPMODE register. This clock cycle T_XClkis defined

by the following formulas for further reference:

BR_Range = BR_Range0: T_XClk= 8 × T_Clk

BR_Range1:

BR_Range2:

BR_Range3:

T_XClk= 4 × T_Clk

T_XClk= 2 × T_Clk

T_XClk= 1 × T_Clk

Polling Mode

According to Figure 3 on page 6, the receiver stays in polling mode in a continuous

cycle of three different modes. In sleep mode, the signal processing circuitry is disabled

for the time period T_Sleepwhile consuming a low current of I_S= I_Soff. During the start-up

period, T_Startup, all signal processing circuits are enabled and settled. In the following bit

check mode, the incoming data stream is analyzed bit by bit against a valid transmitter

signal. If no valid signal is present, the receiver is set back to sleep mode after the

period T_Bitcheck. This period varies check by check as it is a statistical process. An aver-

age value for T_Bitcheckis given in “Electrical Characteristics” on page 23. During T_Startup

and T_Bitcheckthe current consumption is I_S= I_Son. The average current consumption in

polling mode is dependent on the duty cycle of the active mode and can be calculated

as:

I

_Soff× T_Sleep+ I_Son× (T_Startup+ T_Bitcheck

I_Spoll= ------------------------------------------------------------------------------------------------------------

_Sleep+ T_Startup+ T_Bitcheck

)

T

During T_Sleepand T_Startup, the receiver is not sensitive to a transmitter signal. To guaran-

tee the reception of a transmitted command, the transmitter must start the telegram with

an adequate preburst. The required length of the preburst is dependent on the polling

parameters T_Sleep, T_Startup, T_Bitcheckand the startup time of a connected microcontroller

(T_Start,µC). T_Bitcheckthus depends on the actual bit rate and the number of bits (N_Bitcheck) to

be tested.

The following formula indicates how to calculate the preburst length.

T

_Preburst≥ T_Sleep+ T_Startup+ T_Bitcheck+ T_{Start_µC}

Sleep Mode

The length of period T_Sleepis defined by the 5-bit word Sleep of the OPMODE register,

the extension factor X_Sleep, according to Figure 10 on page 13, and the basic clock cycle

T_Clk. It is calculated to be:

T_Sleep= Sleep × X_Sleep× 1024 × T_Clk

In US and European applications, the maximum value of T_Sleepis about 60 ms if X_Sleepis

set to 1. The time resolution is about 2 ms in that case. The sleep time can be extended

to almost half a second by setting X_Sleepto 8. X_Sleepcan be set to 8 by bit X_SleepStdor by

bit X_SleepTempresulting in a different mode of action as described below:

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4662B–RKE–10/04

X_SleepStd= 1 implies the standard extension factor. The sleep time is always extended.

_SleepTemp= 1 implies the temporary extension factor. The extended sleep time is used

X

as long as every bit check is OK. If the bit check fails once, this bit is set back to 0 auto-

matically resulting in a regular sleep time. This functionality can be used to save current

in presence of a modulated disturber similar to an expected transmitter signal. The con-

nected microcontroller is rarely activated in that condition. If the disturber disappears,

the receiver switches back to regular polling and is again sensitive to appropriate trans-

mitter signals.

According to Table 7 on page 19, the highest register value of Sleep sets the receiver to

a permanent sleep condition. The receiver remains in that condition until another value

for Sleep is programmed into the OPMODE register. This function is desirable where

several devices share a single data line.

Figure 8. Polling Mode Flow Chart

Sleep Mode:

All circuits for signal processing are

disabled. Only XTO and polling logic is

enabled.

Output level on pin IC_ACTIVE => low

Sleep:

5-bit word defined by Sleep0 to Sleep4 in

OPMODE register

I

_S= I_SON

X_Sleep

:

Extension factor defined by X_SleepTemp

according to Table 8

T_Sleep= Sleep × X_Sleep× 1024 × T_Clk

T_Clk

:

Basic clock cycle defined by f_XTOand pin

MODE

Start-up Mode:

The signal processing circuits are

enabled. After the start-up time (T_Startup) all

circuits are in stable condition and ready

to receive.

T_Startup

:

Is defined by the selected baud rate range

and T_Clk. The baud-rate range is defined

by Baud0 and Baud1 in the OPMODE

register.

I

_S= I_SON

T_Startup

T_Bit-check

:

Depends on the result of the bit check.

If the bit check is ok, T_Bit-checkdepends

on the number of bits to be checked

(N_Bit-checked) and on the utilized data rate.

Bit-check Mode:

The incomming data stream is analyzed.

If the timing indicates a valid transmitter

signal, the receiver is set to receiving

mode. Otherwise it is set to Sleep mode.

If the bit check fails, the average time

period for that check depends on the

selected baud-rate range on T_Clk. The

baud-rate range is defined by Baud0 and

Baud1 in the OPMODE register.

I

_S= I_Son

T_Bit-check

Bit-check

OK?

NO

YES

Receiving Mode:

The receiver is turned on permanently

and passes the data stream to the

connected microcontroller. It can be set to

Sleep mode through an OFF command

via pin DATA or ENABLE

I

_S= I_SON

OFF command

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U3741BM

4662B–RKE–10/04

U3741BM

Figure 9. Timing Diagram for a Completely Successful Bit Check

Number of Checked Bits: 3

Bit check ok

Enable IC

Bit check

Dem_out

1/2 Bit

DATA

Polling mode

Receiving mode

Bit Check Mode

In bit check mode, the incoming data stream is examined to distinguish between a valid

signal from a corresponding transmitter and signals due to noise. This is done by subse-

quent time frame checks where the distances between 2 signal edges are continuously

compared to a programmable time window. The maximum count of this edge-to-edge

test, before the receiver switches to receiving, mode is also programmable.

Configuring the Bit Check

Assuming a modulation scheme that contains 2 edges per bit, two time frame checks

are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation

schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the

variable N_Bitcheckin the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge

checks respectively. If N_Bitcheckis set to a higher value, the receiver is less likely to

switch to the receiving mode due to noise. In the presence of a valid transmitter signal,

the bit check takes less time if N_Bitcheckis set to a lower value. In polling mode, the bit

check time is not dependent on N_Bitcheck. Figure 9 shows an example where 3 bits are

tested successfully and the data signal is transferred to pin DATA.

According to Figure 10, the time window for the bit check is defined by two separate

time limits. If the edge-to-edge time t_eeis in between the lower bit check limit T_{Lim_min}and

the upper bit check limit T_{Lim_max}, the check will be continued. If t_eeis smaller than

T_{Lim_min}or t_eeexceeds T_{Lim_max}, the bit check will be terminated and the receiver

switches to sleep mode.

Figure 10. Valid Time Window for Bit Check

1/f_Sig

Dem_out

t_ee

T_{lim_min}

T_{lim_max}

For best noise immunity it is recommended to use a low span between T_{Lim_min}and

T_{Lim_max}. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter

preburst. A ‘11111...’ or a ‘10101...’ sequence in Manchester or Bi-phase is a good

choice in this regard. A good compromise between receiver sensitivity and susceptibility

to noise is a time window of ±25% regarding the expected edge-to-edge time t_ee. Using

preburst patterns that contain various edge-to-edge time periods, the bit check limits

must be programmed according to the required span.

13

4662B–RKE–10/04

The bit check limits are determined by means of the formula below:

_{Lim_min}= Lim_min × T_XClk

T

T_{Lim_max}= (Lim_max –1) × T_XClk

Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.

Using the above formulas, Lim_min and Lim_max can be determined according to the

required T_{Lim_min}, T_{Lim_max}and T_XClk. The time resolution when defining T_{Lim_min}and

T_{Lim_max}is T_XClk. The minimum edge-to-edge time t_ee(t_{DATA_L_min}, t_{DATA_H_min}) is defined

according to the section “Receiving Mode” on page 15. Due to this, the lower limit

should be set to Lim_min ≥ 10. The maximum value of the upper limit is Lim_max = 63.

Figure 11, Figure 12 and Figure 13 on page 15 illustrate the bit check for the default bit

check limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal pro-

cessing circuits are enabled during T_Startup. The output of the ASK/FSK demodulator

(Dem_out) is undefined during that period. When the bit check becomes active, the bit

check counter is clocked with the cycle T_XClk

.

Figure 11 shows how the bit check proceeds if the bit-check counter value CV_Lim is

within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In

Figure 12, the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit

check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 13 on page 15.

Figure 11. Timing Diagram During Bit Check

(Lim_min = 14, Lim_max = 24)

Bit check ok

Enable IC

T_Startup

Bit check

1/2 Bit

Dem_out

Bit check

0

Counter

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

1

2

3 4

T_XClk

Figure 12. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)

(Lim_min = 14, Lim_max = 24)

Bit check failed ( CV_Lim < Lim_min )

Enable IC

Bit check

Dem_out

1/2 Bit

Bit check

0

1

3 4 5 6 1 2 3 4

2 5 6 7 8 9 10

1112

Counter

Startup Mode

Bit check Mode

Sleep Mode

14

U3741BM

4662B–RKE–10/04

U3741BM

Figure 13. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)

(Lim_min = 14, Lim_max = 24)

Bit check failed (CV_Lim = Lim_max)

Enable IC

Bit check

Dem_out

1/2 Bit

Bit check

Counter

7

9

24

1011121314151617181920212223

1

2

3 4

5

6

7

1

2

3 4

5

6

8

0

Sleep Mode

Startup Mode

Bit check Mode

Duration of the Bit Check

If no transmitter signal is present during the bit check, the output of the ASK/FSK

demodulator delivers random signals. The bit check is a statistical process and T_Bitcheck

varies for each check. Therefore, an average value for T_Bitcheckis given in “Electrical

Characteristics”. T_Bitcheckdepends on the selected baud rate range and on T_Clk. A higher

baudrate range causes a lower value for T_Bitcheckresulting in lower current consumption

in polling mode.

In the presence of a valid transmitter signal, T_Bitcheckis dependant on the frequency of

that signal, f_Sigand the count of the checked bits, N_Bitcheck. A higher value for N_Bitcheck

thereby results in a longer period for T_Bitcheckrequiring a higher value for the transmitter

preburst T_Preburst

.

Receiving Mode

If the bit check has been successful for all bits specified by N_Bitcheck, the receiver

switches to receiving mode. According to Figure 9 on page 13, the internal data signal is

switched to pin DATA in that case. A connected microcontroller can be woken up by the

negative edge at pin DATA. The receiver stays in that condition until it is switched back

to polling mode explicitly.

Digital Signal Processing

The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different

ways and as a result converted into the output signal data. This processing depends on

the selected baud rate range (BR_Range). Figure 14 on page 16 illustrates how

Dem_out is synchronized by the extended clock cycle T_XClk. This clock is also used for

the bit check counter. Data can change its state only after T_XClkelapsed. The

edge-to-edge time period t_eeof the Data signal as a result is always an integral multiple

of T_XClk

The minimum time period between two edges of the data signal is limited to

_ee≥ T_{DATA_min}. This implies an efficient suppression of spikes at the DATA output. At the

.

t

same time, it limits the maximum frequency of edges at DATA. This eases the interrupt

handling of a connected microcontroller. T_{DATA_min}is to some extent affected by the pre-

ceding edge-to-edge time interval t_eeas illustrated in Figure 15. If t_eeis in between the

specified bit check limits, the following level is frozen for the time period

T_{DATA_min}= tmin1, in case of t_eebeing outside that bit check limits T_{DATA_min}= tmin2 is the

relevant stable time period.

The maximum time period for DATA to be low is limited to T_{DATA_L_max}. This function

ensures a finite response time during programming or switching off the receiver via pin

DATA. T_{DATA_L_max}is thereby longer than the maximum time period indicated by the

transmitter data stream. Figure 16 gives an example where Dem_out remains low after

the receiver has switched to receiving mode.

15

4662B–RKE–10/04

Figure 14. Synchronization of the Demodulator Output

T_XClk

Clock Bitcheck

counter

Dem_out

DATA

t_ee

Figure 15. Debouncing of the Demodulator Output

Dem_out

DATA

Lim_min ≤ CV_Lim < Lim_max

tmin1

t_ee

tmin2

CV_Lim < Lim_min or CV_Lim ≥ Lim_max

t_ee

Figure 16. Steady L State Limited DATA Output Pattern after Transmission

Enable IC

Bit check

Dem_out

DATA

t_{DATA_L_max}

tmin2

Bit check mode

Sleep mode

Receiving mode

After the end of a data transmission, the receiver remains active and random noise

pulses appear at pin DATA. The edge-to-edge time period t_eeof the majority of these

noise pulses is equal to or slightly higher than T_{DATA_min}

.

Switching the Receiver Back

to Sleep Mode

The receiver can be set back to polling mode via pin DATA or via pin ENABLE.

When using pin DATA, this pin must be pulled to low for the period t1 by the connected

microcontroller. Figure 17 illustrates the timing of the OFF command (see also Figure 21

on page 21). The minimum value of t1 depends on the BR_Range. The maximum value

for t1 is not limited but it is recommended not to exceed the specified value to prevent

erasing the reset marker. This item is explained in more detail in the section “Configura-

tion of the Receiver” on page 17. Setting the receiver to sleep mode via DATA is

achieved by programming bit 1 of the OPMODE register to 1. Only one sync pulse (t3) is

issued.

The duration of the OFF command is determined by the sum of t1, t2 and t10. After the

OFF command, the sleep time T_Sleepelapses. Note that the capacitive load at pin DATA

is limited. The resulting time constant τ together with an optional external pull-up resis-

tor may not be exceeded to ensure proper operation.

16

U3741BM

4662B–RKE–10/04

U3741BM

If the receiver is set to polling mode via pin ENABLE, an ‘L’ pulse (T_Doze) must be issued

at that pin. Figure 18 illustrates the timing of that command. After the positive edge of

this pulse, the sleep time T_Sleepelapses. The receiver remains in sleep mode as long as

ENABLE is held to ‘L’. If the receiver is polled exclusively by a microcontroller, T_Sleepcan

be programmed to 0 to enable a instantaneous response time. This command is the

faster option than via pin DATA at the cost of an additional connection to the

microcontroller.

Figure 17. Timing Diagram of the OFF Command Via Pin DATA

t1

t2

t3

t5

t4

t10

t7

Out1 (microcontroller)

DATA (U3741BM)

X

Serial bi-directional

data line

Bit 1

("1")

Receiver

on

(Start bit)

T_Sleep

Startup mode

OFF command

Figure 18. Timing Diagram of the OFF Command Via Pin ENABLE

T_Doze

T_Sleep

toff

ENABLE

DATA (U3741BM)

X

Serial bi-directional

data line

Receiver on

Startup mode

Configuration of the

Receiver

The U3741BM receiver is configured via two 12-bit RAM registers called OPMODE and

LIMIT. The registers can be programmed by means of the bi-directional DATA port. If

the register contents have changed due to a voltage drop, this condition is indicated by a

certain output pattern called reset marker (RM). The receiver must be reprogrammed in

that case. After a power-on reset (POR), the registers are set to default mode. If the

receiver is operated in default mode, there is no need to program the registers.

Table 3 on page 18 shows the structure of the registers. According to Table 2 on page

18, bit 1 defines if the receiver is set back to polling mode via the OFF command, (see

section “Receiving Mode” on page 15) or if it is programmed. Bit 2 represents the regis-

ter address. It selects the appropriate register to be programmed.

17

4662B–RKE–10/04

Table 2. Effect of Bit 1 and Bit 2 in Programming the Registers

Bit 1

Bit 2

Action

1

0

x

1

0

The receiver is set back to polling mode (OFF command)

The OPMODE register is programmed

The LIMIT register is programmed

Table 4 and the following illustrate the effect of the individual configuration words. The

default configuration is highlighted for each word.

BR_Range sets the appropriate baud rate range. At the same time it defines XLim. XLim

is used to define the bit check limits T_{Lim_min}and T_{Lim_max}as shown in Table 4.

POUT can be used to control the sensitivity of the receiver. In that application, POUT is

set to 1 to reduce the sensitivity. This implies that the receiver operates with full sensitiv-

ity after a POR.

Table 3. Effect of the Configuration Words within the Registers

Bit1 Bit2

Bit2

Bit4

Bit5

Bit6

Bit7

Bit8

Bit9

Bit10

Bit11

Bit12

Bit13

Bit14

OFF Command

1

OPMODE Register

0

1

BR_Range

N_Bitcheck

V_POUT

POUT

0

Sleep

Sleep2

0

X_Sleep

X_{Sleep Std}X_{Sleep Temp}

Baud1

0

Baud0

0

BitChk1

1

BitChk0

0

Sleep4

0

Sleep3

1

Sleep1

1

Sleep0

1

(Default)

LIMIT Register

0

Lim_min

Lim_max

Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0

(Default)

0

1

0

1

0

Table 4. Effect of the Configuration Word BR_Range

BR_Range

Baud1

Baud0

Baud Rate Range/Extension Factor for Bit Check Limits (XLim)

BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default)

XLim = 8 (Default)

0

BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud)

XLim = 4

0

1

0

1

BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud)

XLim = 2

BR_Range3 (Application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud)

XLim = 1

18

U3741BM

4662B–RKE–10/04

U3741BM

Table 5. Effect of the Configuration Word N_Bitcheck

N_Bitcheck

BitChk1

BitChk0

Number of Bits to be Checked

0

1

0

1

0

1

0

3

6 (Default)

9

Table 6. Effect of the Configuration Bit VPOUT

VPOUT

Level of the Multi-purpose Output Port POUT

POUT

0

1

0 (Default)

1

Table 7. Effect of the Configuration Word Sleep

Sleep

Sleep4

Sleep3

Sleep2

Sleep1

Sleep0

Start Value for Sleep Counter (T_Sleep= Sleep × X_Sleep× 1024 × T_Clk)

0

1

0

1

0

1

0 (Receiver is continuously polling until a valid signal occurs)

1 (T_Sleep≈ 2ms for X_Sleep= 1 in US-/European applications)

2

3

.

0

1

0

1

11 (USA: T_Sleep= 22.96 ms, Europe: T_Sleep= 23.31 ms) (Default)

.

1

0

1

0

1

29

30

31 (Permanent sleep mode)

Table 8. Effect of the Configuration Word X_Sleep

X_Sleep

X_SleepStd

X_SleepTemp

Extension Factor for Sleep Time (T_Sleep= Sleep × X_Sleep× 1024 × T_Clk

1 (Default)

)

0

1

0

1

0

1

8 (X_Sleepis reset to 1 if bit check fails once)

8 (X_Sleepis set permanently)

19

4662B–RKE–10/04

Table 9. Effect of the Configuration Word Lim_min

Lim_min

Lower Limit Value for Bit Check

Lim_min < 10 is not applicable

(T_{Lim_min}= Lim_min × XLim × T_Clk)

0

1

0

1

0

1

0

1

10

11

12

13

14 (Default)

0

1

0

(USA: T_{Lim_min}= 228 µs, Europe: T_{Lim_min}= 232 µs)

.

1

0

1

0

1

61

62

63

Table 10. Effect of the Configuration Word Lim_max

Lim_max

Upper Limit Value for Bit Check

Lim_max < 12 is not applicable

(T_{Lim_max}= (Lim_max - 1) × XLim × T_Clk)

0

1

0

1

0

1

0

12

13

14

.

24 (Default)

0

1

0

(USA: T_{Lim_max}= 375 µs, Europe: T_{Lim_max}= 381 µs)

.

1

0

1

0

1

61

62

63

Conservation of the Register

Information

The U3741BM has an integrated power-on reset and brown-out detection circuitry to

provide a mechanism to preserve the RAM register information.

According to Figure 19 on page 21, a power-on reset (POR) is generated if the supply

voltage V_Sdrops below the threshold voltage V_ThReset. The default parameters are pro-

grammed into the configuration registers in that condition. Once V_Sexceeds V_ThReset

,

the POR is canceled after the minimum reset period t_Rst. A POR is also generated when

the supply voltage of the receiver is turned on.

To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a

reset. The RM is represented by the fixed frequency f_RMat a 50% duty cycle. RM can be

canceled via an ‘L’ pulse t1 at pin DATA. The RM implies the following characteristics:

20

U3741BM

4662B–RKE–10/04

U3741BM

•

f_RMis lower than the lowest feasible frequency of a data signal. By this means, RM

cannot be misinterpreted by the connected microcontroller.

If the receiver is set back to polling mode via pin DATA, RM cannot be canceled by

accident if t1 is applied according to the proposal in the section “Programming the

Configuration Register” on page 21.

By means of that mechanism, the receiver cannot lose its register information without

communicating that condition via the reset marker RM.

Figure 19. Generation of the Power-on Reset

V_S

V_ThReset

POR

t_Rst

X

DATA (U3741BM)

1/f_RM

Figure 20. Timing of the Register Programming

T_Sleep

t1

t2

t3

t5

t9

t8

t4

t6

t7

Out1

(microcontroller)

DATA (U3741BM)

X

Serial bi-directional

data line

Bit 1

("0")

Bit 2

("1")

Bit 13

("0")

Bit 14

("1")

(Start bit)

(Register select)

(Poll8R)

(Poll8)

Startup

mode

Receiver

on

Programming Frame

Programming the

Configuration Register

The configuration registers are programmed serially via the bi-directional data line

according to Figure 20 and Figure 21.

Figure 21. One-wire Connection to a Microcontroller

U3741BM

Internal pull-up

microcontroller

Bi-directional

data line

resistor

DATA

I/O

Out 1 (µC)

DATA (U3741BM)

21

4662B–RKE–10/04

To start programming, the serial data line DATA is pulled to ‘L’ for the time period t1 by

the microcontroller. When DATA has been released, the receiver becomes the master

device. When the programming delay period t2 has elapsed, it emits 14 subsequent

synchronization pulses with the pulse length t3. After each of these pulses, a program-

ming window occurs. The delay until the program window starts is determined by t4, the

duration is defined by t5. Within the programming window, the individual bits are set. If

the microcontroller pulls down pin DATA for the time period t7 during t5, the according

bit is set to ‘0’. If no programming pulse t7 is issued, this bit is set to ‘1’. All 14 bits are

subsequently programmed in this way. The time frame to program a bit is defined by t6.

Bit 14 is followed by the equivalent time window t9. During this window, the equivalent

acknowledge pulse t8 (E_Ack) occurs if the mode word just programmed is equivalent to

the mode word that was already stored in that register. E_Ack should be used to verify

that the mode word was correctly transferred to the register. The register must be pro-

grammed twice in that case.

Programming of a register is possible both during sleep and active mode of the receiver.

During programming, the LNA, LO, low-pass filter, IF-amplifier and the demodulator are

disabled.

The programming start pulse t1 initiates the programming of the configuration registers.

If bit 1 is set to ‘1’, it represents the OFF command to set the receiver back to polling

mode at the same time. For the length of the programming start pulse t1, the following

convention should be considered:

•

t1(min) < t1 < 1535 × T_Clk: [t1(min) is the minimum specified value for the relevant

BR_Range]

Programming (respectively OFF command) is initiated if the receiver is not in reset

mode. If the receiver is in reset mode, programming (respectively Off command) is not

initiated, and the reset marker RM is still present at pin DATA.

This period is generally used to switch the receiver to polling mode. In a reset condition,

RM is not canceled by accident.

•

t1 > 5632 × T_Clk

Programming (respectively OFF command) is initiated in any case. RM is cancelled if

present. This period is used if the connected microcontroller detected RM. If a configura-

tion register is programmed, this time period for t1 can generally be used.

Note that the capacitive load at pin DATA is limited. The resulting time constant t

together with an optional external pull-up resistor may not be exceeded to ensure proper

operation.

22

U3741BM

4662B–RKE–10/04

U3741BM

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters

Symbol

V_S

Min.

Max.

6

Unit

V

Supply voltage

Power dissipation

P_tot

450

150

+125

+105

10

mW

°C

Junction temperature

Storage temperature

Ambient temperature

Maximum input level, input matched to 50 W

T_j

T_stg

-55

-40

°C

T_amb

P_{in_max}

°C

dBm

Thermal Resistance

Parameters

Symbol

Value

Unit

Junction ambient

R_thJA

100

K/W

Electrical Characteristics

All parameters refer to GND, T_amb= -40°C to +105°C, V_S= 4.5 V to 5.5 V, f₀= 433.92 MHz and f₀= 315 MHz, unless otherwise specified.

(V_S= 5 V, T_amb= 25°C)

6.76438-Mhz Osc.

(Mode 1)

4.90625-Mhz Osc.

(Mode 0)

Variable Oscillator

Typ.

Parameter

Test Condition

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Max.

Unit

Basic Clock Cycle of the Digital Circuitry

Basic clock

cycle

MODE = 0 (USA)

MODE = 1 (Europe)

1/(f_XTO/10)

1/(f_XTO/14)

µs

T_Clk

2.0383

2.0697

BR_Range0

BR_Range1

BR_Range2

BR_Range3

16.6

8.3

4.1

16.3

8.2

4.1

2.0

8 × T_Clk

4 × T_Clk

2 × T_Clk

1 × T_Clk

µs

Extended

basic clock

cycle

T_XClk

2.1

Polling Mode

Sleep ×

X_Sleep×

1024 ×

2.0383

Sleep and X_Sleepare

defined in the

OPMODE register

Sleep ×

X_Sleep

×

Sleep time

T_Sleep

X_Sleep

×

ms

1024 ×

2.0697

1024 × T_Clk

BR_Range0

BR_Range1

BR_Range2

BR_Range3

1855

1061

663

1827

1045

653

896.5

512.5

µs

Start-up time

T_Startup

320.5 × T_Clk

Average bit check

time while polling

BR_Range0

BR_Range1

BR_Range2

0.45

0.24

0.14

0.47

0.26

0.16

0.15

ms

T_Bitcheck

BR_Range3

Time for Bit

Check

Bit check time for a

valid input signal f_Sig

N_Bitcheck= 0

T_XClk

ms

T_Bitcheck

N_Bitcheck= 3

N_Bitcheck= 6

N_Bitcheck= 9

3/f_Sig

6/f_Sig

9/f_Sig

3.5/f_Sig3/f_Sig

6.5/f_Sig6/f_Sig

9.5/f_Sig9/f_Sig

3.5/f_Sig

6.5/f_Sig

9.5/f_Sig

3.5/f_Sig

6.5/f_Sig

9.5/f_Sig

23

4662B–RKE–10/04

Electrical Characteristics (Continued)

All parameters refer to GND, T_amb= -40°C to +105°C, V_S= 4.5 V to 5.5 V, f₀= 433.92 MHz and f₀= 315 MHz, unless otherwise specified.

(V_S= 5 V, T_amb= 25°C)

6.76438-Mhz Osc.

(Mode 1)

4.90625-Mhz Osc.

(Mode 0)

Variable Oscillator

Typ.

Parameter

Test Condition

Symbol

f_IF

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Max.

Unit

Receiving Mode

Intermediate MODE=0 (USA)

frequency

f

_XTO× 64/314

MHz

MODE=1 (Europe)

1.0

f_XTO× 64/432.92

BR_Range0

BR_Range1

BR_Range2

BR_Range3

1.0

1.8

3.2

5.6

1.8

3.2

5.6

1.0

1.8

3.2

5.6

1.8

3.2

5.6

BR_Range0 × 2 µs/T_Clk

BR_Range1 × 2 µs/T_Clk

BR_Range2 × 2 µs/T_Clk

BR_Range3 × 2 µs/T_Clk

kBaud

Baud rate

range

BR_Range

10.0

T_{DATA_min}

tmin1

tmin2

tmin1

tmin2

tmin1

tmin2

tmin1

tmin2

Minimum time BR_Range0

period

149

182

75

147

179

73

9 × T_XClk

11 × T_XCl

9 × T_XClk

11 × T_XClk

9 × T_XClk

11 × T_XClk

9 × T_XClk

11 × T_XClk

µs

between

edges at

pin DATA

(Figure 15)

BR_Range1

BR_Range2

BR_Range3

91

90

37.3

45.5

18.6

22.8

36.7

44.8

18.3

22.4

BR_Range0

BR_Range1

BR_Range2

BR_Range3

2169

1085

542

2136

1068

534

131 × T_XClk

µs

Maximum low

period at DATA

(Figure 16)

T_{DATA_L_max}

271

267

OFF

command at

pin ENABLE

(Figure 18)

1.5 ¥

T_Clk

t_Doze

3.1

3.05

µs

Configuration of the Receiver

Frequency of

the reset

marker

1

---------------------------------

4096 × T_CLK

f_RM

117.9

119.8

Hz

(Figure 19)

1535 ×

T_Clk

1535 ×

T_Clk

1535 ×

T_Clk

1535 ×

T_Clk

BR_Range0

2188

1104

561

3176

2155

1087

553

3128

1057 ×

T_Clk

533 ×

T_Clk

271 ×

T_Clk

140 ×

T_Clk

BR_Range1

Programming

start pulse

(Figure 17,

Figure 20)

BR_Range2

BR_Range3

after POR

t1

µs

290

286

11656

11479

5632 ×

T_Clk

Programming

delay period

(Figure 17,

Figure 20)

384.5×

T_Clk

385.5

× T_Clk

t2

t3

795

798

783

786

µs

Synchroni-

zation pulse

(Figure 17,

Figure 20)

265

261

128 × T_Clk

24

U3741BM

4662B–RKE–10/04

U3741BM

Electrical Characteristics (Continued)

All parameters refer to GND, T_amb= -40°C to +105°C, V_S= 4.5 V to 5.5 V, f₀= 433.92 MHz and f₀= 315 MHz, unless otherwise specified.

(V_S= 5 V, T_amb= 25°C)

6.76438-Mhz Osc.

(Mode 1)

4.90625-Mhz Osc.

(Mode 0)

Variable Oscillator

Typ.

Parameter

Test Condition

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Max.

Unit

Delay until the

program

window starts

(Figure 17,

Figure 20)

t4

131

129

63.5 × T_Clk

µs

Programming

window

(Figure 17,

Figure 20)

t5

530

522

256 × T_Clk

512 × T_Clk

µs

Time frame

of a bit

(Figure 20)

t6

t7

1060

1044

µs

Programming

pulse (Figure

17, Figure 20)

64 ×

T_Clk

256 ×

T_Clk

133

529

131

521

Equivalent

acknowledge

pulse: E_Ack

(Figure 20)

t8

t9

265

534

930

261

526

916

128 × T_Clk

258 × T_Clk

449.5 × T_Clk

µs

Equivalent

time window

(Figure 20)

OFF-bit

programming

window

t10

(Figure 17)

Electrical Characteristics

All parameters refer to GND, T_amb= -40°C to +105°C, V_S= 4.5 V to 5.5 V, f₀= 433.92 MHz and f₀= 315 MHz, unless otherwise specified.

(V_S= 5 V, T_amb= 25°C)

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Sleep mode

(XTO and polling logic active)

IS_off

190

350

µA

Current consumption

IC active

(startup-, bit check-, receiving mode)

pin DATA = H

IS_on

7.0

8.6

-57

mA

LNA Mixer

LNA/mixer/IF amplifier

input matched according to Figure 4

Third-order intercept point

IIP3

-28

dBm

Input matched according to Figure 4,

required according to I-ETS 300220

LO spurious emission at RF_In

Noise figure LNA and mixer (DSB)

LNA_IN input impedance

IS_LORF

NF

-73

7

dBm

dB

Input matching according to Figure 4

at 433.92 MHz

at 315 MHz

1.0 || 1.56

1.3 || 1.0

kΩ || pF

Zi_{LNA_IN}

1 dB compression point (LNA, mixer, IF Input matched according to Figure 4,

IP_1db

-40

dBm

amplifier)

referred to RF_in

25

4662B–RKE–10/04

Electrical Characteristics (Continued)

All parameters refer to GND, T_amb= -40°C to +105°C, V_S= 4.5 V to 5.5 V, f₀= 433.92 MHz and f₀= 315 MHz, unless otherwise specified.

(V_S= 5 V, T_amb= 25°C)

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Input matched according to Figure 4,

BER ≤10^-3,

ASK mode

Maximum input level

P_{in_max}

-28

-20

dBm

Local Oscillator

Operating frequency range VCO

f_VCO

299

449

MHz

f_osc= 432.92 MHz

at 1 MHz

at 10 MHz

Phase noise VCO/LO

L (fm)

-93

-113

-90

-110

dBC/Hz

Spurious of the VCO

VCO gain

at ±f_XTO

-55

-47

dBC

K_VCO

190

MHz/V

For best LO noise

(design parameter)

R1 = 820 Ω

C9 = 4.7 nF

C10 = 1 nF

Loop bandwidth of the PLL

Capacitive load at pin LF

B_Loop

100

kHz

nF

The capacitive load at pin LF is limited

if bit check is used. The limitation

therefore also applies to self polling.

C_{LF_tot}

10

XTO crystal frequency,

appropriate load capacitance must be

connected to XTAL

XTO operating frequency

6.764375 MHz

f_XTO

6.764375 6.764375 6.764375

-30 ppm +30 ppm

4.90625 4.90625 4.90625

MHz

4.90625 MHz

-30 ppm

+30 ppm

f_XTO= 6.764 MHz

4.906 MHz

150

220

Ω

Series resonance resistor of the crystal

R_S

Static capacitance of the crystal

C_xto

6.5

pF

Analog Signal Processing

Input matched according to Figure 4

ASK (level of carrier)

BER ≤10^-3, B = 300 kHz

f_in= 433.92 MHz/315 MHz

T = 25°C, V_S= 5 V

Input sensitivity ASK 300-kHz IF filter

P_{Ref_ASK}

f_IF= 1 MHz

Input sensitivity ASK 300-kHz IF filter BR_Range0

Input sensitivity ASK 300-kHz IF filter BR_Range1

Input sensitivity ASK 300-kHz IF filter BR_Range2

Input sensitivity ASK 300-kHz IF filter BR_Range3

-109

-107

-106

-104

-111

-109

-108

-106

-113

-111

-110

-108

dBm

Input matched according to Figure 4

ASK (level of carrier)

BER ≤10^-3, B = 600 kHz

f_in= 433.92 MHz/315 MHz

T = 25°C, V_S= 5 V

f_IF= 1 MHz

Input sensitivity ASK 600 kHz IF filter

P_{Ref_ASK}

26

U3741BM

4662B–RKE–10/04

U3741BM

Electrical Characteristics (Continued)

All parameters refer to GND, T_amb= -40°C to +105°C, V_S= 4.5 V to 5.5 V, f₀= 433.92 MHz and f₀= 315 MHz, unless otherwise specified.

(V_S= 5 V, T_amb= 25°C)

Parameters

Test Conditions

Symbol

Min.

-108

Typ.

-110

Max.

-112

Unit

dBm

Input sensitivity ASK 600 kHz IF filter BR_Range0

Input sensitivity ASK 600 kHz IF filter BR_Range1

Input sensitivity ASK 600 kHz IF filter BR_Range2

Input sensitivity ASK 600 kHz IF filter BR_Range3

-106.5

-106

-108.5

-108

-110.5

-110

-104

-106

-108

300-kHz and 600-kHz version

f_in= 433.92 MHz/315 MHz

f_IF= 1 MHz

Sensitivity variation ASK for the full

operating range compared to

∆P_Ref

+2.5

-1.5

dB

T_amb= 25°C, V_S= 5 V

P_ASK= P_{Ref_ASK}+ ∆P_Ref

300-kHz version

Sensitivity variation ASK for full

operating range including IF filter

compared to T_amb= 25°C, V_S= 5 V

f_in= 433.92 MHz/315 MHz

f_IF= 0.88 MHz to 1.12 MHz

f_IF= 0.85 MHz to 1.15 MHz

∆P_Ref

+5.5

+7.5

-1.5

dB

P_ASK= P_{Ref_ASK}+ ∆P_Ref

600-kHz version

Sensitivity variation ASK for full

operating range including IF filter

compared to T_amb= 25°C, V_S= 5 V

f_in= 433.92 MHz/315 MHz

f_IF= 0.79 MHz to 1.21 MHz

∆P_Ref

+5.5

+7.5

-1.5

dB

f_IF= 0.73 MHz to 1.27 MHz

P_ASK= P_{Ref_ASK}+ ∆P_Ref

Input matched according to Figure 4,

BER ≤10^-3, B = 600 kHz

Input sensitivity FSK 600 kHz IF filter f_in= 433.92 MHz/315 MHz

P_{Ref_FSK}

T = 25°C, V_S= 5 V

f_IF= 1 MHz

BR_Range0

Input sensitivity FSK 600 kHz IF filter df ≥ ±20 kHz

df ≥ ±30 kHz

-95.5

-96.5

-97.5

-98.5

-99.5

-100.5

dBm

BR_Range1

Input sensitivity FSK 600 kHz IF filter df ≥ ±20 kHz

df ≥ ±30 kHz

-94.5

-95.5

-96.5

-97.5

-98.5

-99.5

dBm

600-kHz version

Sensitivity variation FSK for the full

f_in= 433.92 MHz/315 MHz

operating range compared to

f_IF= 1 MHz

∆P_Ref

+2.5

-1.5

dB

T_amb= 25°C, V_S= 5 V

P_FSK= P_{Ref_FSK}+ ∆P_Ref

600-kHz version

Sensitivity variation FSK for full

operating range including IF filter

compared to T_amb= 25°C, V_S= 5 V

f_in= 433.92 MHz/315 MHz

f_IF= 0.86 MHz to 1.14 MHz

f_IF= 0.82 MHz to 1.18 MHz

∆P_Ref

+5.5

+7.5

-1.5

dB

P_FSK= P_{Ref_FSK}+ ∆P_Ref

The sensitivity of the receiver is higher

for higher values of ∆f_FSK

BR_Range0

20

30

50

kHz

FSK frequency deviation

∆f_FSK

BR_Range1

BR_Range2 and BR_Range3 are not

suitable for FSK operation

S/N ratio to suppress inband noise

signals

ASK mode

FSK mode

SNR_ASK

SNR_FSK

10

2

12

3

dB

Dynamic range RSSI ampl.

∆R_RSSI

60

dB

27

4662B–RKE–10/04

Electrical Characteristics (Continued)

All parameters refer to GND, T_amb= -40°C to +105°C, V_S= 4.5 V to 5.5 V, f₀= 433.92 MHz and f₀= 315 MHz, unless otherwise specified.

(V_S= 5 V, T_amb= 25°C)

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Lower cut-off frequency of the data

filter

1

f_{cu_DF}= -----------------------------------------------------------

2 × π × 30kΩ× CDEM

f_{cu_DF}

0.11

0.16

0.20

kHz

ASK mode

BR_Range0 (Default)

BR_Range1

BR_Range2

39

22

12

8.2

nF

Recommended CDEM for best

performance

CDEM

BR_Range3

FSK mode

BR_Range0 (Default)

BR_Range1

BR_Range2 and BR_Range3 are not

suitable for FSK operation

Recommended CDEM for best

performance

CDEM

27

15

nF

BR_Range0 (Default)

1000

560

320

180

µs

Maximum edge-to-edge time period of BR_Range1

the input data signal for full sensitivity BR_Range2

BR_Range3

t_{ee_sig}

Upper cut-off frequency programmable

in 4 ranges via a serial mode word

BR_Range0 (Default)

BR_Range1

BR_Range2

BR_Range3

Upper cut-off frequency data filter

f_u

2.5

4.3

7.6

3.1

5.4

9.5

3.7

6.5

11.4

20.4

kHz

13.6

17.0

BR_Range0 (Default)

270

156

89

µs

Minimum edge-to-edge time period of BR_Range1

the input data signal for full sensitivity BR_Range2

BR_Range3

t_{ee_sig}

50

dBm

(peak

level)

R_Senseconnected from pin Sens to V_S,

input matched according to Figure 4

Reduced sensitivity

P_{Ref_Red}

R_Sense= 56 kΩ, f_in= 433.92 MHz,

(V_S= 5 V, T_amb= 25°C)

at B = 300 kHz

Reduced sensitivity

-71

-67

-76

-72

-81

-77

dBm

at B = 600 kHz

R_Sense= 100 kΩ, f_in= 433.92 MHz

at B = 300 kHz

at B = 600 kHz

Reduced sensitivity

-80

-76

-85

-81

-90

-86

dBm

R_Sense= 56 kΩ, f_in= 315 MHz

at B = 300 kHz

at B = 600 kHz

-72

-68

-77

-73

-82

-78

dBm

R_Sense= 100 kΩ, f_in= 315 MHz

at B = 300 kHz

at B = 600 kHz

-81

-77

-86

-82

-91

-87

dBm

R_Sense= 56 kΩ

R_Sense= 100 kΩ

5

6

0

dB

Reduced sensitivity variation over full

operating range

∆P_Red

P_Red= P_{Ref_Red}+ DP_Red

28

U3741BM

4662B–RKE–10/04

U3741BM

Electrical Characteristics (Continued)

All parameters refer to GND, T_amb= -40°C to +105°C, V_S= 4.5 V to 5.5 V, f₀= 433.92 MHz and f₀= 315 MHz, unless otherwise specified.

(V_S= 5 V, T_amb= 25°C)

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Values relative to

R_Sense= 56 kΩ

_Sense= 68 kΩ

R_Sense= 82 kΩ

R_Sense= 100 kΩ

0

dB

Reduced sensitivity variation for

different values of R_Sense

R

-3.5

-6.0

-9.0

-11.0

-13.5

∆P_Red

R_Sense= 120 kΩ

R_Sense= 150 kΩ

P_Red= P_{Ref_Red}+ ∆P_Red

Threshold voltage for reset

V_ThRESET

1.95

39

2.8

3.75

V

Digital Ports

Data output

V_OI

R_Pup

τ

C_L

0.08

50

0.3

61

2.5

41

V

- Saturation voltage LOW

- Internal pull-up resistor

- Maximum time constant

- Maximum capacitive load

I_ol= 1 mA

t = C_L(R_pup//R_Ext

without ext. pull-up resistor

R_ext= 5 kΩ

kΩ

µs

pF

)

540

POUT output

- Saturation voltage LOW

- Saturation voltage HIGH

I_POUT= 1 mA

I_POUT= -1 mA

V_Ol

V_Oh

0.08

0.3

V

V_S- 0.3 V V_S- 0.14V

FSK/ASK input

- Low-level input voltage

- High-level input voltage

FSK selected

ASK selected

V_Il

V_Ih

0.2 × V_S

V

0.8 × V_S

ENABLE input

- Low-level input voltage

- High-level input voltage

Idle mode

Active mode

V_Il

V_Ih

V

0.8 × V_S

MODE input

- Low-level input voltage

- High-level input voltage

Division factor = 10

Division factor = 14

V_Il

V_Ih

0.2 × V_S

V

0.8 × V_S

TEST input

- Low-level input voltage

Test input must always be set to LOW

V_Il

V

29

4662B–RKE–10/04

Ordering Information

Extended Type Number

Package

SO20

Remarks

U3741BM-P2FL

2: IF bandwidth of 300 kHz, tube

2: IF bandwidth of 300 kHz, taped and reeled

3: IF bandwidth of 600 kHz, tube

3: IF bandwidth of 600 kHz, taped and reeled

U3741BM-P2FLG3

U3741BM-P3FL

SO20

U3741BM-P3FLG3

SO20

Package Information

9.15

8.65

Package SO20

Dimensions in mm

12.95

12.70

7.5

7.3

2.35

0.25

0.10

0.4

10.50

10.20

1.27

11.43

20

11

technical drawings

according to DIN

specifications

1

10

30

U3741BM

4662B–RKE–10/04

U3741BM

Revision History

Please note that the following page numbers referred to in this section refer to the

specific revision mentioned, not to this document.

Changes from Rev.

4662A - 06/03 to Rev.

4662B - 10/04

1. Put datasheet in a new template.

2. Heading rows at Table “Absolute Maximum Ratings” added.

3. Table “Ordering Information” on page 30 changed.

31

4662B–RKE–10/04

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Printed on recycled paper.

4662B–RKE–10/04

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Transferred	零件包装代码：	SOIC
包装说明：	SOP, SOP20,.4	针数：	20
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.06	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0	长度：	12.825 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	20	最高工作温度：	105 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP20,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	240	电源：	5 V
认证状态：	Not Qualified	子类别：	Other Telecom ICs
最大压摆率：	0.0086 mA	标称供电电压：	5 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	7.4 mm	Base Number Matches：	1

型号	制造商	描述	替代类型	文档
U3741BM-P2FLG3	ATMEL	UHF ASK RECEIVER IC	完全替代
ATA3741P2-TGSY	ATMEL	Telecom Circuit, 1-Func, PDSO20, LEAD FREE, SO-20	类似代替
ATA3741P2-TGQY	ATMEL	Telecom Circuit, 1-Func, PDSO20, LEAD FREE, SO-20	类似代替

型号	制造商	描述	价格	文档
U3741BM-P2FLG3	ATMEL	UHF ASK RECEIVER IC	获取价格
U3741BM-P3FL	ATMEL	UHF ASK RECEIVER IC	获取价格
U3741BM-P3FLG3	ATMEL	UHF ASK RECEIVER IC	获取价格
U3742BM	ATMEL	UHF ASK/FSK RECEIVER	获取价格
U3742BM-M3FL	ATMEL	UHF ASK/FSK RECEIVER	获取价格
U3742BM-M3FLG3	ATMEL	UHF ASK/FSK RECEIVER	获取价格
U3742BM-P3FLY	ATMEL	Telecom Circuit, 1-Func, PDSO20, SO-20	获取价格
U3745BM	ATMEL	UHF ASK RECEIVER IC	获取价格
U3745BM-MFL	ATMEL	UHF ASK RECEIVER IC	获取价格
U3745BM-MFLG3	ATMEL	UHF ASK RECEIVER IC	获取价格

U3741BM-P2FL

U3741BM-P2FL 概述

U3741BM-P2FL 规格参数

U3741BM-P2FL 数据手册

U3741BM-P2FL 替代型号

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