TSC695FL-15MA [ATMEL]
Low-Voltage Rad-Hard 32-bit SPARC Embedded Processor; 低压抗辐射的32位SPARC嵌入式处理器
| 型号： | TSC695FL-15MA |
| 厂家： | 
ATMEL |
| 描述： | Low-Voltage Rad-Hard 32-bit SPARC Embedded Processor |
| 文件： | 总42页 (文件大小：3365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Integer Unit Based on SPARC V7 High-performance RISC Architecture
• Optimized Integrated 32/64-bit Floating-point Unit
• On-chip Peripherals
– EDAC and Parity Generator and Checker
– Memory Interface
Chip Select Generator
Waitstate Generation
Memory Protection
– DMA Arbiter
– Timers
Low-Voltage
Rad-Hard 32-bit
SPARC
General Purpose Timer (GPT)
Real-time Clock Timer (RTCT)
Watchdog Timer (WDT)
– Interrupt Controller With 5 External Inputs
– General Purpose Interface (GPI)
– Dual UART
Embedded
Processor
• Speed Optimized Code RAM Interface
8- or 40-bit boot-PROM (Flash) Interface
• IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes
• Fully Static Design
• Performance: 12 MIPs/3 MFlops (Double Precision) at SYSCLK = 15 MHz
• Core Consumption: 0.3W Typ. at 12 MIPs
• Operating Range: 3.15V to 3.45V -55°C to +125°C
• Tested up to a Total Dose of 300 Krds (si) according toMIL STD 883 Method 1019
• No Single Event Latch-up Below an LET Threshold of 80 MeV/mg/cm2
• Single Event Upsets Error Rate Better than:
– 2 E-7 Error/Component/Day in GEO Orbit
– 5 E-5 Error/Component/Day in LEO Orbit (53°, 1000 km)
• Quality Grades: ESCC, and QMLQ or V with 5962-03246
• Package: 256 MQFPF; Bare Die
TSC695FL
Description
The TSC695FL (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit
RISC embedded processor implementing the SPARC architecture V7 specification. It
has been developed with the support of the ESA (European Space Agency), and
offers a full development environment for embedded space applications.
The processor is manufactured using the Atmel 0.5 µm radiation tolerant (≥ 300
KRADs (Si)) CMOS enhanced process (RTP). It can operate at a low voltage for opti-
mized power consumption (see datasheet TSC695FL). It has been specially designed
for space, as it has on-chip concurrent transient and permanent error detection.
The TSC695FL includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a
Memory Controller and a DMA arbiter. For real-time applications, the TSC695FL
offers a high security watchdog, two timers, an interrupt controller, parallel and serial
interfaces. Fault tolerance is supported using parity on internal/external buses and an
EDAC on the external data bus. The design is highly testable with the support of an
On-Chip Debugger (OCD), and a boundary scan through JTAG interface.
The TSC695FL is a selection of the TSC5695F performed for a narrow 3.3V biasing
voltage range (± 0.15V), as such, this specification can be only met by the products
solds as TSC695FL. Where computing power is not the key factor, it allows for a dra-
matic power consumption reduction (70%).
Rev. 4204C–AERO–05/05
Block Diagram
Figure 1. TSC695FL Block Diagram
32-bit
Integer
Unit
DMA
TAP
DMA Ctrl
Arbiter
32/64-bit
Floating-Point
Unit
Clock
&
Parity
Gen./Chk.
Reset
Access
Controller
Parity
Managt
Mem Ctrl
Gen./Chk.
Wait State
Controller
Ready/Busy
Add.+Size+ASI
Address
Interface
Error
Managt
Real Time Clock
Timer
Watch
Dog
General Purpose
Timer
EDAC
Data+Check bits
Parities
Interrupt
General Purpose
Interface
UART B
UART A
Parity
Gen./Check.
Controller
Interrupts
GPI bits
RxD, TxD
Pin Descriptions
For pin assignment, refer to package section.
Signal
Type
Active
Description
RA[31:0]
RAPAR
RASI[3:0]
RSIZE[1:0]
RASPAR
CPAR
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
32-bit registered address bus
Registered address bus parity
4-bit registered address space identifier
2-bit registered bus transaction size
Registered ASI and SIZE parity
Control bus parity
Output buffer: 400 pF
High
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High
High
D[31:0]
CB[6:0]
DPAR
32-bit data bus
7-bit check-bit bus
High
High
Low
High
High
High
Low
High
Data bus parity
RLDSTO
ALE
Registered atomic load-store
Address latch enable
Data transfer
DXFER
LOCK
I/O
I/O
I/O
I/O
I/O
Bus lock
RD
Read access
WE
Write enable
WRT
Advanced write
MHOLD+FHOLD
+BHOLD+FCCV
MHOLD
O
Low
Memory bus hold
MDS
O
O
I
Low
Low
Low
Memory data strobe
-
MEXC
Memory exception
-
PROM8
BA[1:0]
Select 8-bit wide PROM
Latched address used for 8-bit wide boot PROM
PROM chip select
-
O
O
I
-
ROMCS
ROMWRT
MEMCS[9:0]
MEMWR
Low
Low
Low
Low
-
ROM write enable
-
O
O
Memory chip select
Output buffer: 400 pF
Output buffer: 400 pF
Memory write strobe
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4204C–AERO–05/05
TSC695FL
Signal
Type
Active
Description
OE
O
O
O
O
O
O
O
I
Low
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
Low
High
Low
High
High
High
High
High
Memory output enable
Data buffer enable
Output buffer: 400 pF
BUFFEN
DDIR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Data buffer direction
Data buffer direction
I/O chip select
DDIR
IOSEL[3:0]
IOWR
I/O and exchange memory write strobe
Exchange memory chip select
Bus ready
EXMCS
BUSRDY
BUSERR
DMAREQ
DMAGNT
DMAAS
DRDY
I
Bus error
I
DMA request
O
I
DMA grant
DMA address strobe
Data ready during DMA access
IU error
O
O
O
O
I
IUERR
CPUHALT
SYSERR
SYSHALT
SYSAV
NOPAR
INULL
Processor (IU & FPU) halt and freeze
System error
System halt
O
I
System availability
No parity
O
O
O
O
O
I
Integer unit nullify cycle
Instruction fetch
INST
Used to check the execute
stage of IU
FLUSH
DIA
FPU instruction flush
Delay instruction annulled
Real Time Clock Counter output
Receive data UART ’A’ and ’B’
Transmit data UART ’A’ and ’B’
GPI input/output
instruction pipeline
RTC
-
RxA/RxB
TxA/TxB
GPI[7:0]
GPIINT
EXTINT[4:0]
EXTINTACK
IWDE
Input trigger
O
I/O
O
I
-
Input trigger
High
GPI interrupt
-
External interrupt
Input trigger
O
I
High
High
High
External interrupt acknowledge
Internal watch dog enable
External watch dog input interrupt
Watch dog clock
-
-
EWDINT
WDCLK
CLK2
I
Input trigger
I
-
I
Double frequency clock
System clock
-
SYSCLK
RESET
SYSRESET
TMODE[1:0]
DEBUG
TCK
O
O
I
-
Low
Low
Output reset
-
System input reset
Factory test mode
Input trigger
I
Functional mode=00
I
High
Low
Software debug mode
Test (JTAG) clock
-
I
-
TRST
I
Test (JTAG) reset
pull-up ≈ 37 kΩ
TMS
I
Test (JTAG) mode select
Test (JTAG) data input
Test (JTAG) data output
Main internal power
Output driver power
pull-up ≈ 37 kΩ
TDI
I
pull-up ≈ 37 kΩ
TDO
O
-
-
-
VCCI/VSSI
VCCO/VSSO
Note:
If not specified, the output buffer type is 150 pF, the input buffer type is TTL.
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System Architecture The TSC695FL is to be used as an embedded processor requiring only memory and
application specific peripherals to be added to form a complete on-board computer. All
other system support functions are provided by the core.
Figure 2. System Architecture Based on TSC695FL
DMA Unit
Boot PROM
Ax[31:0]
Xtd PROM
Xchg Mem
Glue
Logic
Xtd RAM
Local
Memory
I/O 0
to
I/O 3
DMAGNT
DMAREQ
DMAAS
Xtd I/O
(BUFFEN, DDIR)
Xtd general
MEMCtrl
(ROMCS, EXMCS, IOSEL[3:0], MEMWR, IOWR, OE, BUSRDY,...)
Memory
Interface
FPU
RAMCtrl
(MEMCS[9:0], MEMWR, OE)
RAM
Memory
DMA
DMA
(0 ws)
A[31:0]
IU
User
Application
Peripherals
TSC695FL
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4204C–AERO–05/05
TSC695FL
Product Description
Integer Unit
The IU is designed for highly dependable space and military applications, and includes
support for error detection. The RISC architecture makes the creation of a processor
that can execute instructions at a rate approaching one instruction per processor clock
possible.
To achieve that rate of execution, the IU employs a four-stage instruction pipeline that
permits parallel execution of multiple instructions.
•
•
Fetch - The processor outputs the instruction address to fetch the instruction.
Decode - The instruction is placed in the instruction register and is decoded. The
processor reads the operands from the register file and computes the next
instruction address.
•
•
Execute - The processor executes the instruction and saves the results in temporary
registers. Pending traps are prioritized and internal traps are taken during this stage.
Write - If no trap is taken, the processor writes the result to the destination register.
All four stages operate in parallel, working on up to four different instructions at a time. A
basic ’single-cycle’ instruction enters the pipeline and completes in four cycles.
By the time it reaches the write stage, three more instructions have entered and are
moving through the pipeline behind it. So, after the first four cycles, a single-cycle
instruction exits the pipeline and a single-cycle instruction enters the pipeline on every
cycle. Of course, a ’single-cycle’ instruction actually takes four cycles to complete, but
they are called single cycle because with this type of instruction the processor can com-
plete one instruction per cycle after the initial four-cycle delay.
Floating-point Unit
The FPU is designed to provide execution of single and double-precision floating-point
instructions concurrently with execution of integer instructions by the IU. The FPU is
compliant to the ANSI/IEEE-754 (1985) floating-point standard.
The FPU is designed for highly dependable space and military applications, and
includes support for concurrent error detection and testability.
The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and
write stages (F, D, E and W). The fetch unit captures instructions and their addresses
from the data and address busses. The decode unit contains logic to decode the float-
ing-point instruction opcodes. The execution unit handles all instruction execution. The
execution unit includes a floating-point queue (FP queue), which contains stored float-
ing-point operate (FPop) instructions under execution and their addresses. The
execution unit controls the load unit, the store unit, and the datapath unit. The FPU
depends upon the IU to access all addresses and control signals for memory access.
Floating-point loads and stores are executed in conjunction with the IU, which provides
addresses and control signals while the FPU supplies or stores the data. Instruction
fetch for integer and floating-point instructions is provided by the IU.
The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR
is a 32-bit status and control register. It keeps track of rounding modes, floating-point
trap types, queue status, condition codes, and various IEEE exception information. The
floating-point queue contains the floating-point instruction currently under execution,
along with its corresponding address.
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Instruction Set
TSC695FL instructions fall into six functional categories: load/store, arithmetic/logi-
cal/shift, control transfer, read/write control register, floating-point, and miscellaneous.
Please refer to SPARC V7 Instruction-set Manual.
Note:
The execution of IFLUSH will cause an illegal instruction trap.
On-chip Peripherals
Memory Interface
The TSC695FL is designed to allow easy interfacing to internal/external memory
resources.
Table 1. Memory Mapping
Memory Contents
Start Address
Size (bytes)
Data Size and Parity Options
8-bit mode
40-bit mode
8-bit mode
40-bit mode
No parity/-No EDAC/-Only byte write
Boot PROM
0x00000000
128K → 16M
Parity + EDAC mandatory/-Only word write
No parity/-No EDAC/-Only byte write
Extended PROM
Exchange Memory
System Registers
RAM (8 blocks)
Extended RAM
I/O Area 0
0x01000000
0x01F00000
0x01F80000
0x02000000
0x04000000
0x10000000
0x11000000
0x12000000
0x13000000
0x14000000
0x80000000
Max: 15M
Parity + EDAC mandatory/-Only word write
4K → 512K
512K (124 used)
8*32K → 8*4M
Max: 192M
0 → 16M
Parity + EDAC option/-Only word write
Parity/-Only word read/write access
Parity + EDAC option/-All data sizes allowed
I/O Area 1
0 → 16M
I/O Area 2
0 → 16M
I/O Area 3
0 → 16M
Extended I/O Area
Extended General
Max: 1728M
Max: 2G
Parity option/-All data sizes allowed
No parity/-All data sizes allowed
System Registers
The system registers are only writeable by IU in the supervisor mode or by DMA during
halt mode.
Table 2. System Registers Address Map
System Register Name
System Control Register
Software Reset
Address
SYSCTR
SWRST
PDOWN
SYSFSR
FAILAR
0x 01F8 0000
0x 01F8 0004
0x 01F8 0008
0x 01F8 00A0
0x 01F8 00A4
0x 01F8 00B0
0x 01F8 00D0
Power Down
System Fault Status Register
Failing Address Register
Error & Reset Status Register
Test Control Register
ERRRSR
TESCTR
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TSC695FL
4204C–AERO–05/05
TSC695FL
Table 2. System Registers Address Map (Continued)
System Register Name
Address
Memory Configuration Register
I/O Configuration Register
MCNFR
0x 01F8 0010
0x 01F8 0014
0x 01F8 0018
0x 01F8 0020
0x 01F8 0024
0x 01F8 0028
0x 01F8 002C
0x 01F8 0044
0x 01F8 0048
0x 01F8 004C
0x 01F8 0050
0x 01F8 0054
0x 01F8 0060
0x 01F8 0064
0x 01F8 0080
0x 01F8 0084
0x 01F8 0088
0x 01F8 008C
0x 01F8 0098
0x 01F8 00A8
0x 01F8 00AC
0x 01F8 00E0
0x 01F8 00E4
0x 01F8 00E8
IOCNFR
WSCNFR
APS1BR
APS1ER
APS2BR
APS2ER
INTSHR
INTPDR
INTMKR
INTCLR
INTFCR
WDOGTR
WDOGST
RTCCR
Waitstate Configuration Register
Access Protection Segment 1 Base Register
Access Protection Segment 1 End Register
Access Protection Segment 2 Base Register
Access Protection Segment 2 End Register
Interrupt Shape Register
Interrupt Pending Register
Interrupt Mask Register
Interrupt Clear Register
Interrupt Force Register
Watchdog Timer Register
Watchdog Timer Trap Door Set
Real Time Clock Timer <Counter> Register
Real Time Clock Timer <Scaler> Register
General Purpose Timer <Counter> Register
General Purpose Timer <Scaler> Register
Timers Control Register
RTCSR
GPTCR
GPTSR
TIMCTR
GPICNFR
GPIDATR
UARTAR
UARTBR
UARTSR
General Purpose Interface Configuration Register
General Purpose Interface Data Register
UART ’A’ Rx & Tx Register
UART ’B’ Rx & Tx Register
UART Status Register
Wait-state and Time-out
Generator
It is possible to control the wait state generation by programming a Waitstate Configura-
tion Register. The maximum programmable number of wait-states is applied by default
at reset.
It is possible to program the number of wait states for the following combinations:
–
–
–
–
RAM read and write
PROM read and write (i.e. EEPROM or Flash write)
Exchange Memory read/write
Four individual I/O peripherals read/write
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4204C–AERO–05/05
A bus time-out function of 256 system clock cycles is provided for the bus ready con-
trolled memory areas, i.e. the Extended PROM, Exchange Memory, Extended RAM,
Extended I/O and the Extended General areas.
EDAC
The TSC695FL includes a 32-bit EDAC (Error Detection And Correction). Seven bits
(CB[6:0]) are used as check bits over the data bus. The Data Bus Parity signal (DPAR)
is used to check and generate the odd parity over the 32-bit data bus. This means that
altogether 40 bits are used when the EDAC is enabled.
The TSC695FL EDAC uses a 7-bit Hamming code which detects any double bit error on
the 40-bit bus as a non-correctable error. In addition, the EDAC detects all bits stuck-at-
one and stuck-at-zero failure for any nibble in the data word as a non-correctable error.
Stuck-at-one and stuck-at-zero for all 32 bits of the data word is also detected as a non-
correctable error.
Memory and I/O Parity
The TSC695FL handles parity towards memory and I/O in a special way. The processor
can be programmed to use no parity, only parity or parity and EDAC protection towards
memory and to use parity or no towards I/O. The signal used for the parity bit is DPAR.
Memory Redundancy
Programming the Memory Configuration Register, the TSC695FL provides chip selects
for two redundant memory banks for replacement of faulty banks.
Memory Access Protection
•
•
Unimplemented Areas - Access to all unimplemented memory areas are handled by
the TSC695FL and detected as illegal.
RAM Write Access Protection - The TSC695FL can be programmed to detect and
mask write accesses in any part of the RAM. The protection scheme is enabled only
for data area, not for the instruction area. The programmable write access
protection is based on two segments.
•
Boot PROM Write Protection - The TSC695FL supports a qualified PROM write for
an 8-bit wide PROM and/or for a 40-bit wide PROM.
DMA
DMA Interface
The TSC695FL supports Direct Memory Access (DMA). The DMA unit requests access
to the processor bus by asserting the DMA request signal (DMAREQ). When the DMA
unit receives the DMAGNT signal in response, the processor bus is granted. In case the
processor is in the power-down mode the processor is permanent tri-stated, and a
DMAREQ will directly give a DMAGNT. The TSC695FL includes a DMA session time-
out function.
Bus Arbiter
The TSC695FL always has the lowest priority on the system bus.
Traps
A trap is a vectored transfer of control to the supervisor through a special trap table that
contains the first four instructions of each trap handler. The base address of the table is
established by supervisor and the displacement, within the table, is determined by the
trap type. Two categories of traps can appear.
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TSC695FL
4204C–AERO–05/05
TSC695FL
Synchronous Traps
Table 3. Synchronous Traps
Trap
Priority
Trap Type (tt) Comments
Sources: SYSRESET* pin
software reset
Reset
1
-
watchdog reset
IU or System error reset
Non-restartable, imprecise
Severe error requiring a re-boot
error
2.1
2.2
64h
62h
65h
63h
61h
TSC695FL enters (if not masked) in halt or reset mode.
Non-restartable,
precise error
Error not removable, PC & nPC OK
TSC695FL enters (if not masked) in halt or reset mode.
Special case of non-restartable, precise error.
TSC695FL enters (if not masked) in halt or reset mode.
2
Register file error
2.3
Retrying instruction but PC & nPC have to be re-adjusted
TSC695FL enters (if not masked) in halt or reset mode.
Restartable, late error
2.4
2.5
Restartable,
precise error
Retrying instruction
TSC695FL enters (if not masked) in halt or reset mode.
Parity error on control bus
Parity error on data bus
Parity error on address bus
Access to protected or unimplemented area
Uncorrectable error in memory
Bus time out
3
Instruction access
(Error on instruction fetch)
01h
Bus error
Illegal Instruction
Privileged instruction
FPU disabled
4
5
6
02h
03h
04h
05h
-
-
-
Overflow
During SAVE instruction or trap taken
Window
7
Underflow
06h
07h
During RESTORE instruction or RETT instruction
Memory address not aligned
Non-restartable error
Data bus error
8
-
9.1
9.2
9.3
9.4
9.5
Severe error, cannot restart the instruction.
Parity error on FPU data bus.
Restartable error
Can be removed restarting the instruction.
Sequence error
-
-
Unimplemented FPop
Invalid operation
Division by zero
Overflow
IEEE exceptions:
9
9.6
08h
Underflow
Inexact
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4204C–AERO–05/05
Table 3. Synchronous Traps (Continued)
Trap
Priority
Trap Type (tt) Comments
Idem “instruction access”
Data access exception
10
09h
(Error on data load)
System register access violation
Tag overflow
11
12
0Ah
TADDccTV and TSUBccTV instructions
Trap on integer condition codes (Ticc)
Trap instructions
80h to FFh
Table 4. Interrupts or Asynchronous Traps
Trap
Priority
Comments
Trap Type (tt)
1Fh
Watchdog time-out
External INT 4
13
Internal or external (EWDINT pin)
14
1Eh
EXTINTAK on only one of EXTINT[4:0]
Real time clock timer
General purpose timer
External INT 3
15
1Dh
-
16
1Ch
-
17
1Bh
EXTINTAK on only one of EXTINT[4:0]
External INT 2
18
1Ah
EXTINTAK on only one of EXTINT[4:0]
DMA time-out
19
19h
-
DMA access error
UART Error
20
18h
-
21
17h
-
Correctable error in memory
Data ready
22
16h
Data read OK but source not updated
UART B
Transmitter ready
23
15h
-
Data ready
UART A
Transmitter ready
24
25
26
14h
13h
12h
-
External INT 1
External INT 0
EXTINTAK on only one of EXTINT[4:0]
EXTINTAK on only one of EXTINT[4:0]
Logical OR of:
IU hardware error masked
IU error mode masked
System hardware error masked
Masked hardware errors
27
11h
It is possible to mask each individual interrupt (except Watchdog time-out). The interrupts in the Interrupt Pending Register
are cleared automatically when the interrupt is acknowledged.
By programming the Interrupt Shape Register, it is possible to define the external interrupts to be either active low or active
high and to define the external interrupts to be either edge or level sensitive.
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TSC695FL
Timers
In software debug mode the timers are controlled by a system register bit and the exter-
nal pin DEBUG.
General Purpose Timer
The General Purpose Timer (GPT) provides, in addition to a generalized counter func-
tion, a mechanism for setting the step size in which actual time counts are performed.
GPT is clocked by the internal system clock. They are possible to program to be either
of single-shot type or periodical type and in both cases generate an interrupt when the
delay time has elapsed. The current value of the scaler and counter of the GPT can be
read.
Real Time Clock Timer
Watchdog Timer
The only functional differences between the two timers are that the Real Time Clock
Timer (RTCT) has an 8-bit scaler (16-bit scaler for GPT) and that the RTCT interrupt has
higher priority than the GPT interrupt.
RTCT information is available on RTC output pin.
Setting the external pin IWDE to Vcc enables the internal watchdog timer. Otherwise the
watchdog function must be externally provided.
The watchdog is supplied from a separate external input (WDCLK). After reset, the timer
is enabled and starts running with the maximum range. If the timer is not refreshed
(reprogrammed) before the counter reaches zero value, an interrupt is sent. Simulta-
neously, the timer starts counting a reset time-out period. If the timer is not
acknowledged before the reset time-out period elapses, a reset is applied to TSC695FL.
UARTs
Two full duplex asynchronous receiver transmitters (UART) are included. In software
debug mode the UART’s are controlled by system register bits.
The data format of the UART’s is eight bits. It is possible to choose between even or odd
parity, or no parity, and between one and two stop bits. The UART’s provide double buff-
ering, i.e. each UART consists of a transmitter holding register, a receiver holding
register, a transmitter shift register, and a receiver shift register. Each of these registers
are 8-bit wide. For each UART a RX and TX Register is provided. The UART’s generate
an interrupt each time a byte has been received or a byte has been sent. There is
another interrupt to indicate errors.
The baud rate of both the UART’s is programmable. The clock is derived either from the
system clock or can use the watchdog clock.
General Purpose Interface
The General Purpose Interface (GPI) is an 8-bit parallel I/O port. Each pin can be config-
ured as an input or an output.
A falling or rising edge detection is made on each selected GPI inputs. Every input tran-
sition on GPI generates an external positive pulse on GPIINT pin of two SYSCLK width.
Execution Modes
Reset Mode
Reset mode is entered when:
–
–
The SYSRES input is asserted
Software reset which is caused by the software writing to a Software Reset
Register,
–
–
Watchdog reset which is caused by a Watchdog counter time-out
Error reset which is caused by a hardware parity error
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4204C–AERO–05/05
This RESET output has a minimum of 1024 SYSCLK width to allow the usage of flash
memories.
The error and Reset Status Register contain the source of the last processor reset.
Run Mode
In this mode the IU/FPU is executing, while all peripherals are running (if software
enabled).
System Halt Mode
System Halt mode is entered when the SYSHALT input is asserted. In this mode, the IU
and FPU are frozen, while the timers (includeing the internal watchdog timer) and
UART’s are stopped.
Power Down Mode
Error Halt Mode
This mode is entered by writing to the Power Down Register. In this mode, the IU and
FPU are frozen. The TSC695FL leaves the power-down mode if an external interrupt is
asserted.
Error Halt mode is entered under the following circumstances:
–
–
A internal hardware parity error.
The IU enters error mode.
The only way to exit Error Halt Mode is through Cold Reset by asserting SYSRESET.
Error Handler
The TSC695FL has one error output signal (SYSERR) which indicates that an
unmasked error has occurred. Any error signalled on the error inputs from the IU and
the FPU is latched and reflected in the Error and Reset Status Register. By default, an
error leads to a processor halt.
Parity Checking
The TSC695FL includes:
–
–
–
–
–
Parity checking and generation (if required) on the external data bus,
Parity checking on the external address bus,
Parity checking on ASI and SIZE,
Parity checking and generation on all system registers,
Parity generation and checking on the internal control bus to the IU,
All external parity checking can be disabled using the NOPAR signal.
System Clock
The TSC695FL uses CLK2 clock input directly and creates a system clock signal by
dividing CLK2 by two. It drives SYSCLK pin with a nominal 50% duty cycle for the appli-
cation. It is highly recommended that only SYSCLK rising edge is used as reference as
far as possible.
System Availability
Test Mode
The SYSAV bit in the Error and Reset Status Register can be used by software to indi-
cate system availability.
The TSC695FL includes a number of software test facilities such as EDAC test, Parity
test, Interrupt test, Error test and a simple Test Access Port. These test functions are
controlled using the Test Control Register.
12
TSC695FL
4204C–AERO–05/05
TSC695FL
Test and Diagnostic
Hardware Functions
A variety of TSC695FL test and diagnostic hardware functions, including boundary
scan, internal scan, clock control and On-chip Debugger, are controlled through an
IEEE 1149.1 (JTAG) standard Test Access Port (TAP).
Test Access Port
The TAP interfaces to the JTAG bus via 5 dedicated pins on the TSC695FL chip. These
pins are:
–
–
–
–
–
TCK (input): Test Clock
TMS (input): Test Mode Select
TDI (input): Test Data Input
TDO (output): Test Data Output
TRST (input): Test Reset
Instruction Register
Five standard instructions are supported by the TSC695FL TAP.
Binary Value Name of Instruction Data Register
Scan Chain Accessed
Boundary Scan
00. 0000
00. 0001
EXTEST
Register
Boundary scan chain
Boundary scan chain
Boundary Scan
Register
SAMPLE/PRELOAD
Boundary Scan
Register
00. 0011
11. 1111
10. 0000
INTEST
BYPASS
IDCODE
Boundary scan chain
Bypass register
Bypass Register
Device ID Register
ID register scan chain
Debugging
The design is highly testable with the support of an On-Chip Debugger (OCD), an inter-
nal and boundary scan through JTAG interface.
13
4204C–AERO–05/05
Electrical Characteristics
Absolute Maximum Ratings
Note: Stresses at or above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Military Range............................................... -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Supply Voltage...................................................-0.5V to +7.0V
Input Voltage......................................................-0.5V to +7.0V
DC Characteristics
Table 5. DC Characteristics at VDD 3.3V ± 0.15V
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
Input Low Voltage
for trigger input
VIL trigger
–
–
1
V
V
CC = 3.15 to 3.45V
CC = 3.15 to 3.45V
CC = 3.15 to 3.45V
CC = 3.15 to 3.45V
Input High Voltage
for trigger input
VIH trigger
∆VT
1.5
–
–
0.3
–
–
–
V
V
V
V
V
V
V
V
Input Hysteresis
for trigger input
Input Low Voltage
for TTL input
VIL TTL
VIH TTL
VOL400 pF
–
0.8
–
Input High Voltage
for TTL input
2
–
VCC = 3.15 to 3.45V
V
CC = 3.15 to 3.45V
Output Low Voltage
for 400 pF buffer
–
–
0.4
IOL = 9 mA
VCC = 3.15 to 3.45V
IOH = -6 mA
Output High Voltage
for 400 pF buffer
VOH400 pF
VOL150 pF
2.4
–
–
–
–
V
V
VCC = 3.15 to 3.45V
IOL = 3 mA
Output Low Voltage
for 150 pF buffer
0.4
V
CC = 3.15 to 3.45V
Output High Voltage
for 150 pF buffer
VOH150 pF
IccOP
2.4
–
–
–
–
–
V
IOH = -2 mA
Operating Supply Current
for core processor
100
10
mA
mA
VCC = 3.45V, f = 15 MHz
VCC = 3.45V, f = 15 MHz
Power Down Supply Current
for core processor
IccPD
–
IIL
IIH
Low Level Input Current
High-Level Input Current
-10
-10
10
–
–
–
10
10
µA
µA
µA
VCC = 3.45V, VIN = 0
VCC = 3.45V; VIN = VCC
VCC = 3.45V; VIN = 0
IILPU
Low Level Input Pull-up Current
350
14
TSC695FL
4204C–AERO–05/05
TSC695FL
Capacitance Ratings
Parameter
CIN
Description
Input Capacitance
Max
7 pF
8 pF
8 pF
COUT
Output Capacitance
Input/Output Capacitance
CIO
AC Characteristics
Table 6. AC Characteristics (SYSCLK Freq. = 15 MHz - 3.3V ± 0.15V) Cload = 50 pF, Vref = VCC/2
Min
(ns)
Max
Parameter
(ns) Comment
Reference Edge
t1
t2
33
66
16
–
–
CLK2 period
–
–
SYSCLK period
–
t3
–
CLK2 high and low pulse width
RA(31:0) RAPAR RSIZE RLDSTO output delay
LOCK Output delay
–
t4_1
t4_2
t5
10
16
18
18
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
–
–
MEMCS*(9:0) ROMCS* EXMCS* output delay
DDIR DDIR* output delay
t6
–
MEMWR* IOWR*output delay
formula: 20 ns + 1/4 t2
t7
–
36.5
SYSCLK- or SYSCLK+
OE* HL output delay
formula: 15 ns + 1/4 t2
t8
–
31.5
–
SYSCLK+
SYSCLK+
t9_1
t9_2
16
13
Data setup time during load
Data setup time during load NOPAR = 0 rpa = rec = either 0 or
1
–
SYSCLK+
SYSCLK+
SYSCLK-
SYSCLK+
SYSCLK+
SYSCLK-
t10
t11
t12
t13
t14
7
–
–
Data hold time during load
Data output delay
44
–
18
–
Data output valid to HZ – guaranteed by design
CB output delay
30
25
–
ALE* output delay
BUFFEN* HL output delay
formula: 16 ns + 1/4 t2
t15
–
32.5
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK-
SYSCLK+
SYSCLK+
t16
t17
t20
t21
t22
–
–
20
20
20
–
MHOLD* output delay – guaranteed by design
MDS* DRDY* output delay
–
MEXC* output delay
15
0
RASI(3:0) RSIZE(1:0) RASPAR setup time
RASI(3:0) RSIZE(1:0) RASPAR hold time
–
15
4204C–AERO–05/05
Table 6. AC Characteristics (SYSCLK Freq. = 15 MHz - 3.3V ± 0.15V) Cload = 50 pF, Vref = VCC/2 (Continued)
Min
(ns)
Max
Parameter
(ns) Comment
Reference Edge
SYSCLK+
t23
t24
t25
–
15
0
20
–
BOOT PROM address output delay
BUSRDY* setup time
BUSRDY* hold time
SYSCLK+
–
SYSCLK+
SYSCLK+ HL
SYSCLK- LH
t27
t28
t29
–
15
0
20
33
33
IOSEL output delay
DMAAS setup time
formula of max: 1/2 t2
SYSCLK+
DMAAS hold time
formula of max: 1/2 t2
SYSCLK-
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
–
t30
t31
t32
t33
t36
t37
t38
t39
t40
t41
t46
t48
t49
t50
t52
t53
t54
t56
t57
t60
15
–
–
20
–
DMAREQ* setup time
DMAGNT* output delay
RA(31:0) RAPAR CPAR setup time
RA(31:0) RAPAR CPAR hold time
TCK period
15
0
–
100
10
4
–
–
TMS setup time
TCK+
–
TMS hold time
TCK+
10
10
–
–
TDI setup time
TCK+
–
TDI hold time
TCK+
20
35
35
20
35
–
TDO output delay
TCK-
–
INULL output delay
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK-
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
–
RESET* CPUHALT* output delay
SYSERR* SYSAV output delay
IUERR* output delay
–
–
15
0
EXTINT(4:0) setup time
EXTINT(4:0) hold time
EXTINTACK output delay
OE* LH output delay (no DMA mode)
BUFFEN* LH output delay
INST output delay
–
–
20
14
15
35
–
–
–
Data output delay to low-Z – guaranteed by design
formula: 14 ns + 1/4 t2
t61
30.5
–
SYSCLK+
16
TSC695FL
4204C–AERO–05/05
TSC695FL
Figure 3. 150 pF Buffer Response (Data from simulation)
30
25
20
15
10
5
DTplh (Vref Vcc/2)
DTplh Typ
DTplh Min
DTplh Max
Table 1 : Pad 150pF - 3,15V up to 3,45V
Cload
50
DTplh min
DTplh typ
DTplh max
0
2,7
5,2
0
4,05
8,4
12,5
16,75
0
100
150
200
250
7,25
14,35
21,45
28,55
0
50 100 150 200 250
7,95
10,65
Cload (pF)
DTphl (Vref Vcc/2)
20
15
10
5
Table 2 : Pad 150pF - 3,15V up to 3,45V
Cload DTphl min DTphl typ DTphl max
50 0
DTphl Min
DTphlTyp
DTphl Max
0
2,65
5
7,35
9,95
0
3,5
6,95
10,45
13,85
100
150
200
250
5,7
11,15
15,6
0
50 100 150 200 250
18,45
Cload (pF)
Trise (Vref 10%-90%Vcc)
60
50
40
30
20
10
0
Table 3 : Pad 150pF - 3,15V up to 3,45V
Cload Trise min Trise typ Trise max
50 4,95 7,3
Trise Min
Trise Typ
Trise Max
12,55
23,5
34,3
45,3
56,4
100
150
200
250
8,4
12,25
15,9
13,15
19,3
25,55
31,8
50 100 150 200 250
19,85
Cload (pF)
Tfall (Vref 10%-90%Vcc)
60
50
40
30
20
10
0
Table 4 : Pad 150pF - 3,15V up to 3,45V
Cload Tfall min Tfall typ Tfall max
50 4,45 6,1
Tfall Min
Tfall Typ
Tfall Max
11,45
21,85
32,45
43,1
100
150
200
250
7,2
11,35
15,8
12
18,25
24,8
20,35
31,4
53,65
50 100 150 200 250
Cload (pF)
17
4204C–AERO–05/05
Figure 4. 400 pF Buffer Response (Data from simulation)
25
20
15
10
5
DTplh (Vref Vcc/2)
DTplh Typ
DTplh Min
DTplh Max
Table 5 : Pad 400pF - 3,15V up to 3,45V
Cload
50
DTplh min
DTplh typ
DTplh max
0
2,8
5,1
6,95
8,9
0
0
5,4
10,4
15,2
20,05
100
150
200
250
3,65
6,55
9,65
12,5
0
50 150 250 350 450
Cload (pF)
DTphl (Vref Vcc/2)
20
15
10
5
DTphl Min
DTphlTyp
DTphl Max
Table 6 : Pad 400pF - 3,15V up to 3,45V
Cload DTphl min DTphl typ DTphl max
50 0
0
0
100
150
200
250
3,6
6,3
8,85
11,5
3,9
6,95
10
5,1
9,7
14,1
18,25
0
50 150 250 350 450
12,95
Cload (pF)
Trise (Vref 10%-90%Vcc)
40
30
20
10
0
Table 7 : Pad 400pF - 3,15V up to 3,45V
Cload Trise min Trise typ Trise max
50 3,9
Trise Min
Trise Typ
Trise Max
3
5,7
12,2
19,15
26,25
33,65
100
150
200
250
5,8
8,1
10,7
13,15
7,7
11,6
15,5
19,5
50 150 250 350 450
Cload (pF)
Tfall (Vref 10%-90%Vcc)
35
30
25
20
15
10
5
Table 8 : Pad 400pF - 3,15V up to 3,45V
Cload Tfall min Tfall typ Tfall max
50 2,95 3,55
Tfall Min
Tfall Typ
Tfall Max
5
10,9
17,75
25
100
150
200
250
5,5
7,85
10,5
6,85
10,35
14,3
0
50 150 250 350 450
13,45
18,55
32,35
Cload (pF)
18
TSC695FL
4204C–AERO–05/05
TSC695FL
Figure 5. OE*/400 pF Buffer Response (Data from simulation)
25
20
15
10
5
DTplh (Vref Vcc/2)
DTplh Typ
DTplh Min
DTplh Max
Table 9 : Pad 400pF - OE* - 3,15V up to 3,45V
Cload
50
DTplh min
DTplh typ
DTplh max
0
2,75
5,1
6,95
8,9
0
3,7
6,6
0
100
150
200
250
5,35
10,35
15,2
0
50 150 250 350 450
9,7
Cload (pF)
12,55
20,05
20
DTphl (Vref Vcc/2)
15
10
5
DTphl Min
DTphlTyp
DTphl Max
Table 10 : Pad 400pF - OE* - 3,15V up to 3,45V
Cload DTphl min DTphl typ DTphl max
50 0
0
0
100
150
200
250
2,95
5,1
6,95
8,7
3,45
6,1
8,6
4,7
8,75
12,7
0
50 150 250 350 450
11,1
16,45
Cload (pF)
Trise (Vref 10%-90%Vcc)
40
30
20
10
0
Trise Min
Trise Typ
Trise Max
Table 11 : Pad 400pF - OE* - 3,15V up to 3,45V
Cload Trise min Trise typ Trise max
50 3,9 5,7
3
100
150
200
250
5,8
8,1
10,7
13,15
7,7
11,6
15,5
19,5
12,2
19,15
26,25
33,65
50 150 250 350 450
Cload (pF)
Tfall (Vref 10%-90%Vcc)
35
30
25
20
15
10
5
Table 12 : Pad 400pF - OE* - 3,15V up to 3,45V
Cload Tfall min Tfall typ Tfall max
50 2,45 3,25 4,7
Tfall Min
Tfall Typ
Tfall Max
100
150
200
250
4,7
6,4
6,1
9,15
10,05
16,25
23,15
30,2
0
8,5
10,55
12,45
16,2
50 150 250 350 450
Cload (pF)
19
4204C–AERO–05/05
Timing Diagrams
Figure 6. RAM Fetch, RAM Load and RAM Store Sequence - n Waitstates for Read, m Waitstates for Write
20
TSC695FL
4204C–AERO–05/05
TSC695FL
Figure 7. RAM “Atomic-load-store” byte Sequence - 0 Waitstate
21
4204C–AERO–05/05
Figure 8. RAM Load-double and RAM Store-double Sequence - 0 Waitstate
22
TSC695FL
4204C–AERO–05/05
TSC695FL
Figure 9. RAM Load with Correctable Error - 0 Waitstate
23
4204C–AERO–05/05
Figure 10. RAM Load with Uncorrectable Error - 0 Waitstate
24
TSC695FL
4204C–AERO–05/05
TSC695FL
Figure 11. RAM Load with Unimplemented Area Access - 0 Waitstate
25
4204C–AERO–05/05
Figure 12. I/O Store Sequence with BUSRDY* and n Waitstates (Timing for 0 Waitstate = Timing for 1 Waitstates)
26
TSC695FL
4204C–AERO–05/05
TSC695FL
Figure 13. I/O Load Sequence with BUSRDY* and n Waitstates (Timing for 0 ws = Timing for 1 ws)
27
4204C–AERO–05/05
Figure 14. EXCHANGE RAM Store with BUSDRY* and n Waitstates
28
TSC695FL
4204C–AERO–05/05
TSC695FL
Figure 15. EXCHANGE RAM Load with BUSDRY* and n Waitstates
29
4204C–AERO–05/05
Figure 16. 8-bit BOOT PROM Fetch (or Load Word) - n Waitstates
30
TSC695FL
4204C–AERO–05/05
TSC695FL
Figure 17. 8-bit BOOT PROM 2x Store byte - n Waitstate
31
4204C–AERO–05/05
Figure 18. DMA RAM load with or without Correctable Error and DMA RAM Store - 0 Waitstates
32
TSC695FL
4204C–AERO–05/05
TSC695FL
Figure 19. Edge Triggered Interrupt Timing
33
4204C–AERO–05/05
Figure 20. Halt Timing
34
TSC695FL
4204C–AERO–05/05
TSC695FL
Figure 21. External Error with Halt Timing
35
4204C–AERO–05/05
Figure 22. Reset Timing
36
TSC695FL
4204C–AERO–05/05
TSC695FL
Figure 23. External Error signaling with BUSERR* and BUSRDY*
1
2
3
4
SYSCLK
BUSRDY*
BUSERR*
MEXC*
t24
t24
t25
t25
t100
t20
37
4204C–AERO–05/05
TSC695FL
Package
Drawings
256-lead MQFP-F
37
4204C–AERO–05/05
256-lead MQFP-F Pin
Assignments
Table 7. Pin Assignments
Pin
Signal
GPIINT
GPI[7]
VCCO
VSSO
GPI[6]
GPI[5]
GPI[4]
GPI[3]
VCCO
VSSO
GPI[2]
GPI[1]
GPI[0]
D[31]
Pin
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
Signal
D[0]
Pin
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
Signal
RA[0]
Pin
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
Signal
DXFER
MEXC
1
2
RSIZE[1]
RSIZE[0]
RASI[3]
VCCO
VSSO
RASI[2]
RASI[1]
RASI[0]
RA[31]
RA[30]
VCCO
VSSO
RA[29]
RA[28]
RA[27]
VCCO
VSSO
RA[26]
RA[25]
RA[24]
VCCI
VCCO
3
VSSO
VCCO
4
RAPAR
RASPAR
DPAR
VSSO
5
RESET
SYSRESET
BA[1]
6
7
VCCO
8
VSSO
BA[0]
9
SYSCLK
TDO
CB[6]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
CB[5]
TRST
VCCO
TMS
VSSO
TDI
CB[4]
TCK
CB[3]
D[30]
CLK2
CB[2]
VCCO
VSSO
D[29]
DRDY
CB[1]
DMAAS
VCCO
VCCO
VSSO
D[28]
VSSO
CB[0]
VCCI
DMAGNT
EXMCS
VCCI
ALE
VSSI
VCCI
D[27]
VSSI
D[26]
VSSI
VSSI
PROM8
ROMCS
MEMCS[9]
VCCO
VCCO
VSSO
D[25]
VCCO
VSSO
RA[23]
RA[22]
RA[21]
VCCO
VSSO
RA[20]
RA[19]
RA[18]
DMAREQ
BUSERR
BUSRDY
ROMWRT
NOPAR
SYSHALT
CPUHALT
VCCO
D[24]
VSSO
D[23]
MEMCS[8]
MEMCS[7]
MEMCS[6]
MEMCS[5]
MEMCS[4]
MEMCS[3]
D[22]
VCCO
VSSO
D[21]
VSSO
D[20]
SYSERR
38
TSC695FL
4204C–AERO–05/05
TSC695FL
Table 7. Pin Assignments (Continued)
Pin
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Signal
D[19]
D[18]
VCCO
VSSO
D[17]
D[16]
VCCI
VSSI
D[15]
D[14]
VCCO
VSSO
D[13]
D[12]
D[11]
D[10]
VCCO
VSSO
D[9]
Pin
Signal
VCCO
VSSO
RA[17]
RA[16]
RA[15]
VCCO
VSSO
RA[14]
VCCI
Pin
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
Signal
SYSAV
EXTINT[4]
EXTINT[3]
EXTINT[2]
EXTINT[1]
EXTINT[0]
VCCI
Pin
Signal
VCCO
VSSO
98
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
MEMCS[2]
MEMCS[1]
MEMCS[0]
VCCI
VSSI
VSSI
OE
EXTINTACK
IUERR
VCCO
VCCO
VSSO
VSSI
RA[13]
RA[12]
VCCO
VSSO
RA[11]
RA[10]
RA[9]
MEMWR
BUFFEN
DDIR
VSSO
CPAR
TXA
VCCO
VSSO
RXA
RXB
DDIR
TXB
MHOLD
MDS
VCCO
VSSO
RA[8]
IOWR
IOSEL[3]
VCCO
WDCLK
IWDE
D[8]
D[7]
RA[7]
VSSO
EWDINT
TMODE[1]
TMODE[0]
DEBUG
INULL
D[6]
RA[6]
IOSEL[2]
IOSEL[1]
IOSEL[0]
WRT
VCCO
VSSO
D[5]
VCCO
VSSO
RA[5]
D[4]
RA[4]
WE
DIA
D[3]
RA[3]
VCCO
VCCO
VSSO
D[2]
VCCO
VSSO
RA[2]
VSSO
VCCO
VSSO
D[1]
RD
FLUSH
INST
RLDSTO
LOCK
RA[1]
RTC
39
4204C–AERO–05/05
Ordering
Information
Table 8. Possible Order Entries
Operating
Part Number
Supply Voltage
Temperature (°C)
Max Speed
Packaging
MQFP-F256
MQFP-F256
MQFP-F256
MQFP-F256
MQFP-F256
Die
Quality Flow
Engineering Samples
Standard Mil.
QML Q
TSC695FL-15MA-E
TSC695FL-15MA
5962-0324601QXC
5962-0324601VXC
TSC695FL-15SASB
TSC695FL-15MB-E
5962-0324601Q9A
5962-0324601V9A
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
25
15
15
15
15
15
15
15
15
-55 to 125
-55 to 125
-55 to 125
-55 to 125
25
QML V
ESCC
Engineering Samples
QML Q
-55 to 125
-55 to 125
Die
Die
QML V
40
TSC695FL
4204C–AERO–05/05
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