T2802-PLQ [ATMEL]
2.4 GHz WDECT/ISM SINGLE-CHIP TRANSCEIVER; 2.4 GHz的WDECT / ISM单芯片收发器
| 型号： | T2802-PLQ |
| 厂家： | 
ATMEL |
| 描述： | 2.4 GHz WDECT/ISM SINGLE-CHIP TRANSCEIVER |
| 文件： | 总29页 (文件大小：538K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fully Integrated TX/RX with VCO
• Fast Settling Synthesizer
• Unlimited Multi-slot Operation with Advanced Closed-loop Modulation
• No Mechanical Tuning Required
• Low Current Consumption
• Auxiliary Voltage Regulator On-chip (3.2 V to 4.6 V)
• Supply-voltage Range 3 V to 4.6 V (Regulated)
• Ramp-signal Generator for Power Ramping and Power Control of External SiGe Power
Amplifier (T7024 and T7026)
• Supports Multiple Reference Clocks (10.368 MHz/13.824 MHz/20.736 MHz/27.648 MHz)
• TX Preamplifier with 3 dBm Output Power at 2.45 GHz
• Few Low-cost External Components
2.4 GHz
WDECT/ISM
Single-chip
Transceiver
Electrostatic sensitive device.
Observe precautions for handling.
Description
T2802
The T2802 is an RF IC for low-power applications in the 2.45 GHz ISM band. The
QFN48-packaged IC is a complete transceiver including image rejection mixer, IF
amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, power-ramping
generator for power amplifiers, integrated synthesizer, fully integrated VCO, TX filter
and modulation compensation circuit for advanced closed-loop modulation concept.
No mechanical tuning is necessary in production.
Preliminary
Figure 1. Block Diagram
DEMOD
TANK
MIXER
OUT
IF_TANK
IF AMP 1
CF
IF_IN
IF AMP 2
IR MIXER
BB_OUT
RSSI
RF_IN
DEMOD
BB FILTER
RAMP_OUT
D/A
RAMP
GEN
RAMP
D/A
DEMOD DAC
RSSI
RAMP_SET
GF
VCO
TX/RX
SWITCH
TX_DATA
CLOCK
3-WIRE
PC
PD
MCC
RC
DATA
ENABLE
f
BUS
TX_OUT
PU_VCO
: n
TX DRIVER
RX_ON
CTRL
TX_ON
CP
LOGIC
PU_RX/TX
PU_PLL
AUX
REG
VCO
REG
f
: n
VREG_VCO
VS_VCO
VREG
VS_REG VTUNE
CP
LD
REF_CLK
GND_VCO
PU_REG REG_CTRL
I_CPSW
Rev. 4509F–DECT–10/03
Table 1. Functional Block Description
Name
Description
AUX REG
BBF
Auxiliary voltage regulator
Baseband filter
CP
Charge pump
DAC
D/A converter for demodulator tuning
Demodulator
DEMOD
GF
Gaussian filter for transmit data
1st intermediate frequency amplifier
2nd intermediate frequency amplifier
Image rejection mixer
IF AMP1
IF AMP2
IR MIXER
MCC
Modulation compensation circuit
Programmable counter
PC
PD
Phase detector
RAMP GEN
RC
Ramp-signal generator
Reference counter
RSSI
Received signal-strength indicator
Buffer amplifier for TX_OUT
Switches VCO signal to IR MIXER respectively TX DRIVER
Voltage-controlled oscillator
Voltage regulator for VCO
TX DRIVER
TX/RX SWITCH
VCO
VCO REG
Pin Configuration
Figure 2. Pinning QFN48
48 47 46 45 44 43 42 41 40 39 38 37
1
CLOCK
36
35
34
33
32
31
30
29
28
27
26
25
RAMP_OUT
2
DATA
ENABLE
IF_IN2
IF_IN1
VS_IF
3
4
REF_CLK
5
LD
PU_REG
VS_PLL
VREG
TX_OUT
GND3
6
T2802
7
RF_IN2
RF_IN1
8
9
REG_CTRL
VS_REG
GND2
10
11
12
IF_TANK2
GND_CP
VS_CP
IF_TANK1
RSSI
13 14 15 16 17 18 19 20 21 22 23 24
2
T2802
4509F–DECT–10/03
T2802
Pin Description
Pin
Symbol
Function
Configuration
VS_PLL
7
1
2
3
CLOCK
DATA
3-wire-bus: Clock input
3-wire-bus: Data input
3-wire-bus: Enable input
CLOCK
DATA
ENABLE
1,2,3
ENABLE
5k
5k
GND_PLL
43
VS_PLL
7
4
REF_CLK
Reference-frequency input
10k
10k
REF_CLK
4
GND_PLL
43
LD
5
100
5
LD
Lock-detect output
GND_PLL
43
PU_REG
6
25k
25k
6
PU_REG
Power-up input for auxiliary voltage regulator
GND_PLL
43
3
4509F–DECT–10/03
Pin Description (Continued)
Pin
Symbol
Function
Configuration
VS_PLL
7
GND1
18
VS_REG
10
VS_CP
12
GND2
28
VS_VCO
14
GND3
31
7
VS_PLL
PLL supply voltage
VS_IF
33
GND_VCO
16
GND_CP
11
VS_MIXER
42
GND_PLL
43
VS_REG
10
VS_PLL
7
REG_CTRL
9
8
9
VREG
REG_CTRL
VS_REG
Auxiliary voltage-regulator output
VREG
8
Auxiliary voltage-regulator control output
Auxiliary voltage-regulator supply voltage
10
GND_PLL
43
VS_CP
12
11
12
13
GND_CP
VS_CP
CP
Charge-pump ground
VS_PLL
7
Charge-pump supply voltage
Charge-pump output
CP
13
GND_PLL
43
GND_CP
11
4
T2802
4509F–DECT–10/03
T2802
Pin Description (Continued)
Pin
Symbol
Function
Configuration
VS_VCO
14
VS_PLL
7
14
15
16
VS_VCO
VREG_VCO
GND_VCO
VCO voltage-regulator supply voltage
VCO voltage-regulator control output
VCO ground
VREG_VCO
15
GND_PLL
43
GND_VCO
16
VREG_VCO
15
VS_PLL
7
17
VTUNE
VCO tuning voltage input
VTUNE
17
GND_PLL
43
GND_VCO
16
VS_PLL
7
GND1
18
VS_REG
10
VS_CP
12
GND2
28
VS_VCO
14
GND3
31
18
GND1
Ground
VS_IF
33
GND_VCO
16
GND_CP
11
VS_MIXER
42
GND_PLL
43
5
4509F–DECT–10/03
Pin Description (Continued)
Pin
Symbol
Function
Configuration
VS_MIXER
42
VS_IF
33
10k
10k
19
20
DEMOD_TANK1
DEMOD_TANK2
Demodulator tank circuit
Demodulator tank circuit
DEMOD
TANK1
19
DEMOD
TANK2
20
GND2
28
GND1
18
VREG_VCO
15
VS_PLL
7
10k
DAC_DEC
21
21
DAC_DEC
Decoupling PIN for VCO_DAC
400
GND_PLL
43
GND_VCO
16
VREG_VCO
15
2k
VS_IF
33
22
REG_DEC
Decoupling PIN for VCO_REG
REG_DEC
22
42k
GND2
28
GND_VCO
16
6
T2802
4509F–DECT–10/03
T2802
Pin Description (Continued)
Pin
Symbol
Function
Configuration
VS_IF
33
BB_CF
23
23
BB_CF
Baseband filter corner-frequency control input
GND2
28
GND1
18
VS_IF
33
24
BB_OUT
Baseband filter output
BB_OUT
24
GND2
28
GND1
18
VS_IF
33
25
RSSI
Received signal strength indicator output
RSSI
25
13k
GND2
28
VS_IF
33
26
27
IF_TANK1
IF_TANK2
IF tank circuit
IF tank circuit
IF_TANK1
26
27
GND2
28
7
4509F–DECT–10/03
Pin Description (Continued)
Pin
Symbol
Function
Configuration
VS_PLL
7
GND1
18
VS_REG
10
VS_CP
12
GND2
28
VS_VCO
14
GND3
31
28
GND2
Ground
VS_IF
33
GND_VCO
16
GND_CP
11
VS_MIXER
42
GND_PLL
43
VS_MIXER
42
29
30
RF_IN1
RF_IN2
RF input of image reject mixer
RF input of image reject mixer
RF_IN1
29
RF_IN2
30
GND2
28
VS_PLL
7
GND1
18
VS_REG
10
VS_CP
12
GND2
28
VS_VCO
14
GND3
31
31
GND3
Ground
VS_IF
33
GND_VCO
16
GND_CP
11
VS_MIXER
42
GND_PLL
43
8
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4509F–DECT–10/03
T2802
Pin Description (Continued)
Pin
Symbol
Function
Configuration
TX_OUT
32
32
TX_OUT
TX driver amplifier output for PA
GND3
31
VS_PLL
7
GND1
18
VS_REG
10
VS_CP
12
GND2
28
VS_VCO
14
GND3
31
33
VS_IF
IF amplifier supply voltage
VS_IF
33
GND_VCO
16
GND_CP
11
VS_MIXER
42
GND_PLL
43
VS_IF
33
34
35
IF_IN1
IF_IN2
IF input of IF amplifier
IF input of IF amplifier
90k
IF_IN1
34
IF_IN2
35
GND2
28
VS_MIXER
42
VS_IF
33
36
RAMP_OUT
Ramp-generator output for PA power ramping
RAMP_OUT
36
GND2
28
9
4509F–DECT–10/03
Pin Description (Continued)
Pin
Symbol
Function
Configuration
VS_MIXER
42
VS_IF
33
37
RAMP_SET
Slew-rate setting of ramping signal
RAMP SET
37
1k
100
GND2
28
VS_IF
33
38
39
RX_ON
TX_ON
RX control input
TX control input
RX_ON
TX_ON
38, 39
5k
5k
GND2
28
GND1
18
VS_MIXER
42
VS_IF
33
270
270
40
41
MIXER_OUT1
MIXER_OUT2
Mixer output to SAW filter
Mixer output to SAW filter
MIXER_OUT2
41
MIXER_OUT1
40
GND2
28
10
T2802
4509F–DECT–10/03
T2802
Pin Description (Continued)
Pin
Symbol
Function
Configuration
VS_PLL
7
GND1
18
VS_REG
10
VS_CP
12
GND2
28
VS_VCO
14
42
43
VS_MIXER
GND_PLL
Mixer supply voltage
PLL ground
GND3
31
VS_IF
33
GND_VCO
16
GND_CP
11
VS_MIXER
42
GND_PLL
43
VS_VCO
14
44
PU_VCO
VCO power-up input
PU_VCO
44
5k
5k
GND_PLL
43
GND_VCO
16
PU_RX/TX
45
25k
25k
45
PU_RX/TX
RX/TX power-up input
GND_PLL
43
GND1
18
11
4509F–DECT–10/03
Pin Description (Continued)
Pin
Symbol
Function
Configuration
20k
10k
140k
10k
25k
10k
25k
46
PU_PLL
PLL power-up input
PU
PLL
46
GND
PLL
43
VS_PLL
7
TX data input of Gaussian filter and modulation-
compensation circuit
47
TX_DATA
TX_DATA
47
2.5k
GND_PLL
43
VS_PLL
7
48
I_CPSW
Charge-pump current control input
I_CPSW
48
5k
GND_PLL
43
12
T2802
4509F–DECT–10/03
T2802
Functional Description
Receiver
The RF signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential
outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110.592 MHz or
112.32 MHz. The IF amplifiers IF_AMP1 and IF_AMP2 with an external IF_TANK and
an integrated RSSI function feed the signal to the demodulator DEMOD working at
f = fIF/2 (W55 MHz) and finally to an integrated baseband filter BB. For demodulator
tunning in production an integrated 5-bit digital-to-analog (D/A) converter is provided to
control the on-chip varicap diode.
Transmitter
Synthesizer
Power Supply
The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to
the fully integrated VCO operating at twice the output frequency. After modulation the
signal is frequency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This
bus-controlled driver amplifier supplies typically +3 dBm output power at TX_OUT. A
ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the
external power amplifier, is integrated. The slope of the ramp signal is controlled by a
capacitor at the RAMP_SET pin.
The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the
fully integrated VCO (including on-chip inductors and varactors). A 3-bit digital-to-analog
converter is used to pretune the frequency. The output signal is frequency-divided to
supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the
IR_MIXER and to be used by the PC for the phase detector PD (fPD = 3.456 MHz).
Unlimited multislot operation is possible by using the integrated advanced closed-loop
modulation concept based on the modulation compensation circuit MCC.
An integrated bandgap-stabilized voltage regulator for use with an external low-cost
PNP transistor is implemented. Multiple power-down and current saving modes are
provided.
13
4509F–DECT–10/03
Figure 3. PLL Principle
RF_IN
Programable counter PC
"- Main counter MC
"- Swallow counter SC
fVCO = fPD x (SMC x 32 + SSC
)
fVCO
ext. loop filter
PA driver
Mixer
Phase frequency
Charge
pump
Divider
by 2
detector PD
fPD = 3.456 MHz
VCO
VCO
DAC
GF_DATA
Modulation
compensation MCC
Gaussian
filter GF
Controlled phase shifting
Reference counter RC
6.912 MHz
SRC
REF_CLK
10.368 MHz
13.824 MHz
20.736 MHz
27.648 MHz
3
4
6
8
1.152 Mbit/s
TX_DATA
PLL reference
Frequency
REF_CLK
Baseband controller
14
T2802
4509F–DECT–10/03
T2802
The following table shows the LO frequencies for RX and TX for the DECT band plus additional channels for the extended
DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported.
Table 1. LO Frequencies
Mode
fIF/MHz
Channel
C0
fANT/MHz
2401.920
2403.648
...
fVCO/MHz
2401.920
2403.648
...
SMC
43
43
...
SSC
14
15
...
C1
TX
...
C45
C46
C0
2479.680
2481.408
2401.920
2403.648
...
2479.680
2498.688
2291.328
2293.056
...
44
44
41
41
...
27
28
14
15
...
C1
110.592
RX
(for 10.368 MHz/ 20.736 MHz
REF_CLK recommended)
...
C45
C46
C0
2479.680
2481.408
2401.920
2403.648
...
2369.088
2370.816
2289.600
2291.328
...
42
42
41
41
...
27
28
13
14
...
C1
112.320
RX
(for 13.824 MHz/ 27.648 MHz
REF_CLK recommended)
...
C45
C46
2479.680
2481.408
2367.360
2369.088
42
42
26
27
Formula
TX:
fANT = fVCO = 1.728 MHz P (32 P SMC + SSC)
RX: fANT = 1.728 MHz P (32 P SMC + SSC) + fIF
Control Signals
Table 2. Control Signals — Functions
Signal
Functions
Charge pump current control
I_CPSW
PU_REG
Activates AUX voltage regulator supplying the complete transceiver
Activates VCO voltage regulator which supplies only the VCO
Activates RX/TX blocks
PU_VCO
PU_RX/TX
PU_PLL
Activates PLL circuits: PC, PD, CP, RC
RX_ON
Activates RX circuits: BBF, DEMOD, IF AMP, IR MIXER
TX_ON
Activates TX circuits: TX-DRIVER, RAMP GEN, Starts RAMP SIGNAL at RAMP OUT
Activates GF in TX mode
Data Word 1 Bit D10
Data Word 1 Bit D9
Activates MCC in TX mode
15
4509F–DECT–10/03
Table 3. Control Signals — Modes
Modes
TX Mode
1
RX Mode
1
RSSI Only
1
PU_REG
PU_VCO
1
1
1
PU_RX/TX
1
1
1
PU_PLL
1
1
1
RX_ON
0
1
1
TX_ON
1
0
1
BB filter
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
58 mA
ON
ON
ON
ON
ON
OFF
OFF
OFF
ON
ON
OFF
ON
OFF
ON
85 mA
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
ON
ON
OFF
ON
OFF
ON
82 mA
Demodulator
IF amplifiers and RSSI
IR mixer
RX switch
TX switch
TX driver
Ramp generator
Programmable counter
Voltage-controlled oscillator
Gaussian filter
Phase detector/charge pump
Modulation compensation circuit
Reference counter
Typical current consumption at VS = 3.2 V
Serial Programming Bus
The transceiver is programmed by the 3-wire bus (CLOCK, DATA and ENABLE).
After the setting enable signal to low condition on the rising edge of the clock signal, the
data is transferred bit by bit into the shift register, starting with the MSB-bit. When the
enable signal has returned to high condition, the programmed information is loaded into
the addressed latches according to the address bit condition (last bit). Additional leading
bits are ignored and there is no check made how many pulses arrived during enable low
condition. During enable low condition the bus current is increased to speed up the bus
logic.
To keep all information in the registers during standby, DATA_HOLD must be set to high
condition. In this case the power-down current is below 100 µA.
The programming of the transceiver is separated into two data words. Data word 1 con-
trols mainly the channel information together with settings, which are closely related with
the channel. Dataword 2 holds setup information, which is adjusted during production.
16
T2802
4509F–DECT–10/03
T2802
Data Word 1
MSB
LSB
Data bits
Address
bit
D22
D21
D20
D19
D18
SC
D17
D16
D15
D14
MC
D13
D12
VS
D11
X
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GF
A0
RC
MCC
GFCS
VCODAC
CPCS
D11 = x: do not care
Data Word 2
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
A0
0
PA
DEMODDAC/RAMPDAC
MCCS
TEST
Data Word 1 Programs
PLL Settings
With the Reference Counter bits D21 - D22
RC (Reference Counter)
D22
0
D21
SRC
3
REF_CLK
10.368 MHz
13.824 MHz
20.736 MHz
27.648 MHz
0
1
0
1
0
4
1
6
1
8
With the Main Counter bits D13 - D15
MC (Main Counter)
D14
D15
0
D13
SMC
40
41
...
0
0
0
1
0
...
1
...
1
...
0
46
47
1
1
1
With the Swallow Counter bits D16 - D20
SC (Swallow Counter)
D20
0
D19
0
D18
0
D17
0
D16
0
SSC
0
1
0
0
0
0
1
0
0
0
1
0
2
...
1
...
1
...
1
...
0
...
1
...
29
30
31
1
1
1
1
0
1
1
1
1
1
17
4509F–DECT–10/03
VCO Selection
With bit D12
VCO Selection
D12
0
VCO Mode
RX-VCO
TX-VCO
1
Gaussian Filter On/Off
With bit D0
GF is used only in TX mode.
D0
0
GF (Gaussian Filter)
OFF
ON
1
Modulation
Compensation Circuit
On/Off
With bit D10
MCC is used only in TX mode.
D10
0
MCC (Modulation Compensation Circuit)
OFF
ON
1
GFCS Adjustment
With bits D7 - D9
Only in TX mode effective for setting the frequency deviation of the modulation.
GFCS (Gaussian Filter Settings)
D9
0
D8
0
D7
0
GFCS
60%
0
0
1
70%
0
1
0
80%
0
1
1
90%
1
0
0
100%
110%
120%
130%
1
0
1
1
1
0
1
1
1
18
T2802
4509F–DECT–10/03
T2802
VCO_DAC Adjustment
With bits D3 - D6
Used to pretune the VCO frequency in case of production tolerances of the device.
Pretune DAC Voltage
D6
0
D5
0
D4
0
D3
0
fVCO/%
-5
...
...
...
...
...
5
0
0
0
1
0
0
1
0
...
1
...
1
...
0
...
1
1
1
1
0
1
1
1
1
CPCS Adjustment
With bits D1 - D2
Used to adjust the charge pump current. This can be used to compensate the change of
the tuning sensitivity over frequency and device tolerances.
CPCS (Charge-pump Current Settings)
D2
0
D1
0
CPCS
-1
0
0
1
1
0
1
1
1
2
Data Word 2 Programs
DEMODDAC Adjustment
With bits E6 - E10
Only in RX mode effective. Used to tune the demodulator center frequency and allows
to compensate tolerances of external components and the T2802.
Demod DAC Voltage
E10
0
E9
0
E8
0
E7
0
E6
0
fIFcenter %
-5
...
...
...
...
...
5
0
0
0
0
1
0
0
0
1
0
...
1
...
1
...
1
...
0
...
1
1
1
1
1
0
1
1
1
1
1
19
4509F–DECT–10/03
RAMPDAC Adjustment
for TX Mode
With bits E6 - E10
Only in TX mode effective. Used to control the power of the external PA by adjusting the
ramping voltage.
RAMPDAC Voltage (at Pin 36 RAMP_OUT)
E10
0
E9
0
E8
0
E7
0
E6
0
VRAMP_OUT
1.1 V
...
0
0
0
0
1
0
0
0
1
0
...
...
1
...
0
...
1
...
1
...
1
...
1.68 V
1.7 V
...
1
1
0
0
0
...
1
...
1
...
1
...
1
...
0
...
1
1
1
1
1
1.7 V
MCCS Adjustment
With bits E3 - E5
Only in TX mode effective. Adjusts the modulation compensation circuit for closed-loop
modulation. This adjustment is done with a test sequence of a long stream of ,1‘ - ,0‘.
The correct setting is achieved if the modulation is not affected by the PLL.
MCCS (Modulation Compensation Settings)
E5
0
E4
0
E3
0
MCCS
60%
0
0
1
70%
0
1
0
80%
0
1
1
90%
1
0
0
100%
110%
120%
130%
1
0
1
1
1
0
1
1
1
TEST Mode Settings
With bits E0 - E2
In normal operation Lock detect output is used. All other settings are for test only.
E2
0
E1
0
E0
0
Signal at Lock Detect Output
Lock detect
CP Mode
Active
0
0
1
PC out/2
Active
0
1
0
RC out/2
Active
0
1
1
MCCTEST: RC out divided by 512
Lock detect
Active
1
0
0
High imp.
High imp.
High imp.
High imp.
1
0
1
PC out/2
1
1
0
RC out/2
1
1
1
GFTEST: RC out
20
T2802
4509F–DECT–10/03
T2802
Output Power Settings
With bits E11 - E12
PA (Output Power Settings)
E12
E11
PA
0
0
1
1
0
1
0
1
-21 dBm
-11 dBm
-4 dBm
+3 dBm
Figure 4. 3-Wire Bus Protocol Timing Diagram
DATA
CLOCK
ENABLE
TL
TC
TPER
TT
TEC
TS
TH
Description
Symbol
TPER
TS
Minimum Value
Unit
ns
Clock period
125
60
Set time data to clock
Hold time data to clock
Clock pulse width
ns
TH
60
ns
TC
125
200
0
ns
Set time enable to clock
Hold time enable to data
Time between two protocols
TL
ns
TEC
TT
ns
250
ns
Figure 5. TX DATA Timing
RefCLK
TX_DATA
TH
TS
Set-up time TX DATA
Hold time TX DATA
TS
TH
> 8 ns
> 8 ns
When using REFCLK = 10.368 MHz, TS and TH must be
considered for falling and rising edge of REFCLK
21
4509F–DECT–10/03
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All voltages refer to GND
Parameters
Pin
10
Symbol
VS_REG
VS
Min.
3.2
Max.
4.7
Unit
V
Supply voltage regulator
Supply voltage
7, 12, 14, 33, 42
3.0
4.7
V
1, 2, 3, 38, 39,
44-48
Logic input voltage
VIN
-0.3
VS
V
Junction temperature
Storage temperature
Tjmax
Tstg
150
150
LC
LC
-40
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
RthJA
25
K/W
Handling
Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test
requirement (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD
test requirement (MM) in accordance to EIA/JESD22-A115A.
Operating Range
Parameters
Pin
Symbol
VS_REG
VS
Min.
3.2
2.9
VS
Typ.
3.6
Max.
4.6
Unit
V
Supply voltage regulator
Supply voltage
10
7, 14, 33, 42
12
3.0
4.6
V
Supply voltage charge pump
Ambient temperature
VSCP
4.6
V
Tamb
-25
+85
LC
22
T2802
4509F–DECT–10/03
T2802
Electrical Characteristics
Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25LC
Parameters
Test Conditions/Pins
Symbol
Min.
Typ.
Max.
Unit
IR Mixer (Pins 29, 30, 40 and 41)
Input impedance
Single ended, pins 29 or 30
Pins 40 and 41
Zin
110 + j12
20
ꢀ
Image rejection ratio
IRR
dB
NFDSB=
NFSSB
DSB noise figure
Single ended, pins 29 or 30
10
dB
Conversion gain
Rload = 200 ꢀ
Gconv
IIP3
11
-7
dB
Input intercept point
Single ended, pins 29 or 30
dBm
175 +
j145
Output impedance
Differential, pins 40 and 41
Differential, pins 34 and 35
Zout
ꢀ
IF Amplifier (Pins 26, 27, 34 and 35)
Input impedance
1200 -
j480
Zin
ꢀ
Lower cut-off frequency
Upper cut-off frequency
Power gain
fl3dB
fu3dB
Gp
90
130
85
10
9
MHz
MHz
dB
Bandwidth of external tank circuit
Noise figure
Pins 26 and 27
BW3dB
NF
MHz
dB
RSSI (Pins 25, 34 and 35)
RSSI sensitivity
At IF_IN1,2; pins 34 and 35
At IF_IN1,2; pins 34 and 35
Pmin
Pmax
DR
Acc
tr
20
100
80
M2
1
dBµV
dBµV
dB
RSSI compression
RSSI dynamic range
RSSI resolution
Slope of the RSSI has to be steady
Pin = 30 to 100 dBµV, pin 25
Pin = 100 to 30 dBµV, pin 25
dB
RSSI rise time
µs
RSSI fall time
tf
1
µs
At Pin < 20 dBµV at IF_IN1, IF_IN2,
Pin 25
Quiescent output voltage
Maximum output voltage
Iout
Iout
0.4
1.9
V
V
At Pin = 100 dBµV at IF_IN1, IF_IN2,
Pin 25
FM Demodulator, BB-filter (Pins 19, 20, 23 and 24)
Co-channel rejection ratio
Sensitivity
At Pin = -75 dBm at IR-mixer input
CCRR
S
10
dB
Quality factor of external tank circuit
approximately 20, fres = FIF/2, pin 24
0.5
V/MHz
Nominal deviation of signal
M288 kHz, pin 24
Amplitude of recovered signal
A
450
680
mVpp
Corner frequency
Pin 23: C = 68 pF
Pin 24
fc
kHz
V
Output voltage DC range
DEMOD_DAC range
VoutDC
ꢁfIFcenter
1
VS - 1
See bus protocol E6 to E10
±5
%
23
4509F–DECT–10/03
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25LC
Parameters
VCOs
Test Conditions/Pins
Symbol
Min.
Typ.
Max.
Unit
TX-VCO, D12 (VS) = 1
RX-VCO, D12 (VS) = 0
fvco
fvco
2400
2289
2500
2389
MHz
MHz
Frequency range
Tuning gain
Gtune
Vtune
70
MHz/V
Frequency control voltage range
VCO_DAC range
Pin 17
0.4
2.8
V
See bus protocol D3 ... D6
ꢁfvco,DAC
M5
%
PLL
Scaling factor prescaler
Scaling factor main counter
Scaling factor swallow counter
SPSC
SMC
SSC
32/33
40 - 47
0
31
10.368
13.824
20.736
27.648
MHz
MHz
MHz
MHz
External reference input frequency AC coupled sinewave, pin 4
fREF_CLK
External reference input voltage
Scaling factor reference counter
Charge Pump (Pin 13)
AC coupled sinewave, pin 4
VREF_CLK
SRC
50
250
mVRMS
3/4/6/8
V
CP = VVS_CP /2, I_CPSW = ‘1’,
Output current
Output current
ICP_nom
7.5
1.2
mA
mA
Pin 48
VCP = VVS_CP /2, I_CPSW = ‘0’,
Pin 48
ICP_nom
ICP_step
IL
P
ICP = ICP_nom + CPCS ICP_step
(see bus protocol D1 ... D2)
Current scaling
Leakage current
0.2
mA
pA
M100
Gaussian Transmit Filter (Gaussian Shape B PꢂT = 0.5)
Tx data filter clock
6 taps in filter
fTXFCLK
6.912
MHz
kHz
Frequency deviation
GFFM_nom
M400
P
GFFM = GFFM_nom GFCS
(see bus protocol D7 ... D9)
Frequency deviation scaling
GFCS
60
60
130
%
Modulation Compensation Circuit
Oversampling
OVS
DSV
6
Digital sum variation
Current scaling factor
TX Driver (Pin 32)
85
See bus protocol E3 ... E5
MCCS
130
%
At L = 5.6 nH, pin 32
(see bus protocol E11 - E12)
Maximum output power
Minimum output power
PTX
PTX
3
dBm
dBm
At L = 5.6 nH, pin 32
(see bus protocol E11 - E12)
-21
24
T2802
4509F–DECT–10/03
T2802
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25LC
Parameters
Test Conditions/Pins
In RX mode
Symbol
Pleak
Min.
Typ.
13 + j40
0.7
Max.
Unit
dBm
ꢀ
RF leakage
-47
Output impedance
Ramp Generator (Pins 36 and 37)
Minimum output voltage
Maximum output voltage
Rise time
At L = 5.6 nH, 2.5 GHz, pin 32
ZOUT
Pin 36 and 37
Vmin
Vmax
tr
V
V
See bus protocol E6 - E10
1.1
1.8
C
ramp = 270 pF at pin 37
ramp = 270 pF at pin 37
5
5
µs
µs
Fall time
C
tf
Lock Detect and Test Mode Output (Pin 5)
locked = ‘1’,
unlocked = ‘0’
test modes
Lock detect output, test mode output
LD
(see bus protocol E0 ... E2)
Leakage current
V
OH = 4.6 V
IL
5
µA
V
Saturation voltage
I
OL = 0.5 mA
VSL
0.4
Auxiliary Regulator (Pins 8, 9 and 10)
Output voltage
V
SREG = 3 V, pin 8
VREG
SVR
2.9
2.6
3.0
3.1
V
VPin10 = VDC + 0.1 Vpp
fPin10 = 0.1 to 10 kHz
CPin8 = 100 nF
Supply voltage rejection
TBD
dB
VCO Regulator (Pins 14, 15 and 12)
Output voltage
3-wire Bus
Clock
VSVCO = 3 V, pin 15
VREG_VCO
2.7
2.8
V
fClock
6.912
MHz
Logic Input Levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, PU_VCO, TX_DATA, DATA_HOLD)
(Pins 1, 2, 3, 38, 39, 44, 47 and 48)
High input level
= ‘1’
= ‘0’
= ‘1’
= ‘0’
ViH
ViL
IiH
1.5
V
V
Low input level
0.5
5
High input current
-5
-5
µA
µA
Low input current
IiL
5
Standby Control (Pins 6, 45 and 46)
Power Up
PU_REG = ‘1‘
PU_RX/TX = ‘1‘
PU_PLL = ‘1‘
High input level
Pin 6
Pin 45
Pin 46
VPU_REG
VPU_RX/TX
VPU_PLL
2.0
V
Standby
PU_REG = ‘0‘
PU_RX/TX = ‘0‘
PU_PLL = ‘0‘
Low input level
Pin 6
Pin 45
Pin 46
VPU_REG,OFF
VPU_RX/TX,OFF
VPU_PLL,OFF
0.7
V
25
4509F–DECT–10/03
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25LC
Parameters
Test Conditions/Pins
Symbol
Min.
Typ.
Max.
Unit
Power Up
PU_REG = ‘1‘
PU_RX/TX = ‘1‘
V
PU = 3 V, pin 6
IPU_REG
IPU_RX/TX
20
60
30
80
40
100
µA
µA
VPU = 4.6 V, pin 45
PU_PLL = ‘1‘
High input current
V
V
PU = 3 V, pin 46
PU = 4.6 V
IPU_PLL
100
200
125
300
150
400
µA
µA
Standby
PU_xxxx = ‘0’
Low input current
V
PU = 0 V, pin 6
IPU,OFF
0.1
1
µA
µA
VPU = 0.5 V, pins 45, 46
Settling Time
Switched from
VS = 0 J active operation
VS = 0 to VS = 3V
tsoa
tssa
tsas
< 10
< 10
< 2
µs
µs
µs
Settling Time
standby J active operation
Switched from
PU = ‘0’ to PU = ‘1’
Settling Time
active operation J standby
Switched from
PU = ‘1’ to standby
Power Supply (Pins 7, 10, 12, 14, 33 and 42)
RX
IS
IS
IS
IS
IS
85
82
54
58
mA
mA
mA
mA
µA
RSSI only
Total supply current
TX
TX (MCC, GF active)
Standby current
PU_RX/TX = GND
10
VVS_CP = 3 V, PLL in lock condition,
Pin 13
Supply current CP
ICP
1
µA
26
T2802
4509F–DECT–10/03
T2802
Figure 6. Typical Application Circuit
RAMP_OUT
TX_OUT
RF_IN
47 pF
180 nH
100 nH
SAW
47pF
Filter
TFS
18 pF
27 pF
112B
RSSI
68 pF
150 nH
27 pF
56 pF
BB_OUT
37 RAMP_SET
BB_OUT 24
BB_CF 23
68 pF
RX_ON
TX_ON
38 RX_ON
39 TX_ON
REG_DEC 22
DAC_DEC 21
2.2 nF
40 MIXER_OUT1
41 MIXER_OUT2
42 VS_MIXER
43 GND_PLL
44 PU_VCO
45 PU_RX/TX
46 PU_PLL
100 pF
DEMOD_TANK2 20
DEMOD_TANK1 19
GND1 18
tbd
T2802
tbd
PU_VCO
PU_RX/TX
PU_PLL
VTUNE 17
GND_VCO 16
VREG_VCO 15
VS_VCO 14
22 nF
47 TX_DATA
48 I_CPSW
TX_DATA
I_CPSW
150 nF
180 Ω
CP 13
56 pF
470 nF
CLOCK
DATA
ENABLE
REF_CLK
LD
220 pF
PU_REG
4.7 nF
VCC
BC808
or similar
tantal
tantal
27
4509F–DECT–10/03
Ordering Information
Extended Type Number
Package
Remarks
T2802-PLQ
QFN48
Taped and reeled
Package Information
28
T2802
4509F–DECT–10/03
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4509F–DECT–10/03
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