QT1081-IS48G [ATMEL]
Analog Circuit,;
ATMEL 
lQ
QT1081
8-KEY QTOUCH™ SENSOR IC
The QT1081 is an improved, lower cost, simplified circuit version of the
popular QT1080 sensor IC. The QT1081 is designed for low cost
appliance, mobile, and consumer electronics applications.
QTouch™ technology is a type of patented charge-transfer sensing
method well known for its robust, stable, EMC-resistant characteristics.
It is the only all-digital capacitive sensing technology in the market
today. This technology has over a decade of applications experience
spanning thousands of designs.
23 22 21 20 19 18
24
17
16
SNS5
OUT_0
25
OUT_1 26
27
SNS4K
SNS4
15
14
13
12
11
10
OUT_2
SNS3K
OUT_3 28
OUT_4 29
QTouch circuits are renowned for simplicity, reliability, ease of design,
and cost effectiveness.
QT1081
32-QFN
SNS3
SNS2K
SNS2
SN1K
OUT_5
OUT_6
30
31
QTouch™ sensors employ a single reference capacitor tied to two pins
of the chip for each sensing key; a signal trace leads from one of the
pins to the sensing electrode which forms the key. The sensing
electrode can be a simple solid shape such as a rectangle or circle. An
LED can be placed near or inside the solid circle for illumination.
OUT_7 32
9
8
2
3
5
7
1
4
6
The key electrodes can be designed into a conventional printed circuit
board (PCB) or flexible printed circuit board (FPCB) as a copper
pattern, or as printed conductive ink.
The QT1081 is also compatible with clear films to make simple
button-style touch screens over LCD displays.
AT A GLANCE
Number of keys:
1 to 8
Patented spread-spectrum charge-transfer (one-per-key mode)
Technology:
Key outline sizes:
Key spacings:
Electrode design:
Layers required:
Substrates:
5mm x 5mm or larger (panel thickness dependent); widely different sizes and shapes possible
6mm or wider, center to center (panel thickness, human factors dependent)
Single solid or ring shaped electrodes; wide variety of possible layouts
One layer substrate; electrodes and components can be on same side
FR-4, low cost CEM-1 or FR-2 PCB materials; polyamide FPCB; PET films, glass
Electrode materials: Copper, silver, carbon, ITO, Orgacon† ink (virtually anything electrically conductive)
Panel materials:
Adjacent Metal:
Panel thickness:
Key sensitivity:
Outputs:
Plastic, glass, composites, painted surfaces (low particle density metallic paints possible)
Compatible with grounded metal immediately next to keys
Up to 50mm glass, 20mm plastic (key size dependent)
Settable via change in reference capacitor (Cs) value
Parallel discrete output, one-per-key, active-high
Moisture tolerance: Good
Power:
2.8V ~ 5.0V, <15µA (8 keys at 2.8V, 340ms Low Power mode).
32-pin 5 x 5mm QFN RoHS compliant
Package:
Signal processing: Self-calibration, auto drift compensation, noise filtering, patented Adjacent Key SuppressionTM
Applications:
Patents:
Portable devices, domestic appliances and A/V gear, PC peripherals, office equipment
AKS™ (patented Adjacent Key Suppression)
QTouch™ (patented Charge-transfer method)
†Orgacon is a registered trademark of Agfa-Gevaert N.V
AVAILABLE OPTIONS
32-QFN
TA
48-SSOP
QT1081-IS48G
-40oC to +85oC
QT1081-ISG
LQ
Copyright © 2006-2007 QRG Ltd
QT1081 R1.03/0107
Contents
2.8 MOD_0, MOD_1 Inputs
2.9 Fast Detect Mode
1 Overview
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3
3
3
3
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3
3
3
3
3
3
4
4
4
5
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1.1 Differences With QT1080
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1.2 Parameters
2.10 Simplified Mode
2.11 Unused Keys
1.2.1 Introduction
1.2.2 Burst Operation
1.2.3 Self-calibration
1.2.4 Autorecalibration
3 Design Notes
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3.1 Oscillator Frequency
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3.2 Spread-Spectrum Circuit
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1.2.5 Drift Compensation
3.3 Cs Sample Capacitors - Sensitivity
3.4 Power Supply
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. . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.6 Detection Integrator Confirmation
1.2.7 Spread-spectrum Operation
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3.5 PCB Layout and Construction
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1.2.8 Sync Mode
4 Specifications
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1.2.9 Low Power (LP) Mode
4.1 Absolute Maximum Specifications
4.2 Recommended Operating Conditions
4.3 AC Specifications
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1.2.10 Adjacent Key Suppression (AKS™)
1.2.11 Outputs
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1.2.12 Simplified Mode
4.4 DC Specifications
4.5 Signal Processing
4.6 Average Idd Curves
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1.3 Wiring
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2 Device Operation
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2.1 Start-up Time
4.7 LP Mode Typical Response Times
4.8 Mechanical - 32-QFN Package
4.9 Mechanical - 48-SSOP Package
4.10 Part Marking
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2.2 Option Resistors
2.3 One-per-key Output Mode
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2.4 Binary Coded Output Mode
2.5 DETECT Pin
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4.11 Moisture Sensitivity Level (MSL)
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2.6 SYNC/LP Pin
2.7 AKS™ Function Pins
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QT1081 R1.03/0107
1.2.6 Detection Integrator Confirmation
Detection Integrator (DI) confirmation reduces the effects of
noise on the QT1081. The ‘detect integrator’ mechanism
requires consecutive detections over a number of
measurement bursts for a touch to be confirmed and
indicated on the outputs. In a like manner, the end of a touch
(loss of signal) has to be confirmed over a number of
measurement bursts. This process acts as a type of
‘debounce’ against noise.
1 Overview
1.1 Differences With QT1080
The QT1081 is a general replacement device for the highly
popular QT1080. It has all of the same features as the older
device but differs in the following ways:
! Rsns resistors on each channel eliminated
! Up to 4x more sensitive for a given value of Cs
! Shorter burst lengths, less power for a given value of Cs
! ‘Burst B’ only mode for lower key counts with less power
A per-key counter is incremented each time the key has
exceeded its threshold and stayed there for a number of
measurement bursts. When this counter reaches a preset
limit the key is finally declared to be touched.
The QT1081 should be used over the QT1080 for new
For example, if the limit value is six, then the device has to
exceed its threshold and stay there for six measurement
bursts in succession without going below the threshold level,
before the key is declared to be touched. If on any
measurement burst the signal is not seen to exceed the
threshold level, the counter is cleared and the process has to
start from the beginning.
designs due to a simpler circuit, lower power and lower cost.
1.2 Parameters
1.2.1 Introduction
The QT1081 is an easy to use, eight-touch-key sensor IC
based on Quantum’s patented charge-transfer principles for
robust operation and ease of design. This device has many
advanced features which provide for reliable, trouble-free
operation over the life of the product.
In normal operation, both the start and end of a touch must
be confirmed for six measurement bursts. In a special ‘Fast
Detect‘ mode (available via jumper resistors), confirmation of
the start of a touch requires only two sequential detections,
but confirmation of the end of a touch is still six bursts.
1.2.2 Burst Operation
The device operates in ‘burst mode’. Each key is acquired
using a burst of charge-transfer sensing pulses whose count
varies depending on the value of the reference capacitor Cs
and the load capacitance Cx. In LP mode, the device sleeps
in an ultra-low current state between bursts to conserve
power. The keys’ signals are acquired using two successive
bursts of pulses:
Fast detect is only available when AKS is disabled.
1.2.7 Spread-spectrum Operation
The bursts operate over a spread of frequencies, so that
external fields will have minimal effect on key operation and
emissions are very weak. Spread-spectrum operation works
with the DI mechanism to dramatically reduce the probability
of false detection due to noise.
Burst A: Keys 0, 1, 4, 5
Burst B: Keys 2, 3, 6, 7
1.2.8 Sync Mode
Bursts always operate in A-B sequence.
The QT1081 features a Sync mode to allow the device to
slave to an external signal source, such as a mains signal
(50/60Hz), to limit interference effects. This is performed
using the SYNC/LP pin. Sync mode operates by triggering
two sequential acquire bursts, in sequence A-B from the Sync
signal. Thus, each Sync pulse causes all eight keys to be
acquired.
1.2.3 Self-calibration
On power-up, all eight keys are self- calibrated within 300
milliseconds (typical) to provide reliable operation under
almost any conditions.
1.2.4 Autorecalibration
The device can time out and recalibrate each key
independently after a fixed interval of continuous touch
detection, so that the keys can never become ‘stuck on’ due
to foreign objects or other sudden influences. After
recalibration the key will continue to function normally. The
delay is selectable to be either 10s, 60s, or infinite (disabled).
1.2.9 Low Power (LP) Mode
The device features an LP mode for microamp levels of
current drain with a slower response time, to allow use in
battery operated devices. On touch detection, the device
automatically reverts to its normal mode and asserts the
DETECT pin active to wake up a host controller. The device
remains in normal, full acquire speed mode until requested to
return to LP mode.
The device also autorecalibrates a key when its signal
reflects a sufficient decrease in capacit ance. In this case the
device recalibrates after ~2 seconds so as to recover normal
operation quickly.
When four or fewer keys are required, current drain in LP
mode can be further reduced by choosing appropri ate
channels on the QT1081.
1.2.5 Drift Compensation
Drift compensation operates to correct the reference level of
each key slowly but automatically over time, to suppress false
detections caused by changes in temperature, humidity, dirt
and other environmental effects.
1.2.10 Adjacent Key Suppression (AKS™)
AKS™ is a Quantum-patented feature that can be enabled
via resistor strap option. AKS works to prevent multiple keys
from responding to a single touch, a common complaint about
capacitive touch panels. This can happen with closely spaced
keys, or with control surfaces that have water films on them.
The drift compensation is asymmetric; in the increasing
capacitive load direction the device drifts more slowly than in
the decreasing direction. In the increasing direction, the rate
of compensation is one count of signal per 2 seconds; in the
opposing direction, it is one count every 500ms.
AKS operates by comparing signal strengths from keys within
a group of keys to suppress touch detections from those that
have a weaker signal change than the dominant one.
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QT1081 R1.03/0107
The QT1081 has two different AKS groupings of keys,
selectable via option resistors. These groupings are:
1.2.11 Outputs
There are two output modes: one-per-key, and binary coded.
" AKS operates in two groups of four keys.
" AKS operates over all eight keys.
One-per-key output: In this mode there is one output pin per
key. This mode has two output drive options, push-pull and
open-drain. The outputs can also be made either active-high
or active-low. These options are set via external configuration
resistors.
These two modes allow the designer to provide AKS while
also providing for shift or function operations.
If AKS is disabled, all keys can operate simultaneously.
Binary coded output: In this mode, three output lines encode
for one possible key in detect. If more than one key is
detecting, only the first one touched will be indicated.
1.2.12 Simplified Mode
To reduce the need for option resistors, the simplified
operating mode places the part into fixed settings with only
the AKS feature being selectable. LP mode is also possible in
this configuration. Simplified mode is suitable for most
applications.
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QT1081 R1.03/0107
1.3 Wiring
Table 1.1 Pinlist
Function
32-QFN 48-SSOP
Name
Type
Notes
If Unused
Pin
Pin
1
-
2
3
33
34
35
36
SS
n/c
/RST
Vdd
OD
-
I
Spread spectrum
Spread spectrum drive
Leave open
Active low reset
100K resistor to Vss
-
Vdd
-
-
Reset input
Power
Pwr
+2.8 ~ +5.0V
Resistor to Vdd and optional
spread spectrum RC network
4
5
37
OSC
n/c
I
Oscillator
-
-
38, 39, 40,
41, 42
-
Leave open
-
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin and
mode select
To Cs0 and/or
option resistor
To Cs0 + Key
To Cs1 and/or
option resistor*
To Cs1 + Key
To Cs2 and/or
option resistor*
To Cs2 + Key
To Cs3 and/or
option resistor*
To Cs3 + Key
To Cs4 and/or
option resistor*
To Cs4 + Key
To Cs5 and/or
option resistor*
To Cs5 + Key
To Cs6 and/or
option resistor*
To Cs6 + Key and/or
mode resistor†
6
43
44
45
46
47
48
1
SNS0
SNS0K
SNS1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Option resistor
7
Open
Open or
option resistor*
Open
Open or
option resistor*
Open
Open or
option resistor*
Open
Open or
option resistor*
Open
Open or
option resistor*
Open
8
9
SNS1K
SNS2
10
11
12
13
14
15
16
17
18
SNS2K
SNS3
2
SNS3K
SNS4
3
4
SNS4K
SNS5
5
6
SNS5K
SNS6
Open or
option resistor*
7
Open or
19
20
8
9
SNS6K
SNS7
I/O
I/O
mode resistor†
Open or mode
resistor† or option
resistor*
Sense pin and mode To Cs7 and/or mode resistor†
or option select
or option resistor*
To Cs7 + Key
Leave open
21
-
10
SN7K
n/c
I/O
-
Sense pin
-
Open
11, 12, 13,
14, 15, 16
-
22
-
23
24
-
25
26
27
28
29
17
18, 19, 20
21
22
23, 24
25
Vss
n/c
Pwr
-
I
O/OD
-
O/OD
O/OD
O/OD
O/OD
O/OD
Ground
0V
-
-
-
Sync In or LP In
Detect Status
-
Leave open
SYNC/LP‡
DETECT
n/c
Rising edge sync or LP pulse
Active = any key in detect
Leave open
Also, binary coded output 0
Also, binary coded output 1
Also, binary coded output 2
Vdd or Vss
Open
-
Open
Open
Open
Open
Open
OUT_0
OUT_1
OUT_2
OUT_3
OUT_4
Out 0
Out 1
Out 2
Out 3
26
27
28
29
Out 4
In binary coded mode, these
pins are clamped internally to
Vss
30
31
32
30
31
32
OUT_5
OUT_6
OUT_7
O/OD
O/OD
O/OD
Out 5
Out 6
Out 7
Open
Open
Open
Pin Type
I
CMOS input only
CMOS I/O
CMOS push-pull output
CMOS open drain output
CMOS push pull or open-drain output (option selected)
Power / ground
I/O
O
OD
O/OD
Pwr
Notes
† Mode resistor is required only in Simplified mode (see Figure 1.2)
* Option resistor is required only in Full Options mode (see Figure 1.1)
‡ Pin is either Sync or LP depending on options selected (functions SL_0, SL_1, see Figure 1.1)
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QT1081 R1.03/0107
Figure 1.1 Connection Diagram - Full Options; Shown for 32-QFN Package
VDD
+2.8 ~ +5V
Voltage Reg
Vunreg
* Note: one bypass capacitor to be tightly wired
between Vdd and Vss. Follow manufacturer’s
recommendations for input and output capacitors.
*4.7uF
*4.7uF
*100nF
Keep these parts
close to the IC
Keep these parts
close to the IC
1nF
11
1M
2
3
MOD_1
12
VDD
/RST
Vdd / Vss
SNS3
SNS2K
SNS2
KEY 2
KEY 1
10K
SNS2
C
S2
S1
S0
C
S3
1nF
1M
R
R
SNS3
13
10
SNS3K
1M
KEY 3
KEY 4
MOD_0
10K
Vdd / Vss
10K
SNS1
1nF
C
9
8
POL
Vdd / Vss
SNS1K
SNS1
14
15
R
SNS4
1nF CS4
1M
R
SNS4
AKS_1
Vdd / Vss
SNS4K
1nF
C
7
6
10K
SNS0K
SNS0
KEY 0
1M
OUT_D
10K
SNS0
R
16
Vdd / Vss
SNS5
1M
AKS_0
1nF
Vdd / Vss
R
SNS5
Recommended Rb1, Rb2 Values
SNS5K
VDD
KEY 5
KEY 6
KEY 7
Rb1 Rb2
Vdd Range
2.8 ~ 3.59V 12K
3.6 ~ 5V
10K
22K
27K
1M
SL_0
Vdd / Vss
Rb1
15K
18
19
SNS6
The required value of spread-spectrum capacitor CSS
will vary according to the lengths of the acquire bursts,
see Section 3.2. A typical value of CSS is 100nF.
4
QT1081
OSC
1nF
R
SNS6
SNS6K 32-QFN
Rb2
10K
C
SS
1M
1
SL_1
Vdd / Vss
SS
OUT_7
OUT_6
OUT_5
OUT_4
OUT_3
OUT_2
OUT_1
OUT_0
20
21
SNS7
32
31
30
29
28
27
26
25
OUT_7
OUT_6
OUT_5
OUT_4
OUT_3
OUT_2
OUT_1
OUT_0
C
S7
1nF
R
SNS7
10K
SNS7K
22
23
24
VSS
SYNC or LP IN
DETECT OUT
SYNC/LP
DETECT
Binary coded
output mode
Table 1.2
AKS / Fast-Detect Options
AKS_1
Vss
Vss
Vdd
Vdd
AKS_0
Vss
Vdd
Vss
Vdd
AKS MODE
Off
Off
On, in 2 groups
On, global
FAST-DETECT
Off
Enabled
Off
Off
Table 1.3
Max On-Duration
MOD_1
Vss
Vss
MOD_0
Vss
Vdd
MAX ON-DURATION MODE
10 seconds (nom) to recalibrate
60 seconds (nom) to recalibrate
Infinite (disabled)
Vdd
Vss
Vdd
Vdd
(reserved)
Table 1.4
Polarity and Output
OUT_D
Vss
Vss
Vdd
Vdd
POL
Vss
Vdd
Vss
Vdd
OUT_n, DETECT PIN MODE
Binary coded, active high, push-pull
One-per-key, active low, open-drain
One-per-key, active high, push-pull
One-per-key, active low, push-pull
Table 1.5
SYNC/LP Function
SL_1
Vss
Vss
Vdd
Vdd
SL_0
Vss
Vdd
Vss
SYNC/LP PIN MODE
Sync
LP mode: 100ms nom response time
LP mode: 180ms nom response time
LP mode: 340ms nom response time
Vdd
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QT1081 R1.03/0107
Figure 1.2 Connection Diagram - Simplified Mode; Shown for 32-QFN
VDD
+2.8 ~ +5V
Voltage Reg
Vunreg
* Note: one bypass capacitor to be tightly wired
between Vdd and Vss. Follow manufacturer’s
recommendations for input and output capacitors.
*4.7uF
*100nF
*4.7uF
Keep these parts
close to the IC
Keep these parts
close to the IC
2
3
R
SNS2
VDD
/RST
1nF
11
10
9
12
1nF
SNS2K
SNS2
SNS3
KEY 2
KEY 1
KEY 0
R
R
SNS3
10K
C
S3
13
C
S2
S1
S0
SNS3K
SNS4
KEY 3
KEY 4
KEY 5
RSNS1
10K
1nF
1nF
SNS1K
SNS1
SNS4
10K
8
C
S4
15
C
SNS4K
SNS5
RSNS0
1nF
10K
7
1nF 16
SNS0K
SNS0
RSNS5
10K
6
17
C
S5
C
SNS5K
10K
18
19
AKS_0
Vdd / Vss
1nF
S6
SNS6
R
SNS6
10K
1M
C
SNS6K
KEY 6
VDD
Rb1
Recommended Rb1, Rb2 Values
Vdd Range
Rb1 Rb2
SMR
1M
2.8 ~ 3.59V 12K
3.6 ~ 5V 15K
The required value of spread-spectrum capacitor CSS
will vary according to the lengths of the acquire bursts,
see Section 3.2. A typical value of CSS is 100nF.
22K
27K
4
1
OSC
20
21
QT1081
32-QFN
Rb2
SNS7
1nF
S7
R
SNS7
10K
C
KEY 7
SNS7K
C
SS
SS
OUT_7
OUT_6
OUT_5
OUT_4
OUT_3
OUT_2
OUT_1
OUT_0
32
31
30
29
28
27
26
25
OUT_7
OUT_6
OUT_5
OUT_4
OUT_3
OUT_2
OUT_1
OUT_0
22
VSS
23
24
LP IN
SYNC/LP
DETECT
DETECT OUT
Table 1.6
AKS Resistor Options
AKS_0
Vss
Vdd
AKS MODE
Off
On, global
FAST-DETECT
Enabled
Off
Table 1.7
Functions in Simplified Mode
Function
Parameter
Output Drive, Polarity
SYNC/LP pin
Max on-duration delay
Detect Pin
One-per-key outputs, push-pull, active high
180ms nom LP function; sync not available
60 seconds (nom)
Active high on any detect
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QT1081 R1.03/0107
2.5 DETECT Pin
2 Device Operation
2.1 Start-up Time
After a reset or power-up event, the device requires 300ms to
initialize, calibrate, and start operating normally. Keys will
work properly once all keys have been calibrated after reset.
DETECT represents the functional logical-OR of all eight
keys. DETECT can be used to wake up a battery-operated
product upon human touch.
DETECT is also required to indicate to a host when the binary
coded output pins (in that mode) are showing an active key.
While DETECT is active, the binary coded outputs should be
read at least twice along with DETECT to make sure that the
code was not transitioning between states, to prevent a false
reading.
2.2 Option Resistors
The option resistors are read on power-up only; it is not
possible to change the operating mode of the device once it
has powered up. There are two primary option mode
configurations: Full, and simplified.
The output polarity and drive of DETECT are governed
according to Table 1.4.
Full options mode: Eight 1M✡ option resistors are required
as shown in Figure 1.1. All eight resistors are mandatory.
2.6 SYNC/LP Pin
When full options are in use, the SYNC/LP pin function is
selected according to the SL_0 and SL_1 resistor
connections as given in Table 1.5. When the QT1081 is in
sync mode the pin acts as a SYNC input; when the QT1081 is
in LP mode the pin acts as an LP input.
Simplified mode: A 1M✡ resistor should be connected from
SNS6K to SNS7. In simplified mode, only one additional 1M✡
option resistor is required for the AKS feature (Figure 1.2).
Note that the presence and connection of option resistors will
affect the required values of Cs; this effect will be especially
noticeable if the Cs values are under 22nF. Cs values should
be adjusted for optimal sensitivity after the option resistors
are connected.
When simplified options are in use, the QT1081 is always in
LP mode and the SYNC/LP pin acts as an LP input.
Sync mode: Sync mode allows the designer to synchronize
acquire bursts to an external signal source, such as mains
frequency (50/60 Hz) to suppress interference. It can also be
used to synchronize two QT parts which operate near each
other, so that only one part generates acquire bursts at a time
and hence they do not cross-interfere.
2.3 One-per-key Output Mode
One-per-key output mode is selected via option resistors, as
shown in Table 1.4.
In this mode, there is one output for each key; each is active
when a touch is confirmed on the corresponding electrode.
Unused OUT pins should be left open.
The SYNC input of the QT1081 is positive edge triggered.
Following each rising edge the QT1081 will generate a pair of
acquire bursts in A-B sequence; this operation is shown in
Figure 2.1.
If AKS is off, it is possible for all OUT pins to be active at the
same time.
Figure 2.1 Acquire Bursts in A-B Sequence
Circuit of Figure 1.1: OUT polarity and drive are governed
by the resistor connections to Vdd or Vss according to
Table 1.4. The drive can be either push-pull or open-drain,
active low or high.
SYNC
Circuit of Figure 1.2: In this simplified circuit, the OUT pins
are active high, push-pull only.
Burst A
Burst B
2.4 Binary Coded Output Mode
This mode is useful to reduce the number of connections to a
host controller, at the expense of only being able to report
one active key at a time. Note that in global AKS mode
(Section 2.7), only one key can report active at a time
anyway. Binary coded mode is selected via option resistors,
as shown in Table 1.4.
If the SYNC input does not change level for ~150ms, the
QT1081 will free-run, generating a continuous stream of
acquire bursts A-B-A-B-A-... . While the QT1081 is in free-run
operation, a rising edge on the SYNC input will return the
QT1081 to synchronised operation.
In this mode, a key detection is registered as a binary code
on pins OUT_2, OUT_1 and OUT_0, with possible values
from 000 to 111. In practice, four lines are required to read
the code, unless key 0 is not implemented; the output code
000 can mean either ‘nothing detecting’ or ‘key 0 is detecting’.
The fourth required line (if all eight keys are implemented) is
the DETECT signal, which is active-high when any key is
active.
Note that the SYNC input must remain at one level (high or
low) for >150µs to guarantee that the QT1081 will recognise
that level.
Low Power LP Mode: LP mode allows the device to be
switched between full speed operation (20ms typical
response time and normal power consumption), and Low
Power operation (low average power consumption but an
increased maximum response time) according to the needs of
the application. There are three maximum response time
settings for low power operation: 100ms, 180ms, and 340ms
nominal; the response time setting is determined by option
resistors SL_1 and SL_0; see Table 1.5. Slower response
times result in a lower average power drain.
The first key touched always wins and shows its output. Keys
that come afterwards are hidden until the currently reported
key has stopped detecting, in which case the code will
change to a latent key.
Circuit of Figure 1.1: OUT polarity and drive can only be
push-pull and active high.
Operation in low power mode is governed by the state of the
LP input and whether at least one key has a confirmed touch.
Circuit of Figure 1.2: Binary coded not available.
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QT1081 R1.03/0107
If the LP input is at a constant low level, then the QT1081 will
remain in full speed operation (20ms typical response time
and normal power consumption), as in Figure 2.2.
Note that the LP input must remain at one level (high or low)
for >150µs to guarantee that the QT1081 will recognise that
level.
Optimization of LP Mode: For the lowest possible power
consumption when up to four keys are required, all keys
should be connected to QT1081 channels that are measured
during acquire burst B (i.e. k2, k3, k6 and k7). If this is done
the QT1081 automatically selects optimized LP operation,
which gives a significantly lower power consumption than
would be achieved if the burst A channels were used.
Figure 2.2 Full Speed Operation
touch
LP pin
Optimized LP operation is identical to the standard LP
operation in all other ways; it is controlled as described
above.
bursts
full speed operation
2.7 AKS™ Function Pins
If the LP input is at a constant high level, then the QT1081 will
enter low power operation whenever it is not detecting a
touch. It will switch automatically to full speed operation while
there is a touch, and revert to low power operation at the end
of the touch. This is shown in Figure 2.3.
The QT1081 features an adjacent key suppression (AKS)
function with two modes. Option resistors act to set this
feature according to Tables 1.2 and 1.6. AKS can also be
disabled, allowing any combination of keys to become active
at the same time. When operating, the modes are:
Figure 2.3 Low Power/Full Speed Operation
Global: AKS functions operates across all eight keys. This
means that only one key can be active at any one time.
touch
e
Groups: AKS functions among two groups of four keys:
0-1-4-5 and 2-3-6-7. This means that up to two keys can be
active at any one time.
LP pin
bursts
In Group mode, keys in one group have no AKS interaction
with keys in the other group.
Note that in Fast Detect mode, AKS can only be off.
low power
full speed
low power
2.8 MOD_0, MOD_1 Inputs
While there is no touch, if the LP input is driven high then low,
the QT1081 will enter low power operation, as described
above, and remain in low power operation when LP is taken
low. When there is a touch the QT1081 will switch
automatically to full speed operation. At the end of the touch
the choice of operation depends on the state of the LP input.
This is shown in Figures 2.4 and 2.5 - the first with the LP pin
being low at the end of the touch, and the second with the LP
pin being high at the end of the touch.
In full option mode, MOD_0 and MOD_1 resistors are used to
set the ‘Max On-Duration’ recalibration timeouts. If a key
becomes stuck on for a lengthy duration of time, this feature
will cause an automatic recalibration event of that specific key
once the specified on-time has been exceeded. Settings of
10s, 60s, and infinite are available.
The Max On-Duration feature operates on a key-by-key basis;
when one key is stuck on, its recalibration has no effect on
other keys.
Figure 2.4 LP Pin Low at End of Touch
The logic combination on the MOD option pins sets the
timeout delay (see Table 1.3).
touch
e
Simplified mode MOD timing: In simplified mode, the max
on-duration is fixed at 60 seconds.
LP pin
bursts
2.9 Fast Detect Mode
In many applications, it is desirable to sense touch at high
speed. Examples include scrolling ‘slider’ strips or ‘Off’
buttons. It is possible to place the device into a ‘Fast Detect’
mode that usually requires under 10ms to respond. This is
accomplished internally by setting the Detect Integrator to
only two counts, i.e. only two successive detections are
required to detect touch.
low power
full speed
Figure 2.5 LP Pin High at End of Touch
In LP mode, ‘Fast’ detection will not speed up the initial delay
(which could be up to 340ms nominal depending on the
option setting). However, once a key is detected the device is
forced back into normal speed mode. It will remain in this
faster mode until requested to return to LP mode.
touch
LP pin
bursts
When used in a ‘slider’ application, it is normally desirable to
run the keys without AKS.
low power
full speed
low power
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QT1081 R1.03/0107
In both normal and ‘Fast’ modes, the time required to process
a key release is the same. It takes six sequential
confirmations of nondetection to turn a key off.
The other option features are fixed as follows:
OUT_n, DETECT Pins: Push-pull, active high,
one-per-key outputs
Fast Detect mode can be enabled as shown in Tables 1.2
and 1.6.
SYNC/LP Function: LP mode, ~180ms response time
Max On-Duration: 60 seconds
See Tables 1.6 and 1.7.
2.10 Simplified Mode
A simplified operating mode which does not require the
majority of option resistors is available. This mode is set by
connecting a resistor labelled SMR between pins SNS6K and
SNS7 (see Figure 1.2).
2.11 Unused Keys
Unused keys should be disabled by removing the
corresponding Cs, Rs, and Rsns components and connecting
SNS pins as shown in the ‘Unused’ column of Table 1.1.
Unused keys are ignored and do not factor into the AKS
function (Section 2.7).
In this mode there is only one option possible - AKS enable or
disable. When AKS is disabled, Fast Detect mode is enabled;
when AKS is enabled, Fast Detect mode is off.
AKS in this mode is Global only (i.e. operates across all
functioning keys).
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QT1081 R1.03/0107
In both cases the exact value depends on the precise circuit
component values and timing. Vdd variations can shift the
center frequency and spread slightly.
3 Design Notes
3.1 Oscillator Frequency
The QT1081’s internal oscillator runs from an external resistor
network connected to the OSC and SS pins, as shown in
Figures 1.1 and 1.2, to achieve spread-spectrum operation. If
spread-spectrum mode is not required, the OSC pin should
be connected to Vdd with an 18KΩ one percent resistor.
3.3 Cs Sample Capacitors - Sensitivity
The Cs sample capacitors accumulate the charge from the
key electrodes and determine sensitivity. Higher values of Cs
make the corresponding sensing channel more sensitive. The
values of Cs can differ for each channel, permitting
Under different Vdd voltage conditions the resistor network
(or the solitary 18KΩ resistor) might require minor adjustment
to obtain the specified burst center frequency. The network
should be adjusted slightly so that the positive pulses on any
key are approximately 2.67µs wide in the ‘solitary 18KΩ
resistor’ mode, or 2.87µs wide at the beginning of a burst with
the recommended spread-spectrum circuit (see next section).
differences in sensitivity from key to key or to balance
unequal sensitivities. Unequal sensitivities can occur due to
key size and placement differences and stray wiring
capacitances. More stray capacitance on a sense trace will
desensitize the corresponding key; increasing the Cs for that
key will compensate for the loss of sensitivity.
The Cs capacitors can be virtually any plastic film or low to
medium-K ceramic capacitor. The normal Cs range is 1nF to
50nF depending on the sensitivity required; larger values of
Cs require better quality to ensure reliable sensing. In certain
circumstances the normal Cs range may be exceeded, hence
the different values in Section 4.2. Acceptable capacitor types
for most uses include PPS film, polypropylene film, and NP0
and X5R / X7R ceramics. Lower grades than X5R or X7R are
not recommended.
In practice, the pulse width has little effect on circuit
performance if it varies in the range of 2µs to 3.3µs. The only
effects seen will be proportional variations in Max
On-Duration and non-LP mode response times.
3.2 Spread-Spectrum Circuit
The QT1081 offers the ability to spectrally spread its
frequency of operation to heavily reduce susceptibility to
external noise sources and to limit RF emissions. The SS pin
is used to modulate an external passive RC network that
modulates the OSC pin. OSC is the main oscillator current
input. The circuit is shown in both Figures 1.1 and 1.2.
The required values of Cs can be noticeably affected by the
presence and connection of the option resistors (see
Section 2.2). Cs values should be adjusted for optimal
sensitivity after the option resistors are connected.
The resistors Rb1 and Rb2 should be changed depending on
Vdd. As shown in Figures 1.1 and 1.2, two sets of values are
recommended for these resistors depending on Vdd. The
power curves in Section 4.6 also show the effect of these
resistors.
3.4 Power Supply
The power supply can range from 2.8 to 5.0 volts. If this
fluctuates slowly with temperature, the device will track and
compensate for these changes automatically with only minor
changes in sensitivity. If the supply voltage drifts or shifts
quickly, the drift compensation mechanism will not be able to
keep up, causing sensitivity anomalies or false detections.
The circuit can be eliminated, if it is not desired, by using an
18KΩ resistor from OSC to Vdd to drive the oscillator, and
connecting SS to Vss with a 100KΩ resistor.
The power supply should be locally regulated, using a
three-terminal device, to between 2.8V and 5.0V. If the supply
is shared with another electronic system, care should be
taken to ensure that the supply is free of digital spikes, sags
and surges which can cause adverse effects. It is not
recommended to include a series inductor in the power
supply to the QT1081.
The spread-spectrum RC network will need to be adjusted
according to the burst lengths. The sawtooth waveform
observed on SS should reach a crest height as follows:
Vdd >= 3.6V:17 percent of Vdd
Vdd < 3.6V: 20 percent of Vdd
The Css capacitor connected to the SS pin (Figures 1.1 and
1.2) should be adjusted so that the waveform approximates
the above amplitude, ±10 percent, during normal operation in
the target circuit. Where the bursts are of differing lengths,
the adjustment should be done for the longer burst . If this is
done, the circuit will give a spectral modulation of 12-15
percent.
For proper operation a 0.1µF or greater bypass capacitor
must be used between Vdd and Vss; the bypass capacitor
should be routed with very short tracks to the device’s Vss
and Vdd pins.
3.5 PCB Layout and Construction
Refer to Quantum application note AN-KD02 for information
related to layout and construction matters.
Use of the spread-spectrum facility has the following effect on
Idd:
•
•
Full speed operation: Idd changes within ±10 percent.
Idd increases by up to 15 percent.
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QT1081 R1.03/0107
4 Specifications
4.1 Absolute Maximum Specifications
Operating temperature, Ta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85oC
Storage temp, Ts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50oC to +125oC
Vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0V
Max continuous pin current, any control or drive pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Short circuit duration to ground or Vdd, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite
Voltage forced onto any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V (Vdd + 0.3) Volts
4.2 Recommended Operating Conditions
Operating temperature, Ta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40o to +85oC
V
DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.8 to +5.0V
Short-term supply ripple+noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mV/s
Long-term supply stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mV
Cs range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1nF to 100nF
Cx range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 50pF
4.3 AC Specifications
Vdd = 5.0, Ta = recommended, Cx = 5pF, Cs = 1nF; circuit of Figure 1.1
Parameter Description
Min
Typ
Max
Units
Notes
Trc
Fc
Recalibration time
150
132
15
ms
kHz
%
Burst center frequency
Burst modulation, percent
Fm
Total deviation
Pulses appear 33 percent longer when
viewed on an oscilloscope.
Tpc
Sample pulse duration
2
µs
Tsu
Tbd
Tdf
Tdn
Tdl
Start-up time from cold start
Burst duration
300
2.5
6
ms
ms
ms
ms
ms
ms
Both bursts together
Response time - Fast mode
Response time - Normal mode
Response time - LP mode
Release time - all modes
20
180
20
180ms LP setting
End of touch
Tdr
4.4 DC Specifications
Vdd = 5.0, Ta = recommended, Cx = 5pF, Cs = 1nF; circuit of Figure 1.1 unless noted
Parameter Description
Min
Typ
Max
Units
Notes
5.6
3.6
2.3
1.6
@ Vdd = 5.0
@ Vdd = 4.0
@ Vdd = 3.3
@ Vdd = 2.8
Average supply current,
normal mode*
I
DDN
8
mA
I
DDL
Average supply current, LP
mode*
22
15
@ Vdd = 3.3V; 340ms LP mode
@ Vdd = 2.8V; 340ms LP mode
µA
µA
Average supply current, LP
mode, keys on burst B only
15
10
@ Vdd = 3.3V
@ Vdd = 2.8V
V
DDS
Average supply turn-on slope
Low input logic level
High input logic level
Low output voltage
100
V/s
V
@ Vdd = 2.8V
V
IL
0.7
0.5
±1
V
HL
3.5
V
V
OL
V
7mA sink
V
OH
High output voltage
Vdd-0.5
V
2.5mA source
I
IL
Input leakage current
Acquisition resolution
µA
bits
A
R
8
*No spread spectrum circuit; Rosc = 18KΩ
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QT1081 R1.03/0107
4.5 Signal Processing
Vdd = 5.0, Ta = recommended, Cx = 5pF, Cs = 1nF
Description
Value
Units
Notes
Detection threshold
10
2
counts
counts
counts
secs
Threshold for increase in Cx load
Detection hysteresis
Anti-detection threshold
Anti-detection recalibration delay
6
Threshold for decrease of Cx load
2
Time to recalibrate if Cx load has exceeded anti-detection
threshold
Detect Integrator filter, normal mode
Detect Integrator filter, ‘fast’ mode
Max On-Duration
6
2
samples
samples
secs
Must be consecutive or detection fails
Must be consecutive or detection fails
Option pin selected
10, 60, ∞
2,000
500
Normal drift compensation rate
Anti-drift compensation rate
ms/level
ms/level
Towards increasing Cx load
Towards decreasing Cx load
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QT1081 R1.03/0107
4.6 Average Idd Curves
All Idd curves are average values, under the following conditions: Cx = 5pF , Ta = 20oC, Rosc = 18KΩ; no spread-spectrum
circuit. Refer to page 9 for more information about optimization of LP modes.
Full speed operation
QT1081, average Idd (full speed operation)
6.0
5.0
Vdd=5V
4.0
Vdd=4V
3.0
Vdd=3.3V
Vdd=2.8V
2.0
1.0
0.0
0
1
2
3
4
5
6
burst length (ms)
Low Power operation (optimized - only burst B in use)
QT1081, average Idd (100ms optimized LP operation)
QT1081, average Idd (180ms optimized LP operation)
400.0
800.0
600.0
300.0
200.0
100.0
0.0
Vdd=5V
Vdd=5V
Vdd=4V
Vdd=4V
400.0
Vdd=3.3V
Vdd=2.8V
Vdd=3.3V
Vdd=2.8V
200.0
0.0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
burst length (ms)
burst length (ms)
QT1081, average Idd (340ms optimized LP operation)
200.0
150.0
100.0
50.0
0.0
Vdd=5V
Vdd=4V
Vdd=3.3V
Vdd=2.8V
0
1
2
3
4
5
6
burst length (ms)
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QT1081 R1.03/0107
Low Power operation (non-optimized)
QT1081, average Idd (100ms LP operation)
QT1081, average Idd (180ms LP operation)
800.0
600.0
400.0
200.0
0.0
400.0
300.0
200.0
100.0
0.0
Vdd=5V
Vdd=5V
Vdd=4V
Vdd=4V
Vdd=3.3V
Vdd=2.8V
Vdd=3.3V
Vdd=2.8V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
burst length (ms)
burst length (ms)
QT1081, average Idd (340ms LP operation)
200.0
150.0
100.0
50.0
Vdd=5V
Vdd=4V
Vdd=3.3V
Vdd=2.8V
0.0
0
1
2
3
4
5
6
burst length (ms)
4.7 LP Mode Typical Response Times
QT1081 Response Time (100ms LP operation)
QT1081 Response Time (180ms LP operation)
130
240
230
220
210
200
190
180
170
160
125
120
115
110
105
100
95
90
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Vdd
Vdd
QT1081 Response Time (340ms LP operation)
430
410
390
370
350
330
310
290
2.5
3
3.5
4
4.5
5
5.5
Vdd
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QT1081 R1.03/0107
4.8 Mechanical - 32-QFN Package
Corner tie
bar
Exposed
Centre
Pad
PIN 1
Depending upon the IC assembly supplier, the package may
be slightly different from that depicted above. See the
magnified areas for the main difference between the ICs.
Dimensions In Millimeters
Symbol Minimum Nominal Maximum
A
A1
b
C
D
D2
E
E2
e
L
y
0.70
0.00
0.18
-
4.90
3.05
4.90
3.05
-
-
0.95
0.05
0.32
-
5.10
3.65
5.10
3.65
-
Dimension L1 represents terminal pull-back from the package
edge. Where terminal pull-back exists, only the upper half of
the lead is visible on the package edge due to half etching of
the leadframe.
0.02
0.25
0.20 REF
5.00
The corner tie bar is connected internally to the exposed
central pad.
-
5.00
-
0.50
0.40
-
0.30
0.00
0.00
0.50
0.075
0.10
L1
-
Note that there is no functional requirement for the large pad on the underside of this package to be
soldered. If the final application requires this area to be soldered for mechanical reasons, the pad to
which it is soldered must be isolated and contained under the footprint only.
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QT1081 R1.03/0107
4.9 Mechanical - 48-SSOP Package
A
B
C
G
J
H
D
a
F
E
All dimensions in millimeters
A
10.03
10.67
B
7.39
7.59
C
0.20
0.30
D
2.16
2.51
E
F
0.10
0.25
G
15.57
16.18
H
0.10
0.30
J
0.64
0.89
a
Min
Max
0o
8o
0.635
Typ
4.10 Part Marking
32-QFN
48-SSOP
QRG Part
No.
QRG
Revision
Code
QT1081
©QRG 1
YYWWG
run nr.
QT1081-IS48G
© QRG 73CD R1
QProxTM
<datecode>
DIMPLE
‘YY’ = Year of manufacture
‘WW’ = Week of manufacture
‘G’ = Green/RoHS Compliant
or ‘XX’ depending upon the
IC assembly supplier
Pin 1
Pin 1
Identification
'run nr.' = 6 Digit Run Number
(depending upon the IC assembly
supplier, this line may not appear)
4.11 Moisture Sensitivity Level (MSL)
MSL Rating
Peak Body Temperature
Specifications
IPC/JEDEC J-STD-020C
MSL3
260OC
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Copyright © 2006-2007 QRG Ltd. All rights reserved
Patented and patents pending
Corporate Headquarters
1 Mitchell Point
Ensign Way, Hamble SO31 4RF
Great Britain
Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 8045 3939
www.qprox.com
North America
651 Holiday Drive Bldg. 5 / 300
Pittsburgh, PA 15220 USA
Tel: 412-391-7367 Fax: 412-291-1015
The specifications set out in this document are subject to change without notice. All products sold and services supplied by QRG are subject to
QRG’s Terms and Conditions of sale and services. QRG patents, trademarks and Terms and Conditions can be found online at
http://www.qprox.com/about/legal.php. Numerous further patents are pending, one or more which may apply to this device or the applications
thereof.
QRG products are not suitable for medical (including lifesaving equipment), safety or mission critical applications or other similar purposes.
Except as expressly set out in QRG's Terms and Conditions, no licenses to patents or other intellectual property of QRG (express or implied)
are granted by QRG in connection with the sale of QRG products or provision of services. QRG will not be liable for customer product design
and customers are entirely responsible for their products and applications which incorporate QRG's products.
Development Team: John Dubery, Alan Bowens, Matthew Trend
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