EVAL-CONTROLBRD22 [ATMEL]
Software Selectable True Bipolar Input, 2-Channel, 12-Bit Plus Sign ADC; 软件可选的真双极性输入，双通道， 12位加符号位ADC
| 型号： | EVAL-CONTROLBRD22 |
| 厂家： | 
ATMEL |
| 描述： | Software Selectable True Bipolar Input, 2-Channel, 12-Bit Plus Sign ADC |
| 文件： | 总18页 (文件大小：844K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Software Selectable True Bipolar Input,
2-Channel, 12-Bit Plus Sign ADC
Preliminary Technical Data
AD7322*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
• 12-Bit Plus Sign SAR ADC
• True Bipolar Analog Inputs
• Software Selectable Input Ranges
1ꢀ0, ꢁ0, 2.ꢁ0, ꢀ to 1ꢀ0
• Two Analog Inputs with Channel Sequencer
• Single Ended, True Differential and Pseudo Differential
Capability.
• High Analog Input Impedance
• Low Power:- 6 mW
• Full Power Signal Bandwidth: >13 MHz
• Internal 2.ꢁ 0 Reference
• High Speed Serial Interface
• Power Down Modes
• 14-Lead TSSOP
• For 8 and 4 channel equivalent devices see AD7328 and
AD7324 respectively.
Figure 1.
The Serial clock frequency, SCLK, applied to the ADC will
determine the maximum throughput rate the ADC can operate
at. The SCLK signal is used as the conversion clock and also to
transfer data to and from the ADC. The Serial interface is
SPITM, QSPITM, MICROWIRETM and DSP compatible.
GENERAL DESCRIPTION
The AD7322 is a 2-Channel, 12-Bit Plus Sign, 1 MSPS
Successive Approximation ADC. The ADC has a high speed
serial interface that can operate at throughput rates up to 1
MSPS.
The AD7322 offers power down modes to reduce the power
consumption of the ADC at lower throughput rates.
The AD7322 can handle True Bipolar Analog input signals. The
Bipolar ranges are software selectable by programming the on
board Range Register. Bipolar input ranges include 1ꢀ0, ꢁ0,
2.ꢁ0. The AD7322 can also handle a ꢀ to 1ꢀ 0 uniploar input
range, which is also software selectable. Each analog input
channel can be independently programmed to one of the input
ranges by setting the appropriate bits in the Range Register.
PRODUCT HIGHLIGHTS
1. The AD7322 can accept True Bipolar Analog Input signals,
1ꢀ0, ꢁ0, 2.ꢁ0 and ꢀ to 1ꢀ0 unipolar signals.
2. The Two Analog Inputs can be configured as Two Single-
Ended inputs, One True Differential or One Pseudo Differential
Input. The AD7322 has high Impedance Analog Inputs.
The Analog Input Channels can be configured as Single-Ended,
Fully Differential or Pseudo Differential. Dedicated Control
Register bits are used to configure the Analog inputs. The
AD7322 contains a Channel Sequencer, allowing automatic
conversions between each analog input channel.
3. The AD7322 features a High Speed Serial Interface.
Throughput Rates up to 1 MSPS can be achieved on the
AD7322.
The ADC contains a 2.ꢁ0 Internal reference. The AD7322 also
allows for external Reference operation. If a 30 external
reference is applied to the REFIN/OUT pin, the ADC can
handle a True Bipolar 12 0 Analog input range. Minimum
0DD and 0SS supplies of 120 are required for this 12 0 input
range.
4. Low Power, 12 mW at maximum throughput rate of 1 MSPS.
* Patent Pending
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 91ꢀ6, Norwood, MA ꢀ2ꢀ62-91ꢀ6, U.S.A.
Tel: 781.329.47ꢀꢀ
Fax: 781.326.87ꢀ3
www.analog.com
© 2ꢀꢀ4 Analog Devices, Inc. All rights reserved.
AD7322
Preliminary Technical Data
TABLE OF CONTENTS
AD7322—Specifications.................................................................. 3
Absolute Maximum Ratings............................................................ 6
Pin Functional Descriptions ....................................................... 7
Terminology ...................................................................................... 8
Theory of Operation.....................................................................9
AD7322 Registers........................................................................... 12
Serial interface ................................................................................ 17
OUTLINE DIMENSIONS.................................................................. 18
RE0ISION HISTORY
Revision PrE: Preliminary 0ersion
Rev. PrE | Page 2 of 18
AD7322
Preliminary Technical Data
AD7322—SPECIFICATIONS1
Table 1. Unless otherwise noted, VDD = + 4.75V to +16.5V, VSS = -4.75V to –16.5V, VCC = 2.7V to 5.25V, VDRIVE = 2.7V to 5.25V, VREF
= 2.5V Internal/External, fSCLK = 20 MHz, fS = 1 MSPS TA = TMAX to TMIN
Parameter
Specification Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise Ratio (SNR) 2
FIN = 50 kHz Sine Wave
Differential Mode
Single-Ended /Pseudo Differential Mode
Differential Mode
Single-Ended/Pseudo Differential Mode
78
75
77
74
dB min
dB min
dB min
dB min
dB max
Signal to Noise + Distortion (SINAD)2
Total Harmonic Distortion (THD)2
-TBD
Peak Harmonic or Spurious Noise
(SFDR) 2
-TBD
dB max
Intermodulation Distortion (IMD) 2
Second Order Terms
Fa = 40.1 kHz, Fb = 41.5 kHz
-88
-88
10
dB typ
dB typ
ns max
ps typ
Third Order Terms
Aperature Delay2
Aperature Jitter2
50
Common Mode Rejection (CMRR)2
Channel-to-Channel Isolation2
Full Power Bandwidth2
TBD
-80
13
dB typ
dB typ
MHz typ
MHz typ
FIN = 400 kHz
@ 3 dB
@ 0.1 dB
1.5
DC ACCURACY
Resolution
12+Sign
±1.5
± 0.ꢀ5
±±
±0.5
±2
±0.±
±2
±0.±
±±
Bits
Integral Nonlinearity2
Differential Nonlinearity2
Offset Error3
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Guaranteed No Missing Codes to 13-Bits
Unipolar Range with Straight Binary output coding
Offset Error Match2
Gain Error2
Gain Error Match2
Positive Full-Scale Error2
Positive Full Scale Error Match2
Bipolar Zero Error2
Bipolar Range with Twos Complement Output Coding
Bipolar Zero Error Match2
Negative Full Scale Error2
Negative Full Scale Error Match2
ANALOG INPUT
±0.5
±2
±0.5
Input Voltage Ranges
(Programmed via Range Register)
±10V
±5V
±2.5V
0 to 10V
±10
8
11
1ꢀ
±
Volts
V
V
V
V
DD = +10V min , VSS = -10V min, VCC = 2.7V to 5.25V
DD = +5V min, VSS = -5V min, VCC = 2.7V to 5.25V
DD = +5V min, VSS = - 5V min, VCC = 2.7V to 5.25V
DD = +10V min, VSS = 0 V min, VCC = 2.7V to 5.25V
DC Leakage Current
Input Capacitance
nA max
pF typ
pF typ
pF typ
pF typ
When in Track, ±10V Range
When in Track, ±5V, 0 to 10V Range
When in Track, ±2.5V Range
When in Hold
REFERENCE INPUT/OUTPUT
Input Voltage Range
+2.5 to +3V
V min to
max
Input DC Leakage Current
Input Capactiance
±1
20
µA max
pF typ
Reference Output Voltage
Reference Temperature Coefficient
2.4ꢀ/2.51
25
Vmin/max
ppm/°C
max
Rev. PrE | Page 3 of 18
AD7322
Preliminary Technical Data
Parameter
Specification Units
Test Conditions/Comments
Reference Output Impedance
25
Ω typ
LOGIC INPUTS
Input High Voltage, VINH
Input High Voltage, VINL
Input Current, IIN
0.7*VDRIVE
0.3*VDRIVE
± 1
V min
V max
µA max
pF max
VIN = 0V or VCC
3
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance3
Output Coding
VDRIVE- 0.2V
V min
ISOURCE = 200 µA
ISINK = 200 µA
0.4
±1
10
Straight
Natural
Binary
V max
µA max
pF max
Coding bit set to 1 in Control Register
Coding bit set to 0 in Control Register
Two’s
Complement
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
800
150
150
1
ns max
ns max
ns max
MSPS max
1± SCLK Cycles with SCLK = 20 MHz
Sine Wave Input
Full Scale Step input
See Serial Interface section
Digital Inputs = 0V or VCC
See Table ꢁ
Throughput Rate
POWER REQUIREMENTS
VDD
4.75V/+1±.5V V min/max
VSS
VCC
-4.75V/1±.5V
2.7V / 5.25V
V min/max
V min/max
See Table ꢁ
See Table ꢁ
Normal Mode
IDD
ISS
ICC
200
200
2
µA max
µA max
mA max
Auto-Standby Mode
FSAMPLE = TBD
IDD
ISS
ICC
TBD
TBD
1.±
µA max
µA max
mA typ
Auto-Standby Mode
FSAMPLE = TBD
IDD
ISS
ICC
TBD
TBD
1
µA max
µA max
mA typ
Full Shutdown Mode
IDD
ISS
ICC
TBD
TBD
1
µA max
µA max
µA max
SCLK On or Off
POWER DISSIPATION
Normal Mode
12
mW max
VDD = +5V, VSS = -5V, VCC = 5V,
NOTES
1 Temperature ranges as follows: -40°C to +85°C
2 See Terminology
3 Guaranteed by Characterization
Specifications subject to change without notice.
Rev. PrE | Page 4 of 18
AD7322
Preliminary Technical Data
TIMING SPECIFICATIONS
Table 2. Unless otherwise noted, 0DD = +4.7ꢁ0 to + 16.ꢁ0, 0SS = -4.7ꢁ to –16.ꢁ0, 0CC =2.70 to ꢁ.2ꢁ, 0DRI0E=2.70 to ꢁ.2ꢁ, 0REF
=
2.ꢁ0 Internal/External, TA = TMAX to TMIN
Parameter
Limit at TMIN, TMAX Unit
Description
fSCLK
10
kHz min
20
MHz max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
µs max
µs max
tCONVERT
1±×tSCLK
50
TSCLK = 1/fSCLK
tQUIET
t1
CS
Minimum Time between End of Serial Read and Next Falling Edge of
10
CS
Minimum
Pulse width
to SCLK Setup Time
t2
10
CS
t3
20
CS
Delay from until DOUT Three-State Disabled
Data Access Time after SCLK Falling Edge.
SCLK Low Pulsewidth
t4
TBD
0.4tSCLK
0.4tSCLK
10
t5
t±
SCLK High Pulsewidth
t7
SCLK to Data Valid Hold Time
t8
25
SCLK Falling Edge to DOUT High Impedance
SCLK Falling Edge to DOUT High Impedance
DIN set-up time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power up from Auto Standby
10
tꢀ
TBD
5
t10
1
TBD
Power up from Full Shutdown/Auto Shutdown Mode
Figure 2. Serial Interface timing Diagram
Rev. PrE | Page 5 of 18
AD7322
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 3. TA = 25°C, unless otherwise noted
VDD to AGND, DGND
-0.3 V to +17.5 V
+0.3 V to –17.5 V
-0.3V to +7V
VSS to AGND, DGND
VCC to AGND, DGND
VDRIVE to VCC
-0.3 V to VCC + 0.3V
-0.3 V to +7V
-0.3 V to +0.3 V
TBD
VDRIVE to AGND, DGND
AGND to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to GND
REFIN to AGND
Input Current to Any Pin Except Supplies2
Operating Temperature Range
Storage Temperature Range
Junction Temperature
TSSOP Package
-0.3 V to +7 V
-0.3 V to VDRIVE +0.3V
-0.3 V to VCC +0.3V
±10mA
-40°C to +85°C
-±5°C to +150°C
+150°C
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Reflow (10 – 30 sec)
143 °C/W
45 °C/W
+235(-0/+5)°C
TBD
ESD
Rev. PrE | Page ± of 18
AD7322
Preliminary Technical Data
Pin Functional Descriptions
14 SCLK
13 DGND
CS
DIN
1
2
3
4
5
6
7
12
DGND
AGND
AD7322
DOUT
V
11
10
9
DRIVE
V
CC
REFIN/OUT
TOP VIEW
(Not to
Scale)
V
V
SS
DD
V
1
V
0
8
IN
IN
Figure 3. AD7322 Pin Configuration TSSOP
Table 4. AD7324 Pin Function Descriptions
Pin
Pin
Description
Mnemonic Number
SCLK
DOUT
14
12
Serial Clock. Logic Input. A serial clock input provides the SCLK used for accessing the data
from the AD7322. This clock is also used as the clock source for the conversion process.
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream.
The bits are clocked out on the falling edge of the SCLK input and 1± SCLKs are required to
access the data. The data stream consists of two leading zeros, one channel identification bit, a
Sign bit followed by 12 bits of conversion data. The data is provided MSB first. See the Serial
Interface section.
CS
1
2
4
5
Chip Select. Active low logic input. This input provides the dual function of initiating
conversions on the AD7322 and frames the serial data transfer.
DIN
Data In. Data to be written to the on-chip registers is provided on this input and is clocked into
the register on the falling edge of SCLK. See Register section.
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7322. All analog input
signals and any external reference signal should be referred to this AGND voltage.
REF
IN/REFOUT
Reference Input/ Reference Output pin. When enabled the on-chip reference is available on
this pin for use external to the AD7322. Alternativley, the internal reference can be disabled
and an external reference applied to this input. When using the AD7322 with an external
reference, the internal reference must be disabled via the control register. The nominal
reference voltage is 2.5 V, which appears at the pin. The default on power up is for external
Reference operation. See Table 8.
VCC
10
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the
AD7322. This supply should be decoupled to AGND.
VDD
VSS
ꢀ
±
Positive power supply voltage. This is the positive supply voltage for the Analog Input section.
Negative power supply voltage. This is the negavtive supply voltage for the Analog Input
section.
DGND
VDRIVE
3,13
11
This is the Digital Ground pin.
Logic Power Supply input. The voltage applied to this pin determines the operating voltge of
the sertial inteface.
Vin0-Vin1
7,8
Analog input 0 through Analog Input 1. The analog inputs are multiplexed into the on-chip
track-and-hold. The analog input channel for conversion is selected by programming the
channel address bit ADD0, in the control register. The inputs can be configured as 2 Single-
Ended Inputs, 1 True Differential Input pair, 1 Pseudo Differential inputs. The configuration of
the Analog inputs is selected by programming the Mode bits, Mode1 and Mode0, in the
Control Register. The input range on each input channel is controlled by programming the
range register. Inputs ranges of ±10V, ±5V, ±2.5V and 0 to 10V can be selected on each analog
input channel. See Register section.
Rev. PrE | Page 7 of 18
AD7322
Preliminary Technical Data
(i.e., - 4 x 0REF + 1 LSB, - 2 x 0REF + 1 LSB, - 0REF + 1 LSB) after
the Bipolar Zero Code Error has been adjusted out.
TERMINOLOGY
Differential Nonlinearity
Negative Full Scale Error Match
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
This is the difference in Negative Full Scale error between any
two input channels.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode after the
fifteenth SCLK falling edge. Track-and-hold acquisition time is
the time required for the output of the track-and-hold amplifier
to reach its final value, within 1/2 LSB, after the end of
conversion.
Offset Code Error
This applies to Straight Binary output coding. It is the deviation
of the first code transition (ꢀꢀ . . . ꢀꢀꢀ) to (ꢀꢀ . . . ꢀꢀ1) from the
ideal, i.e., AGND + 1 LSB.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all non-fundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Offset Error Match
This is the difference in Offset Error between any two input
channels.
Gain Error
This applies to Straight Binary output coding. It is the deviation
of the last code transition (111 . . . 11ꢀ) to (111 . . . 111) from the
ideal (i.e., 4 x 0Ref – 1 LSB, 2 x 0REF –1 LSB, 0REF –1 LSB) after
the offset error has been adjusted out.
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 13-bit converter, this is 8ꢀ.ꢀ2 dB.
Total Harmonic Distortion
Gain Error Match
This is the difference in Gain Error between any two input
channels channels.
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7322 it is defined as:
Bipolar Zero Code Error
This applies when using twos complement output coding and a
bipolar Analog Input. It is the deviation of the midscale
transition (all 1s to all ꢀs) from the ideal 0IN voltage, i.e., AGND
- 1 LSB.
2
2
2
V2 +V32 +V4 +V52 +V6
THD(dB) = 20log
V1
Bipolar Zero Code Error Match
where 01 is the rms amplitude of the fundamental and 02, 03,
04, 0ꢁ and 06 are the rms amplitudes of the second through the
sixth harmonics.
This refers to the difference in Bipolar Zero Code Error
between any two input channels.
Positive Full Scale Error
Peak Harmonic or Spurious Noise
This applies when using twos complement output coding and
any of the bipolar Analog Input ranges. It is the deviation of the
last code transition (ꢀ11…11ꢀ) to (ꢀ11…111) from the ideal (
+4 x 0REF - 1 LSB, + 2 x 0REF – 1 LSB, + 0REF – 1 LSB) after the
bipolar Zero Code Error has been adjusted out.
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will
be a noise peak.
Positive Full Scale Error Match
This is the difference in Positive Full Scale error between any
two input channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between any two channels. It is measured by applying
a full-scale, 4ꢀꢀ kHz sine wave signal to all unselected input
channels and determining how much that signal is attenuated in
Negative Full Scale Error
This applies when using twos complement output coding and
any of the bipolar Analog Input ranges. This is the deviation of
the first code transition (1ꢀ…ꢀꢀꢀ) to (1ꢀ…ꢀꢀ1) from the ideal
Rev. PrE | Page 8 of 18
Preliminary Technical Data
AD7322
the selected channel with a ꢁꢀ kHz signal. The figure given is
the worst-case across all eight channels for the AD7322.
Table ꢁ. Reference and Supply Requirements for each Analog
Input Range
Ain Range
VDD/VSS
Min
VCC
Reference V
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with non-linearities will create distortion
products at sum and difference frequencies of mfa nfb where
m, n = ꢀ, 1, 2, 3, etc. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa
– 2fb).
12 0
1ꢀ 0
12 0
1ꢀ0
ꢁ 0
3 0 to ꢁ0
3 0 to ꢁ 0
30 to ꢁ0
3 0 to ꢁ 0
3 0 to ꢁ 0
30
2.ꢁ 0
2.ꢁ 0
2.ꢁ 0
2.ꢁ 0
ꢁ 0
2.ꢁ 0
ꢁ 0
ꢀ to 1ꢀ 0
1ꢀ 0
The AD7322 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in
frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
The Analog Inputs can be configured as either 2 Single-Ended
inputs, 1 True Differential Inputs, or 1 Pseudo Differential
Input. Selection can be made by programming the Mode bits,
Modeꢀ and Mode1, in the on-chip Control Register.
The serial clock input accesses data from the part but also
provides the clock source for each successive approximation
ADC. The AD7322 has an on-chip 2.ꢁ 0 reference. If an
External Reference is the preferred option the user must write
to the reference bit in the control register to disable the internal
Reference.
PSR (Power Supply Rejection)
0ariations in power supply will affect the full-scale transition
but not the converter’s linearity. Power supply rejection is the
maximum change in full-scale transition point due to a change
in power supply voltage from the nominal value. See Typical
Performance Curves.
The AD7322 also features power-down options to allow power
saving between conversions. The power-down modes are
selected by programming the power management bits in the on-
chip Control Register, as described in the Modes of Operation
section.
Theory of Operation
CIRCUIT INFORMATION
CON0ERTER OPERATION
The AD7322 is a fast, 2-Channel, 12-bit plus Sign, Bipolar Input,
Serial A/D converter. The AD7322 can accept bipolar input
ranges that include 1ꢀ0, ꢁ0, 2.ꢁ0, it can also accept ꢀ to 1ꢀ0
unipolar input range. Different Analog input ranges can be
programmed on each analog input Channel via the on-chip
range register. The AD7322 has a high speed serial interface that
can operate at throughput rates up to 1 MSPS.
The AD7322 is a successive approximation analog-to-digital
converter, based around two capacitive DACs. Figure 4 and
Figure ꢁ show simplified schematics of the ADCs in Single
Ended Mode during the acquisition and conversion phase,
respectively. Figure 6 and Figure 7 show simplified schematics
of the ADC in Differential Mode during acquisition and
conversion phase, respectively. The ADC is comprised of
control logic, a SAR, and a capacitive DAC. In Figure 4 (the
acquisition phase), SW2 is closed and SW1 is in position A, the
comparator is held in a balanced condition, and the sampling
capacitor array acquires the signal on the input.
The AD7322 requires 0DD and 0SS dual supplies for the high
voltage Analog input structure. These supplies must be equal to
or greater than the Analog input range. See Table 5 for the
minimum requirements on these supplies for each Analog Input
Range. The AD7322 requires a low voltage 2.70 to ꢁ.2ꢁ 0 0CC
supply to power the ADC core.
CAPACITIVE
DAC
COMPARATOR
C
S
B
A
Vin0
CONTROL
LOGIC
SW1
SW2
AGND
Figure 4. ADC Acquisition Phase(Single Ended)
Rev. PrE | Page ꢀ of 18
AD7322
Preliminary Technical Data
When the ADC starts a conversion (Figure ꢁ), SW2 will open
and SW1 will move to position B, causing the comparator to
become unbalanced. The control logic and the charge
redistribution DAC is used to add and subtract fixed amounts
of charge from the sampling capacitor arrays to bring the
comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
Control Logic generates the ADC output code.
Table 6. LSB sizes for each Analog Input Range
Input Range
1ꢀ0
Full Scale Range/4096 LSB Size
2ꢀ0/4ꢀ96
1ꢀ0/4ꢀ96
ꢁ0/4ꢀ96
4.882 m0
2.441 m0
1.22 m0
ꢁ0
2.ꢁ0
ꢀ to 1ꢀ0
1ꢀ0/4ꢀ96
2.441 m0
CAPACITIVE
DAC
COMPARATOR
C
S
B
A
Vin0
CONTROL
LOGIC
SW1
SW2
The ideal transfer characteristic for the AD7322 when Twos
Complement coding is selected is shown in Figure 8, and the
ideal transfer characteristic for the AD7322 when Straight
Binary coding is selected is shown in Figure 9.
AGND
Figure 5. ADC Conversion Phase(Single Ended)
Figure 6 shows the differential configuration during the
Acquisition phase. For the Conversion Phase, SW3 will open,
SW1 and SW2 will move to position B, see Figure 7. The output
impedances of the source driving the 0in+ and 0in- pins must
be matched; otherwise the two inputs will have different settling
times, resulting in errors.
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
CAPACITIVE
DAC
COMPARATOR
C
B
S
-FSR/2 + 1LSB
+FSR/2 - 1LSB
Vin+
Vin-
V
- 1LSB
REF
A
A
SW1
SW2
CONTROL
LOGIC
SW3
ANALOG INPUT
C
S
B
Figure 8. Twos Complement Transfer Characteristic (Bipolar Ranges)
V
REF
CAPACITIVE
DAC
111...111
111...110
Figure 6. ADC Differential Configuration during Acquisition Phase
CAPACITIVE
DAC
111...000
011...111
COMPARATOR
C
B
S
Vin+
Vin-
A
A
SW1
SW2
CONTROL
LOGIC
SW3
000...010
000...001
C
B
S
V
REF
CAPACITIVE
DAC
000...000
1LSB
FSR/2 -1LSB
ANALOG INPUT
-FSR/2
Figure 7. ADC Differential Configuration during Conversion Phase
Figure 9. Straight Binary Transfer Characteristic (Bipolar Ranges)
Output Coding
ANALOG INPUT
The AD7322 default output coding is set to two’s complement.
The output coding is controlled by the Coding bit in the
Control Register. To change the output coding to Straight
Binary Coding the Coding bit in the Control Register must be
set. When operating in Sequence mode the output coding for
each channel in the sequence will be the value written to the
coding bit during the last write to the Control Register.
The analog inputs of the AD7322 may be configured as Single-
Ended, True differential or Pseudo Differential via the Control
Register Mode Bits as shown in Table 9 of the Register Section.
The AD7322 can accept True bipolar input signals. On power
up the Analog inputs will operate as 2 Single-Ended Analog
Input Channels. If True Differential or Pseudo Differential is
required, a write to the Control register is necessary to change
this configuration after power up.
Transfer Functions
The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is dependant
on the Analog input Range selected.
Figure 1ꢀ shows the equivalent Analog input circuit of the
AD7322 in Single-Ended Mode. Figure 11 shows the equivalent
Analog input structure in Differential mode. The Two Diodes
provide ESD protection for the Analog Inputs.
Rev. PrE | Page 10 of 18
Preliminary Technical Data
AD7322
V
DD
seen by the track-and-hold amplifier looking back on the input.
For the AD7322, the value of R will include the on-resistance of
the input multiplexer. The value of R is typically 3ꢀꢀ Ω. RSOURCE
should include any extra source impedance on the Analog
input.
D
R1
C2
Vin0
C1
D
V
SS
TYPICAL CONNECTION DIAGRAM
Figure 10. Equivalent Analog Input Circuit-(Single Ended)
Figure 12 shows a typical connection diagram for the AD7322.
In this configuration the AGND pin is connected to the Analog
ground plane of the system. The DGND pin is connected to the
Digital ground plane of the system. The Analog Inputs on the
AD7322 can be configured to operate in Single Ended, True
Differential or Pseudo Differential Mode. The AD7322 can
operate with either the internal or an external reference. In
Figure 12, the AD7322 is configured to operate with the internal
2.ꢁ0 reference. A 47ꢀ nF decoupling capacitor is required when
operating with the internal reference.
V
DD
D
D
R1
C2
Vin+
C1
V
V
SS
DD
D
R1
C2
Vin-
C1
D
The 0CC pin can be connected to either a 30 or a ꢁ0 supply
voltage. The 0DD and 0SS are the dual supplies for the high
voltage analog input structures. The voltage on these pins must
be equal to or greater than the highest analog input range
selected on the analog input channels, see Table 5 for more
information. The 0DRI0E pin is connected to the supply voltage
of the microprocessor. The voltage applied to the 0DRI0E input
controls the voltage at which the serial interface operates.
V
SS
Figure 11. Equivalent Analog Input Circuit-(Differential)
Care should be taken to ensure the Analog Input never exceeds
the 0DD and 0SS supply rails by more than 3ꢀꢀ m0. This will
cause the diodes to become forward biased and start
conducting into either the 0DD or 0SS rails. These diodes can
conduct up to 1ꢀ mA without causing irreversible damage to
the part.
The Capacitor C1, in Figure 1ꢀ and Figure 11 is typically 4 pF
and can primarily be attributed to pin capacitance. The resistor
R1, is a lumped component made up of the on-resistance of the
input multiplexer and the track-and-hold switch. The Capacitor
C2, is the sampling capacitor, its capacitance will vary
depending on the Analog input range selected.
Track-and-Hold Section
The Track-and-Hold on the Analog Input of the AD7322 allows
the ADC to accurately convert an input sine wave of full scale
amplitude to 13-Bit accuracy. The input bandwidth of the
Track-and-Hold is greater than the Nyquist rate of the ADC ,
the AD7322 can handle frequencies up to 13 MHz.
The Track-and-Hold enters its tracking mode on the 1ꢁth SCLK
CS
falling edge after the
falling edge. The time required to
acquire an input signal will depend on how quickly the
sampling capacitor is charged. With zero source impedance 3ꢀꢀ
ns will be sufficient to acquire the signal to the 13-bit level.
Figure 12. Typical Connection Diagram
The acquisition time required is calculated using the following
formula:
tACQ = 1ꢀ x ((RSOURCE + R) C)
where C is the Sampling Capacitance and R is the resistance
Rev. PrE | Page 11 of 18
AD7322
Preliminary Technical Data
AD7322 REGISTERS
The AD7322 has two-programmable registers, the Control Register and the Range Register. These registers are write only registers.
Addressing these Registers
A serial transfer on the AD7322 consists of 16 SCLK cycles. The three MSBs on the DIN line during each 16 SCLK transfer are decoded to
determine which register is addressed. The three MSBs consists of the Write bit, ZERO bit and a Register Select bit. The Register Select bit
is used to determine which of the Two on-board registers is selected. The Write bit will determine if the Data on the DIN line following
the Register select bit is loaded into the addressed register or not. If the Write bit is 1 the bits will be loaded into the register addressed by
the Register Select bit. If the Write Bit is a ꢀ the data on the DIN will not be loaded into any register and both registers will remain
unchanged.
Table 7. Decoding Register Select bit and Write bit.
Write
ZERO
Register Select2
Comment
ꢀ
ꢀ
ꢀ
Data on the DIN line during this serial transfer will be ignored. Register contents will
remain unchanged.
1
1
ꢀ
ꢀ
ꢀ
1
This combination selects the Control Register. The subsequent 12 bits will be loaded into
the Control Register.
This combination selects the Range Register. The subsequent 8 bits will be loaded into
the Range Register.
CONTROL REGISTER
The Control Register is used to select the Analog Input configuration, Reference, Coding, Power mode etc. The Control Register is a write
only 12-bit register. Data loaded on the DIN line corresponds to the AD7322 configuration for the next conversion. Data should be
loaded into the Control Register after the Range Register has been initialized. The bit functions of the Control Register are outlined in
Table 8.
Control Register (The Power-up status of all bits is ꢀ)
Table 8. Control Register
MSB
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
PM0
DB5
DB4
Ref
DB3
Seq1
DB2
DB1
Register
Select
Write ZERO
ZERO ZERO ADD0 Mode1 Mode0 PM1
Coding
Seq2 ZERO
Bit
Mnemonic
ADD0
Comment
10
ThIs Channel Address bit is used to select the analog input channel for the next conversion if the Sequencer is
not being used.
ꢀ, 8
Mode1,
Mode0
These two mode bits are used to select the configuation on the two analog Input Pins. They are used in
conjunction with the channel Address bit. On the AD7322 the analog inputs can be configured as either 2
Single Ended Inputs, 1 Fully Differential Input, 1 Pseudo Differential input. See Table 9.
7,±
5
PM1, PM0
Coding
Power Management Bits. These two bits are used to select different power mode options on the AD7322. See
Table 1ꢀ.
This bit is used to select the type of output coding the AD7322 will use for the next conversion result. If the
Coding = 0 then the output coding will be 2s Complement. If Coding = 1, then the output coding will be
Straight Binary. When operating in Sequence mode the output coding for each channel will be the value
written to the coding bit during the last write to the Control Register.
4
Ref
Reference bit. This bit is used to enable or disable the internal reference. If this Ref = 0 then the Internal
Reference will be enable and used for the next conversion. If ref = 1 then an external Reference will be used
for the next conversion and the internal reference will be disabled. When operating in Sequence mode the
Rev. PrE | Page 12 of 18
Preliminary Technical Data
AD7322
Reference used for each channel will be the value written to the Ref bit during the last write to the Control
Register.
3,2
Seq1/Seq2
The Sequence 1 and Sequence 2 bits are used to control the operation of the Sequencer. See Table 8
A zero must be written to this bit to ensure correct operation of the AD7322.
14,12,11,1 ZERO
Table 9. Analog Input Configuration Selection
Channel Address Bit
Mode1 =1, Modeꢀ = 1
Mode1 = 1, Modeꢀ =ꢀ Mode1 = ꢀ, Modeꢀ =1
1Fully Differential i/p Not Allowed
Mode1 =ꢀ, Modeꢀ =ꢀ
1 Pseudo Differential I/p
Two-Single Ended i/ps
ADDꢀ 0in+
0in-
Vin1
Vin1
0in+
Vin0
Vin0
0in-
Vin1
Vin1
0in+
Vin0
Vin1
0in-
0
1
Vin0
Vin0
AGND
AGND
Table 1ꢀ. Power Mode Selection
PM1 PM0 Description
Full Shutdown Mode, In this mode all internal circuitry on the
AD7322 is powered down. Information in the Control register is
retained when the AD7322 is in Full Shutdown Mode.
1
1
1
0
Auto Shutdown Mode, The AD7322 will enter Full Shut down
at the end of each conversion when the control register is
updated. All internal circuitry is powered down in Full
Shutdown.
Auto Standby Mode, In this mode all internal circuitry is
powered down excluding the internal Reference. The AD7322
will enter Auto Standby Mode at the end of the Conversion after
the control register is updated.
0
0
1
0
Normal Mode, All internal Circuitry is powered up at all times.
Table 11. Sequencer Selection
Seq1 Seq2 Sequence type
0
0
The Channel Sequencer is not used. The Analog Channel selected by programming the ADD0 bit in the
Control Register selects the next channel for conversion.
1
0
This Configuration is used in conjunction with the Channel Address Bit in the Control Register. Provided that
the channel Address bit is 1, the ADC will convert firstly on channel 0 then channel 1 and will repeat this
sequence until the Seq bits are changed in the Control Register.
1
1
The Channel Sequencer is not used. The Analog Channel selected by programming the ADD0 bit in the
Control Register selects the next channel for conversion.
Rev. PrE | Page 13 of 18
AD7322
Preliminary Technical Data
RANGE REGISTER
The Range register to used to select one Analog input Range per Analog input channel. It is a 4-Bit write only Register, with two dedicated
Range bits for each of the two Analog Input Channels. There are four Analog input Ranges to choose from, 1ꢀ0, ꢁ0, 2.ꢁ0, ꢀ to 1ꢀ0. A
write to the Range Register is selected by setting the Write bit to 1 and the Register Select bit to 1. Once the initial write to the Range
Register occurs the AD7322 automatically configures the two Analog inputs to the appropriate range, as indicated by the Range register,
each time any one of these analog input channels is selected. The 1ꢀ0 input Range is selected by default on each analog input channel.
See Table 12.
Table 12. Range Register
Register Register
Select 1 Select 2
Write
Vin0A Vin0B Vin1A Vin1B
VinXA VinXB Description
ꢀ
1
ꢀ
1
ꢀ
ꢀ
1
1
This combination selects the 1ꢀ0
Input Range on Analog Input X.
This combination selects the ꢁ0 Input
Range on Analog Input X.
This combination selects the 2.ꢁ0
Input Range on Analog Input X.
This combination selects the ꢀ to 1ꢀ0
Input Range on Analog Input X.
Rev. PrE | Page 14 of 18
AD7322
Preliminary Technical Data
REFERENCE
The AD7322 can operate with either the internal 2.ꢁ0 on-chip
reference or an externally applied reference. The internal
reference is selected by setting the REF bit in the Control
Register to 1. On power up the REF bit will be ꢀ, selecting the
external Reference for the AD7322 conversion. For external
reference operation the REFIN/REFOUT pin should be decoupled
to AGND with a 47ꢀ nF capacitor.
The internal Reference circuitry consists of a 2.ꢁ0 band gap
reference and a reference buffer. When operating the AD7322 in
internal Reference mode the 2.ꢁ0 internal reference is available
at the REFIN/REFOUT pin. When using the AD7322 with the
internal reference the REFIN/REFOUT pin should be
decoupled to AGND using a ꢀ.47 µF cap. It is recommended
that the Internal Reference be buffered before applying it else
where in the system.
The AD7322 is specified for a 2.ꢁ0 to 30 reference range. When
a 30 reference is selected the ranges will be, 120, 60, 30
and ꢀ to 120. For these ranges the 0DD and 0SS supply must be
equal to or greater than the max Analog Input Range selected.
On power up if the internal reference operation is required for
the ADC conversion, a write to the control register is necessary
to set the REF bit to 1. During the Control Register write the
conversion result from the first initial conversion will be invalid.
The reference buffer will require TBD us to power up and
charge the ꢀ.47 µF decoupling cap, during the power up time
the conversion result from the ADC will be invalid.
Rev. PrE | Page 15 of 18
AD7322
Preliminary Technical Data
If a write to the control register occurs while the part is in Full
Shut down mode, with the power management bits, PM1 and
PMꢀ set to ꢀ, normal mode, the part will begin to power up on
MODES OF OPERATION
The AD7322 has a number of different modes of operation.
These modes are designed to provide flexible power
management options. These options can be chosen to optimize
the power dissipation/throughput rate ratio for the differing
application requirements. The mode of operation of the
AD7322 is controlled by the Power Management bits, PM1 and
PMꢀ, in the Control register as detailed in Table 10.The default
mode is Normal Mode, where all internal circuitry is fully
powered up.
CS
the
rising edge.
To ensure the AD7322 is fully powered up, tPOWER UP, should
elapse before the next CS falling edge.
Auto Shutdown Mode (PM1 = 1, PM0 = 0)
Once the Auto Shutdown mode is selected the AD7322 will
automatically enter shutdown at the end of each conversion.
The AD7322 retains information in the registers during
Shutdown. The track-and-hold is in hold during shutdown. On
Normal Mode (PM1 = PM0 = 0)
CS
the falling
edge, the track-and-hold that was in hold during
This mode is intended for the fastest throughput rate
performance, the AD7322 is fully powered up at all times.
Figure 13 shows the general diagram of operation of the
AD7322 in Normal Mode.
shutdown will return to track.
The power-up from Auto Shutdown is TBD µs
In this mode the power consumption of the AD7322 is greatly
reduced with the part entering shutdown at the end of each
conversion. When the control registers is programmed to move
into Auto Shutdown mode, it does so at the end of the
conversion.
CS
The Conversion is initiated on the falling edge of
and the
track and hold will enter hold mode as described in the Serial
Interface Section. The Data on the DIN line during the 16 SCLK
transfer will be loaded into one of the on-chip registers,
provided the Write bit is set. The register is selected by
programming the Register select bits, see Table 1 of the Register
section.
Auto Standby Mode (PM1 = 0, PM0 =1)
In Auto Standby mode portions of the AD7322 are powered
down but the on-chip reference remains powered up. The
reference bit in the Control register should be ꢀ to ensure the
on-chip reference is enabled. This mode is similar to Auto
Shutdown but allows the AD7322 to power up much faster,
allowing faster throughput rates to be achieved.
The AD7322 will enter standby at the end of the conversion.
The part retains information in the Registers during Standby.
CS
The AD7322 will remain in standby until it receives a
falling
falling edge.
falling edge the track-and-hold that was in hold
Figure 13. Normal Mode
CS
edge. The ADC will begin to power up on the
CS
On this
The AD7322 will remain fully powered up at the end of the
conversion provided both PM1 and PMꢀ contain ꢀ in the
control Register.
mode while the part was in Standby will return to track. Wake-
up time from Standby is 1 µs. The user should ensure that 1 µs
has elapsed before attempting a valid conversion. When running
the AD7322 with the maximum 2ꢀ MHz SCLK, one dummy
conversion of 16 x SCLKs is sufficient to power up the ADC.
This dummy conversion effectively halves the throughput rate
of the AD7322, with every second conversion result being a
valid result. Once Auto Standby mode is selected, the ADC can
Sixteen serial clock cycles are required to complete the
conversion and access the conversion result. At the end of the
may idle high until the next conversion or may
idle low until sometime prior to the next conversion.
CS
conversion
Once the data transfer is complete, another conversion can be
initiated after the quiet time, tQUIET, has elapsed.
CS
move in and out of the low power state by controlling the
signal.
Full Shutdown Mode (PM1 = PM0 = 1)
In this mode all internal circuitry on the AD7322 is powered
down. The part retains information in the Registers during Full
Shut down. The AD7322 remains in Full shutdown mode until
the power managements bits in the Control Register, PM1 and
PMꢀ, are changed.
Rev. PrE | Page 1± of 18
AD7322
Preliminary Technical Data
CS
when the
signal is brought high the addressed register may
SERIAL INTERFACE
or may not be updated. Data is clocked into the AD7322 on the
SCLK falling edge. The three MSB on the DIN line are decoded
to select which register is being addressed. The Control Register
is an eleven bit register, if the control register is addressed by the
three MSB, the data on the DIN line will be loaded into the
Control on the 1ꢁth SCLK falling edge. If the Range registers is
addressed the data on the DIN line will be loaded into the
addressed register on the 11th SCLK falling edge.
Figure 14 shows the timing diagram for the serial interface of
the AD7322. The serial clock applied to the SCLK pin provides
the conversion clock and also controls the transfer of
information to and from the AD7322 during a conversion.
CS
The
signal initiates the data transfer and the conversion
CS
process. The falling edge of
puts the track-and-hold into
hold mode, take the bus out of three-state and the analog input
signal is sampled at this point. Once the conversion is initiated
it will require 16 SCLK cycles to complete.
Conversion data is clocked out of the AD7322 on each SCLK
falling edge. Data on the DOUT line will consist of two leading
zeros, a channel identifier bit, a Sign bit and the 12-bit
conversion result. The channel identifier bit is used to indicate
which channel the conversion result corresponds to.
The track-and-hold will go back into track on the 1ꢁth SCLK
falling edge. On the sixteenth SCLK falling edge, the DOUT line
will return to three-state. If the rising edge of
CS
occurs before
16 SCLK cycles have elapsed, the conversion will be terminated,
the DOUT line will return to three-state, and depending on
Figure 14. Serial Interface timing Diagram (Control register write)
Rev. PrE | Page 17 of 18
AD7322
Preliminary Technical Data
OUTLINE DIMENSIONS
14-Lead Thin Shrink Small Outline (TSSOP)
(RU-14)
Ordering Guide
AD7322 Products
AD7322BRU
Temperature Package
–40°C to +85°C
Package Description
TSSOP
Package Outline
RU-14
EVAL-AD7322CB1
EVAL-CONTROL BRD22
Evaluation Board
Controller Board
NOTES
1 This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL Board for evaluation/demonstration purposes.
2 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete
evaluation kit, the particular ADC evaluation board, e.g., EVAL-AD7322CB, the EVAL-CONTROL BRD2, and a 12V transformer must be ordered. See relevant Evaluation
Board Technical note for more information.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrE | Page 18 of 18
相关型号：
EVAL-CONTROLBRD2Z
2-Channel, Software-Selectable, True Bipolar Input, 1 MSPS, 12-Bit Plus Sign ADC
ADI
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