ATTINY84V-10MU [ATMEL]
8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash; 8位微控制器与2/4 / 8K字节的系统内可编程闪存
| 型号： | ATTINY84V-10MU |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| 文件： | 总21页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny24/44/84)
Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny24/44/84)
Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM (ATtiny24/44/84)
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
• Peripheral Features
– Two Timer/Counters, 8- and 16-bit counters with two PWM Channels on both
– 10-bit ADC
8 single-ended channels
12 differential ADC channel pairs with programmable gain (1x, 20x)
Temperature Measurement
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
ATtiny24/44/84
– Universal Serial Interface
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Pin Change Interrupt on 12 pins
Preliminary
Summary
– Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
– On-chip Temperature Sensor
• I/O and Packages
– 14-pin SOIC, PDIP and 20-pin QFN/MLF: Twelve Programmable I/O Lines
• Operating Voltage:
– 1.8 - 5.5V for ATtiny24V/44V/84V
– 2.7 - 5.5V for ATtiny24/44/84
• Speed Grade
– ATtiny24V/44V/84V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny24/44/84: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
• Industrial Temperature Range
• Low Power Consumption
– Active Mode:
1 MHz, 1.8V: 380 µA
– Power-down Mode:
1.8V: 100 nA
Rev. 8006FS–AVR–02/07
1. Pin Configurations
Figure 1-1. Pinout ATtiny24/44/84
PDIP/SOIC
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
GND
(PCINT8/XTAL1/CLKI) PB0
(PCINT9/XTAL2) PB1
PA0 (ADC0/AREF/PCINT0)
PA1 (ADC1/AIN0/PCINT1)
PA2 (ADC2/AIN1/PCINT2)
PA3 (ADC3/T0/PCINT3)
PA4 (ADC4/USCK/SCL/T1/PCINT4)
PA5 (ADC5/DO/MISO/OC1B/PCINT5)
(PCINT11/RESET/dW) PB3
(PCINT10/INT0/OC0A/CKOUT) PB2
(PCINT7/ICP/OC0B/ADC7) PA7
(PCINT6/OC1A/SDA/MOSI/ADC6) PA6
8
QFN/MLF
Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/ADC6)
Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5)
(ADC4/USCK/SCL/T1/PCINT4) PA4
(ADC3/T0/PCINT3) PA3
1
15 PA7 (PCINT7/ICP/OC0B/ADC7)
14 PB2 (PCINT10/INT0/OC0A/CKOUT)
13 PB3 (PCINT11/RESET/dW)
12 PB1 (PCINT9/XTAL2)
2
3
4
5
(ADC2/AIN1/PCINT2) PA2
(ADC1/AIN0/PCINT1) PA1
(ADC0/AREF/PCINT0) PA0
11 PB0 (PCINT8/XTAL1/CLKI)
NOTE
Bottom pad should be
soldered to ground.
DNC: Do Not Connect
1.1
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers
manufactured on the same process technology. Min and Max values will be available after the device is characterized.
2
ATtiny24/44/84
8006FS–AVR–02/07
ATtiny24/44/84
2. Overview
The ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24/44/84
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
VCC
8-BIT DATABUS
INTERNAL
INTERNAL
OSCILLATOR
CALIBRATED
OSCILLATOR
GND
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
MCU CONTROL
REGISTER
PROGRAM
FLASH
SRAM
MCU STATUS
REGISTER
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
TIMER/
COUNTER0
X
Y
Z
INSTRUCTION
DECODER
TIMER/
COUNTER1
CONTROL
LINES
ALU
STATUS
REGISTER
INTERRUPT
UNIT
PROGRAMMING
LOGIC
EEPROM
OSCILLATORS
ISP INTERFACE
DATA REGISTER
PORT A
DATA DIR.
REG.PORT A
ADC
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
PORT A DRIVERS
PORT B DRIVERS
PA7-PA0
PB3-PB0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
3
8006FS–AVR–02/07
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny24/44/84 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32
general purpose working registers, a 8-bit Timer/Counter with two PWM channels, a 16-bit
timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC,
programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable
Watchdog Timer with internal Oscillator, internal calibrated oscillator, and three software select-
able power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Inter-
rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions. In Standby mode, the crys-
tal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low power consumption.
The device is manufactured ng Atmel’s high density non-volatile memory technology. The On-
chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny24/44/84 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
4
ATtiny24/44/84
8006FS–AVR–02/07
ATtiny24/44/84
2.2
Pin Descriptions
2.2.1
VCC
Supply voltage.
2.2.2
2.2.3
GND
Ground.
Port B (PB3...PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of
RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low
will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny24/44/84 as listed on
Section 12.3 ”Alternate Port Functions” on page 61.
2.2.4
2.2.5
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 22-3 on page
183. Shorter pulses are not guaranteed to generate a reset.
Port A (PA7...PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A has an alternate functions as analog inputs for the ADC, analog comparator,
timer/counter, SPI and pin change interrupt as described in ”Alternate Port Functions” on page
61
3. Resources
A comprehensive set of development tools, drivers and application notes, and datasheets are
available for download on http://www.atmel.com/avr.
5
8006FS–AVR–02/07
4. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31))
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
SREG
SPH
I
–
T
–
H
–
S
–
V
–
N
–
Z
C
Page 9
Page 12
Page 12
Page 89
Page 53
Page 54
Page 90
Page 90
Page 163
Page 89
Page 53
Page 46
Page 88
Page 89
Page 33
Page 85
Page 114
Page 116
Page 118
Page 118
Page 118
Page 118
Page 118
Page 118
Page 159
Page 33
Page 119
Page 119
Page 122
Page 117
Page 46
Page 54
Page 23
Page 23
Page 23
Page 23
Page 72
Page 72
Page 72
Page 72
Page 72
Page 73
Page 25
Page 25
Page 25
Page 55
SP9
SP1
SP8
SP0
SPL
SP7
SP6
SP5
SP4
SP3
SP2
Timer/Counter0 – Output Compare Register B
OCR0B
GIMSK
GIFR
PCIE0
PCIF0
–
–
–
INT0
PCIE1
–
–
–
–
INTF0
PCIF1
–
–
–
–
–
TIMSK0
TIFR0
–
–
–
–
–
–
–
–
OCIE0B
OCF0B
PGWRT
OCIE0A
OCF0A
PGERS
TOIE0
TOV0
SPMEN
–
SPMCSR
OCR0A
MCUCR
MCUSR
TCCR0B
TCNT0
OSCCAL
TCCR0A
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
DWDR
–
CTPB
RFLB
Timer/Counter0 – Output Compare Register A
–
–
PUD
–
SE
–
SM1
SM0
–
ISC01
EXTRF
CS01
ISC00
PORF
CS00
–
–
WDRF
WGM02
BORF
CS02
FOC0A
FOC0B
–
Timer/Counter0
CAL7
CAL6
COM0A0
COM1A0
ICES1
CAL5
COM0B1
COM1B1
–
CAL4
CAL3
CAL2
CAL1
WGM01
WGM11
CS11
CAL0
WGM00
WGM10
CS10
COM0A1
COM1A1
ICNC1
COM0B0
COM1B0
WGM13
–
–
WGM12
CS12
Timer/Counter1 – Counter Register High Byte
Timer/Counter1 – Counter Register Low Byte
Timer/Counter1 – Compare Register A High Byte
Timer/Counter1 – Compare Register A Low Byte
Timer/Counter1 – Compare Register B High Byte
Timer/Counter1 – Compare Register B Low Byte
DWDR[7:0]
CLKPR
ICR1H
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
ICR1L
GTCCR
TCCR1C
WDTCSR
PCMSK1
EEARH
EEARL
EEDR
TSM
FOC1A
WDIF
–
–
FOC1B
WDIE
–
–
–
–
–
–
–
–
–
PSR10
–
–
WDP3
–
–
WDCE
–
WDE
PCINT11
–
WDP2
PCINT10
–
WDP1
PCINT9
–
WDP0
PCINT8
EEAR8
EEAR0
–
–
–
–
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEPROM Data Register
EECR
–
–
EEPM1
EEPM0
EERIE
PORTA3
DDA3
EEMPE
PORTA2
DDA2
EEPE
PORTA1
DDA1
EERE
PORTA0
DDA0
PORTA
DDRA
PORTA7
PORTA6
PORTA5
PORTA4
DDA7
DDA6
DDA5
DDA4
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
PORTB
DDRB
–
–
–
–
–
–
–
–
–
–
–
–
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
PINB
PINB3
PINB2
PINB1
PINB0
GPIOR2
GPIOR1
GPIOR0
PCMSK0
Reserved
USIBR
General Purpose I/O Register 2
General Purpose I/O Register 1
General Purpose I/O Register 0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
–
USI Buffer Register
USI Data Register
Page 131
Page 131
Page 131
Page 132
Page 119
Page 120
USIDR
USISR
USISIF
USIOIF
USIPF
USIWM1
ICIE1
USIDC
USICNT3
USICNT2
USICS0
OCIE1B
OCF1B
USICNT1
USICLK
OCIE1A
OCF1A
USICNT0
USITC
TOIE1
USICR
USISIE
USIOIE
USIWM0
USICS1
TIMSK1
TIFR1
–
–
–
–
–
–
–
–
ICF1
TOV1
Reserved
Reserved
ACSR
–
–
ACD
REFS1
ADEN
ACBG
REFS0
ADSC
ACO
MUX5
ADATE
ACI
MUX4
ADIF
ACIE
MUX3
ADIE
ACIC
MUX2
ADPS2
ACIS1
MUX1
ADPS1
ACIS0
MUX0
ADPS0
Page 137
Page 151
Page 154
Page 155
Page 155
Page 156
ADMUX
ADCSRA
ADCH
ADC Data Register High Byte
ADC Data Register Low Byte
ADCL
ADCSRB
Reserved
DIDR0
BIN
ACME
–
ADLAR
–
ADTS2
ADTS1
ADTS0
–
ADC7D
–
ADC6D
–
ADC5D
–
ADC4D
–
ADC3D
PRTIM1
ADC2D
PRTIM0
ADC1D
PRUSI
ADC0D
PRADC
Page 138,Page 157
Page 36
PRR
6
ATtiny24/44/84
8006FS–AVR–02/07
ATtiny24/44/84
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
7
8006FS–AVR–02/07
5. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
CBR
INC
Rd ← Rd ⊕ Rr
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
Z,N,V
DEC
TST
Rd
Decrement
Rd ← Rd − 1
Z,N,V
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
CLR
SER
Rd
Z,N,V
Rd
Set Register
None
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
RCALL
ICALL
RET
k
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
Subroutine Return
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
k
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
LSR
P,b
P,b
Rd
Rd
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
I/O(P,b) ← 0
None
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Z,C,N,V
Logical Shift Right
8
ATtiny24/44/84
8006FS–AVR–02/07
ATtiny24/44/84
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd
Rd
Rd
s
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S
V
V
T
S ← 0
V ← 1
V ← 0
T ← 1
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
None
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/Timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
9
8006FS–AVR–02/07
6. Ordering Information
6.1
ATtiny24
Speed (MHz)
Power Supply
Ordering Code(1)
Package(2)
Operational Range
ATtiny24V-10SSU
ATtiny24V-10PU
ATtiny24V-10MU
14S1
14P3
20M1
Industrial
(-40°C to 85°C)
10
20
1.8 - 5.5V
ATtiny24-20SSU
ATtiny24-20PU
ATtiny24-20MU
14S1
14P3
20M1
Industrial
(-40°C to 85°C)
2.7 - 5.5V
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
Package Type
14S1
14P3
20M1
14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
10
ATtiny24/44/84
8006FS–AVR–02/07
ATtiny24/44/84
6.2
ATtiny44
Speed (MHz)
Power Supply
Ordering Code(1)
Package(2)
Operational Range
ATtiny44V-10SSU
ATtiny44V-10PU
ATtiny44V-10MU
14S1
14P3
20M1
Industrial
(-40°C to 85°C)
10
20
1.8 - 5.5V
ATtiny44-20SSU
ATtiny44-20PU
ATtiny44-20MU
14S1
14P3
20M1
Industrial
(-40°C to 85°C)
2.7 - 5.5V
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
Package Type
14S1
14P3
20M1
14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
11
8006FS–AVR–02/07
6.3
ATtiny84
Speed (MHz)
Power Supply
Ordering Code(1)
Package(2)
Operational Range
ATtiny84V-10PU
ATtiny84V-10MU
14P3
20M1
Industrial
(-40°C to 85°C)
10
20
1.8 - 5.5V
ATtiny84-20PU
ATtiny84-20MU
14P3
20M1
Industrial
(-40°C to 85°C)
2.7 - 5.5V
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
Package Type
14S1
14P3
20M1
14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
12
ATtiny24/44/84
8006FS–AVR–02/07
ATtiny24/44/84
7. Packaging Information
7.1
20M1
D
1
2
Pin 1 ID
SIDE VIEW
E
3
TOP VIEW
A2
A1
D2
A
0.08
C
1
2
3
Pin #1
Notch
(0.20 R)
COMMON DIMENSIONS
(Unit of Measure = mm)
E2
MIN
0.70
–
MAX
0.80
0.05
b
NOM
0.75
NOTE
SYMBOL
A
A1
A2
b
0.01
L
0.20 REF
0.23
0.18
2.45
2.45
0.35
0.30
2.75
2.75
0.55
e
D
4.00 BSC
2.60
D2
E
BOTTOM VIEW
4.00 BSC
2.60
E2
e
0.50 BSC
0.40
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
Note:
L
10/27/04
DRAWING NO. REV.
20M1
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,
A
R
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
13
8006FS–AVR–02/07
7.2
14P3
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
MIN
–
MAX
5.334
–
NOM
NOTE
SYMBOL
eC
A
–
–
–
–
–
–
–
–
–
–
–
eB
A1
D
0.381
18.669
7.620
6.096
0.356
1.143
2.921
0.203
–
19.685 Note 2
8.255
E
E1
B
7.112 Note 2
0.559
B1
L
1.778
Notes: 1. This package conforms to JEDEC reference MS-001, Variation AA.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
3.810
C
0.356
eB
eC
e
10.922
0.000
1.524
2.540 TYP
11/02/05
DRAWING NO. REV.
14P3
TITLE
2325 Orchard Parkway
San Jose, CA 95131
14P3, 14-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
A
R
14
ATtiny24/44/84
8006FS–AVR–02/07
ATtiny24/44/84
7.3
14S1
1
E
H
E
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm/inches)
e
b
MIN
MAX
NOM
NOTE
SYMBOL
A
A1
b
1.35/0.0532
0.1/.0040
–
1.75/0.0688
0.25/0.0098
0.5/0.02005
8.74/0.3444
3.99/0.1574
6.19/0.2440
1.27/0.0500
A1
A
–
0.33/0.0130
8.55/0.3367
3.8/0.1497
5.8/0.2284
0.41/0.0160
–
D
E
H
L
–
2
D
–
3
Side View
–
–
4
e
1.27/0.050 BSC
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-012, Variation AB for additional information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not
exceed 0.15 mm (0.006") per side.
3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm
(0.010") per side.
4. L is the length of the terminal for soldering to a substrate.
5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value
of 0.61 mm (0.024") per side.
2/5/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
14S1, 14-lead, 0.150" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
14S1
A
R
15
8006FS–AVR–02/07
8. Errata
The revision letter in this section refers to the revision of the ATtiny24/44/84 device.
8.1
ATtiny24
8.1.1
Rev. D
No known errata.
8.1.2
Rev. C
• Reading EEPROM when system clock frequency is below 900 kHz may not work
1. Reading EEPROM when system clock frequency is below 900 kHz may not work
Reading data from the EEPROM at system clock frequency below 900 kHz may result in
wrong data read.
Problem Fix/Work around
Avoid using the EEPROM at clock frequency below 900 kHz.
8.1.3
Rev. B
• EEPROM read from application code does not work in Lock Bit Mode 3
• Reading EEPROM when system clock frequency is below 900 kHz may not work
1. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does
not work from the application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from
EEPROM.
2. Reading EEPROM when system clock frequency is below 900 kHz may not work
Reading data from the EEPROM at system clock frequency below 900 kHz may result in
wrong data read.
Problem Fix/Work around
Avoid using the EEPROM at clock frequency below 900 kHz.
8.1.4
Rev. A
Not sampled.
16
ATtiny24/44/84
8006FS–AVR–02/07
ATtiny24/44/84
8.2
ATtiny44
8.2.1
Rev. B
No known errata.
8.2.2
Rev. A
• Reading EEPROM when system clock frequency is below 900 kHz may not work
1. Reading EEPROM when system clock frequency is below 900 kHz may not work
Reading data from the EEPROM at system clock frequency below 900 kHz may result in
wrong data read.
Problem Fix/Work around
Avoid using the EEPROM at clock frequency below 900 kHz.
17
8006FS–AVR–02/07
8.3
ATtiny84
8.3.1
Rev. A
No known errata.
18
ATtiny24/44/84
8006FS–AVR–02/07
ATtiny24/44/84
9. Datasheet Revision History
9.1
Rev F. 02/07
1.
2.
Updated Figure 1-1 on page 2, Figure 9-7 on page 45, Figure 22-5 on page
187.
Updated Table 10-1 on page 50, Table 12-7 on page 69, Table 13-2 on page
85, Table 13-3 on page 85, Table 13-5 on page 86, Table 13-6 on page 86,
Table 13-7 on page 87, Table 13-8 on page 87, Table 22-6 on page 185,
Table 22-8 on page 187.
3.
4.
Updated table references in ”TCCR0A – Timer/Counter Control Register
A” on page 85.
Updated Port B, Bit 0 functions in ”Alternate Functions of Port B” on page
69.
5.
6.
7.
8.
9.
Updated WDTCR bit name to WDTCSR in assembly code examples.
Updated bit5 name in Section 14.11.9 on page 120.
Updated bit5 in Section 14.11.9 on page 120.
Updated ”SPI Master Operation Example” on page 126.
Updated step 5 in ”Enter High-voltage Serial Programming Mode” on
page 174.
9.2
Rev E. 09/06
1.
2.
All characterization data is moved to ”Electrical Characteristics” on page
180.
All Register Descriptions are gathered up in separate sections in the end
of each chapter.
3.
4.
Updated ”System Control and Reset” on page 40.
Updated Table 13-3 on page 85, Table 13-6 on page 86, Table 13-8 on page
87, Table 14-2 on page 114 and Table 14-4 on page 116.
5.
6.
7.
8.
9.
Updated ”Fast PWM Mode” on page 105.
Updated Figure 14-7 on page 106 and Figure 18-1 on page 140.
Updated ”Analog Comparator Multiplexed Input” on page 135.
Added note in Table 21-11 on page 171.
Updated ”Electrical Characteristics” on page 180.
10. Updated ”Typical Characteristics – Preliminary Data” on page 188.
9.3
Rev D. 08/06
1.
2.
3.
4.
5.
6.
Updated ”Calibrated Internal RC Oscillator” on page 30.
Updated ”Oscillator Calibration Register – OSCCAL” on page 33.
Added Table 22-1 on page 182.
Updated code examples in ”SPI Master Operation Example” on page 126.
Updated code examples in ”SPI Slave Operation Example” on page 127.
Updated ”Signature Bytes” on page 167.
19
8006FS–AVR–02/07
9.4
9.5
Rev C. 07/06
1.
2.
3.
Updated Features in ”USI – Universal Serial Interface” on page 123.
Added ”Clock speed considerations” on page 130.
Updated Bit description in ”ADMUX – ADC Multiplexer Selection Regis-
ter” on page 151.
4.
Added note to Table 20-1 on page 163.
Rev B. 05/06
1.
2.
3.
Updated ”Default Clock Source” on page 27
Updated ”Power Reduction Register” on page 36.
Updated Table 22-3 on page 183, Table 9-4 on page 42, Table 18-3 on page
151, Table 21-5 on page 167, Table 21-11 on page 171, Table 21-15 on
page 177, Table 22-6 on page 185.
4.
5.
6.
7.
8.
9.
Updated Features in ”Analog to Digital Converter” on page 139.
Updated Operation in ”Analog to Digital Converter” on page 139.
Updated ”Temperature Measurement” on page 150.
Updated DC Characteristics in ”Electrical Characteristics” on page 180.
Updated ”Typical Characteristics – Preliminary Data” on page 188.
Updated ”Errata” on page 223.
9.6
Rev A. 12/05
Initial revision.
20
ATtiny24/44/84
8006FS–AVR–02/07
Atmel Corporation
Atmel Operations
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