ATTINY261_0611_技术文档

Features

• High Performance, Low Power AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 123 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

• Non-volatile Program and Data Memories

– 2/4/8K Byte of In-System Programmable Program Memory Flash

(ATtiny261/461/861)

8-bit

Endurance: 10,000 Write/Erase Cycles

– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny261/461/861)

Endurance: 100,000 Write/Erase Cycles

– 128/256/512 Bytes Internal SRAM (ATtiny261/461/861)

– Programming Lock for Self-Programming Flash Program and EEPROM Data

Security

Microcontroller

with 2/4/8K

Bytes In-System

Programmable

Flash

• Peripheral Features

– 8/16-bit Timer/Counter with Prescaler and Two PWM Channels

– 8/10-bit High Speed Timer/Counter with Separate Prescaler

3 High Frequency PWM Outputs with Separate Output Compare Registers

Programmable Dead Time Generator

– Universal Serial Interface with Start Condition Detector

– 10-bit ADC

ATtiny261/V

ATtiny461/V

ATtiny861/V

11 Single Ended Channels

16 Differential ADC Channel Pairs

15 Differential ADC Channel Pairs with Programmable Gain (1x, 8x, 20x, 32x)

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– debugWIRE On-chip Debug System

Preliminary

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, and Power-down Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

• I/O and Packages

– 16 Programmable I/O Lines

– 20-pin PDIP, 20-pin SOIC and 32-pad MLF

• Operating Voltage:

– 1.8 - 5.5V for ATtiny261V/461V/861V

– 2.7 - 5.5V for ATtiny261/461/861

• Speed Grade:

– ATtiny261V/461V/861V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATtiny261/461/861: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

• Industrial Temperature Range

• Low Power Consumption

– Active Mode: 1 MHz, 1.8V: 380μA

– Power-down Mode: 0.1μA at 1.8V

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1. Pin Configurations

Figure 1-1. Pinout ATtiny261/461/861

PDIP/SOIC

(MOSI/DI/SDA/OC1A/PCINT8) PB0

1

20

19

18

17

16

15

14

13

12

11

PA0 (ADC0/DI/SDA/PCINT0)

PA1 (ADC1/DO/PCINT1)

PA2 (ADC2/INT1/USCK/SCL/PCINT2)

PA3 (AREF/PCINT3)

(MISO/DO/OC1A/PCINT9) PB1

(SCK/USCK/SCL/OC1B/PCINT10) PB2

(OC1B/PCINT11) PB3

2

3

4

VCC

5

AGND

GND

6

AVCC

(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4

(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5

(ADC9/INT0/T0/PCINT14) PB6

(ADC10/RESET/PCINT15) PB7

7

PA4 (ADC3/ICP0/PCINT4)

PA5 (ADC4/AIN2/PCINT5)

PA6 (ADC5/AIN0/PCINT6)

PA7 (ADC6/AIN1/PCINT7)

8

9

10

NC

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

(OC1B/PCINT11) PB3

PA2 (ADC2/INT1/USCK/SCL/PCINT2)

NC

PA3 (AREF/PCINT3)

VCC

AGND

QFN/MLF

GND

NC

(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4

(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5

AVCC

PA4 (ADC3/ICP0/PCINT4)

Note:

The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical

stability.

1.1

Disclaimer

Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers

manufactured on the same process technology. Min and Max values will be available after the device is characterized.

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2. Overview

The ATtiny261/461/861 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the

ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

Watchdog

Timer

Power

Supervision

POR / BOD &

RESET

debugWIRE

Watchdog

Oscillator

PROGRAM

LOGIC

Oscillator

Circuits /

Clock

Flash

SRAM

Generation

CPU

EEPROM

AVCC

AGND

AREF

Timer/Counter0

USI

Timer/Counter1

Analog Comp.

A/D Conv.

Internal

Bandgap

3

11

PORT B (8)

PORT A (8)

RESET

XTAL[1..2]

PB[0..7]

PA[0..7]

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The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATtiny261/461/861 provides the following features: 2/4/8K byte of In-System Programmable

Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 6 general purpose I/O lines, 32

general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high

speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel,

10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software select-

able power saving modes. The Idle mode stops the CPU while allowing the SRAM,

Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The

Power-down mode saves the register contents, disabling all chip functions until the next Inter-

rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules

except ADC, to minimize switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code

running on the AVR core.

The ATtiny261/461/861 AVR is supported with a full suite of program and system development

tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu-

lators, and Evaluation kits.

2.2

Pin Descriptions

2.2.1

VCC

Supply voltage.

Ground.

2.2.2

2.2.3

2.2.4

2.2.5

GND

AVCC

AGND

Analog supply voltage.

Analog ground.

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the ATtiny261/461/861 as listed

on page 65.

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2.2.6

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny261/461/861 as listed

on page 61.

2.2.7

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 23-3 on page

189. Shorter pulses are not guaranteed to generate a reset.

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3. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

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4. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

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5. AVR CPU Core

5.1

Overview

This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

Figure 5-1. Block Diagram of the AVR Architecture

Data Bus 8-bit

Program

Counter

Status

and Control

Flash

Program

Memory

32 x 8

General

Purpose

Registrers

Instruction

Register

Interrupt

Unit

Instruction

Decoder

Watchdog

Timer

ALU

Analog

Comparator

Control Lines

I/O Module1

I/O Module 2

I/O Module n

Data

SRAM

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the Program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the Program memory. This concept enables instructions to be executed

in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File – in one clock cycle.

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Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash Program memory. These

added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single register operations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat. Every Program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F.

5.2

5.3

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set” section for a detailed description.

Status Register

The Status Register contains information about the result of the most recently executed arith-

metic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the Instruction Set Reference. This will in many cases remove the need for using the

dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software.

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5.3.1

SREG – AVR Status Register

The AVR Status Register – SREG – is defined as:

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

0x3F (0x5F)

Read/Write

Initial Value

SREG

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

Register is cleared, none of the interrupts are enabled independent of the individual interrupt

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful

in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

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5.4

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve

the required performance and flexibility, the following input/output schemes are supported by the

Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 5-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 5-2. AVR CPU General Purpose Working Registers

7

0

Addr.

R0

R1

0x00

0x01

0x02

R2

…

R13

R14

R15

R16

R17

…

0x0D

0x0E

0x0F

0x10

0x11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

X-register Low Byte

X-register High Byte

Y-register Low Byte

Y-register High Byte

Z-register Low Byte

Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 5-2, each register is also assigned a Data memory address, mapping them

directly into the first 32 locations of the user Data Space. Although not being physically imple-

mented as SRAM locations, this memory organization provides great flexibility in access of the

registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

5.4.1

The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 5-3 on page 12.

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Figure 5-3. The X-, Y-, and Z-registers

15

XH

XL

0

X-register

7

0

7

R27 (0x1B)

R26 (0x1A)

15

YH

YL

ZL

0

Y-register

Z-register

7

R29 (0x1D)

R28 (0x1C)

15

ZH

0

7

0

R31 (0x1F)

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see the instruction set reference for details).

5.5

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-

tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack

Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the program before

any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to

point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack

with the PUSH instruction, and it is decremented by two when the return address is pushed onto

the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is

popped from the Stack with the POP instruction, and it is incremented by two when data is

popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present

5.5.1

SPH and SPL – Stack Pointer Register

Bit

15

14

13

12

11

10

9

8

0x3E (0x5E)

0x3D (0x5D)

SP15

SP7

SP14

SP6

SP13

SP5

SP12

SP4

SP11

SP3

SP10

SP2

SP9

SP8

SPH

SPL

SP1

SP0

7

6

5

4

3

2

1

0

Read/Write

Initial Value

R/W

RAMEND

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5.6

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 5-4. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clk_CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 5-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Figure 5-5. Single Cycle ALU Operation

T1

T2

T3

T4

clk_CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

5.7

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate Program Vector in the Program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the Program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 48. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0.

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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a

Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the

Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-

tor in order to execute the interrupt handling routine, and hardware clears the corresponding

Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)

to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is

cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is

cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt

Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the

Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence..

Assembly Code Example

in r16, SREG

; store SREG value

cli ; disable interrupts during timed sequence

sbiEECR, EEMPE ; start EEPROM write

sbiEECR, EEPE

outSREG, r16

; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG;/* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set Global Interrupt Enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

5.7.1

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clock cycles the Program Vector address for the actual interrupt handling routine

is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt

execution response time is increased by four clock cycles. This increase comes in addition to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock

cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is

incremented by two, and the I-bit in SREG is set.

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6. AVR Memories

This section describes the different memories in the ATtiny261/461/861. The AVR architecture

has two main memory spaces, the Data memory and the Program memory space. In addition,

the ATtiny261/461/861 features an EEPROM Memory for data storage. All three memory

spaces are linear and regular.

6.1

In-System Re-programmable Flash Program Memory

The ATtiny261/461/861 contains 2/4/8K byte On-chip In-System Reprogrammable Flash mem-

ory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized

as 1024/2048/4096 x 16.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATtiny261/461/861 Program Counter (PC) is 10/11/12 bits wide, thus addressing the

1024/2048/4096 Program memory locations. ”Memory Programming” on page 168 contains a

detailed description on Flash data serial downloading using the SPI pins.

Constant tables can be allocated within the entire Program memory address space (see the

LPM – Load Program memory instruction description).

Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-

ing” on page 13.

Figure 6-1. Program Memory Map

Program Memory

0x0000

0x03FF/0x07FF/0x0FFF

6.2

SRAM Data Memory

Figure 6-2 shows how the ATtiny261/461/861 SRAM Memory is organized.

The lower 224/352/608 Data memory locations address both the Register File, the I/O memory

and the internal data SRAM. The first 32 locations address the Register File, the next 64 loca-

tions the standard I/O memory, and the last 128/256/512 locations address the internal data

SRAM.

The five different addressing modes for the Data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

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ATtiny261/461/861

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-

nal data SRAM in the ATtiny261/461/861 are all accessible through all these addressing modes.

The Register File is described in ”General Purpose Register File” on page 11.

Figure 6-2. Data Memory Map

Data Memory

0x0000 - 0x001F

0x0020 - 0x005F

0x0060

32 Registers

64 I/O Registers

Internal SRAM

(128/256/512 x 8)

0x0DF/0x15F/0x25F

6.2.1

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk_CPUcycles as described in Figure 6-3.

Figure 6-3. On-chip Data SRAM Access Cycles

T1

T2

T3

clk_CPU

Address valid

Compute Address

Address

Data

WR

Data

RD

Memory Access Instruction

Next Instruction

6.3

EEPROM Data Memory

The ATtiny261/461/861 contains 128/256/512 bytes of data EEPROM memory. It is organized

as a separate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM

Data Register, and the EEPROM Control Register. For a detailed description of Serial data

downloading to the EEPROM, see page 181.

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6.3.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access times for the EEPROM are given in Table 6-1. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contains instruc-

tions that write the EEPROM, some precautions must be taken. In heavily filtered power

supplies, V_CCis likely to rise or fall slowly on Power-up/down. This causes the device for some

period of time to run at a voltage lower than specified as minimum for the clock frequency used.

See ”Preventing EEPROM Corruption” on page 20 for details on how to avoid problems in these

situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to ”Atomic Byte Programming” on page 18 and ”Split Byte Programming” on page 18 for

details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

6.3.2

Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the

user must write the address into the EEARL Register and data into EEDR Register. If the

EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the

erase/write operation. Both the erase and write cycle are done in one operation and the total

programming time is given in Table 1. The EEPE bit remains set until the erase and write opera-

tions are completed. While the device is busy with programming, it is not possible to do any

other EEPROM operations.

6.3.3

Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be useful if

the system requires short access time for some limited period of time (typically if the power sup-

ply voltage falls). In order to take advantage of this method, it is required that the locations to be

written have been erased before the write operation. But since the erase and write operations

are split, it is possible to do the erase operations when the system allows doing time-critical

operations (typically after Power-up).

6.3.4

6.3.5

Erase

Write

To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the

EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (program-

ming time is given in Table 1). The EEPE bit remains set until the erase operation completes.

While the device is busy programming, it is not possible to do any other EEPROM operations.

To write a location, the user must write the address into EEAR and the data into EEDR. If the

EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger

the write operation only (programming time is given in Table 1). The EEPE bit remains set until

the write operation completes. If the location to be written has not been erased before write, the

data that is stored must be considered as lost. While the device is busy with programming, it is

not possible to do any other EEPROM operations.

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ATtiny261/461/861

The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre-

quency is within the requirements described in ”OSCCAL – Oscillator Calibration Register” on

page 32.

The following code examples show one assembly and one C function for erase, write, or atomic

write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling

interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set Programming mode

ldi r16, (0<<EEPM1)|(0<<EEPM0)

out EECR, r16

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to data register

out EEDR, r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned char ucAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set Programming mode */

EECR = (0<<EEPM1)|(0<<EEPM0);

/* Set up address and data registers */

EEAR = ucAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

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The next code examples show assembly and C functions for reading the EEPROM. The exam-

ples assume that interrupts are controlled so that no interrupts will occur during execution of

these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned char ucAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = ucAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

6.3.6

Preventing EEPROM Corruption

During periods of low V_CC, the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V_CCreset protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

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ATtiny261/461/861

6.4

I/O Memory

The I/O space definition of the ATtiny261/461/861 is shown in ”Register Summary” on page 218.

All ATtiny261/461/861 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32

general purpose working registers and the I/O space. I/O Registers within the address range

0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the

instruction set section for more details. When using the I/O specific commands IN and OUT, the

I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using

LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

6.4.1

General Purpose I/O Registers

The ATtiny261/461/861 contains three General Purpose I/O Registers. These registers can be

used for storing any information, and they are particularly useful for storing global variables and

Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly

bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

6.5

Register Description

6.5.1

EEARH and EEARL – EEPROM Address Register

Bit

7

6

5

4

3

2

1

0

EEAR8

EEAR0

0

0x1F (0x3F)

0x1E (0x3E)

Bit

-

EEARH

EEARL

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

7

R

6

R

5

R

4

R

3

R

2

R

1

R

Read/Write

Initial Value

R/W

X

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

X

• Bit 7:1 – Res6:0: Reserved Bits

These bits are reserved for future use and will always read as 0 in ATtiny261/461/861.

• Bits 8:0 – EEAR8:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL – specifies the high EEPROM address

in the 128/256/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly

between 0 and 127/255/511. The initial value of EEAR is undefined. A proper value must be writ-

ten before the EEPROM may be accessed.

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6.5.2

EEDR – EEPROM Data Register

Bit

7

6

EEDR6

R/W

0

5

EEDR5

R/W

0

4

EEDR4

R/W

0

3

EEDR3

R/W

0

2

EEDR2

R/W

0

1

EEDR1

R/W

0

EEDR0

R/W

0

0x1D (0x3D)

Read/Write

Initial Value

EEDR7

R/W

0

EEDR

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

6.5.3

EECR – EEPROM Control Register

Bit

0x1C (0x3C)

7

6

–

5

EEPM1

R/W

X

4

EEPM0

R/W

X

3

EERIE

R/W

0

2

EEMPE

R/W

0

1

EEPE

R/W

X

0

EERE

R/W

0

–

EECR

Read/Write

Initial Value

R

0

R

0

• Bit 7 – Res: Reserved Bit

This bit is reserved for future use and will always read as 0 in ATtiny261/461/861. For compati-

bility with future AVR devices, always write this bit to zero. After reading, mask out this bit.

• Bit 6 – Res: Reserved Bit

This bit is reserved in the ATtiny261/461/861 and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be

triggered when writing EEPE. It is possible to program data in one atomic operation (erase the

old value and program the new value) or to split the Erase and Write operations in two different

operations. The Programming times for the different modes are shown in Table 6-1. While EEPE

is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00

unless the EEPROM is busy programming.

Table 6-1.

EEPROM Mode Bits

Programming

EEPM1

EEPM0

Time

3.4 ms

1.8 ms

–

Operation

0

1

0

1

0

1

Erase and Write in one operation (Atomic Operation)

Erase Only

Write Only

Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant inter-

rupt when Non-volatile memory is ready for programming.

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ATtiny261/461/861

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the

selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been

written to one by software, hardware clears the bit to zero after four clock cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM.

When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting.

The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no

EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared

by hardware. When EEPE has been set, the CPU is halted for two cycles before the next

instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor-

rect address is set up in the EEAR Register, the EERE bit must be written to one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed. The user should poll the EEPE bit before starting the read opera-

tion. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change

the EEAR Register.

6.5.4

6.5.5

6.5.6

GPIOR2 – General Purpose I/O Register 2

Bit

0x0C (0x2C)

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

GPIOR2

GPIOR1

GPIOR0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

GPIOR1 – General Purpose I/O Register 1

Bit

7

6

5

4

3

2

1

0

0x0B (0x2B)

Read/Write

Initial Value

MSB

R/W

0

LSB

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

GPIOR0 – General Purpose I/O Register 0

Bit

7

6

5

4

3

2

1

0

0x0A (0x2A)

Read/Write

Initial Value

MSB

R/W

0

LSB

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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7. System Clock and Clock Options

7.1

Clock Systems and their Distribution

Figure 7-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules

not being used can be halted by using different sleep modes, as described in ”Power Manage-

ment and Sleep Modes” on page 34. The clock systems are detailed below.

Figure 7-1. Clock Distribution

7.1.1

7.1.2

CPU Clock – clk_CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

I/O Clock – clk_I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is

also used by the External Interrupt module, but note that some external interrupts are detected

by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

7.1.3

7.1.4

Flash Clock – clk_FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

ADC Clock – clk_ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

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ATtiny261/461/861

7.1.5

Internal PLL for Fast Peripheral Clock Generation - clk_PCK

The internal PLL in ATtiny261/461/861 generates a clock frequency that is 8x or 4x multiplied

from a source input depending on the Low Speed Mode (LSM) bit. The source of the PLL input

clock is the output of the internal RC oscillator having a frequency of 8.0 MHz. Thus the output of

the PLL, the fast peripheral clock is 64 MHz or 32 MHz. The fast peripheral clock, or a clock

prescaled from that, can be selected as the clock source for Timer/Counter1. See the Figure 7-2

on page 25.

The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will

adjust the fast peripheral clock at the same time. However, even if the RC oscillator is taken to a

higher frequency than 8 MHz, the fast peripheral clock frequency saturates at 85 MHz (worst

case) and remains oscillating at the maximum frequency. It should be noted that the PLL in this

case is not locked any longer with the RC oscillator clock.

Therefore, it is recommended not to take the OSCCAL adjustments to a higher frequency than 8

MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only

when the PLLE bit in the register PLLCSR is set or the CKSEL fuses are programmed to ‘0001’.

The bit PLOCK from the register PLLCSR is set when PLL is locked.

Both internal RC oscillator and PLL are switched off in power down and stand-by sleep modes.

Figure 7-2. PCK Clocking System

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2588B–AVR–11/06

7.2

Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the

appropriate modules.

Table 7-1.

Device Clocking Options Select⁽¹⁾vs. PB4 and PB5 Functionality

Device Clocking Option

CKSEL3..0

0000

0001

0010

0011

01xx

PB4

XTAL1

I/O

PB5

I/O

External Clock

PLL Clock

I/O

Calibrated Internal RC Oscillator 8.0 MHz

Watchdog Oscillator 128 kHz

I/O

External Low-frequency Oscillator

XTAL1

XTAL2

External Crystal/Ceramic Resonator (0.4 - 0.9 MHz)

External Crystal/Ceramic Resonator (0.9 - 3.0 MHz)

External Crystal/Ceramic Resonator (3.0 - 8.0 MHz)

External Crystal/Ceramic Resonator (8.0 - 20.0 MHz)

1000

1001

1010

1011

1100

1101

1110

1111

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU

wakes up from Power-down or Power-save, the selected clock source is used to time the start-

up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts

from reset, there is an additional delay allowing the power to reach a stable level before com-

mencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the

start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 7-

2.

Table 7-2.

Number of Watchdog Oscillator Cycles

Typ Time-out

4 ms

Number of Cycles

512

64 ms

8K (8,192)

7.3

Default Clock Source

The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default

clock source setting is therefore the Internal RC Oscillator running at 8 MHz with longest start-up

time and an initial system clock prescaling of 8. This default setting ensures that all users can

make their desired clock source setting using an In-System or High-voltage Programmer.

7.4

External Clock

To drive the device from an external clock source, CLKI should be driven as shown in Figure 7-

3. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.

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ATtiny261/461/861

Figure 7-3. External Clock Drive Configuration

EXTERNAL

CLOCK

CLKI

GND

SIGNAL

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 7-3.

Start-up Times for the External Clock Selection

Start-up Time from Power-

down and Power-save

Additional Delay from

SUT1..0

00

Reset

Recommended Usage

BOD enabled

6 CK

14CK

01

14CK + 4 ms

14CK + 64 ms

Reserved

Fast rising power

Slowly rising power

10

11

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page

31 for details.

7.5

High Frequency PLL Clock - PLL_CLK

There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator

for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as

a system clock source, by programming the CKSEL fuses to ‘0001’, it is divided by four like

shown in Table 7-4. When this clock source is selected, start-up times are determined by the

SUT fuses as shown in Table 7-5. See also ”PCK Clocking System” on page 25.

Table 7-4.

PLLCK Operating Modes

CKSEL3..0

Nominal Frequency

0001

16 MHz

Table 7-5.

Start-up Times for the PLLCK

Start-up Time from Power

Down

Additional Delay from

SUT1..0

00

Reset (V_CC= 5.0V)

14CK + 4 ms

Recommended usage

BOD enabled

1K (1024) + 4 ms

16K (16384) + 4 ms

1K (1024) + 64 ms

16K (16384) + 64 ms

01

Fast rising power

Slowly rising power

10

11

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2588B–AVR–11/06

7.6

Calibrated Internal RC Oscillator

By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage

and temperature dependent, this clock can be very accurately calibrated by the user. See Table

23-1 on page 188 and ”Internal Oscillator Speed” on page 211 for more details. The device is

shipped with the CKDIV8 Fuse programmed. See ”System Clock Prescaler” on page 31 for

more details.

This clock may be selected as the system clock by programming the CKSEL Fuses as shown in

Table 7-6 on page 28. If selected, it will operate with no external components. During reset,

hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby

automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory

calibration in Table 23-1 on page 188.

By changing the OSCCAL register from SW, see ”OSCCAL – Oscillator Calibration Register” on

page 32, it is possible to get a higher calibration accuracy than by using the factory calibration.

The accuracy of this calibration is shown as User calibration in Table 23-1 on page 188.

When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali-

bration value, see the section ”Calibration Byte” on page 170.

Table 7-6.

Internal Calibrated RC Oscillator Operating Modes⁽¹⁾⁽³⁾

Frequency Range⁽²⁾(MHz)

CKSEL3..0

7.3 - 8.1

0010

Notes: 1. The device is shipped with this option selected.

2. The frequency ranges are preliminary values. Actual values are TBD.

3. If 8 MHz frequency exceeds the specification of the device (depends on V_CC), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 7-7 on page 28.

Table 7-7.

Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

Start-up Time

from Power-down

Additional Delay from

Reset (V_CC= 5.0V)

SUT1..0

00

Recommended Usage

BOD enabled

6 CK

14CK

01

14CK + 4 ms

14CK + 64 ms

Reserved

Fast rising power

Slowly rising power

10⁽¹⁾

11

Note:

1. The device is shipped with this option selected.

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ATtiny261/461/861

7.7

128 kHz Internal Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-

quency is nominal at 3V and 25°C. This clock may be select as the system clock by

programming the CKSEL Fuses to “0011”.

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 7-8.

Start-up Times for the 128 kHz Internal Oscillator

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset

SUT1..0

00

Recommended Usage

BOD enabled

6 CK

14CK

01

14CK + 4 ms

14CK + 64 ms

Reserved

Fast rising power

Slowly rising power

10

11

7.8

Low-frequency Crystal Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal

oscillator must be selected by setting CKSEL fuses to ‘0100’. The crystal should be connected

as shown in Figure 7-4. Refer to the 32 kHz Crystal Oscillator Application Note for details on

oscillator operation and how to choose appropriate values for C1 and C2.

When this oscillator is selected, start-up times are determined by the SUT fuses as shown in

Table 7-9.

Start-up Times for the Low Frequency Crystal Oscillator Clock Selection

Start-up Time from

Power Down and Power

Save

Additional Delay from

Reset (V_CC= 5.0V)

SUT1..0

Recommended usage

Fast rising power or BOD

enabled

00

1K (1024) CK⁽¹⁾

4 ms

01

10

11

1K (1024) CK⁽¹⁾

32K (32768) CK

64 ms

Slowly rising power

64 ms

Stable frequency at start-up

Reserved

Notes: 1. These options should only be used if frequency stability at start-up is not important for the

application.

7.9

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-

figured for use as an On-chip Oscillator, as shown in Figure 7-4. Either a quartz crystal or a

ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the

capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the

electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for

use with crystals are given in Table 7-10. For ceramic resonators, the capacitor values given by

the manufacturer should be used.

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2588B–AVR–11/06

Figure 7-4. Crystal Oscillator Connections

C2

XTAL2

XTAL1

GND

C1

The Oscillator can operate in three different modes, each optimized for a specific frequency

range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 7-10.

Table 7-10. Crystal Oscillator Operating Modes

Recommended Range for Capacitors C1 and

CKSEL3..1

100⁽¹⁾

101

Frequency Range (MHz)

C2 for Use with Crystals (pF)

0.4 - 0.9

0.9 - 3.0

3.0 - 8.0

8.0 -

–

12 - 22

110

111

Notes: 1. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

7-11.

Table 7-11. Start-up Times for the Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

CKSEL0

SUT1..0

(V_CC= 5.0V)

Recommended Usage

Ceramic resonator, fast

rising power

0

00

258 CK⁽¹⁾

14CK + 4.1 ms

14CK + 65 ms

14CK

Ceramic resonator, slowly

rising power

0

1

01

10

11

00

01

10

11

258 CK⁽¹⁾

Ceramic resonator, BOD

enabled

1K (1024) CK⁽²⁾

1K (1024)CK⁽²⁾

16K (16384) CK

Ceramic resonator, fast

rising power

14CK + 4.1 ms

14CK + 65 ms

14CK

Ceramic resonator, slowly

rising power

Crystal Oscillator, BOD

enabled

Crystal Oscillator, fast

rising power

14CK + 4.1 ms

14CK + 65 ms

Crystal Oscillator, slowly

rising power

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ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystals when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

7.10 Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-

cuits on the system. Note that the clock will not be output during reset and the normal operation

of I/O pin will be overridden when the fuse is programmed. Any clock source, including the inter-

nal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock

Prescaler is used, it is the divided system clock that is output.

7.11 System Clock Prescaler

The ATtiny261/461/861 system clock can be divided by setting the Clock Prescale Register –

CLKPR. This feature can be used to decrease power consumption when the requirement for

processing power is low. This can be used with all clock source options, and it will affect the

clock frequency of the CPU and all synchronous peripherals. clk_I/O, clk_ADC, clk_CPU, and clk_FLASH

are divided by a factor as shown in Table 7-12.

7.11.1

Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occur in the clock system and that no intermediate frequency is higher than neither the

clock frequency corresponding to the previous setting, nor the clock frequency corresponding to

the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the

state of the prescaler – even if it were readable, and the exact time it takes to switch from one

clock division to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the

new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the

previous clock period, and T2 is the period corresponding to the new prescaler setting.

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7.12 Register Description

7.12.1

OSCCAL – Oscillator Calibration Register

Bit

7

6

5

4

3

2

1

0

0x31 (0x51)

Read/Write

CAL7

R/W

CAL6

R/W

CAL5

R/W

CAL4

R/W

CAL3

R/W

CAL2

R/W

CAL1

R/W

CAL0

R/W

OSCCAL

Initial Value

Device Specific Calibration Value

• Bits 7:0 – CAL7:0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to

remove process variations from the oscillator frequency. A pre-programmed calibration value is

automatically written to this register during chip reset, giving the Factory calibrated frequency as

specified in Table 23-1 on page 188. The application software can write this register to change

the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 23-

1 on page 188. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write

times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more

than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the

lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-

quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher

frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00

gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the

range.

7.12.2

CLKPR – Clock Prescale Register

Bit

0x28 (0x48)

7

6

–

R

0

5

–

R

0

4

–

R

0

3

2

1

0

CLKPCE

CLKPS3

R/W

CLKPS2

R/W

CLKPS1

R/W

CLKPS0

R/W

CLKPR

Read/Write

Initial Value

R/W

0

See Bit Description

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is

cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting

the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

• Bits 6:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and will always read as zero.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written run-time to vary the clock frequency to suit the application

requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-

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ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 7-12.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,

the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to

“0011”, giving a division factor of eight at start up. This feature should be used if the selected

clock source has a higher frequency than the maximum frequency of the device at the present

operating conditions. Note that any value can be written to the CLKPS bits regardless of the

CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is

chosen if the selcted clock source has a higher frequency than the maximum frequency of the

device at the present operating conditions. The device is shipped with the CKDIV8 Fuse

programmed.

Table 7-12. Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

Reserved

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2588B–AVR–11/06

8. Power Management and Sleep Modes

The high performance and industry leading code efficiency makes the AVR microcontrollers an

ideal choise for low power applications.

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving

power. The AVR provides various sleep modes allowing the user to tailor the power consump-

tion to the application’s requirements.

8.1

Sleep Modes

Figure 7-1 on page 24 presents the different clock systems in the ATtiny261/461/861, and their

distribution. The figure is helpful in selecting an appropriate sleep mode. Table 8-1 shows the

different sleep modes and their wake up sources.

Table 8-1.

Active Clock Domains and Wake-up Sources in the Different Sleep Modes

Active Clock Domains

Oscillators

Wake-up Sources

Sleep Mode

Idle

X

ADC Noise

Reduction

X⁽¹⁾

Power-down

Standby

X⁽¹⁾

X

Note:

1. For INT0 and INT1, only level interrupt.

To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a

SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which

sleep mode (Idle, ADC Noise Reduction, Power-down, or Standby) will be activated by the

SLEEP instruction. See Table 8-2 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU

is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the Register File and

SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,

the MCU wakes up and executes from the Reset Vector.

8.2

Idle Mode

When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,

stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the

interrupt system to continue operating. This sleep mode basically halts clk_CPUand clk_FLASH, while

allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,

the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator

Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the

ADC is enabled, a conversion starts automatically when this mode is entered.

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ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

8.3

ADC Noise Reduction Mode

When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise

Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the

Watchdog to continue operating (if enabled). This sleep mode halts clk_I/O, clk_CPU, and clk_FLASH

while allowing the other clocks to run.

,

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out

Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change

interrupt can wake up the MCU from ADC Noise Reduction mode.

8.4

Power-down Mode

When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watch-

dog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out

Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This

sleep mode halts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to ”External Interrupts” on page 50

for details.

8.5

8.6

Standby Mode

When the SM1..0 bits are written to 11 and an external crystal/resonator clock option is selected,

the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-

down with the exception that the Oscillator is kept running. From Standby mode, the device

wakes up in six clock cycles.

Power Reduction Register

The Power Reduction Register (PRR), see ”PRR – Power Reduction Register” on page 37, pro-

vides a method to stop the clock to individual peripherals to reduce power consumption. The

current state of the peripheral is frozen and the I/O registers can not be read or written.

Resources used by the peripheral when stopping the clock will remain occupied, hence the

peripheral should in most cases be disabled before stopping the clock. Waking up a module,

which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. See ”Supply Current of I/O modules” on page 200 for examples. In all other

sleep modes, the clock is already stopped.

8.7

Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR

controlled system. In general, sleep modes should be used as much as possible, and the sleep

mode should be selected so that as few as possible of the device’s functions are operating. All

functions not needed should be disabled. In particular, the following modules may need special

consideration when trying to achieve the lowest possible power consumption.

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2588B–AVR–11/06

8.7.1

8.7.2

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to ”ADC – Analog to Digital Converter” on

page 142 for details on ADC operation.

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep

modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is

set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis-

abled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,

independent of sleep mode. Refer to ”AC – Analog Comparator” on page 138 for details on how

to configure the Analog Comparator.

8.7.3

8.7.4

Brown-out Detector

If the Brown-out Detector is not needed in the application, this module should be turned off. If the

Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes,

and hence, always consume power. In the deeper sleep modes, this will contribute significantly

to the total current consumption. Refer to ”Brown-out Detection” on page 41 for details on how to

configure the Brown-out Detector.

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the

Analog Comparator or the ADC. If these modules are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming power. When

turned on again, the user must allow the reference to start up before the output is used. If the

reference is kept on in sleep mode, the output can be used immediately. Refer to ”Internal Volt-

age Reference” on page 42 for details on the start-up time.

8.7.5

8.7.6

Watchdog Timer

If the Watchdog Timer is not needed in the application, this module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to ”Watchdog Timer” on page 42 for details on how to configure the Watchdog Timer.

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important thing is then to ensure that no pins drive resistive loads. In sleep modes where

both the I/O clock (clk_I/O) and the ADC clock (clk_ADC) are stopped, the input buffers of the device

will be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 57 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an

analog signal level close to V_CC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V_CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR0, DIDR1).

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ATtiny261/461/861

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ATtiny261/461/861

Refer to ”DIDR0 – Digital Input Disable Register 0” on page 160 or ”DIDR1 – Digital Input Dis-

able Register 1” on page 160 for details.

8.8

Register Description

8.8.1

MCUCR – MCU Control Register

The MCU Control Register contains control bits for power management.

Bit

7

–

R

0

6

5

4

3

2

1

0

0x35 (0x55)

Read/Write

Initial Value

PUD

R/W

0

SE

R/W

0

SM1

R/W

0

SM0

R/W

0

—

R

0

ISC01

R/W

0

ISC00

R/W

0

MCUCR

• Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

• Bits 4, 3 – SM1:0: Sleep Mode Select Bits 2..0

These bits select between the three available sleep modes as shown in Table 8-2.

Table 8-2.

SM1

Sleep Mode Select

SM0

Sleep Mode

Idle

0

1

0

1

0

1

ADC Noise Reduction

Power-down

Standby

• Bit 2 – Res: Reserved Bit

This bit is a reserv ed bit in the ATtiny261/461/861 and will always read as zero.

8.8.2

PRR – Power Reduction Register

Bit

0x36 (0x56)

7

6

-

5

-

4

-

3

2

1

0

–

PRTIM1

R/W

0

PRTIM0

R/W

0

PRUSI

R/W

0

PRADC

R/W

0

PRR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bits 7, 6, 5, 4- Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and will always read as zero.

• Bit 3- PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1

is enabled, operation will continue like before the shutdown.

37

2588B–AVR–11/06

• Bit 2- PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0

is enabled, operation will continue like before the shutdown.

• Bit 1 - PRUSI: Power Reduction USI

Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When

waking up the USI again, the USI should be re initialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.

The analog comparator cannot use the ADC input MUX when the ADC is shut down.

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ATtiny261/461/861

9. System Control and Reset

9.0.1

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative

Jump – instruction to the reset handling routine. If the program never enables an interrupt

source, the Interrupt Vectors are not used, and regular program code can be placed at these

locations. The circuit diagram in Figure 9-1 shows the reset logic. ”System and Reset Character-

istics” on page 189 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-

ferent selections for the delay period are presented in ”Clock Sources” on page 26.

9.0.2

Reset Sources

The ATtiny261/461/861 has four sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset

threshold (V_POT).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than

the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage V_CCis below the Brown-out Reset

threshold (V_BOT) and the Brown-out Detector is enabled.

Figure 9-1. Reset Logic

DATA BUS

MCU Status

Register (MCUSR)

Power-on Reset

Circuit

Brown-out

BODLEVEL [1..0]

Reset Circuit

Pull-up Resistor

SPIKE

FILTER

Watchdog

Oscillator

Delay Counters

Clock

CK

Generator

TIMEOUT

CKSEL[1:0]

SUT[1:0]

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2588B–AVR–11/06

9.0.3

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in ”System and Reset Characteristics” on page 189. The POR is activated whenever

_CCis below the detection level. The POR circuit can be used to trigger the Start-up Reset, as

V

well as to detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V_CCrise. The RESET signal is activated again, without any delay,

when V_CCdecreases below the detection level.

Figure 9-2. MCU Start-up, RESET Tied to V_CC

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 9-3. MCU Start-up, RESET Extended Externally

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

9.0.4

External Reset

An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer

than the minimum pulse width (see ”System and Reset Characteristics” on page 189) will gener-

ate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a

reset. When the applied signal reaches the Reset Threshold Voltage – V_RST– on its positive

edge, the delay counter starts the MCU after the Time-out period – t_TOUT– has expired.

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ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Figure 9-4. External Reset During Operation

CC

9.0.5

Brown-out Detection

ATtiny261/461/861 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V_CC

level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can

be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free

Brown-out Detection. The hysteresis on the detection level should be interpreted as V_BOT+

_BOT+ V_HYST/2 and V_BOT-= V_BOT- V_HYST/2.

=

V

When the BOD is enabled, and V_CCdecreases to a value below the trigger level (V_BOT-in Figure

9-5), the Brown-out Reset is immediately activated. When V_CCincreases above the trigger level

(V_BOT+in Figure 9-5), the delay counter starts the MCU after the Time-out period t_TOUThas

expired.

The BOD circuit will only detect a drop in V_CCif the voltage stays below the trigger level for

longer than t_BODgiven in ”System and Reset Characteristics” on page 189.

Figure 9-5. Brown-out Reset During Operation

V_BOT+

V_CC

V_BOT-

RESET

t

TOUT

TIME-OUT

INTERNAL

RESET

9.0.6

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t_TOUT. Refer to

page 42 for details on operation of the Watchdog Timer.

41

2588B–AVR–11/06

Figure 9-6. Watchdog Reset During Operation

CC

CK

9.1

Internal Voltage Reference

ATtiny261/461/861 features an internal bandgap reference. This reference is used for Brown-out

Detection, and it can be used as an input to the Analog Comparator or the ADC.

9.1.1

Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in ”System and Reset Characteristics” on page 189. To save power, the

reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting the

ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

9.2

Watchdog Timer

The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling

the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table

9-3 on page 46. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The

Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different

clock cycle periods can be selected to determine the reset period. If the reset period expires

without another Watchdog Reset, the ATtiny261/461/861 resets and executes from the Reset

Vector. For timing details on the Watchdog Reset, refer to Table 9-3 on page 46.

The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can

be very helpful when using the Watchdog to wake-up from Power-down.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,

two different safety levels are selected by the fuse WDTON as shown in Table 9-1. Refer to

”Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43 for

details.

42

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Table 9-1.

WDT Configuration as a Function of the Fuse Settings of WDTON

Safety

Level

WDT Initial

State

How to Disable the

WDT

How to Change Time-

out

WDTON

Unprogrammed

Programmed

1

2

Disabled

Enabled

Timed sequence

Always enabled

No limitations

Timed sequence

Figure 9-7. Watchdog Timer

WATCHDOG

PRESCALER

128 kHz

OSCILLATOR

WATCHDOG

RESET

WDP0

WDP1

WDP2

WDP3

WDE

MCU RESET

9.3

Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing configuration differs slightly between the two safety levels. Separate

procedures are described for each level.

9.3.1

Safety Level 1

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit

to one without any restriction. A timed sequence is needed when disabling an enabled Watch-

dog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written

to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as

desired, but with the WDCE bit cleared.

9.3.2

Safety Level 2

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A

timed sequence is needed when changing the Watchdog Time-out period. To change the

Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE

always is set, the WDE must be written to one to start the timed sequence.

2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,

but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

43

2588B–AVR–11/06

9.4

Register Description

9.4.1

MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU Reset.

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

–

R

0

3

2

1

0

0x34 (0x54)

Read/Write

Initial Value

WDRF

R/W

BORF

R/W

EXTRF

R/W

PORF

R/W

MCUSR

See Bit Description

• Bits 7:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and will always read as zero.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then reset

the MCUSR as early as possible in the program. If the register is cleared before another reset

occurs, the source of the reset can be found by examining the Reset Flags.

9.4.2

WDTCR – Watchdog Timer Control Register

Bit

0x21 (0x41)

7

6

5

4

3

2

1

0

WDIF

WDIE

WDP3

R/W

0

WDCE

R/W

0

WDE

R/W

X

WDP2

R/W

0

WDP1

R/W

0

WDP0

R/W

0

WDTCR

Read/Write

Initial Value

R/W

0

R/W

0

• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-

ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in

SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable

When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the

Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed

instead of a reset if a timeout in the Watchdog Timer occurs.

If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful

for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared,

44

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after

each interrupt.

Table 9-2.

Watchdog Timer Configuration

WDE

WDIE

Watchdog Timer State

Stopped

Action on Time-out

None

0

1

0

1

0

1

Running

Interrupt

Running

Reset

Running

Interrupt

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not

be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the

description of the WDE bit for a Watchdog disable procedure. This bit must also be set when

changing the prescaler bits. See Section “9.3” on page 43.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written

to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit

has logic level one. To disable an enabled Watchdog Timer, the following procedure must be

followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written

to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm

described above. See Section “9.3” on page 43.

In safety level 1, WDE is overridden by WDRF in MCUSR. See ”MCUSR – MCU Status Regis-

ter” on page 44 for description of WDRF. This means that WDE is always set when WDRF is set.

To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure

described above. This feature ensures multiple resets during conditions causing failure, and a

safe start-up after the failure.

Note:

If the watchdog timer is not going to be used in the application, it is important to go through a

watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally

enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which

in turn will lead to a new watchdog reset. To avoid this situation, the application software should

always clear the WDRF flag and the WDE control bit in the initialization routine.

• Bits 5, 2:0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is

enabled. The different prescaling values and their corresponding Timeout Periods are shown in

Table 9-3 on page 46.

45

2588B–AVR–11/06

Table 9-3.

Watchdog Timer Prescale Select

Number of WDT Oscillator

Typical Time-out at

V_CC= 5.0V

WDP3

WDP2

WDP1

WDP0

Cycles

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2K (2048) cycles

16 ms

32 ms

64 ms

0.125 s

0.25 s

0.5 s

4K (4096) cycles

8K (8192) cycles

16K (16384) cycles

32K (32764) cycles

64K (65536) cycles

128K (131072) cycles

256K (262144) cycles

512K (524288) cycles

1024K (1048576) cycles

1.0 s

2.0 s

4.0 s

8.0 s

Reserved

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2588B–AVR–11/06

ATtiny261/461/861

The following code example shows one assembly and one C function for turning off the WDT.

The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that

no interrupts will occur during execution of these functions.

Assembly Code Example⁽¹⁾

WDT_off:

WDR

; Clear WDRF in MCUSR

ldi r16, (0<<WDRF)

out MCUSR, r16

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional Watchdog Reset

in r16, WDTCR

ori r16, (1<<WDCE)|(1<<WDE)

out WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example⁽¹⁾

void WDT_off(void)

{

_WDR();

/* Clear WDRF in MCUSR */

MCUSR = 0x00

/* Write logical one to WDCE and WDE */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

Note:

1. The example code assumes that the part specific header file is included.

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2588B–AVR–11/06

10. Interrupts

This section describes the specifics of the interrupt handling as performed in ATtiny261/461/861.

For a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling”

on page 13.

10.1 Interrupt Vectors in ATtiny261/461/861

Table 10-1. Reset and Interrupt Vectors

Vector Program

No. Address

Source

Interrupt Definition

External Pin, Power-on Reset, Brown-out

Reset, Watchdog Reset

1

0x0000

RESET

2

3

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

0x000C

0x000D

0x000E

0x000F

0x0010

0x0011

0x0012

INT0

External Interrupt Request 0

Pin Change Interrupt Request

Timer/Counter1 Compare Match A

Timer/Counter1 Compare Match B

Timer/Counter1 Overflow

Timer/Counter0 Overflow

USI Start

PCINT

4

TIMER1_COMPA

TIMER1_COMPB

TIMER1_OVF

TIMER0_OVF

USI_START

USI_OVF

5

6

7

8

9

USI Overflow

10

11

12

13

14

15

16

17

18

19

EE_RDY

EEPROM Ready

ANA_COMP

ADC

Analog Comparator

ADC Conversion Complete

Watchdog Time-out

WDT

INT1

External Interrupt Request 1

Timer/Counter0 Compare Match A

Timer/Counter0 Compare Match B

Timer/Counter1 Capture Event

Timer/Counter1 Compare Match D

TIMER0_COMPA

TIMER0_COMPB

TIMER0_CAPT

TIMER1_COMPD

FAULT_PROTECTION Timer/Counter1 Fault Protection

If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular

program code can be placed at these locations. The most typical and general program setup for

the Reset and Interrupt Vector Addresses in ATtiny261/461/861 is:

Address Labels Code

Comments

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

rjmp

RESET

; Reset Handler

EXT_INT0

PCINT

; IRQ0 Handler

; PCINT Handler

TIM1_COMPA

TIM1_COMPB

TIM1_OVF

TIM0_OVF

; Timer1 CompareA Handler

; Timer1 CompareB Handler

; Timer1 Overflow Handler

; Timer0 Overflow Handler

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ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

0x0007

0x0008

0x0009

0x000A

0x000B

0x000C

0x000D

0x000E

0x000F

0x0010

0x0011

0x0012

rjmp

USI_START

USI_OVF

EE_RDY

; USI Start Handler

; USI Overflow Handler

; EEPROM Ready Handler

; Analog Comparator Handler

; ADC Conversion Handler

; WDT Interrupt Handler

; IRQ1 Handler

ANA_COMP

ADC

WDT

EXT_INT1

TIM0_COMPA

TIM0_COMPB

TIM0_CAPT

TIM1_COMPD

; Timer0 CompareA Handler

; Timer0 CompareB Handler

; Timer0 Capture Event Handler

; Timer1 CompareD Handler

FAULT_PROTECTION ; Timer1 Fault Protection

r16, low(RAMEND) ; Main program start

r17, high(RAMEND); Tiny861 have also SPH

0x0013 RESET: ldi

0x0014

0x0015

0x0016

0x0017

0x0018

...

ldi

out

SPL, r16

SPH, r17

; Set Stack Pointer to top of RAM

; Tiny861 have also SPH

; Enable interrupts

out

sei

<instr> xxx

...

... ...

49

2588B–AVR–11/06

11. External Interrupts

The External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT15..0 pins.

Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT15..0 pins are

configured as outputs. This feature provides a way of generating a software interrupt. Pin

change interrupts PCI will trigger if any enabled PCINT15..0 pin toggles. The PCMSK Register

control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT15..0

are detected asynchronously. This implies that these interrupts can be used for waking the part

also from sleep modes other than Idle mode.

The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is

set up as indicated in the specification for the MCU Control Register – MCUCR. When the INT0

interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the

pin is held low. Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires

the presence of an I/O clock, described in ”Clock Systems and their Distribution” on page 24.

Low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be

used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in

all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described

in ”System Clock and Clock Options” on page 24.

11.1 Register Description

11.1.1

MCUCR – MCU Control Register

The MCU Register contains control bits for interrupt sense control.

Bit

7

–

R

0

6

5

4

3

2

–

R

0

1

0

0x35 (0x55)

Read/Write

Initial Value

PUD

R/W

0

SE

R/W

0

SM1

R/W

0

SM0

R/W

0

ISC01

R/W

0

ISC00

R/W

0

MCUCR

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 or INT1 if the SREG I-flag and the

corresponding interrupt mask are set. The level and edges on the external INT0 or INT1 pin that

activate the interrupt are defined in Table 11-1. The value on the INT0 or INT1 pin is sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one

clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-

rupt. If low level interrupt is selected, the low level must be held until the completion of the

currently executing instruction to generate an interrupt.

Table 11-1. Interrupt 0 Sense Control

ISC01

ISC00

Description

0

1

0

1

0

1

The low level of INT0 or INT1 generates an interrupt request.

Any logical change on INT0 or INT1 generates an interrupt request.

The falling edge of INT0 or INT1 generates an interrupt request.

The rising edge of INT0 or INT1 generates an interrupt request.

50

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

11.1.2

GIMSK – General Interrupt Mask Register

Bit

7

6

5

4

3

–

R

0

2

–

R

0

1

–

R

0

–

R

0

0x3B (0x5B)

Read/Write

Initial Value

INT1

R/W

0

INT0

R/W

0

PCIE1

R/W

0

PCIE0

R/w

0

GIMSK

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU

Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-

ing edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even

if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is

executed from the INT1 Interrupt Vector.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU

Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-

ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even

if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is

executed from the INT0 Interrupt Vector.

• Bit 5 – PCIE1: Pin Change Interrupt Enable

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt is enabled. Any change on any enabled PCINT7..0 or PCINT15..12 pin will

cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed

from the PCI Interrupt Vector. PCINT7..0 and PCINT15..12 pins are enabled individually by the

PCMSK0 and PCMSK1 Register.

• Bit 4 – PCIE0: Pin Change Interrupt Enable

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt is enabled. Any change on any enabled PCINT11..8 pin will cause an interrupt.

The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt

Vector. PCINT11..8 pins are enabled individually by the PCMSK1 Register.

• Bits 3..0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and will always read as zero.

11.1.3

GIFR – General Interrupt Flag Register

Bit

0x3A (0x5A)

7

6

5

4

–

R

0

3

–

R

0

2

–

R

0

1

–

R

0

–

R

0

INT1

INTF0

R/W

0

PCIF

R/W

0

GIFR

Read/Write

Initial Value

R/W

0

• Bit 7– INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set

(one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

51

2588B–AVR–11/06

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT1 is configured as a level interrupt.

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set

(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

• Bit 5 – PCIF: Pin Change Interrupt Flag

When a logic change on any PCINT15 pin triggers an interrupt request, PCIF becomes set

(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it.

• Bits 4:0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and will always read as zero.

11.1.4

PCMSK0 – Pin Change Mask Register A

Bit

0x23 (0x43)

7

6

5

4

3

2

1

0

PCINT7

PCINT6

R/W

1

PCINT5

R/W

0

PCINT4

R/w

PCINT3

R/W

1

PCINT2

R/W

0

PCINT1

R/W

0

PCINT0

R/W

0

PCMSK0

Read/Write

Initial Value

R/W

1

0

• Bits 7:0 – PCINT7:0: Pin Change Enable Mask 7..0

Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.

If PCINT7:0 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the cor-

responding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is

disabled.

11.1.5

PCMSK1 – Pin Change Mask Register B

Bit

0x22 (0x42)

7

6

5

4

3

2

1

0

PCINT15

PCINT14

PCINT13

PCINT12

PCINT11

PCINT10

PCINT9

R/W

1

PCINT8

R/W

1

PCMSK1

Read/Write

Initial Value

R/W

1

R/W

1

R/W

1

R/w

1

R/W

1

R/W

1

• Bits 7:0 – PCINT15:8: Pin Change Enable Mask 15..8

Each PCINT15:8 bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT11:8 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on

the corresponding I/O pin, and if PCINT15:12 is set and the PCIE1 bit in GIMSK is set, pin

change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change

interrupt on the corresponding I/O pin is disabled.

52

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ATtiny261/461/861

12. I/O Ports

12.1 Overview

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.

This means that the direction of one port pin can be changed without unintentionally changing

the direction of any other pin with the SBI and CBI instructions. The same applies when chang-

ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as

input). Each output buffer has symmetrical drive characteristics with both high sink and source

capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-

vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have

protection diodes to both V_CCand Ground as indicated in Figure 12-1. Refer to ”Electrical Char-

acteristics” on page 185 for a complete list of parameters.

Figure 12-1. I/O Pin Equivalent Schematic

R_PU

Pxn

Logic

C_PIN

See Figure

"General Digital I/O" for

Details

All registers and bit references in this section are written in general form. A lower case “x” repre-

sents the numbering letter for the port, and a lower case “n” represents the bit number. However,

when using the register or bit defines in a program, the precise form must be used. For example,

PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-

ters and bit locations are listed in ”Register Description” on page 68.

Three I/O memory address locations are allocated for each port, one each for the Data Register

– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins

I/O location is read only, while the Data Register and the Data Direction Register are read/write.

However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-

ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the

pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in ”Ports as General Digital I/O” on page

54. Most port pins are multiplexed with alternate functions for the peripheral features on the

device. How each alternate function interferes with the port pin is described in ”Alternate Port

Functions” on page 58. Refer to the individual module sections for a full description of the alter-

nate functions.

53

2588B–AVR–11/06

Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the port as general digital I/O.

12.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 12-2 shows a func-

tional description of one I/O-port pin, here generically called Pxn.

Figure 12-2. General Digital I/O⁽¹⁾

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

1

0

Q

D

Pxn

PORTxn

Q _CLR

RESET

WPx

WRx

SLEEP

RRx

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

clk _I/O

WDx:

RDx:

WRx:

RRx:

RPx:

WPx:

WRITE DDRx

READ DDRx

WRITE PORTx

PUD:

SLEEP:

clk_I/O

PULLUP DISABLE

SLEEP CONTROL

I/O CLOCK

:

READ PORTx REGISTER

READ PORTx PIN

WRITE PINx REGISTER

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

,

SLEEP, and PUD are common to all ports.

12.2.1

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in ”Register

Description” on page 68, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits

at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input

pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is

activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to

be configured as an output pin. The port pins are tri-stated when reset condition becomes active,

even if no clocks are running.

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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

12.2.2

12.2.3

Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

Note that the SBI instruction can be used to toggle one single bit in a port.

Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output

low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-

able, as a high-impedant environment will not notice the difference between a strong high driver

and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all

pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b10) as an intermediate step.

Table 12-1 summarizes the control signals for the pin value.

Table 12-1. Port Pin Configurations

PUD

DDxn

PORTxn

(in MCUCR)

I/O

Pull-up

No

Comment

0

1

0

1

0

1

X

0

Input

Tri-state (Hi-Z)

Input

Yes

No

Pxn will source current if ext. pulled low.

Tri-state (Hi-Z)

1

Input

X

Output

No

Output Low (Sink)

Output High (Source)

No

12.2.4

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 12-2, the PINxn Register bit and the preceding latch con-

stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value

near the edge of the internal clock, but it also introduces a delay. Figure 12-3 shows a timing dia-

gram of the synchronization when reading an externally applied pin value. The maximum and

minimum propagation delays are denoted t_pd,maxand t_pd,minrespectively.

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Figure 12-3. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

XXX

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_{pd, max}

0xFF

r17

t_{pd, min}

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-

cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 12-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of

the clock. In this case, the delay tpd through the synchronizer is one system clock period.

Figure 12-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

0xFF

r16

out PORTx, r16

nop

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_pd

0xFF

r17

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define

the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values

are read back again, but as previously discussed, a nop instruction is included to be able to read

back the value recently assigned to some of the pins.

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Assembly Code Example⁽¹⁾

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB4)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in

r16,PINB

...

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB4)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

_NOP();

/* Read port pins */

i = PINB;

...

Note:

1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as

low and redefining bits 0 and 1 as strong high drivers.

12.2.5

Digital Input Enable and Sleep Modes

As shown in Figure 12-2, the digital input signal can be clamped to ground at the input of the

schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in

Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if

some input signals are left floating, or have an analog signal level close to V_CC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt

request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various

other alternate functions as described in ”Alternate Port Functions” on page 58.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as

“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt

is not enabled, the corresponding External Interrupt Flag will be set when resuming from the

above mentioned Sleep mode, as the clamping in these sleep mode produces the requested

logic change.

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12.2.6

Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even

though most of the digital inputs are disabled in the deep sleep modes as described above, float-

ing inputs should be avoided to reduce current consumption in all other modes where the digital

inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.

In this case, the pull-up will be disabled during reset. If low power consumption during reset is

important, it is recommended to use an external pull-up or pulldown. Connecting unused pins

directly to V_CCor GND is not recommended, since this may cause excessive currents if the pin is

accidentally configured as an output.

12.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 12-5

shows how the port pin control signals from the simplified Figure 12-2 can be overridden by

alternate functions. The overriding signals may not be present in all port pins, but the figure

serves as a generic description applicable to all port pins in the AVR microcontroller family.

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Figure 12-5. Alternate Port Functions⁽¹⁾

PUOExn

PUOVxn

1

0

PUD

DDOExn

DDOVxn

1

0

Q

D

DDxn

Q _CLR

WDx

RDx

PVOExn

PVOVxn

RESET

1

0

1

Pxn

Q

D

0

PORTxn

PTOExn

Q _CLR

DIEOExn

DIEOVxn

SLEEP

WPx

RESET

WRx

RRx

1

0

SYNCHRONIZER

RPx

SET

D

Q

D

L

Q

PINxn

_CLRQ

CLR

clk _I/O

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

PUD:

WDx:

RDx:

RRx:

WRx:

RPx:

WPx:

PULLUP DISABLE

WRITE DDRx

READ DDRx

READ PORTx REGISTER

WRITE PORTx

READ PORTx PIN

WRITE PINx

I/O CLOCK

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

clk_I/O

:

SLEEP:

SLEEP CONTROL

DIxn:

AIOxn:

DIGITAL INPUT PIN n ON PORTx

ANALOG INPUT/OUTPUT PIN n ON PORTx

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

,

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

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Table 12-2 summarizes the function of the overriding signals. The pin and port indexes from Fig-

ure 12-5 are not shown in the succeeding tables. The overriding signals are generated internally

in the modules having the alternate function.

Table 12-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name

Full Name

Description

If this signal is set, the pull-up enable is controlled by the PUOV

signal. If this signal is cleared, the pull-up is enabled when

{DDxn, PORTxn, PUD} = 0b010.

Pull-up Override

Enable

PUOE

If PUOE is set, the pull-up is enabled/disabled when PUOV is

set/cleared, regardless of the setting of the DDxn, PORTxn,

and PUD Register bits.

Pull-up Override

Value

PUOV

DDOE

DDOV

If this signal is set, the Output Driver Enable is controlled by the

DDOV signal. If this signal is cleared, the Output driver is

enabled by the DDxn Register bit.

Data Direction

Override Enable

If DDOE is set, the Output Driver is enabled/disabled when

DDOV is set/cleared, regardless of the setting of the DDxn

Register bit.

Data Direction

Override Value

If this signal is set and the Output Driver is enabled, the port

value is controlled by the PVOV signal. If PVOE is cleared, and

the Output Driver is enabled, the port Value is controlled by the

PORTxn Register bit.

Port Value

Override Enable

PVOE

Port Value

Override Value

If PVOE is set, the port value is set to PVOV, regardless of the

setting of the PORTxn Register bit.

PVOV

PTOE

Port Toggle

Override Enable

If PTOE is set, the PORTxn Register bit is inverted.

Digital Input

Enable Override

Enable

If this bit is set, the Digital Input Enable is controlled by the

DIEOV signal. If this signal is cleared, the Digital Input Enable

is determined by MCU state (Normal mode, sleep mode).

DIEOE

DIEOV

Digital Input

Enable Override

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state (Normal

mode, sleep mode).

This is the Digital Input to alternate functions. In the figure, the

signal is connected to the output of the schmitt-trigger but

before the synchronizer. Unless the Digital Input is used as a

clock source, the module with the alternate function will use its

own synchronizer.

DI

Digital Input

This is the Analog Input/Output to/from alternate functions. The

signal is connected directly to the pad, and can be used bi-

directionally.

Analog

Input/Output

AIO

The following subsections shortly describe the alternate functions for each port, and relate the

overriding signals to the alternate function. Refer to the alternate function description for further

details.

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12.3.1

Alternate Functions of Port B

The Port B pins with alternate function are shown in Table 12-3.

Table 12-3. Port B Pins Alternate Functions

Port Pin

PB7

Alternate Function

RESET / dW / ADC10 / PCINT15

ADC9 / T0 / INT0 / PCINT14

PB6

PB5

XTAL2 / CLKO / OC1D / ADC8 / PCINT13

XTAL1 / CLKI / OC1D / ADC7 / PCINT12

OC1B / PCINT11

PB4

PB3

PB2

SCK / USCK / SCL / OC1B /PCINT10

MISO / DO / OC1A / PCINT9

MOSI / DI / SDA / OC1A / PCINT8

PB1

PB0

The alternate pin configuration is as follows:

• Port B, Bit 7 - RESET/ dW/ ADC10/ PCINT15

RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O

pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources.

When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the

pin can not be used as an I/O pin.

If PB7 is used as a reset pin, DDB7, PORTB7 and PINB7 will all read 0.

dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unpro-

grammed, the RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin

with pull-up enabled and becomes the communication gateway between target and emulator.

ADC10: ADC input Channel 10. Note that ADC input channel 10 uses analog power.

PCINT15: Pin Change Interrupt source 15.

• Port B, Bit 6 - ADC9/ T0/ INT0/ PCINT14

ADC9: ADC input Channel 9. Note that ADC input channel 9 uses analog power.

T0: Timer/Counter0 counter source.

INT0: The PB6 pin can serve as an External Interrupt source 0.

PCINT14: Pin Change Interrupt source 14.

• Port B, Bit 5 - XTAL2/ CLKO/ ADC8/ PCINT13

XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency

crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

CLKO: The divided system clock can be output on the PB5 pin, if the CKOUT Fuse is pro-

grammed, regardless of the PORTB5 and DDB5 settings. It will also be output during reset.

OC1D Output Compare Match output: The PB5 pin can serve as an external output for the

Timer/Counter1 Compare Match D when configured as an output (DDA1 set). The OC1D pin is

also the output pin for the PWM mode timer function.

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ADC8: ADC input Channel 8. Note that ADC input channel 8 uses analog power.

PCINT13: Pin Change Interrupt source 13.

• Port B, Bit 4 - XTAL1/ CLKI/ OC1B/ ADC7/ PCINT12

XTAL1/CLKI: Chip clock Oscillator pin 1. Used for all chip clock sources except internal cali-

brated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

OC1D: Inverted Output Compare Match output: The PB4 pin can serve as an external output for

the Timer/Counter1 Compare Match D when configured as an output (DDA0 set). The OC1D pin

is also the inverted output pin for the PWM mode timer function.

ADC7: ADC input Channel 7. Note that ADC input channel 7 uses analog power.

PCINT12: Pin Change Interrupt source 12.

• Port B, Bit 3 - OC1B/ PCINT11

OC1B, Output Compare Match output: The PB3 pin can serve as an external output for the

Timer/Counter1 Compare Match B. The PB3 pin has to be configured as an output (DDB3 set

(one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer

function.

PCINT11: Pin Change Interrupt source 11.

• Port B, Bit 2 - SCK/ USCK/ SCL/ OC1B/ PCINT10

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a

Slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDB2. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit.

USCK: Three-wire mode Universal Serial Interface Clock.

SCL: Two-wire mode Serial Clock for USI Two-wire mode.

OC1B: Inverted Output Compare Match output: The PB2 pin can serve as an external output for

the Timer/Counter1 Compare Match B when configured as an output (DDB2 set). The OC1B pin

is also the inverted output pin for the PWM mode timer function.

PCINT10: Pin Change Interrupt source 10.

• Port B, Bit 1 - MISO/ DO/ OC1A/ PCINT9

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a

Master, this pin is configured as an input regardless of the setting of DDB1. When the SPI is

enabled as a Slave, the data direction of this pin is controlled by DDB1. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB1 bit.

DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data output over-

rides PORTB1 value and it is driven to the port when data direction bit DDB1 is set (one).

PORTB1 still enables the pull-up, if the direction is input and PORTB1 is set (one).

OC1A: Output Compare Match output: The PB1 pin can serve as an external output for the

Timer/Counter1 Compare Match B when configured as an output (DDB1 set). The OC1A pin is

also the output pin for the PWM mode timer function.

PCINT9: Pin Change Interrupt source 9.

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• Port B, Bit 0 - MOSI/ DI/ SDA/ OC1A/ PCINT8

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a

Slave, this pin is configured as an input regardless of the setting of DDB0. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB0 bit.

DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port

functions, so pin must be configure as an input for DI function.

SDA: Two-wire mode Serial Interface Data.

OC1A: Inverted Output Compare Match output: The PB0 pin can serve as an external output for

the Timer/Counter1 Compare Match B when configured as an output (DDB0 set). The OC1A pin

is also the inverted output pin for the PWM mode timer function.

PCINT8: Pin Change Interrupt source 8.

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Table 12-4 and Table 12-5 relate the alternate functions of Port B to the overriding signals

shown in Figure 12-5 on page 59.

Table 12-4. Overriding Signals for Alternate Functions in PB7..PB4

Signal PB7/RESET/dW/

PB6/ADC9/T0/INT0/ PB5/XTAL2/CLKO/

PB4/XTAL1/OC1D/

ADC7/PCINT12⁽¹⁾

Name

PUOE

PUOV

DDOE

ADC10/PCINT15

PCINT14

OC1D/ADC8/PCINT13⁽¹⁾

INTRC • EXTCLK

0

RSTDISBL⁽¹⁾

DWEN⁽¹⁾

•

0

INTRC

0

1

RSTDISBL⁽¹⁾

DWEN⁽¹⁾

INTRC • EXTCLK

INTRC

DDOV

PVOE

PVOV

PTOE

debugWire Transmit 0

0

OC1D Enable

OC1D

0

OC1D

0

RSTDISBL + (PCINT5 INTRC • EXTCLK + PCINT4 • INTRC + PCINT12

DIEOE

0

• PCIE + ADC9D)

PCIE + ADC8D

• PCIE + ADC7D

DIEOV ADC10D

ADC9D

(INTRC • EXTCLK) + ADC8D INTRC • ADC7D

DI

PCINT15

T0/INT0/PCINT14

ADC9

PCINT13

PCINT12

AIO

RESET / ADC10

XTAL2, ADC8

XTAL1, ADC7

Note:

1. 1 when the Fuse is “0” (Programmed).

Table 12-5. Overriding Signals for Alternate Functions in PB3..PB0

PB3/OC1B/

Signal

Name PCINT11

PB2/SCK/USCK/SCL/

OC1B/PCINT10

PB1/MISO/DO/OC1A/

PCINT9

PB0/MOSI/DI/SDA/

OC1A/PCINT8

PUOE

PUOV

0

USI_TWO_WIRE •

USIPOS

DDOE

DDOV

0

USI_TWO_WIRE • USIPOS

0

(USI_SCL_HOLD +

PORTB2) • DDB2 • USIPOS

(SDA + PORTB0) •

DDRB0 • USIPOS

OC1A Enable +

OC1B Enable + USIPOS •

USI_TWO_WIRE • DDRB2

OC1A Enable + USIPOS

• USI_THREE_WIRE

PVOE OC1B Enable

PVOV OC1B

(USI_TWO_WIRE •

DDRB0 • USIPOS)

OC1B

OC1A + (DO • USIPOS) OC1A

PTOE

0

USI_PTOE • USIPOS

0

PCINT10 • PCIE + USISIE •

USIPOS

PCINT8 • PCIE +

(USISIE • USIPOS)

DIEOE PCINT11 • PCIE

PCINT9 • PCIE

DIEOV

DI

0

PCINT11

USCK/SCL/PCINT10

PCINT9

DI/SDA/PCINT8

AIO

Note:

1. INTRC means that one of the internal RC Oscillators are selected (by the CKSEL fuses),

EXTCK means that external clock is selected (by the CKSEL fuses).

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12.3.2

Alternate Functions of Port A

The Port A pins with alternate function are shown in Table 12-6.

Table 12-6. Port B Pins Alternate Functions

Port Pin

PA7

Alternate Function

ADC6 / AIN0 / PCINT7

ADC5 / AIN1 / PCINT6

ADC4 / AIN2 / PCINT5

ADC3 /ICP0/ PCINT4

AREF / PCINT3

PA6

PA5

PA4

PA3

PA2

ADC2 / INT1 / USCK / SCL / PCINT2

ADC1 / DO / PCINT1

PA1

PA0

ADC0 / DI / SDA / PCINT0

The alternate pin configuration is as follows:

• Port A, Bit 7- ADC6/AIN0/PCINT7

ADC6: Analog to Digital Converter, Channel 6.

AIN0: Analog Comparator Input. Configure the port pin as input with the internal pull-up switched

off to avoid the digital port function from interfering with the function of the Analog Comparator.

PCINT7: Pin Change Interrupt source 8.

• Port A, Bit 6 - ADC5/AIN1/PCINT6

ADC5: Analog to Digital Converter, Channel 5.

AIN1: Analog Comparator Input. Configure the port pin as input with the internal pull-up switched

off to avoid the digital port function from interfering with the function of the Analog Comparator.

PCINT6: Pin Change Interrupt source 6.

• Port A, Bit 5 - ADC4/AIN2/PCINT5

ADC4: Analog to Digital Converter, Channel 4.

AIN2: Analog Comparator Input. Configure the port pin as input with the internal pull-up switched

off to avoid the digital port function from interfering with the function of the Analog Comparator.

PCINT5: Pin Change Interrupt source 5.

• Port A, Bit 4 - ADC3/ICP0/PCINT4

ADC3: Analog to Digital Converter, Channel 3.

ICP0: Timer/Counter0 Input Capture Pin.

PCINT4: Pin Change Interrupt source 4.

• Port A, Bit 3 - AREF/PCINT3

AREF: External analog reference for ADC. Pullup and output driver are disabled on PA3 when

the pin is used as an external reference or internal voltage reference with external capacitor at

the AREF pin.

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PCINT3: Pin Change Interrupt source 3.

• Port A, Bit 2 - ADC2/INT1/USCK/SCL/PCINT2

ADC2: Analog to Digital Converter, Channel 2.

INT1: The PA2 pin can serve as an External Interrupt source 1.

USCK: Three-wire mode Universal Serial Interface Clock.

SCL: Two-wire mode Serial Clock for USI Two-wire mode.

PCINT2: Pin Change Interrupt source 2.

• Port A, Bit 1 - ADC1/DO/PCINT1

ADC1: Analog to Digital Converter, Channel 1.

DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data output over-

rides PORTA1 value and it is driven to the port when data direction bit DDA1 is set. PORTA1 still

enables the pull-up, if the direction is input and PORTA1 is set.

PCINT1: Pin Change Interrupt source 1.

• Port A, Bit 0 - ADC0/DI/SDA/PCINT0

ADC0: Analog to Digital Converter, Channel 0.

DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port

functions, so pin must be configure as an input for DI function.

SDA: Two-wire mode Serial Interface Data.

PCINT0: Pin Change Interrupt source 0.

Table 12-7 and Table 12-8 relate the alternate functions of Port A to the overriding signals

shown in Figure 12-5 on page 59.

Table 12-7. Overriding Signals for Alternate Functions in PA7..PA4

PA7/ADC6/AIN0/

PCINT7

PA6/ADC5/AIN1/

PCINT6

PA5/ADC4/AIN2/

PCINT5

PA4/ADC3/ICP0/

PCINT4

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

0

PCINT7 • PCIE +

ADC6D

PCINT6 • PCIE +

ADC5D

PCINT5 • PCIE +

ADC4D

PCINT4 • PCIE +

ADC3D

DIEOV

DI

ADC6D

ADC5D

ADC4D

ADC3D

PCINT7

PCINT6

PCINT5

ICP0/PCINT4

ADC3

AIO

ADC6, AIN0

ADC5, AIN1

ADC4, AIN2

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Table 12-8. Overriding Signals for Alternate Functions in PA3..PA0

PA3/AREF/

PCINT3

PA2/ADC2/INT1/

PA1/ADC1/DO/

PCINT1

PA0/ADC0/DI/SDA/

PCINT0

Signal

Name

USCK/SCL/PCINT2

PUOE

PUOV

DDOE

0

USI_TWO_WIRE • USIPOS

USI_TWO_WIRE •

USIPOS

0

DDOV

PVOE

0

(USI_SCL_HOLD +

PORTB2) • DDB2 • USIPOS

(SDA + PORTB0) •

DDRB0 • USIPOS

USI_TWO_WIRE • DDRB2 USI_THREE_WIRE USI_TWO_WIRE •

• USIPOS

DO • USIPOS

0

DDRB0 • USIPOS

PVOV

PTOE

DIEOE

0

USI_PTOE • USIPOS

PCINT3 • PCIE PCINT2 • PCIE + INT1 +

PCINT1 • PCIE +

ADC2D + USISIE • USIPOS ADC1D

PCINT0 • PCIE + ADC0D

+ USISIE • USIPOS

DIEOV

DI

0

ADC2D

ADC1D

PCINT1

ADC1

ADC0D

PCINT3

AREF

USCK/SCL/INT1/ PCINT2

ADC2

DI/SDA/PCINT0

ADC0

AIO

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2588B–AVR–11/06

12.4 Register Description

12.4.1

MCUCR – MCU Control Register

Bit

7

-

6

5

4

3

2

-

1

0

0x35 (0x55)

Read/Write

Initial Value

PUD

R/W

0

SE

R/W

0

SM1

R/W

0

SM0

R/W

0

ISC01

ISC00

MCUCR

R

0

R

0

R

0

R

0

• Bit 6 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and

PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See ”Con-

figuring the Pin” on page 54 for more details about this feature.

12.4.2

12.4.3

12.4.4

PORTA – Port A Data Register

Bit

7

6

5

4

3

2

1

0

0x1B (0x3B)

Read/Write

Initial Value

PORTA7

R/W

PORTA6

R/W

PORTA5

R/W

PORTA4

PORTA3

R/W

PORTA2

R/W

PORTA1

R/W

PORTA0

R/W

PORTA

DDRA

PINA

R/W

0

DDRA – Port A Data Direction Register

Bit

7

6

5

4

3

2

1

0

0x1A (0x3A)

Read/Write

Initial Value

DDA7

R/W

0

DDA6

R/W

0

DDA5

R/W

0

DDA4

R/W

0

DDA3

R/W

0

DDA2

R/W

0

DDA1

R/W

0

DDA0

R/W

0

PINA – Port A Input Pins Address

Bit

7

6

5

4

3

2

1

0

0x19 (0x39)

Read/Write

Initial Value

PINA7

R/W

N/A

PINA6

R/W

N/A

PINA5

R/W

N/A

PINA4

R/W

N/A

PINA3

R/W

N/A

PINA2

R/W

N/A

PINA1

R/W

N/A

PINA0

R/W

N/A

12.4.5

12.4.6

12.4.7

PORTB – Port B Data Register

Bit

7

6

5

4

3

2

1

0

0x18 (0x38)

Read/Write

Initial Value

PORTB7

PORTB6

PORTB5

PORTB4

PORTB3

PORTB2

PORTB1

PORTB0

PORTB

DDRB

PINB

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

DDRB – Port B Data Direction Register

Bit

7

6

5

4

3

2

1

0

0x17 (0x37)

Read/Write

Initial Value

DDB7

R/W

0

DDB6

R/W

0

DDB5

R/W

0

DDB4

R/W

0

DDB3

R/W

0

DDB2

R/W

0

DDB1

R/W

0

DDB0

R/W

0

PINB – Port B Input Pins Address

Bit

7

6

5

4

3

2

1

0

0x16 (0x36)

Read/Write

Initial Value

PINB7

R/W

N/A

PINB6

R/W

N/A

PINB5

R/W

N/A

PINB4

R/W

N/A

PINB3

R/W

N/A

PINB2

R/W

N/A

PINB1

R/W

N/A

PINB0

R/W

N/A

68

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ATtiny261/461/861

13. Timer/Counter0 Prescaler

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This

provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

clock frequency (f_{CLK_I/O}). Alternatively, one of four taps from the prescaler can be used as a

clock source. The prescaled clock has a frequency of either f_{CLK_I/O}/8, f_{CLK_I/O}/64, f_{CLK_I/O}/256, or

f_{CLK_I/O}/1024. See Table 13-1 on page 71 for details.

13.0.1

Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the

Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state

of the prescaler will have implications for situations where a prescaled clock is used. One exam-

ple of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >

CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count

occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64,

256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to

program execution.

13.0.2

External Clock Source

An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk_T0). The

T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-

nized (sampled) signal is then passed through the edge detector. Figure 13-1 shows a functional

equivalent block diagram of the T0 synchronization and edge detector logic. The registers are

clocked at the positive edge of the internal system clock (clk_I/O). The latch is transparent in the

high period of the internal system clock.

The edge detector generates one clk_T₀pulse for each positive (CSn2:0 = 7) or negative (CSn2:0

= 6) edge it detects. See Table 13-1 on page 71 for details.

Figure 13-1. T0 Pin Sampling

Tn_sync

(To Clock

Tn

D

Q

D

Q

D

Q

Select Logic)

LE

clk_I/O

Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T0 has been stable for at least one

system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f_ExtClk< f_{clk_I/O}/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f_{clk_I/O}/2.5.

69

2588B–AVR–11/06

An external clock source can not be prescaled.

Figure 13-2. Prescaler for Timer/Counter0

clk_I/O

Clear

PSR0

T0

Synchronization

clk_T0

Note:

1. The synchronization logic on the input pins (T0) is shown in Figure 13-1.

13.1 Register Description

13.1.1

TCCR0B – Timer/Counter0 Control Register B

Bit

7

-

6

-

5

-

4

3

PSR0

R/W

0

2

CS02

R/W

0

1

0

CS01

R/W

0

0x33 (0x53)

Read/Write

Initial Value

TSM

R/W

0

CS01

R/W

0

TCCR0B

R

0

R

0

R

0

• Bit 4 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSR0 bit is kept, hence keeping the Prescaler Reset signal asserted.

This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-

ing during configuration. When the TSM bit is written to zero, the PSR0 bit is cleared by

hardware, and the Timer/Counter start counting.

• Bit 3 – PSR0: Prescaler Reset Timer/Counter0

When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared

immediately by hardware, except if the TSM bit is set.

• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bit 2, 1, and 0

The Clock Select0 bits 2, 1, and 0 define the prescaling source of Timer0.

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ATtiny261/461/861

Table 13-1. Clock Select Bit Description

CS02

CS01

CS00

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped)

clk_I/O/(No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on T0 pin. Clock on falling edge.

External clock source on T0 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

71

2588B–AVR–11/06

14. Timer/Counter0

14.1 Features

• Clear Timer on Compare Match (Auto Reload)

• Input Capture unit

• Four Independent Interrupt Sources (TOV0, OCF0A, OCF0B, ICF0)

• 8-bit Mode with Two Independent Output Compare Units

• 16-bit Mode with One Independent Output Compare Unit

14.2 Overview

Timer/Counter0 is a general purpose 8-/16-bit Timer/Counter module, with two/one Output Com-

pare units and Input Capture feature.

The Timer/Counter0 general operation is described in 8-/16-bit mode. A simplified block diagram

of the 8-/16-bit Timer/Counter is shown in Figure 14-1. For the actual placement of I/O pins, refer

to ”Pinout ATtiny261/461/861” on page 2. CPU accessible I/O Registers, including I/O bits and

I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the

”Register Description” on page 84.

Figure 14-1. 8-/16-bit Timer/Counter Block Diagram

TOVn (Int. Req.)

Count

Clock Select

Clear

Direction

Control Logic

Edge

Detector

Tn

clk_Tn

( From Prescaler )

TOP

Timer/Counter

TCNTnL

=

TCNTnH

Fixed TOP value

OCnA (Int. Req.)

OCnB (Int. Req.)

=

ICFn (Int. Req.)

OCRnB

OCRnA

( From Analog

Comparator Ouput )

Edge

Noise

Detector

Canceler

TCCRnA

TCCRnB

ICPn

14.2.1

Registers

The Timer/Counter0 Low Byte Register (TCNT0L) and Output Compare Registers (OCR0A and

OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in Figure 14-1) signals are

all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with

the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure.

In 16-bit mode the Timer/Counter consists one more 8-bit register, the Timer/Counter0 High

Byte Register (TCNT0H). Furthermore, there is only one Output Compare Unit in 16-bit mode as

the two Output Compare Registers, OCR0A and OCR0B, are combined to one 16-bit Output

Compare Register. OCR0A contains the low byte of the word and OCR0B contains the high byte

of the word. When accessing 16-bit registers, special procedures described in section ”Access-

ing Registers in 16-bit Mode” on page 80 must be followed.

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ATtiny261/461/861

14.2.2

Definitions

Many register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-

pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or

bit defines in a program, the precise form must be used, i.e., TCNT0L for accessing

Timer/Counter0 counter value and so on.

The definitions in Table 14-1 are also used extensively throughout the document.

Table 14-1. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0.

The counter reaches its MAXimum when it becomes 0xFF (decimal 255) in 8-bit mode or

0xFFFF (decimal 65535) in 16-bit mode.

MAX

The counter reaches the TOP when it becomes equal to the highest value in the count

TOP

sequence. The TOP value can be assigned to be the fixed value 0xFF/0xFFFF (MAX) or

the value stored in the OCR0A Register.

14.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T0 pin. The Clock Select logic is controlled by the Clock Select (CS02:0) bits located in the

Timer/Counter Control Register 0 B (TCCR0B), and controls which clock source and edge the

Timer/Counter uses to increment its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk_T0). For

details on clock sources and prescaler, see ”Timer/Counter0 Prescaler” on page 69.

14.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

14-3 shows a block diagram of the counter and its surroundings.

Table 14-2. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

Clock Select

Edge

Detector

Tn

clk_Tn

count

TCNTn

Control Logic

( From Prescaler )

top

Signal description (internal signals):

count

clk_Tn

top

Increment or decrement TCNT0 by 1.

Timer/Counter clock, referred to as clk_T0in the following.

Signalize that TCNT0 has reached maximum value.

The counter is incremented at each timer clock (clk_T0) until it passes its TOP value and then

restarts from BOTTOM. The counting sequence is determined by the setting of the WGM00 bits

located in the Timer/Counter Control Register (TCCR0A). For more details about counting

sequences, see ”Modes of Operation” on page 74. clk_T0can be generated from an external or

73

2588B–AVR–11/06

internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is

selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the

CPU, regardless of whether clk_T0is present or not. A CPU write overrides (has priority over) all

counter clear or count operations. The Timer/Counter Overflow Flag (TOV0) is set when the

counter reaches the maximum value and it can be used for generating a CPU interrupt.

14.5 Modes of Operation

The mode of operation is defined by the Timer/Counter Width (TCW0), Input Capture Enable

(ICEN0) and Wave Generation Mode (WGM00) bits in ”TCCR0A – Timer/Counter0 Control Reg-

ister A” on page 84. Table 14-3 shows the different Modes of Operation.

Table 14-3. Modes of operation

Timer/Counter Mode

of Operation

TOV Flag

Set on

Update of

OCRx at

Mode

ICEN0

TCW0

WGM00

TOP

0xFF

0

1

2

3

4

0

1

0

1

0

1

0

1

Normal 8-bit Mode

8-bit CTC

Immediate

MAX (0xFF)

OCR0A

0xFFFF

0xFF

X

16-bit Mode

MAX (0xFFFF)

MAX (0xFF)

8-bit Input Capture Mode

16-bit Input Capture Mode

0xFFFF

MAX (0xFFFF)

14.5.1

Normal 8-bit Mode

In the Normal 8-bit mode, see Table 14-3 on page 74, the counter (TCNT0L) is incrementing

until it overruns when it passes its maximum 8-bit value (MAX = 0xFF) and then restarts from the

bottom (0x00). The Overflow Flag (TOV0) will be set in the same timer clock cycle as the

TCNT0L becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only

set, not cleared. However, combined with the timer overflow interrupt that automatically clears

the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to

consider in the Normal 8-bit mode, a new counter value can be written anytime. The Output

Compare Unit can be used to generate interrupts at some given time.

14.5.2

Clear Timer on Compare Match (CTC) 8-bit Mode

In Clear Timer on Compare or CTC mode, see Table 14-3 on page 74, the OCR0A Register is

used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the

counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter,

hence also its resolution. This mode allows greater control of the Compare Match output fre-

quency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 14-2. The counter value (TCNT0)

increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter

(TCNT0) is cleared.

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ATtiny261/461/861

Figure 14-2. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR0A is lower than the current

value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can

occur. As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle

that the counter counts from MAX to 0x00.

14.5.3

16-bit Mode

In 16-bit mode, see Table 14-3 on page 74, the counter (TCNT0H/L) is a incrementing until it

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

bottom (0x0000). The Overflow Flag (TOV0) will be set in the same timer clock cycle as the

TCNT0H/L becomes zero. The TOV0 Flag in this case behaves like a 17th bit, except that it is

only set, not cleared. However, combined with the timer overflow interrupt that automatically

clears the TOV0 Flag, the timer resolution can be increased by software. There are no special

cases to consider in the Normal mode, a new counter value can be written anytime. The Output

Compare Unit can be used to generate interrupts at some given time.

14.5.4

14.5.5

8-bit Input Capture Mode

The Timer/Counter0 can also be used in an 8-bit Input Capture mode, see Table 14-3 on page

74 for bit settings. For full description, see the section ”Input Capture Unit” on page 76.

16-bit Input Capture Mode

The Timer/Counter0 can also be used in a 16-bit Input Capture mode, see Table 14-3 on page

74 for bit settings. For full description, see the section ”Input Capture Unit” on page 76.

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2588B–AVR–11/06

14.6 Input Capture Unit

The Timer/Counter incorporates an Input Capture unit that can capture external events and give

them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-

tiple events, can be applied via the ICP0 pin or alternatively, via the analog-comparator unit. The

time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-

nal applied. Alternatively the time-stamps can be used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 14-3. The elements of

the block diagram that are not directly a part of the Input Capture unit are gray shaded.

Figure 14-3. Input Capture Unit Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

OCR0B (8-bit)

OCR0A (8-bit)

TCNT0H (8-bit)

TCNT0L (8-bit)

ICR0 (16-bit Register)

TCNT0 (16-bit Counter)

WRITE

ACO*

ACIC0*

ICNC0

ICES0

Analog

Comparator

Noise

Canceler

Edge

Detector

ICF0 (Int.Req.)

ICP0

The Output Compare Register OCR0A is a dual-purpose register that is also used as an 8-bit

Input Capture Register ICR0. In 16-bit Input Capture mode the Output Compare Register

OCR0B serves as the high byte of the Input Capture Register ICR0. In 8-bit Input Capture mode

the Output Compare Register OCR0B is free to be used as a normal Output Compare Register,

but in 16-bit Input Capture mode the Output Compare Unit cannot be used as there are no free

Output Compare Register(s). Even though the Input Capture register is called ICR0 in this sec-

tion, it is refering to the Output Compare Register(s).

When a change of the logic level (an event) occurs on the Input Capture pin (ICP0), alternatively

on the Analog Comparator output (ACO), and this change confirms to the setting of the edge

detector, a capture will be triggered. When a capture is triggered, the value of the counter

(TCNT0) is written to the Input Capture Register (ICR0). The Input Capture Flag (ICF0) is set at

the same system clock as the TCNT0 value is copied into Input Capture Register. If enabled

(TICIE0=1), the Input Capture Flag generates an Input Capture interrupt. The ICF0 flag is auto-

matically cleared when the interrupt is executed. Alternatively the ICF0 flag can be cleared by

software by writing a logical one to its I/O bit location.

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ATtiny261/461/861

14.6.1

Input Capture Trigger Source

The default trigger source for the Input Capture unit is the Input Capture pin (ICP0).

Timer/Counter0 can alternatively use the Analog Comparator output as trigger source for the

Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog

Comparator Input Capture Enable (ACIC0) bit in the Timer/Counter Control Register A

(TCCR0A). Be aware that changing trigger source can trigger a capture. The Input Capture Flag

must therefore be cleared after the change.

Both the Input Capture pin (ICP0) and the Analog Comparator output (ACO) inputs are sampled

using the same technique as for the T0 pin (Figure 13-1 on page 71). The edge detector is also

identical. However, when the noise canceler is enabled, additional logic is inserted before the

edge detector, which increases the delay by four system clock cycles. An Input Capture can also

be triggered by software by controlling the port of the ICP0 pin.

14.6.2

Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The

noise canceler input is monitored over four samples, and all four must be equal for changing the

output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC0) bit in

Timer/Counter Control Register B (TCCR0B). When enabled the noise canceler introduces addi-

tional four system clock cycles of delay from a change applied to the input, to the update of the

ICR0 Register. The noise canceler uses the system clock and is therefore not affected by the

prescaler.

14.6.3

Using the Input Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor capacity

for handling the incoming events. The time between two events is critical. If the processor has

not read the captured value in the ICR0 Register before the next event occurs, the ICR0 will be

overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the ICR0 Register should be read as early in the inter-

rupt handler routine as possible. The maximum interrupt response time is dependent on the

maximum number of clock cycles it takes to handle any of the other interrupt requests.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after

each capture. Changing the edge sensing must be done as early as possible after the ICR0

Register has been read. After a change of the edge, the Input Capture Flag (ICF0) must be

cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,

the trigger edge change is not required (if an interrupt handler is used).

14.7 Output Compare Unit

The comparator continuously compares Timer/Counter (TCNT0) with the Output Compare Reg-

isters (OCR0A and OCR0B), and whenever the Timer/Counter equals to the Output Compare

Regisers, the comparator signals a match. A match will set the Output Compare Flag at the next

timer clock cycle. In 8-bit mode the match can set either the Output Compare Flag OCF0A or

OCF0B, but in 16-bit mode the match can set only the Output Compare Flag OCF0A as there is

only one Output Compare Unit. If the corresponding interrupt is enabled, the Output Compare

Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared

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2588B–AVR–11/06

when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a log-

ical one to its I/O bit location. Figure 14-4 shows a block diagram of the Output Compare unit.

Figure 14-4. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

=

(8/16-bit Comparator )

OCFnx (Int.Req.)

14.7.1

14.7.2

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0H/L Register will block any Compare Match that occur in

the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A/B to be

initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter

clock is enabled.

Using the Output Compare Unit

Since writing TCNT0H/L will block all Compare Matches for one timer clock cycle, there are risks

involved when changing TCNT0H/L when using the Output Compare Unit, independently of

whether the Timer/Counter is running or not. If the value written to TCNT0H/L equals the

OCR0A/B value, the Compare Match will be missed.

14.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T0) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set. Figure 14-5 contains timing data for basic Timer/Counter operation. The figure

shows the count sequence close to the MAX value.

Figure 14-5. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 14-6 shows the same timing data, but with the prescaler enabled.

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Figure 14-6. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 14-7 shows the setting of OCF0A and OCF0B in Normal mode.

Figure 14-7. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.

Figure 14-8. Timer/Counter Timing Diagram, CTC mode, with Prescaler (f_{clk_I/O}/8)

clk_PCK

clk_Tn

(clk_PCK/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRnx

TOP

OCFnx

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14.9 Accessing Registers in 16-bit Mode

In 16-bit mode (the TCW0 bit is set to one) the TCNT0H/L and OCR0A/B or TCNT0L/H and

OCR0B/A are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The

16-bit register must be byte accessed using two read or write operations. The 16-bit

Timer/Counter has a single 8-bit register for temporary storing of the high byte of the 16-bit

access. The same temporary register is shared between all 16-bit registers. Accessing the low

byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written

by the CPU, the high byte stored in the temporary register, and the low byte written are both cop-

ied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read

by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same

clock cycle as the low byte is read.

There is one exception in the temporary register usage. In the Output Compare mode the 16-bit

Output Compare Register OCR0A/B is read without the temporary register, because the Output

Compare Register contains a fixed value that is only changed by CPU access. However, in 16-

bit Input Capture mode the ICR0 register formed by the OCR0A and OCR0B registers must be

accessed with the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low

byte must be read before the high byte.

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The following code examples show how to access the 16-bit timer registers assuming that no

interrupts updates the temporary register. The same principle can be used directly for accessing

the OCR0A/B registers.

Assembly Code Example

...

; Set TCNT0 to 0x01FF

ldir17,0x01

ldir16,0xFF

outTCNT0H,r17

outTCNT0L,r16

; Read TCNT0 into r17:r16

in r16,TCNT0L

in r17,TCNT0H

...

C Code Example

unsigned int i;

...

/* Set TCNT0 to 0x01FF */

TCNT0H = 0x01;

TCNT0L = 0xff;

/* Read TCNT0 into i */

i = TCNT0L;

i |= ((unsigned int)TCNT0H << 8);

...

Note:

1. The example code assumes that the part specific header file is included.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example returns the TCNT0H/L value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt

occurs between the two instructions accessing the 16-bit register, and the interrupt code

updates the temporary register by accessing the same or any other of the 16-bit timer registers,

then the result of the access outside the interrupt will be corrupted. Therefore, when both the

main code and the interrupt code update the temporary register, the main code must disable the

interrupts during the 16-bit access.

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The following code examples show how to do an atomic read of the TCNT0 register contents.

Reading any of the OCR0 register can be done by using the same principle.

Assembly Code Example

TIM0_ReadTCNT0:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNT0 into r17:r16

in r16,TCNT0L

in r17,TCNT0H

; Restore global interrupt flag

outSREG,r18

ret

C Code Example

unsigned int TIM0_ReadTCNT0( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNT0 into i */

i = TCNT0L;

i |= ((unsigned int)TCNT0H << 8);

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example returns the TCNT0H/L value in the r17:r16 register pair.

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The following code examples show how to do an atomic write of the TCNT0H/L register con-

tents. Writing any of the OCR0A/B registers can be done by using the same principle.

Assembly Code Example

TIM0_WriteTCNT0:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNT0 to r17:r16

outTCNT0H,r17

outTCNT0L,r16

; Restore global interrupt flag

outSREG,r18

ret

C Code Example

void TIM0_WriteTCNT0( unsigned int i )

{

unsigned char sreg;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNT0 to i */

TCNT0H = (i >> 8);

TCNT0L = (unsigned char)i;

/* Restore global interrupt flag */

SREG = sreg;

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example requires that the r17:r16 register pair contains the value to be writ-

ten to TCNT0H/L.

14.9.1

Reusing the temporary high byte register

If writing to more than one 16-bit register where the high byte is the same for all registers written,

then the high byte only needs to be written once. However, note that the same rule of atomic

operation described previously also applies in this case.

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14.10 Register Description

14.10.1 TCCR0A – Timer/Counter0 Control Register A

Bit

7

TCW0

R/W

0

6

ICEN0

R/W

0

5

ICNC0

R/W

0

4

ICES0

R/W

0

3

ACIC0

R/W

0

2

–

1

–

0

WGM00

R/W

0

TCCR0A

0x15 (0x35)

Read/Write

Initial Value

R

0

R

0

• Bit 7– TCW0: Timer/Counter0 Width

When this bit is written to one 16-bit mode is selected as described Figure 14-5 on page 78.

Timer/Counter0 width is set to 16-bits and the Output Compare Registers OCR0A and OCR0B

are combined to form one 16-bit Output Compare Register. Because the 16-bit registers

TCNT0H/L and OCR0B/A are accessed by the AVR CPU via the 8-bit data bus, special proce-

dures must be followed. These procedures are described in section ”Accessing Registers in 16-

bit Mode” on page 80.

• Bit 6– ICEN0: Input Capture Mode Enable

When this bit is written to onem, the Input Capture Mode is enabled.

• Bit 5 – ICNC0: Input Capture Noise Canceler

Setting this bit activates the Input Capture Noise Canceler. When the noise canceler is acti-

vated, the input from the Input Capture Pin (ICP0) is filtered. The filter function requires four

successive equal valued samples of the ICP0 pin for changing its output. The Input Capture is

therefore delayed by four System Clock cycles when the noise canceler is enabled.

• Bit 4 – ICES0: Input Capture Edge Select

This bit selects which edge on the Input Capture Pin (ICP0) that is used to trigger a capture

event. When the ICES0 bit is written to zero, a falling (negative) edge is used as trigger, and

when the ICES0 bit is written to one, a rising (positive) edge will trigger the capture. When a cap-

ture is triggered according to the ICES0 setting, the counter value is copied into the Input

Capture Register. The event will also set the Input Capture Flag (ICF0), and this can be used to

cause an Input Capture Interrupt, if this interrupt is enabled.

• Bit 3 - ACIC0: Analog Comparator Input Capture Enable

When written logic one, this bit enables the input capture function in Timer/Counter0 to be trig-

gered by the Analog Comparator. The comparator output is in this case directly connected to the

input capture front-end logic, making the comparator utilize the noise canceler and edge select

features of the Timer/Counter0 Input Capture interrupt. When written logic zero, no connection

between the Analog Comparator and the input capture function exists. To make the comparator

trigger the Timer/Counter0 Input Capture interrupt, the TICIE0 bit in the Timer Interrupt Mask

Register (TIMSK) must be set.

• Bits 2:1 – Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and will always read as zero.

• Bit 0 – WGM00: Waveform Generation Mode

This bit controls the counting sequence of the counter, the source for maximum (TOP) counter

value, see Figure 14-5 on page 78. Modes of operation supported by the Timer/Counter unit are:

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Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see ”Modes of Oper-

ation” on page 74).

14.10.2 TCNT0L – Timer/Counter0 Register Low Byte

Bit

7

6

5

4

3

2

1

0

0x32 (0x52)

Read/Write

Initial Value

TCNT0L[7:0]

TCNT0L

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter0 Register Low Byte, TCNT0L, gives direct access, both for read and write

operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0L Register blocks (dis-

ables) the Compare Match on the following timer clock. Modifying the counter (TCNT0L) while

the counter is running, introduces a risk of missing a Compare Match between TCNT0L and the

OCR0x Registers. In 16-bit mode the TCNT0L register contains the lower part of the 16-bit

Timer/Counter0 Register.

14.10.3 TCNT0H – Timer/Counter0 Register High Byte

Bit

7

6

5

4

3

2

1

0

0x14 (0x34)

Read/Write

Initial Value

TCNT0H[7:0]

R/W R/W

TCNT0H

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

When 16-bit mode is selected (the TCW0 bit is set to one) the Timer/Counter Register TCNT0H

combined to the Timer/Counter Register TCNT0L gives direct access, both for read and write

operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes

are read and written simultaneously when the CPU accesses these registers, the access is per-

formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by

all the other 16-bit registers. See ”Accessing Registers in 16-bit Mode” on page 80

14.10.4 OCR0A – Timer/Counter0 Output Compare Register A

Bit

7

6

5

4

3

2

1

0

0x13 (0x33)

Read/Write

Initial Value

OCR0A[7:0]

OCR0A

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT0L). A match can be used to generate an Output Compare interrupt.

In 16-bit mode the OCR0A register contains the low byte of the 16-bit Output Compare Register.

To ensure that both the high and the low bytes are written simultaneously when the CPU writes

to these registers, the access is performed using an 8-bit temporary high byte register (TEMP).

This temporary register is shared by all the other 16-bit registers. See ”Accessing Registers in

16-bit Mode” on page 80.

14.10.5 OCR0B – Timer/Counter0 Output Compare Register B

Bit

7

6

5

4

3

2

1

0

0x12 (0x32)

Read/Write

Initial Value

OCR0B[7:0]

OCR0B

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register B contains an 8-bit value that is continuously compared with the

counter value (TCNT0L in 8-bit mode and TCNTH in 16-bit mode). A match can be used to gen-

erate an Output Compare interrupt.

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In 16-bit mode the OCR0B register contains the high byte of the 16-bit Output Compare Regis-

ter. To ensure that both the high and the low bytes are written simultaneously when the CPU

writes to these registers, the access is performed using an 8-bit temporary high byte register

(TEMP). This temporary register is shared by all the other 16-bit registers. See ”Accessing Reg-

isters in 16-bit Mode” on page 80.

14.10.6 TIMSK – Timer/Counter0 Interrupt Mask Register

Bit

0x39 (0x59)

7

6

5

4

OCIE0A

R/W

0

3

OCIE0B

R/W

0

2

TOIE1

R/W

0

1

TOIE0

R/W

0

OCIE1D

OCIE1A

OCIE1B

R/W

0

TICIE0

TIMSK

Read/Write

Initial Value

R/W

0

R/W

0

R

0

• Bit 4 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter

Interrupt Flag Register – TIFR0.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-

rupt Flag Register – TIFR0.

• Bit 0 – TICIE0: Timer/Counter0, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt

Vector (See Section “10.” on page 48.) is executed when the ICF0 flag, located in TIFR, is set.

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14.10.7 TIFR – Timer/Counter0 Interrupt Flag Register

Bit

7

OCF1D

R/W

0

6

OCF1A

R/W

0

5

OCF1B

R/W

0

4

OCF0A

R/W

0

3

OCF0B

R/W

0

2

TOV1

R/W

0

1

TOV0

R/W

0

ICF0

R

0x38 (0x58)

Read/Write

Initial Value

TIFR

0

• Bit 4– OCF0A: Output Compare Flag 0 A

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data

in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),

and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.

The OCF0A is also set in 16-bit mode when a Compare Match occurs between the

Timer/Counter and 16-bit data in OCR0B/A. The OCF0A is not set in Input Capture mode when

the Output Compare Register OCR0A is used as an Input Capture Register.

• Bit 3 – OCF0B: Output Compare Flag 0 B

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in

OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),

and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

The OCF0B is not set in 16-bit Output Compare mode when the Output Compare Register

OCR0B is used as the high byte of the 16-bit Output Compare Register or in 16-bit Input Cap-

ture mode when the Output Compare Register OCR0B is used as the high byte of the Input

Capture Register.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by

writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt

Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.

• Bits 0 – ICF0: Timer/Counter0, Input Capture Flag

This flag is set when a capture event occurs on the ICP0 pin. When the Input Capture Register

(ICR0) is set to be used as the TOP value, the ICF0 flag is set when the counter reaches the

TOP value.

ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICF0 can be cleared by writing a logic one to its bit location.

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15. Timer/Counter1 Prescaler

Figure 15-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchro-

nous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses

the system clock (CK) as a clock timebase and asynchronous mode uses the fast peripheral

clock (PCK) as a clock time base. The PCKE bit from the PLLCSR register enables the asyn-

chronous mode when it is set (‘1’).

Figure 15-1. Timer/Counter1 Prescaler

PCKE

PSR1

CK

T1CK

S

A

14-BIT

T/C PRESCALER

PCK 64/32 MHz

0

CS10

CS11

CS12

CS13

TIMER/COUNTER1 COUNT ENABLE

In the asynchronous clocking mode the clock selections are from PCK to PCK/16384 and stop,

and in the synchronous clocking mode the clock selections are from CK to CK/16384 and stop.

The clock options are described in Table 15-1 on page 90 and the Timer/Counter1 Control Reg-

ister, TCCR1B.

The frequency of the fast peripheral clock is 64 MHz or 32 MHz in Low Speed mode (the LSM bit

in PLLCSR register is set to one). The Low Speed Mode is recommended to use when the sup-

ply voltage below 2.7 volts are used.

15.0.1

15.0.2

Prescaler Reset

Setting the PSR1 bit in TCCR1B register resets the prescaler. It is possible to use the Prescaler

Reset for synchronizing the Timer/Counter to program execution.

Prescaler Initialization for Asynchronous Mode

To change Timer/Counter1 to the asynchronous mode follow the procedure below:

1. Enable PLL.

2. Wait 100 µs for PLL to stabilize.

3. Poll the PLOCK bit until it is set.

4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode.

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15.1 Register Description

15.1.1

PLLCSR – PLL Control and Status Register

Bit

7

6

-

5

-

4

-

3

-

2

1

0

0x29 (0x49)

Read/Write

Initial value

LSM

R/W

0

PCKE

R/W

0

PLLE

R/W

0/1

PLOCK

PLLCSR

R

0

R

0

R

0

R

0

R

0

• Bit 7- LSM: Low Speed Mode

The Low Speed mode is selected, if the LSM bit is written to one, and then the fast peripheral

clock is scaled down from 64 MHz to 32 MHz. As default the LSM bit is reset to zero, the Low

Speed Mode is disabled and the fast peripheral clock is 64 MHz. The Low Speed Mode must be

set, if the supply voltage is below 2.7 volts, because the Timer/Counter1 is not running fast

enough on low voltage levels. It is recommended that the Timer/Counter1 is stopped whenever

the LSM bit is written.

• Bit 6:3- Res : Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and always read as zero.

• Bit 2- PCKE: PCK Enable

The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock

mode is enabled and fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock is used as a

Timer/Counter1 clock source. If this bit is cleared, the synchronous clock mode is enabled, and

system clock CK is used as Timer/Counter1 clock source. It is safe to set this bit only when the

PLL is locked i.e the PLOCK bit is 1. Note that the PCKE bit can be set only, if the PLL has been

enabled earlier. The PLL is enabled when the CKSEL fuses have been programmed to 0x0001

(the PLL clock mode is selected) or the PLLE bit has been set to one.

• Bit 1- PLLE: PLL Enable

When the PLLE is set, the PLL is started and if needed internal RC-oscillator is started as a PLL

reference clock. If PLL is selected as a system clock source the value for this bit is always 1.

• Bit 0- PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be

ignored during initial PLL lock-in sequence when PLL frequency overshoots and undershoots,

before reaching steady state. The steady state is obtained within 100 µs. After PLL lock-in it is

recommended to check the PLOCK bit before enabling PCK for Timer/Counter1.

15.1.2

TCCR1B – Timer/Counter1 Control Register B

Bit

0x2F (0x4F)

7

6

5

4

3

2

1

0

-

PSR1

DTPS11

R/W

0

DTPS10

R/W

0

CS13

R/W

0

CS12

R/W

0

CS11

R/W

0

CS10

R/W

0

TCCR1B

Read/Write

Initial value

R/W

0

R/W

0

• Bit 7 - Res: Reserved Bit

• Bit 6 - PSR1 : Prescaler Reset Timer/Counter1

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When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. The

bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have

no effect. This bit will always read as zero.

• Bits 3:0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

Table 15-1. Timer/Counter1 Prescale Select

Synchronous

Asynchronous

Clocking Mode

CS13

CS12

CS11

CS10

Clocking Mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

T/C1 stopped

PCK

T/C1 stopped

CK

PCK/2

CK/2

PCK/4

CK/4

PCK/8

CK/8

PCK/16

CK/16

PCK/32

CK/32

PCK/64

CK/64

PCK/128

PCK/256

PCK/512

PCK/1024

PCK/2048

PCK/4096

PCK/8192

PCK/16384

CK/128

CK/256

CK/512

CK/1024

CK/2048

CK/4096

CK/8192

CK/16384

The Stop condition provides a Timer Enable/Disable function.

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16. Timer/Counter1

16.1 Features

• 10/8-Bit Accuracy

• Three Independent Output Compare Units

• Clear Timer on Compare Match (Auto Reload)

• Glitch Free, Phase and Frequency Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Independent Dead Time Generators for each PWM channels

• Five Independent Interrupt Sources (TOV1, OCF1A, OCD1B, OCF1D, FPF1)

• High Speed Asynchronous and Synchronous Clocking Modes

• Separate Prescaler Unit

16.2 Overview

Timer/Counter1 is a general purpose high speed Timer/Counter module, with three independent

Output Compare Units, and with PWM support.

The Timer/Counter1 features a high resolution and a high accuracy usage with the lower pres-

caling opportunities. It can also support three accurate and high speed Pulse Width Modulators

using clock speeds up to 64 MHz. In PWM mode Timer/Counter1 and the output compare regis-

ters serve as triple stand-alone PWMs with non-overlapping non-inverted and inverted outputs.

Similarly, the high prescaling opportunities make this unit useful for lower speed functions or

exact timing functions with infrequent actions. A simplified block diagram of the Timer/Counter1

is shown in Figure 16-1. For actual placement of the I/O pins, refer to ”Pinout

ATtiny261/461/861” on page 2. The device-specific I/O register and bit locations are listed in the

”Register Description” on page 113.

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Figure 16-1. Timer/Counter1 Block Diagram

TOV1

OCF1A

OCF1B

OCF1D

OC1A

OC1B

OC1D

FAULT_PROTECTION

DEAD TIME GENERATOR

OCW1A

OCW1B

OCW1D

T/C INT. MASK

REGISTER (TIMSK)

T/C INT. FLAG

REGISTER (TIFR)

T/C CONTROL

REGISTER A (TCCR1A)

T/C CONTROL

REGISTER C (TCCR1D)

T/C CONTROL

REGISTER B (TCCR1B)

T/C CONTROL

REGISTER C (TCCR1C)

CLK

TIMER/COUNTER1

(TCNT1)

COUNT

CLEAR

TIMER/COUNTER1 CONTROL LOGIC

DIRECTION

T/C CONTROL

REGISTER D (TCCR1E)

10-BIT COMPARATOR

10-BIT OUTPUT

COMPARE REGISTER B

COMPARE REGISTER A

COMPARE REGISTER C

COMPARE REGISTER D

8-BIT OUTPUT COMPARE

REGISTER A (OCR1A)

8-BIT OUTPUT COMPARE

REGISTER C (OCR1C)

8-BIT OUTPUT COMPARE

REGISTER D (OCR1D)

8-BIT OUTPUT COMPARE

REGISTER B (OCR1B)

2-BIT HIGH BYTE

REGISTER (TC1H)

8-BIT DATABUS

16.2.1

16.2.2

Speed

The maximum speed of the Timer/Counter1 is 64 MHz. However, if a supply voltage below 2.7

volts is used, it is highly recommended to use the Low Speed Mode (LSM), because the

Timer/Counter1 is not running fast enough on low voltage levels. In the Low Speed Mode the

fast peripheral clock is scaled down to 32 MHz. For more details about the Low Speed Mode,

see ”PLLCSR – PLL Control and Status Register” on page 89.

Accuracy

The Timer/Counter1 is a 10-bit Timer/Counter module that can alternatively be used as an 8-bit

Timer/Counter. The Timer/Counter1 registers are basically 8-bit registers, but on top of that

there is a 2-bit High Byte Register (TC1H) that can be used as a common temporary buffer to

access the two MSBs of the 10-bit Timer/Counter1 registers by the AVR CPU via the 8-bit data

bus, if the 10-bit accuracy is used. Whereas, if the two MSBs of the 10-bit registers are written to

zero the Timer/Counter1 is working as an 8-bit Timer/Counter. When reading the low byte of any

8-bit register the two MSBs are written to the TC1H register, and when writing the low byte of

any 8-bit register the two MSBs are written from the TC1H register. Special procedures must be

followed when accessing the 10-bit Timer/Counter1 values via the 8-bit data bus. These proce-

dures are described in the section ”Accessing 10-Bit Registers” on page 110.

16.2.3

Registers

The Timer/Counter (TCNT1) and Output Compare Registers (OCR1A, OCR1B, OCR1C and

OCR1D) are 8-bit registers that are used as a data source to be compared with the TCNT1 con-

tents. The OCR1A, OCR1B and OCR1D registers determine the action on the OC1A, OC1B and

OC1D pins and they can also generate the compare match interrupts. The OCR1C holds the

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Timer/Counter TOP value, i.e. the clear on compare match value. The Timer/Counter1 High

Byte Register (TC1H) is a 2-bit register that is used as a common temporary buffer to access the

MSB bits of the Timer/Counter1 registers, if the 10-bit accuracy is used.

Interrupt request (overflow TOV1, and compare matches OCF1A, OCF1B, OCF1D and fault pro-

tection FPF1) signals are visible in the Timer Interrupt Flag Register (TIFR) and Timer/Counter1

Control Register D (TCCR1D). The interrupts are individually masked with the Timer Interrupt

Mask Register (TIMSK) and the FPIE1 bit in the Timer/Counter1 Control Register D (TCCR1D).

Control signals are found in the Timer/Counter Control Registers TCCR1A, TCCR1B, TCCR1C,

TCCR1D and TCCR1E.

16.2.4

Synchronization

In asynchronous clocking mode the Timer/Counter1 and the prescaler allow running the CPU

from any clock source while the prescaler is operating on the fast peripheral clock (PCK) having

frequency of 64 MHz (or 32 MHz in Low Speed Mode). This is possible because there is a syn-

chronization boundary between the CPU clock domain and the fast peripheral clock domain.

Figure 16-2 shows Timer/Counter 1 synchronization register block diagram and describes syn-

chronization delays in between registers. Note that all clock gating details are not shown in the

figure.

The Timer/Counter1 register values go through the internal synchronization registers, which

cause the input synchronization delay, before affecting the counter operation. The registers

TCCR1A, TCCR1B, TCCR1C, TCCR1D, OCR1A, OCR1B, OCR1C and OCR1D can be read

back right after writing the register. The read back values are delayed for the Timer/Counter1

(TCNT1) register, Timer/Counter1 High Byte Register (TC1H) and flags (OCF1A, OCF1B,

OCF1D and TOV1), because of the input and output synchronization.

The system clock frequency must be lower than half of the PCK frequency, because the syn-

chronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the

PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk

that data or control values are lost.

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Figure 16-2. Timer/Counter1 Synchronization Register Block Diagram.

8-BIT DATABUS

IO-registers

OCR1A

Input synchronization

registers

Timer/Counter1

Output synchronization

registers

OCR1A_SI

OCR1B_SI

OCR1C_SI

OCR1D_SI

TCCR1A_SI

TCCR1B_SI

TCNT1

TC1H

OCR1B

OCR1C

OCR1D

TCCR1A

TCCR1B

TCNT1_SO

TC1H_SO

OCF1A

OCF1B

OCF1A_SO

OCF1B_SO

TCCR1C

TCCR1D

TCNT1

TC1H

TCCR1C_SI

TCCR1D_SI

TCNT1_SI

TCNT1

TC1H_SI

OCF1A

OCF1B

OCF1D

TOV1

OCF1A_SI

OCF1B_SI

OCF1D_SI

TOV1_SI

OCF1D

OCF1D_SO

TOV1_SO

TOV1

PCKE

CK

S

A

S

A

PCK

SYNC

MODE

1/2 CK Delay

~1/2 CK Delay

1 CK Delay

1 PCK Delay

1/2 CK Delay

~1 CK Delay

ASYNC

MODE

1 PCK Delay

16.2.5

Definitions

Many register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-

pare Unit, in this case Compare Unit A, B, C or D. However, when using the register or bit

defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1

counter value and so on. The definitions in Table 16-1 are used extensively throughout the

document.

Table 16-1. Definitions

BOTTOM

The counter reaches the BOTTOM when it becomes 0.

MAX

The counter reaches its MAXimum value when it becomes 0x3FF (decimal 1023).

The counter reaches the TOP value (stored in the OCR1C) when it becomes equal to the

highest value in the count sequence. The TOP has a value 0x0FF as default after reset.

TOP

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16.3 Counter Unit

The main part of the Timer/Counter1 is the programmable bi-directional counter unit. Figure 16-

3 shows a block diagram of the counter and its surroundings.

Figure 16-3. Counter Unit Block Diagram

DATA BUS

TOV1

clk_T1

Timer/Counter1 Count Enable

count

clear

( From Prescaler )

PCKE

PCK

CK

TCNT1

Control Logic

direction

bottom

top

Signal description (internal signals):

count

direction

clear

TCNT1 increment or decrement enable.

Select between increment and decrement.

Clear TCNT1 (set all bits to zero).

clk_Tn

Timer/Counter clock, referred to as clk_T1in the following.

Signalize that TCNT1 has reached maximum value.

Signalize that TCNT1 has reached minimum value (zero).

top

bottom

Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T1). The timer clock is generated from an synchronous system clock or an

asynchronous PLL clock using the Clock Select bits (CS13:0) and the PCK Enable bit (PCKE).

When no clock source is selected (CS13:0 = 0) the timer is stopped. However, the TCNT1 value

can be accessed by the CPU, regardless of whether clk_T1is present or not. A CPU write over-

rides (has priority over) all counter clear or count operations.

The counting sequence of the Timer/Counter1 is determined by the setting of the WGM10 and

PWM1x bits located in the Timer/Counter1 Control Registers (TCCR1A, TCCR1C and

TCCR1D). For more details about advanced counting sequences and waveform generation, see

”Modes of Operation” on page 101. The Timer/Counter Overflow Flag (TOV1) is set according to

the mode of operation selected by the PWM1x and WGM10 bits. The Overflog Flag can be used

for generating a CPU interrupt.

16.3.1

Counter Initialization for Asynchronous Mode

To change Timer/Counter1 to the asynchronous mode follow the procedure below:

1. Enable PLL.

2. Wait 100 µs for PLL to stabilize.

3. Poll the PLOCK bit until it is set.

4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode.

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16.4 Output Compare Unit

The comparator continuously compares TCNT1 with the Output Compare Registers (OCR1A,

OCR1B, OCR1C and OCR1D). Whenever TCNT1 equals to the Output Compare Register, the

comparator signals a match. A match will set the Output Compare Flag (OCF1A, OCF1B or

OCF1D) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Com-

pare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically

cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writ-

ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to

generate an output according to operating mode set by the PWM1x, WGM10 and Compare Out-

put mode (COM1x1:0) bits. The top and bottom signals are used by the Waveform Generator for

handling the special cases of the extreme values in some modes of operation (See Section

“16.7” on page 101.). Figure 16-4 shows a block diagram of the Output Compare unit.

Figure 16-4. Output Compare Unit, Block Diagram

8-BIT DATA BUS

TCnH

TCNTn

OCRnx

10-BIT OCRnx

10-BIT TCNTn

=

(10-bit Comparator )

OCFnx (Int.Req.)

TOP

BOTTOM

FOCn

PWMnx

Waveform Generator

WGM10

COMnX1:0

OCWnx

The OCR1x Registers are double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the normal mode of operation, the double buffering is disabled. The double

buffering synchronizes the update of the OCR1x Compare Registers to either top or bottom of

the counting sequence. The synchronization prevents the occurrence of odd-length, non-sym-

metrical PWM pulses, thereby making the output glitch-free. See Figure 16-5 for an example.

During the time between the write and the update operation, a read from OCR1A, OCR1B,

OCR1C or OCR1D will read the contents of the temporary location. This means that the most

recently written value always will read out of OCR1A, OCR1B, OCR1C or OCR1D.

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Figure 16-5. Effects of Unsynchronized OCR Latching

Compare Value changes

Counter Value

Compare Value

Output Compare

Waveform OCWnx

Synchronized WFnx Latch

Compare Value changes

Counter Value

Compare Value

Output Compare

Wafeform OCWnx

Glitch

Unsynchronized WFnx Latch

16.4.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC1x) bit. Forcing Compare Match will not set the

OCF1x Flag or reload/clear the timer, but the Waveform Output (OCW1x) will be updated as if a

real Compare Match had occurred (the COM1x1:0 bits settings define whether the Waveform

Output (OCW1x) is set, cleared or toggled).

16.4.2

16.4.3

Compare Match Blocking by TCNT1 Write

All CPU write operations to the TCNT1 Register will block any Compare Match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initial-

ized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output Compare Unit

Since writing TCNT1 in any mode of operation will block all Compare Matches for one timer

clock cycle, there are risks involved when changing TCNT1 when using the Output Compare

Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT1

equals the OCR1x value, the Compare Match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is

down-counting.

The setup of the Waveform Output (OCW1x) should be performed before setting the Data Direc-

tion Register for the port pin to output. The easiest way of setting the OCW1x value is to use the

Force Output Compare (FOC1x) strobe bits in Normal mode. The OC1x keeps its value even

when changing between Waveform Generation modes.

Be aware that the COM1x1:0 bits are not double buffered together with the compare value.

Changing the COM1x1:0 bits will take effect immediately.

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16.5 Dead Time Generator

The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving

external power control switches safely. The Dead Time Generator is a separate block that can

be used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary

output pairs OC1x and OC1x when the PWM mode is enabled and the COM1x1:0 bits are set to

“01”. The sharing of tasks is as follows: the Waveform Generator generates the Waveform Out-

put (OCW1x) and the Dead Time Generator generates the non-overlapping PWM output pair

from the Waveform Output. Three Dead Time Generators are provided, one for each PWM out-

put. The non-overlap time is adjustable and the PWM output and it’s complementary output are

adjusted separately, and independently for both PWM outputs.

Figure 16-6. Output Compare Unit, Block Diagram

OCnx

top

OCWnx

bottom

FOCn

Waveform Generator

Dead Time Generator

OCnx

CK OR PCK

CLOCK

PWMnx WGM10 COMnx

DTPSn

DTnH

DTnL

The Dead Time Generation is based on the 4-bit down counters that count the dead time, as

shown in Figure 16-7. There is a dedicated prescaler in front of the Dead Time Generator that

can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8. This provides for large range of

dead times that can be generated. The prescaler is controlled by two control bits DTPS11..10.

The block has also a rising and falling edge detector that is used to start the dead time counting

period. Depending on the edge, one of the transitions on the rising edges, OC1x or OC1x is

delayed until the counter has counted to zero. The comparator is used to compare the counter

with zero and stop the dead time insertion when zero has been reached. The counter is loaded

with a 4-bit DT1H or DT1L value from DT1 I/O register, depending on the edge of the Waveform

Output (OCW1x) when the dead time insertion is started. The Output Compare Output are

delayed by one timer clock cycle at minimum from the Waveform Output when the Dead Time is

adjusted to zero. The outputs OC1x and OC1x are inverted, if the PWM Inversion Mode bit

PWM1X is set. This will also cause both outputs to be high during the dead time.

Figure 16-7. Dead Time Generator

PWM1X

COMPARATOR

OCnx

CK OR PCK

CLOCK

DEAD TIME

CLOCK CONTROL

4-BIT COUNTER

PRE-SCALER

OCnx

PWM1X

TCCRnB REGISTER

DTn I/O REGISTER

OCWnx

DATA BUS (8-bit)

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The length of the counting period is user adjustable by selecting the dead time prescaler setting

by using the DTPS11:10 control bits, and selecting then the dead time value in I/O register DT1.

The DT1 register consists of two 4-bit fields, DT1H and DT1L that control the dead time periods

of the PWM output and its' complementary output separately in terms of the number of pres-

caled dead time generator clock cycles. Thus the rising edge of OC1x and OC1x can have

different dead time periods as the t_{non-overlap / rising edge}is adjusted by the 4-bit DT1H value and the

t_{non-overlap / falling edge}is adjusted by the 4-bit DT1L value.

Figure 16-8. The Complementary Output Pair, COM1x1:0 = 1

OCWnx

OCnx

(COMnx = 1)

t _{non-overlap / rising edge}t _{non-overlap / falling edge}

16.6 Compare Match Output Unit

The Compare Output Mode (COM1x1:0) bits have two functions. The Waveform Generator uses

the COM1x1:0 bits for defining the inverted or non-inverted Waveform Output (OCW1x) at the

next Compare Match. Also, the COM1x1:0 bits control the OC1x and OC1x pin output source.

Figure 16-9 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The

I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general

I/O Port Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown.

In Normal Mode (non-PWM) the Dead Time Generator is disabled and it is working like a syn-

chronizer: the Output Compare (OC1x) is delayed from the Waveform Output (OCW1x) by one

timer clock cycle. Whereas in Fast PWM Mode and in Phase and Frequency Correct PWM

Mode when the COM1x1:0 bits are set to “01” both the non-inverted and the inverted Output

Compare output are generated, and an user programmable Dead Time delay is inserted for

these complementary output pairs (OC1x and OC1x). The functionality in PWM modes is similar

to Normal mode when any other COM1x1:0 bit setup is used. When referring to the OC1x state,

the reference is for the Output Compare output (OC1x) from the Dead Time Generator, not the

OC1x pin. If a system reset occur, the OC1x is reset to “0”.

The general I/O port function is overridden by the Output Compare (OC1x / OC1x) from the

Dead Time Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction

(input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data

Direction Register bit for the OC1x and OC1x pins (DDR_OC1x and DDR_OC1x) must be set as

output before the OC1x and OC1x values are visible on the pin. The port override function is

independent of the Output Compare mode.

The design of the Output Compare Pin Configuration logic allows initialization of the OC1x state

before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain

modes of operation. For Output Compare Pin Configurations refer to Table 16-2 on page 102,

Table 16-3 on page 104, Table 16-4 on page 105, and Table 16-5 on page 107.

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Figure 16-9. Compare Match Output Unit, Schematic

WGM11

clk

I/O

OC1OE1:0

COM1A1:0

Output Compare

Pin Configuration

D

Q

PORTB0

0

1

OC1A

1

D

Q

0

DDRB0

OC1A

OCW1A

D

Q

Dead Time

Generator A

clk

Tn

PORTB1

1

0

OC1A

D

Q

DDRB1

WGM11

OC1OE3:2

COM1B1:0

Output Compare

Pin Configuration

Q

D

PORTB2

2

1

0

1

0

OC1B

Q

D

DDRB2

OCW1B

OC1B

1

0

Q

D

Q

Dead Time

Generator B

clk

Tn

1

0

PORTB3

OC1B

Q

D

DDRB3

WGM11

OC1OE5:4

COM1D1:0

Output Compare

Pin Configuration

D

Q

PORTB4

2

1

0

1

0

OC1D

D

Q

DDRB4

OCW1D

OC1D

1

0

D

Q

Dead Time

Generator D

clk

Tn

1

0

PORTB5

OC1D

D

Q

DDRB5

16.6.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM1x1:0 bits differently in Normal mode and PWM modes.

For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the

OCW1x Output is to be performed on the next Compare Match. For compare output actions in

the non-PWM modes refer to Table 16-6 on page 113. For fast PWM mode, refer to Table 16-7

on page 113, and for the Phase and Frequency Correct PWM refer to Table 16-8 on page 114.

A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC1x strobe bits.

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16.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (bits PWM1x and WGM10) and

Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect the

counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control

whether the PWM output generated should be inverted, non-inverted or complementary. For

non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared, or tog-

gled at a Compare Match.

16.7.1

Normal Mode

The simplest mode of operation is the Normal mode (PWM1x = 0), the counter counts from

BOTTOM to TOP (defined as OCR1C) then restarts from BOTTOM. The OCR1C defines the

TOP value for the counter, hence also its resolution, and allows control of the Compare Match

output frequency. In toggle Compare Output Mode the Waveform Output (OCW1x) is cleared on

the Compare Match between TCNT1 and OCR1x and set at BOTTOM. In non-inverting Com-

pare Output Mode the Waveform Output is cleared on the Compare Match and set at BOTTOM.

In inverting Compare Output Mode the Waveform Output is set on Compare Match and cleared

at BOTTOM.

The timing diagram for the Normal mode is shown in Figure 16-10. The counter value (TCNT1)

that is shown as a histogram in the timing diagram is incremented until the counter value

matches the TOP value. The counter is then cleared at the following clock cycle The diagram

includes the Waveform Output (OCW1x) in toggle Compare Mode. The small horizontal line

marks on the TCNT1 slopes represent Compare Matches between OCR1x and TCNT1.

Figure 16-10. Normal Mode, Timing Diagram

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

TCNTn

OCWnx

(COMnx=1)

1

2

3

4

Period

The Timer/Counter Overflow Flag (TOV1) is set in the same clock cycle as the TCNT1 becomes

zero. The TOV1 Flag in this case behaves like a 11th bit, except that it is only set, not cleared.

However, combined with the timer overflow interrupt, that automatically clears the TOV1 Flag,

the timer resolution can be increased by software. There are no special cases to consider in the

Normal mode, a new counter value can be written anytime.

The Output Compare Unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time. For generating a waveform, the OCW1x output can be set to

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2588B–AVR–11/06

toggle its logical level on each Compare Match by setting the Compare Output mode bits to tog-

gle mode (COM1x1:0 = 1). The OC1x value will not be visible on the port pin unless the data

direction for the pin is set to output. The waveform generated will have a maximum frequency of

f

_OC1x= f_clkT1/4 when OCR1C is set to zero. The waveform frequency is defined by the following

equation:

f

clkT1

f

= ------------------------------------------

OC1x

2 ⋅ (1 + OCR1C)

Resolution shows how many bit is required to express the value in the OCR1C register. It is cal-

culated by following equation:

Resolution_PWM= log₂(OCR1C + 1).

The Output Compare Pin configurations in Normal Mode are described in Table 16-2.

Table 16-2.

Output Compare Pin Configurations in Normal Mode

COM1x1

COM1x0

OC1x Pin

Disconnected

OC1x

0

1

0

1

0

1

Disconnected

OC1x

16.7.2

IFast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (PWM1x = 1 and WGM10 = 0) provides a

high frequency PWM waveform generation option. The fast PWM differs from the other PWM

option by its single-slope operation. The counter counts from BOTTOM to TOP (defined as

OCR1C) then restarts from BOTTOM. In non-inverting Compare Output mode the Waveform

Output (OCW1x) is cleared on the Compare Match between TCNT1 and OCR1x and set at

BOTTOM. In inverting Compare Output mode, the Waveform Output is set on Compare Match

and cleared at BOTTOM. In complementary Compare Output mode the Waveform Output is

cleared on the Compare Match and set at BOTTOM.

Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice

as high as the Phase and Frequency Correct PWM mode that use dual-slope operation. This

high frequency makes the fast PWM mode well suited for power regulation, rectification, and

DAC applications. High frequency allows physically small sized external components (coils,

capacitors), and therefore reduces total system cost.

The timing diagram for the fast PWM mode is shown in Figure 16-11. The counter is incre-

mented until the counter value matches the TOP value. The counter is then cleared at the

following timer clock cycle. The TCNT1 value is in the timing diagram shown as a histogram for

illustrating the single-slope operation. The diagram includes the Waveform Output in non-

inverted and inverted Compare Output modes. The small horizontal line marks on the TCNT1

slopes represent Compare Matches between OCR1x and TCNT1.

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Figure 16-11. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and

TOVn Interrupt Flag Set

TCNTn

OCWnx

(COMnx1:0 = 2)

OCWnx

(COMnx1:0 = 3)

1

2

3

4

5

6

7

Period

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC1x pins.

Setting the COM1x1:0 bits to two will produce a non-inverted PWM and setting the COM1x1:0 to

three will produce an inverted PWM output. Setting the COM1x1:0 bits to one will enable com-

plementary Compare Output mode and produce both the non-inverted (OC1x) and inverted

output (OC1x). The actual value will only be visible on the port pin if the data direction for the

port pin is set as output. The PWM waveform is generated by setting (or clearing) the Waveforn

Output (OCW1x) at the Compare Match between OCR1x and TCNT1, and clearing (or setting)

the Waveform Output at the timer clock cycle the counter is cleared (changes from TOP to

BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clkT1

f

= ------------

OCnxPWM

N

The N variable represents the number of steps in single-slope operation. The value of N equals

either to the TOP value.

The extreme values for the OCR1C Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR1C is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR1C equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM1x1:0

bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting the Waveform Output (OCW1x) to toggle its logical level on each Compare Match

(COM1x1:0 = 1). The waveform generated will have a maximum frequency of f_OC1= f_clkT1/4 when

OCR1C is set to three.

The general I/O port function is overridden by the Output Compare value (OC1x / OC1x) from

the Dead Time Generator, if either of the COM1x1:0 bits are set and the Data Direction Register

bits for the OC1X and OC1X pins are set as an output. If the COM1x1:0 bits are cleared, the

actual value from the port register will be visible on the port pin. The Output Compare Pin config-

urations are described in Table 16-3.

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Table 16-3.

Output Compare Pin Configurations in Fast PWM Mode

COM1x1

COM1x0

OC1x Pin

Disconnected

OC1x

0

1

0

1

0

1

Disconnected

OC1x

Disconnected

OC1x

16.7.3

Phase and Frequency Correct PWM Mode

The Phase and Frequency Correct PWM Mode (PWMx = 1 and WGM10 = 1) provides a high

resolution Phase and Frequency Correct PWM waveform generation option. The Phase and

Frequency Correct PWM mode is based on a dual-slope operation. The counter counts repeat-

edly from BOTTOM to TOP (defined as OCR1C) and then from TOP to BOTTOM. In non-

inverting Compare Output Mode the Waveform Output (OCW1x) is cleared on the Compare

Match between TCNT1 and OCR1x while upcounting, and set on the Compare Match while

down-counting. In inverting Output Compare mode, the operation is inverted. In complementary

Compare Output Mode, the Waveform Ouput is cleared on the Compare Match and set at BOT-

TOM. The dual-slope operation has lower maximum operation frequency than single slope

operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes

are preferred for motor control applications.

The timing diagram for the Phase and Frequency Correct PWM mode is shown on Figure 16-12

in which the TCNT1 value is shown as a histogram for illustrating the dual-slope operation. The

counter is incremented until the counter value matches TOP. When the counter reaches TOP, it

changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle.

The diagram includes the Waveform Output (OCW1x) in non-inverted and inverted Compare

Output Mode. The small horizontal line marks on the TCNT1 slopes represent Compare

Matches between OCR1x and TCNT1.

Figure 16-12. Phase and Frequency Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

OCWnx

(COMnx = 2)

OCWnx

(COMnx = 3)

1

2

3

Period

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

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In the Phase and Frequency Correct PWM mode, the compare unit allows generation of PWM

waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted

PWM and setting the COM1x1:0 to three will produce an inverted PWM output. Setting the

COM1A1:0 bits to one will enable complementary Compare Output mode and produce both the

non-inverted (OC1x) and inverted output (OC1x). The actual values will only be visible on the

port pin if the data direction for the port pin is set as output. The PWM waveform is generated by

clearing (or setting) the Waveform Output (OCW1x) at the Compare Match between OCR1x and

TCNT1 when the counter increments, and setting (or clearing) the Waveform Output at Compare

Match when the counter decrements. The PWM frequency for the output when using the Phase

and Frequency Correct PWM can be calculated by the following equation:

f

clkT1

f

= ------------

OCnxPCPWM

N

The N variable represents the number of steps in dual-slope operation. The value of N equals to

the TOP value.

The extreme values for the OCR1C Register represent special cases when generating a PWM

waveform output in the Phase and Frequency Correct PWM mode. If the OCR1C is set equal to

BOTTOM, the output will be continuously low and if set equal to MAX the output will be continu-

ously high for non-inverted PWM mode. For inverted PWM the output will have the opposite

logic values.

The general I/O port function is overridden by the Output Compare value (OC1x / OC1x) from

the Dead Time Generator, if either of the COM1x1:0 bits are set and the Data Direction Register

bits for the OC1X and OC1X pins are set as an output. If the COM1x1:0 bits are cleared, the

actual value from the port register will be visible on the port pin. The configurations of the Output

Compare Pins are described in Table 16-4.

Table 16-4. Output Compare pin configurations in Phase and Frequency Correct PWM Mode

COM1x1

COM1x0

OC1x Pin

Disconnected

OC1x

0

1

0

1

0

1

Disconnected

OC1x

Disconnected

OC1x

16.7.4

PWM6 Mode

The PWM6 Mode (PWM1A = 1, WGM11 = 1 and WGM10 = x) provide PWM waveform genera-

tion option e.g. for controlling Brushless DC (BLDC) motors. In the PWM6 Mode the OCR1A

Register controls all six Output Compare waveforms as the same Waveform Output (OCW1A)

from the Waform Generator is used for generating all waveforms. The PWM6 Mode also pro-

vides an Output Compare Override Enable Register (OC1OE) that can be used with an instant

response for disabling or enabling the Output Compare pins. If the Output Compare Override

Enable bit is cleared, the actual value from the port register will be visible on the port pin.

The PWM6 Mode provides two counter operation modes, a single-slope operation and a dual-

slope operation. If the single-slope operation is selected (the WGM10 bit is set to 0), the counter

counts from BOTTOM to TOP (defined as OCR1C) then restart from BOTTOM like in Fast PWM

Mode. The PWM waveform is generated by setting (or clearing) the Waveforn Output (OCW1A)

at the Compare Match between OCR1A and TCNT1, and clearing (or setting) the Waveform

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Output at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The

Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches the TOP and, if the

interrupt is enabled, the interrupt handler routine can be used for updating the compare value.

Whereas, if the dual-slope operation is selected (the WGM10 bit is set to 1), the counter counts

repeatedly from BOTTOM to TOP (defined as OCR1C) and then from TOP to BOTTOM like in

Phase and Frequency Correct PWM Mode. The PWM waveform is generated by setting (or

clearing) the Waveforn Output (OCW1A) at the Compare Match between OCR1A and TCNT1

when the counter increments, and clearing (or setting) the Waveform Output at the he Compare

Match between OCR1A and TCNT1 when the counter decrements. The Timer/Counter Overflow

Flag (TOV1) is set each time the counter reaches the BOTTOM and, if the interrupt is enabled,

the interrupt handler routine can be used for updating the compare value.

The timing diagram for the PWM6 Mode in single-slope operation (WGM11 = 0) when the

COM1A1:0 bits are set to “10” is shown in Figure 16-13. The counter is incremented until the

counter value matches the TOP value. The counter is then cleared at the following timer clock

cycle. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-

slope operation. The timing diagram includes Output Compare pins OC1A and OC1A, and the

corresponding Output Compare Override Enable bits (OC1OE1..OC1OE0).

Figure 16-13. PWM6 Mode, Single-slope Operation, Timing Diagram

TCNT1

OCW1A

OC1OE0

OC1A Pin

OC1OE1

OC1A Pin

OC1OE2

OC1B Pin

OC1OE3

OC1B Pin

OC1OE4

OC1D Pin

OC1OE5

OC1D Pin

The general I/O port function is overridden by the Output Compare value (OC1x / OC1x) from

the Dead Time Generator if either of the COM1x1:0 bits are set. The Output Compare pins can

also be overriden by the Output Compare Override Enable bits OC1OE5..OC1OE0. If an Over-

ride Enable bit is cleared, the actual value from the port register will be visible on the port pin

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and, if the Override Enable bit is set, the Output Compare pin is allowed to be connected on the

port pin. The Output Compare Pin configurations are described in Table 16-5.

Table 16-5. Output Compare Pin configurations in PWM6 Mode

COM1A1

COM1A0

OC1A Pin (PB0)

Disconnected

OC1A Pin (PB1)

Disconnected

0

1

OC1A • OC1OE0

OC1B Pin (PB2)

Disconnected

OC1A • OC1OE1

OC1B Pin (PB3)

Disconnected

1

0

1

COM1B1

COM1B0

0

1

OC1A • OC1OE2

OC1D Pin (PB4)

Disconnected

OC1A • OC1OE3

OC1D Pin (PB5)

Disconnected

1

0

1

COM1D1

COM1D0

0

1

0

1

0

1

OC1A • OC1OE4

OC1A • OC1OE5

16.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T1) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set.

Figure 16-14 contains timing data for basic Timer/Counter operation. The figure shows the count

sequence close to the MAX value in all modes other than Phase and Frequency Correct PWM

Mode. Figure 16-15 shows the same timing data, but with the prescaler enabled, in all modes

other than Phase and Frequency Correct PWM Mode. Figure 16-16 shows the setting of

OCF1A, OCF1B and OCF1D in all modes, and Figure 16-17 shows the setting of TOV1 in

Phase and Frequency Correct PWM Mode.

Figure 16-14. Timer/Counter Timing Diagram, no Prescaling

clk_PCK

clk_Tn

(clk_PCK/1)

TCNTn

TOVn

TOP - 1

TOP

BOTTOM

BOTTOM + 1

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Figure 16-15. Timer/Counter Timing Diagram, with Prescaler (f_clkT1/8)

clk_PCK

clk_Tn

(clk_PCK/8)

TCNTn

TOVn

TOP - 1

TOP

BOTTOM

BOTTOM + 1

Figure 16-16. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f_clkT1/8)

clk_PCK

clk_Tn

(clk_PCK/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 16-17. Timer/Counter Timing Diagram, with Prescaler (f_clkT1/8)

clk_PCK

clk_Tn

(clk_PCK/8)

TCNTn

BOTTOM + 1

BOTTOM

BOTTOM + 1

TOVn

16.9 Fault Protection Unit

The Timer/Counter1 incorporates a Fault Protection unit that can disable the PWM output pins, if

an external event is triggered. The external signal indicating an event can be applied via the

external interrupt INT0 pin or alternatively, via the analog-comparator unit. The Fault Protection

unit is illustrated by the block diagram shown in Figure 16-18. The elements of the block diagram

that are not directly a part of the Fault Protection unit are gray shaded.

Figure 16-18. Fault Protection Unit Block Diagram

FAULT_PROTECTION (Int. Req.)

ACO*

FPAC1

FPNC1

FPES1

FPEN1

Analog

Comparator

Noise

Canceler

Edge

Detector

Timer/Counter1

INT0

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When the Fault Protection mode is enabled by the Fault Protection Enable (FPEN1) bit and a

change of the logic level (an event) occurs on the external interrupt pin (INT0), alternatively on

the Analog Comparator output (ACO), and this change confirms to the setting of the edge detec-

tor, a Fault Protection mode will be triggered. When a Fault Protection is triggered, the COM1x

bits are cleared, Output Comparators are disconnected from the PWM output pins and the

PORTB register bits are connected on the PWM output pins. The Fault Protection Enable

(FPEN1) is automatically cleared at the same system clock as the COM1nx bits are cleared. If

the Fault Protection Interrupt Enable bit (FPIE1) is set, a Fault Protection interrupt is generated

and the FPEN1 bit is cleared. Alternatively the FPEN1 bit can be polled by software to figure out

when the Timer/Counter has entered to Fault Protection mode.

16.9.1

Fault Protection Trigger Source

The main trigger source for the Fault Protection unit is the external interrupt pin (INT0). Alterna-

tively the Analog Comparator output can be used as trigger source for the Fault Protection unit.

The Analog Comparator is selected as trigger source by setting the Fault Protection Analog

Comparator (FPAC1) bit in the Timer/Counter1 Control Register (TCCR1D). Be aware that

changing trigger source can trigger a Fault Protection mode. Therefore it is recommended to

clear the FPF1 flag after changing trigger source, setting edge detector or enabling the Fault

Protection.

Both the external interrupt pin (INT0) and the Analog Comparator output (ACO) inputs are sam-

pled using the same technique as for the T0 pin (Figure 13-1 on page 69). The edge detector is

also identical. However, when the noise canceler is enabled, additional logic is inserted before

the edge detector, which increases the delay by four system clock cycles. An Input Capture can

also be triggered by software by controlling the port of the INT0 pin.

16.9.2

Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The

noise canceler input is monitored over four samples, and all four must be equal for changing the

output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Fault Protection Noise Canceler (FPNC1) bit in

Timer/Counter1 Control Register D (TCCR1D). When enabled the noise canceler introduces

additional four system clock cycles of delay from a change applied to the input. The noise can-

celer uses the system clock and is therefore not affected by the prescaler.

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16.10 Accessing 10-Bit Registers

If 10-bit values are written to the TCNT1 and OCR1A/B/C/D registers, the 10-bit registers can be

byte accessed by the AVR CPU via the 8-bit data bus using two read or write operations. The

10-bit registers have a common 2-bit Timer/Counter1 High Byte Register (TC1H) that is used for

temporary storing of the two MSBs of the 10-bit access. The same TC1H register is shared

between all 10-bit registers. Accessing the low byte triggers the 10-bit read or write operation.

When the low byte of a 10-bit register is written by the CPU, the high byte stored in the TC1H

register, and the low byte written are both copied into the 10-bit register in the same clock cycle.

When the low byte of a 10-bit register is read by the CPU, the high byte of the 10-bit register is

copied into the TC1H register in the same clock cycle as the low byte is read.

To do a 10-bit write, the high byte must be written to the TC1H register before the low byte is

written. For a 10-bit read, the low byte must be read before the high byte.

The following code examples show how to access the 10-bit timer registers assuming that no

interrupts updates the TC1H register. The same principle can be used directly for accessing the

OCR1A/B/C/D registers.

Assembly Code Example

...

; Set TCNT1 to 0x01FF

ldir17,0x01

ldir16,0xFF

outTC1H,r17

outTCNT1,r16

; Read TCNT1 into r17:r16

in r16,TCNT1

in r17,TC1H

...

C Code Example

unsigned int i;

...

/* Set TCNT1 to 0x01FF */

TC1H = 0x01;

TCNT1 = 0xFF;

/* Read TCNT1 into i */

i = TCNT1;

i |= ((unsigned int)TC1H << 8);

...

Note:

1. The example code assumes that the part specific header file is included.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

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It is important to notice that accessing 10-bit registers are atomic operations. If an interrupt

occurs between the two instructions accessing the 10-bit register, and the interrupt code

updates the TC1H register by accessing the same or any other of the 10-bit timer registers, then

the result of the access outside the interrupt will be corrupted. Therefore, when both the main

code and the interrupt code update the TC1H register, the main code must disable the interrupts

during the 16-bit access.

The following code examples show how to do an atomic read of the TCNT1 register contents.

Reading any of the OCR1A/B/C/D registers can be done by using the same principle.

Assembly Code Example

TIM1_ReadTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNT1 into r17:r16

in r16,TCNT1

in r17,TC1H

; Restore global interrupt flag

outSREG,r18

ret

C Code Example

unsigned int TIM1_ReadTCNT1( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNT1 into i */

i = TCNT1;

i |= ((unsigned int)TC1H << 8);

/* Restore global interrupt flag

SREG = sreg;

return i;

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

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The following code examples show how to do an atomic write of the TCNT1 register contents.

Writing any of the OCR1A/B/C/D registers can be done by using the same principle.

Assembly Code Example

TIM1_WriteTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNT1 to r17:r16

outTC1H,r17

outTCNT1,r16

; Restore global interrupt flag

outSREG,r18

ret

C Code Example

void TIM1_WriteTCNT1( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNT1 to i */

TC1H = (i >> 8);

TCNT1 = (unsigned char)i;

/* Restore global interrupt flag */

SREG = sreg;

}

Note:

1. The example code assumes that the part specific header file is included.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example requires that the r17:r16 register pair contains the value to be writ-

ten to TCNT1.

16.10.1 Reusing the temporary high byte register

If writing to more than one 10-bit register where the high byte is the same for all registers written,

then the high byte only needs to be written once. However, note that the same rule of atomic

operation described previously also applies in this case.

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16.11 Register Description

16.11.1 TCCR1A – Timer/Counter1 Control Register A

Bit

7

COM1A1

R/W

6

COM1A0

R/W

5

COM1B1

R/W

4

COM1B0

R/W

3

FOC1A

W

2

FOC1B

W

1

PWM1A

R/W

0

PWM1B

R/W

0

TCCR1A

0x30 (0x50)

Read/Write

Initial value

0

• Bits 7,6 - COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0

These bits control the behaviour of the Waveform Output (OCW1A) and the connection of the

Output Compare pin (OC1A). If one or both of the COM1A1:0 bits are set, the OC1A output

overrides the normal port functionality of the I/O pin it is connected to. The complementary

OC1B output is connected only in PWM modes when the COM1A1:0 bits are set to “01”. Note

that the Data Direction Register (DDR) bit corresponding to the OC1A and OC1A pins must be

set in order to enable the output driver.

The function of the COM1A1:0 bits depends on the PWM1A, WGM10 and WGM11 bit settings.

Table 16-6 shows the COM1A1:0 bit functionality when the PWM1A bit is set to Normal Mode

(non-PWM).

Table 16-6. Compare Output Mode, Normal Mode (non-PWM)

COM1A1..0

OCW1A Behaviour

OC1A Pin

Disconnected

Connected

OC1A Pin

00

01

10

11

Normal port operation.

Toggle on Compare Match.

Clear on Compare Match.

Set on Compare Match.

Disconnected

Table 16-7 shows the COM1A1:0 bit functionality when the PWM1A, WGM10 and WGM11 bits

are set to fast PWM mode.

Table 16-7. Compare Output Mode, Fast PWM Mode

COM1A1..0

OCW1A Behaviour

OC1A

00

Normal port operation.

Disconnected

Cleared on Compare Match.

Set when TCNT1 = 0x000.

01

10

11

Connected

Disconnected

Cleared on Compare Match.

Set when TCNT1 = 0x000.

Set on Compare Match.

Cleared when TCNT1 = 0x000.

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Table 16-8 shows the COM1A1:0 bit functionality when the PWM1A, WGM10 and WGM11 bits

are set to Phase and Frequency Correct PWM Mode.

Table 16-8. Compare Output Mode, Phase and Frequency Correct PWM Mode

COM1A1..0

OCW1A Behaviour

OC1A Pin

00

Normal port operation.

Disconnected

Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting.

01

10

11

Connected

Disconnected

Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting.

Set on Compare Match when up-counting.

Cleared on Compare Match when down-counting.

Table 16-9 shows the COM1A1:0 bit functionality when the PWM1A, WGM10 and WGM11 bits

are set to single-slope PWM6 Mode. In the PWM6 Mode the same Waveform Output (OCW1A)

is used for generating all waveforms and the Output Compare values OC1A and OC1A are con-

nected on thw all OC1x and OC1x pins as described below.

Table 16-9. Compare Output Mode, Single-Slope PWM6 Mode

COM1A1..0

OCW1A Behaviour

OC1x Pin

00

Normal port operation.

Disconnected

Cleared on Compare Match.

Set when TCNT1 = 0x000.

01

10

11

OC1A

Cleared on Compare Match.

Set when TCNT1 = 0x000.

Set on Compare Match.

Cleared when TCNT1 = 0x000.

Table 16-10 shows the COM1A1:0 bit functionality when the PWM1A, WGM10 and WGM11 bits

are set to dual-slope PWM6 Mode.I

Table 16-10. Compare Output Mode, Dual-Slope PWM6 Mode

COM1A1..0

OCW1A Behaviour

OC1x Pin

00

Normal port operation.

Disconnected

Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting.

01

10

11

OC1A

Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting.

Set on Compare Match when up-counting.

Cleared on Compare Match when down-counting.

• Bits 5,4 - COM1B1, COM1B0: Comparator B Output Mode, Bits 1 and 0

These bits control the behaviour of the Waveform Output (OCW1B) and the connection of the

Output Compare pin (OC1B). If one or both of the COM1B1:0 bits are set, the OC1B output

overrides the normal port functionality of the I/O pin it is connected to. The complementary

OC1B output is connected only in PWM modes when the COM1B1:0 bits are set to “01”. Note

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that the Data Direction Register (DDR) bit corresponding to the OC1B pin must be set in order to

enable the output driver.

The function of the COM1B1:0 bits depends on the PWM1B and WGM10 bit settings. Table 16-

11 shows the COM1B1:0 bit functionality when the PWM1B bit is set to Normal Mode (non-

PWM).

Table 16-11. Compare Output Mode, Normal Mode (non-PWM)

COM1B1..0

OCW1B Behaviour

OC1B Pin

Disconnected

Connected

OC1B Pin

00

01

10

11

Normal port operation.

Toggle on Compare Match.

Clear on Compare Match.

Set on Compare Match.

Disconnected

Table 16-12 shows the COM1B1:0 bit functionality when the PWM1B and WGM10 bits are set to

Fast PWM Mode.

Table 16-12. Compare Output Mode, Fast PWM Mode

COM1B1..0

OCW1B Behaviour

OC1B Pin

00

Normal port operation.

Disconnected

Cleared on Compare Match.

Set when TCNT1 = 0x000.

01

10

11

Connected

Disconnected

Cleared on Compare Match.

Set when TCNT1 = 0x000.

Set on Compare Match.

Cleared when TCNT1 = 0x000.

Table 16-13 shows the COM1B1:0 bit functionality when the PWM1B and WGM10 bits are set to

Phase and Frequency Correct PWM Mode.

Table 16-13. Compare Output Mode, Phase and Frequency Correct PWM Mode

COM1B1..0

OCW1B Behaviour

OC1B Pin

00

Normal port operation.

Disconnected

Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting.

01

10

11

Connected

Disconnected

Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting.

Set on Compare Match when up-counting.

Cleared on Compare Match when down-counting.

• Bit 3 - FOC1A: Force Output Compare Match 1A

The FOC1A bit is only active when the PWM1A bit specify a non-PWM mode.

Writing a logical one to this bit forces a change in the Waveform Output (OCW1A) and the Out-

put Compare pin (OC1A) according to the values already set in COM1A1 and COM1A0. If

COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used. The

Force Output Compare bit can be used to change the output pin value regardless of the timer

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2588B–AVR–11/06

value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare

match had occurred, but no interrupt is generated. The FOC1A bit is always read as zero.

• Bit 2 - FOC1B: Force Output Compare Match 1B

The FOC1B bit is only active when the PWM1B bit specify a non-PWM mode.

Writing a logical one to this bit forces a change in the Waveform Output (OCW1B) and the Out-

put Compare pin (OC1B) according to the values already set in COM1B1 and COM1B0. If

COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The

Force Output Compare bit can be used to change the output pin value regardless of the timer

value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare

match had occurred, but no interrupt is generated.

The FOC1B bit is always read as zero.

• Bit 1 - PWM1A: Pulse Width Modulator A Enable

When set (one) this bit enables PWM mode based on comparator OCR1A

• Bit 0 - PWM1B: Pulse Width Modulator B Enable

When set (one) this bit enables PWM mode based on comparator OCR1B.

16.11.2 TCCR1B – Timer/Counter1 Control Register B

Bit

0x2F (0x4F)

7

6

5

DTPS11

R/W

0

4

DTPS10

R/W

0

3

CS13

R/W

0

2

CS12

R/W

0

1

CS11

R/W

0

CS10

R/W

0

PWM1X

PSR1

TCCR1B

Read/Write

Initial value

R/W

0

R/W

0

• Bit 7 - PWM1X : PWM Inversion Mode

When this bit is set (one), the PWM Inversion Mode is selected and the Dead Time Generator

outputs, OC1x and OC1x are inverted.

• Bit 6 - PSR1 : Prescaler Reset Timer/Counter1

When this bit is set (one), the Timer/Counter1 prescaler (TCNT1 is unaffected) will be reset. The

bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have

no effect. This bit will always read as zero.

• Bits 5,4 - DTPS11, DTPS10: Dead Time Prescaler Bits

The Timer/Counter1 Control Register B is a 8-bit read/write register.

The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the

Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can

be generated. The Dead Time prescaler is controlled by two bits DTPS11 and DTPS10 from the

Dead Time Prescaler register. These bits define the division factor of the Dead Time prescaler.

The division factors are given in Table 16-14.

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Table 16-14. Division factors of the Dead Time prescaler

DTPS11

DTPS10

Prescaler divides the T/C1 clock by

0

1

0

1

0

1

1x (no division)

2x

4x

8x

• Bits 3 .. 0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

Table 16-15. Timer/Counter1 Prescaler Select

CS13 CS12 CS11 CS10 Asynchronous Clocking Mode Synchronous Clocking Mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

T/C1 stopped

PCK

T/C1 stopped

CK

PCK/2

CK/2

PCK/4

CK/4

PCK/8

CK/8

PCK/16

CK/16

PCK/32

CK/32

PCK/64

CK/64

PCK/128

PCK/256

PCK/512

PCK/1024

PCK/2048

PCK/4096

PCK/8192

PCK/16384

CK/128

CK/256

CK/512

CK/1024

CK/2048

CK/4096

CK/8192

CK/16384

The Stop condition provides a Timer Enable/Disable function.

16.11.3 TCCR1C – Timer/Counter1 Control Register C

Bit

7

6

5

4

3

2

1

0

PWM1D

R/W

0

0x27 (0x47)

Read/Write

Initial value

COM1A1S COM1A0S COM1B1S COM1B0S COM1D1

COM1D0

FOC1D

R/W

0

TCCR1C

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 7,6 - COM1A1S, COM1A0S: Comparator A Output Mode, Bits 1 and 0

These bits are the shadow bits of the COM1A1 and COM1A0 bits that are described in the sec-

tion ”TCCR1A – Timer/Counter1 Control Register A” on page 113.

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• Bits 5,4 - COM1B1S, COM1B0S: Comparator B Output Mode, Bits 1 and 0

These bits are the shadow bits of the COM1A1 and COM1A0 bits that are described in the sec-

tion ”TCCR1A – Timer/Counter1 Control Register A” on page 113.

• Bits 3,2 - COM1D1, COM1D0: Comparator D Output Mode, Bits 1 and 0

These bits control the behaviour of the Waveform Output (OCW1D) and the connection of the

Output Compare pin (OC1D). If one or both of the COM1D1:0 bits are set, the OC1D output

overrides the normal port functionality of the I/O pin it is connected to. The complementary

OC1D output is connected only in PWM modes when the COM1D1:0 bits are set to “01”. Note

that the Data Direction Register (DDR) bit corresponding to the OC1D pin must be set in order to

enable the output driver.

The function of the COM1D1:0 bits depends on the PWM1D and WGM10 bit settings. Table 16-

16 shows the COM1D1:0 bit functionality when the PWM1D bit is set to a Normal Mode (non-

PWM).

Table 16-16. Compare Output Mode, Normal Mode (non-PWM)

COM1D1..0

OCW1D Behaviour

OC1D Pin

Disconnected

Connected

OC1D Pin

00

01

10

11

Normal port operation.

Toggle on Compare Match.

Clear on Compare Match.

Set on Compare Match.

Disconnected

Table 16-17 shows the COM1D1:0 bit functionality when the PWM1D and WGM10 bits are set

to Fast PWM Mode.

Table 16-17. Compare Output Mode, Fast PWM Mode

COM1D1..0

OCW1D Behaviour

OC1D Pin

00

Normal port operation.

Disconnected

Cleared on Compare Match.

Set when TCNT1 = 0x000.

01

10

11

Connected

Disconnected

Cleared on Compare Match.

Set when TCNT1 = 0x000.

Set on Compare Match.

Clear when TCNT1 = 0x000.

Table 16-18 on page 119 shows the COM1D1:0 bit functionality when the PWM1D and WGM10

bits are set to Phase and Frequency Correct PWM Mode.

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Table 16-18. Compare Output Mode, Phase and Frequency Correct PWM Mode

COM1D1..0 OCW1D Behaviour

OC1D Pin

00

Normal port operation.

Disconnected

Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting.

01

Connected

Disconnected

Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting.

10

11

Set on Compare Match when up-counting.

Cleared on Compare Match when down-counting.

• Bit 1 - FOC1D: Force Output Compare Match 1D

The FOC1D bit is only active when the PWM1D bit specify a non-PWM mode.

Writing a logical one to this bit forces a change in the Waveform Output (OCW1D) and the Out-

put Compare pin (OC1D) according to the values already set in COM1D1 and COM1D0. If

COM1D1 and COM1D0 written in the same cycle as FOC1D, the new settings will be used. The

Force Output Compare bit can be used to change the output pin value regardless of the timer

value. The automatic action programmed in COM1D1 and COM1D0 takes place as if a compare

match had occurred, but no interrupt is generated. The FOC1D bit is always read as zero.

• Bit 0 - PWM1D: Pulse Width Modulator D Enable

When set (one) this bit enables PWM mode based on comparator OCR1D.

16.11.4 TCCR1D – Timer/Counter1 Control Register D

Bit

0x26 (0x46)

7

6

5

FPNC1

R/W

0

4

FPES1

R/W

0

3

FPAC1

R/W

0

2

FPF1

R/W

0

1

WGM11

R/W

0

WGM10

R/W

0

FPIE1

FPEN1

TCCR1D

Read/Write

Initial value

R/W

0

R/W

0

• Bit 7 - FPIE1: Fault Protection Interrupt Enable

Setting this bit (to one) enables the Fault Protection Interrupt.

• Bit 6– FPEN1: Fault Protection Mode Enable

Setting this bit (to one) activates the Fault Protection Mode.

• Bit 5 – FPNC1: Fault Protection Noise Canceler

Setting this bit activates the Fault Protection Noise Canceler. When the noise canceler is acti-

vated, the input from the Fault Protection Pin (INT0) is filtered. The filter function requires four

successive equal valued samples of the INT0 pin for changing its output. The Fault Protection is

therefore delayed by four Oscillator cycles when the noise canceler is enabled.

• Bit 4 – FPES1: Fault Protection Edge Select

This bit selects which edge on the Fault Protection pin (INT0) is used to trigger a fault event.

When the FPES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the

FPES1 bit is written to one, a rising (positive) edge will trigger the fault.

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• Bit 3 - FPAC1: Fault Protection Analog Comparator Enable

When written logic one, this bit enables the Fault Protection function in Timer/Counter1 to be

triggered by the Analog Comparator. The comparator output is in this case directly connected to

the Fault Protection front-end logic, making the comparator utilize the noise canceler and edge

select features of the Timer/Counter1 Fault Protection interrupt. When written logic zero, no con-

nection between the Analog Comparator and the Fault Protection function exists. To make the

comparator trigger the Timer/Counter1 Fault Protection interrupt, the FPIE1 bit in the

Timer/Counter1 Control Register D (TCCR1D) must be set.

• Bit 2- FPF1: Fault Protection Interrupt Flag

When the FPIE1 bit is set (one), the Fault Protection Interrupt is enabled. Activity on the pin will

cause an interrupt request even, if the Fault Protection pin is configured as an output. The corre-

sponding interrupt of Fault Protection Interrupt Request is executed from the Fault Protection

Interrupt Vector. The bit FPF1 is cleared by hardware when executing the corresponding inter-

rupt handling vector. Alternatively, FPF1 is cleared after a synchronization clock cycle by writing

a logical one to the flag. When the SREG I-bit, FPIE1 and FPF1 are set, the Fault Interrupt is

executed.

• Bits 1:0 - WGM11, WGM10: Waveform Generation Mode Bits

This bit associated with the PWMx bits control the counting sequence of the counter, the source

for type of waveform generation to be used, see Table 16-19. Modes of operation supported by

the Timer/Counter1 are: Normal mode (counter), Fast PWM Mode, Phase and Frequency Cor-

rect PWM and PWM6 Modes.

Table 16-19. Waveform Generation Mode Bit Description

Update of TOV1 Flag

PWM1x

WGM11..10 Timer/Counter Mode of Operation

TOP

OCR1x at

Set on

0

1

xx

00

01

10

11

Normal

OCR1C

Immediate TOP

Fast PWM

TOP

Phase and Frequency Correct PWM

PWM6 / Single-slope

PWM6 / Dual-slope

BOTTOM

TOP

BOTTOM

TOP

BOTTOM

16.11.5 TCCR1E – Timer/Counter1 Control Register E

Bit

7

-

6

-

5

OC1OE5

R/W

4

OC1OE4

R/W

3

OC1OE3

R/W

2

OC1OE2

R/W

1

0

0x00 (0x20)

Read/Write

Initial value

OC1OE1

OC1OE0

TCCR1E

R

0

R

0

R/W

0

R/W

0

• Bits 7:6 - Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and always reads as zero.

• Bits 5:0 – OC1OE5:OC1OE0: Ouput Compare Override Enable Bits

These bits are the Ouput Compare Override Enable bits that are used to connect or disconnect

the Output Compare Pins in PWM6 Modes with an instant response on the corresponding Out-

put Compare Pins. The actual value from the port register will be visible on the port pin, when

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the Output Compare Override Enable Bit is cleared. Table 16-20 shows the Output Compare

Override Enable Bits and their corresponding Output Compare pins.

Table 16-20. Output Compare Override Enable Bits vs. Output Compare Pins

OC1OE0

OC1OE1

OC1OE2

OC1OE3

OC1OE4

OC1OE5

OC1A (PB0)

OC1A (PB1)

OC1B (PB2)

OC1B (PB3)

OC1D (PB4)

OC1D (PB5)

16.11.6 TCNT1 – Timer/Counter1

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

0x2E (0x4E)

Read/Write

Initial value

LSB

R/W

0

TCNT1

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

This 8-bit register contains the value of Timer/Counter1.

The Timer/Counter1 is realized as a 10-bit up/down counter with read and write access. Due to

synchronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one

and half CPU clock cycles in synchronous mode and at most one CPU clock cycles for asyn-

chronous mode. When a 10-bit accuracy is preferred, special procedures must be followed for

accessing the 10-bit TCNT1 register via the 8-bit AVR data bus. These procedures are

described in section ”Accessing 10-Bit Registers” on page 110. Alternatively the Timer/Counter1

can be used as an 8-bit Timer/Counter. Note that the Timer/Counter1 always starts counting up

after writing the TCNT1 register.

16.11.7 TC1H – Timer/Counter1 High Byte

Bit

0x25 (0x45)

7

6

-

5

-

4

-

3

-

2

-

1

TC19

R/W

0

TC18

R/W

0

-

TC1H

Read/Write

Initial value

R

0

R

0

R

0

R

0

R

0

R

0

The temporary Timer/Counter1 register is an 2-bit read/write register.

• Bits 7:2 - Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and always reads as zero.

• Bits 1:0 - TC19, TC18: Two MSB bits of the 10-bit accesses

If 10-bit accuracy is used, the Timer/Counter1 High Byte Register (TC1H) is used for temporary

storing the MSB bits (TC19, TC18) of the 10-bit acceses. The same TC1H register is shared

between all 10-bit registers within the Timer/Counter1. Note that special procedures must be fol-

lowed when accessing the 10-bit TCNT1 register via the 8-bit AVR data bus. These procedures

are described in section ”Accessing 10-Bit Registers” on page 110.

16.11.8 OCR1A – Timer/Counter1 Output Compare Register A

Bit

0x2D (0x4D)

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

OCR1A

Read/Write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The output compare register A is an 8-bit read/write register.

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2588B–AVR–11/06

The Timer/Counter Output Compare Register A contains data to be continuously compared with

Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does

only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and

OCR1A to the same value does not generate a compare match.

A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow-

ing the compare event.

Note that, if 10-bit accuracy is used special procedures must be followed when accessing the

internal 10-bit Ouput Compare Registers via the 8-bit AVR data bus. These procedures are

described in section ”Accessing 10-Bit Registers” on page 110.

16.11.9 OCR1B – Timer/Counter1 Output Compare Register B

Bit

0x2C (0x4C)

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

OCR1B

Read/Write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The output compare register B is an 8-bit read/write register.

The Timer/Counter Output Compare Register B contains data to be continuously compared with

Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does

only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and

OCR1B to the same value does not generate a compare match.

A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow-

ing the compare event.

Note that, if 10-bit accuracy is used special procedures must be followed when accessing the

internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are

described in section ”Accessing 10-Bit Registers” on page 110.

16.11.10 OCR1C – Timer/Counter1 Output Compare Register C

Bit

0x2B (0x4B)

7

6

5

4

3

2

1

0

MSB

LSB

R/W

1

OCR1C

Read/Write

Initial value

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

The output compare register C is an 8-bit read/write register.

The Timer/Counter Output Compare Register C contains data to be continuously compared with

Timer/Counter1, and a compare match will clear TCNT1. This register has the same function in

Normal mode and PWM modes.

Note that, if a smaller value than three is written to the Output Compare Register C, the value is

automatically replaced by three as it is a minumum value allowed to be written to this register.

Note that, if 10-bit accuracy is used special procedures must be followed when accessing the

internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are

described in section ”Accessing 10-Bit Registers” on page 110.

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16.11.11 OCR1D – Timer/Counter1 Output Compare Register D

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

0x2A (0x4A)

Read/Write

Initial value

LSB

R/W

0

OCR1D

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The output compare register D is an 8-bit read/write register.

The Timer/Counter Output Compare Register D contains data to be continuously compared with

Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does

only occur if Timer/Counter1 counts to the OCR1D value. A software write that sets TCNT1 and

OCR1D to the same value does not generate a compare match.

A compare match will set the compare interrupt flag OCF1D after a synchronization delay follow-

ing the compare event.

Note that, if 10-bit accuracy is used special procedures must be followed when accessing the

internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are

described in section ”Accessing 10-Bit Registers” on page 110.

16.11.12 TIMSK – Timer/Counter1 Interrupt Mask Register

Bit

0x39 (0x59)

7

6

5

4

OCIE0A

R/W

0

3

OCIE0B

R/W

0

2

TOIE1

R/W

0

1

TOIE0

R/W

0

TICIE0

R/W

0

OCIE1D

OCIE1A

OCIE1B

R/W

0

TIMSK

Read/Write

Initial value

R/W

0

R/W

0

• Bit 7- OCIE1D: Timer/Counter1 Output Compare Interrupt Enable

When the OCIE1D bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare MatchD, interrupt is enabled. The corresponding interrupt at vector

$010 is executed if a compare matchD occurs. The Compare Flag in Timer/Counter1 is set (one)

in the Timer/Counter Interrupt Flag Register.

• Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector

$003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one)

in the Timer/Counter Interrupt Flag Register.

• Bit 5 - OCIE1B: Timer/Counter1 Output Compare Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector

$009 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one)

in the Timer/Counter Interrupt Flag Register.

• Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is

executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the

Timer/Counter Interrupt Flag Register - TIFR.

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2588B–AVR–11/06

16.11.13 TIFR – Timer/Counter1 Interrupt Flag Register

Bit

7

OCF1D

R/W

0

6

OCF1A

R/W

0

5

OCF1B

R/W

0

4

OCF0A

R/W

0

3

OCF0B

R/W

0

2

TOV1

R/W

0

1

TOV0

R/W

0

0x38 (0x58)

Read/Write

Initial value

ICF0

R/W

0

TIFR

• Bit 7- OCF1D: Output Compare Flag 1D

The OCF1D bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1D - Output Compare Register 1D. OCF1D is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1D is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1D, and OCF1D

are set (one), the Timer/Counter1 D compare match interrupt is executed.

• Bit 6 - OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A

are set (one), the Timer/Counter1 A compare match interrupt is executed.

• Bit 5 - OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1B - Output Compare Register 1A. OCF1B is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B

are set (one), the Timer/Counter1 B compare match interrupt is executed.

• Bit 2 - TOV1: Timer/Counter1 Overflow Flag

In Normal Mode and Fast PWM Mode the TOV1 bit is set (one) each time the counter reaches

TOP at the same clock cycle when the counter is reset to BOTTOM. In Phase and Frequency

Correct PWM Mode the TOV1 bit is set (one) each time the counter reaches BOTTOM at the

same clock cycle when zero is clocked to the counter.

The bit TOV1 is cleared by hardware when executing the corresponding interrupt handling vec-

tor. Alternatively, TOV1 is cleared, after synchronization clock cycle, by writing a logical one to

the flag. When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and

TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.

16.11.14 DT1 – Timer/Counter1 Dead Time Value

Bit

0x24 (0x44)

7

6

5

DT1H1

R/W

0

4

DT1H0

R/W

0

3

DT1L3

R/W

0

2

DT1L2

R/W

0

1

DT1L1

R/W

0

DT1L0

R/W

0

DT1H3

DT1H2

R/W

0

DT1

Read/Write

Initial value

R/W

0

The dead time value register is an 8-bit read/write register.

The dead time delay of all Timer/Counter1 channels are adjusted by the dead time value regis-

ter, DT1. The register consists of two fields, DT1H3..0 and DT1L3..0, one for each

complementary output. Therefore a different dead time delay can be adjusted for the rising edge

of OC1x and the rising edge of OC1x.

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• Bits 7:4- DT1H3:DT1H0: Dead Time Value for OC1x Output

The dead time value for the OC1x output. The dead time delay is set as a number of the pres-

caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the

prescaled time/counter clock period multiplied by 15.

• Bits 3:0- DT1L3:DT1L0: Dead Time Value for OC1x Output

The dead time value for the OC1x output. The dead time delay is set as a number of the pres-

caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the

prescaled time/counter clock period multiplied by 15.

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17. USI – Universal Serial Interface

17.1 Features

• Two-wire Synchronous Data Transfer (Master or Slave)

• Three-wire Synchronous Data Transfer (Master or Slave)

• Data Received Interrupt

• Wakeup from Idle Mode

• In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode

• Two-wire Start Condition Detector with Interrupt Capability

17.2 Overview

The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial

communication. Combined with a minimum of control software, the USI allows significantly

higher transfer rates and uses less code space than solutions based on software only. Interrupts

are included to minimize the processor load.

A simplified block diagram of the USI is shown on Figure 17-1. For the actual placement of I/O

pins, refer to ”Pinout ATtiny261/461/861” on page 2. CPU accessible I/O Registers, including I/O

bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed

in the ”Register Descriptions” on page 133.

Figure 17-1. Universal Serial Interface, Block Diagram

(Output only)

DO

D

Q

LE

(Input/Open Drain)

DI/SDA

3

2

USIDR

USIDB

1

0

TIM0 COMP

3

2

0

1

(Input/Open Drain)

USCK/SCL

4-bit Counter

1

0

CLOCK

HOLD

[1]

Two-wire Clock

Control Unit

USISR

2

USICR

The 8-bit USI Data Register is directly accessible via the data bus and contains the incoming

and outgoing data. The register has no buffering so the data must be read as quickly as possible

to ensure that no data is lost. The USI Data Register is a serial shift register and the most signif-

icant bit that is the output of the serial shift register is connected to one of two output pins

depending of the wire mode configuration. A transparent latch is inserted between the USI Data

Register Output and output pin, which delays the change of data output to the opposite clock

edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin

independent of the configuration.

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The 4-bit counter can be both read and written via the data bus, and can generate an overflow

interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same

clock source. This allows the counter to count the number of bits received or transmitted and

generate an interrupt when the transfer is complete. Note that when an external clock source is

selected the counter counts both clock edges. In this case the counter counts the number of

edges, and not the number of bits. The clock can be selected from three different sources: The

USCK pin, Timer/Counter0 Compare Match or from software.

The Two-wire clock control unit can generate an interrupt when a start condition is detected on

the Two-wire bus. It can also generate wait states by holding the clock pin low after a start con-

dition is detected, or after the counter overflows.

17.3 Functional Descriptions

17.3.1

Three-wire Mode

The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but

does not have the slave select (SS) pin functionality. However, this feature can be implemented

in software if necessary. Pin names used by this mode are: DI, DO, and USCK.

Figure 17-2. Three-wire Mode Operation, Simplified Diagram

DO

DI

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USCK

SLAVE

DO

DI

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USCK

PORTxn

MASTER

Figure 17-2 shows two USI units operating in Three-wire mode, one as Master and one as

Slave. The two USI Data Register are interconnected in such way that after eight USCK clocks,

the data in each register are interchanged. The same clock also increments the USI’s 4-bit

counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine

when a transfer is completed. The clock is generated by the Master device software by toggling

the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR.

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Figure 17-3. Three-wire Mode, Timing Diagram

( Reference )

1

2

3

4

5

6

7

8

CYCLE

USCK

DO

MSB

6

5

4

3

2

1

LSB

6

5

4

3

2

1

DI

A

B

C

D

E

The Three-wire mode timing is shown in Figure 17-3. At the top of the figure is a USCK cycle ref-

erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The

USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI

is sampled at positive edges, and DO is changed (Data Register is shifted by one) at negative

edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., sam-

ples data at negative and changes the output at positive edges. The USI clock modes

corresponds to the SPI data mode 0 and 1.

Referring to the timing diagram (Figure 17-3.), a bus transfer involves the following steps:

1. The Slave device and Master device sets up its data output and, depending on the proto-

col used, enables its output driver (mark A and B). The output is set up by writing the

data to be transmitted to the USI Data Register. Enabling of the output is done by setting

the corresponding bit in the port Data Direction Register. Note that point A and B does

not have any specific order, but both must be at least one half USCK cycle before point C

where the data is sampled. This must be done to ensure that the data setup requirement

is satisfied. The 4-bit counter is reset to zero.

2. The Master generates a clock pulse by software toggling the USCK line twice (C and D).

The bit value on the slave and master’s data input (DI) pin is sampled by the USI on the

first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter

will count both edges.

3. Step 2. is repeated eight times for a complete register (byte) transfer.

4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that

the transfer is completed. The data bytes transferred must now be processed before a

new transfer can be initiated. The overflow interrupt will wake up the processor if it is set

to Idle mode. Depending of the protocol used the slave device can now set its output to

high impedance.

17.3.2

SPI Master Operation Example

The following code demonstrates how to use the USI module as a SPI Master:

SPITransfer:

sts

ldi

sts

ldi

USIDR,r16

r16,(1<<USIOIF)

USISR,r16

r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)

SPITransfer_loop:

sts

USICR,r16

lds

r16, USISR

r16, USIOIF

sbrs

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rjmp

lds

SPITransfer_loop

r16,USIDR

ret

The code is size optimized using only eight instructions (+ ret). The code example assumes that

the DO and USCK pins are enabled as output in the DDRA or DDRB Register. The value stored

in register r16 prior to the function is called is transferred to the Slave device, and when the

transfer is completed the data received from the Slave is stored back into the r16 Register.

The second and third instructions clears the USI Counter Overflow Flag and the USI counter

value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock,

count at USITC strobe, and toggle USCK. The loop is repeated 16 times.

The following code demonstrates how to use the USI module as a SPI Master with maximum

speed (fsck = fck/4):

SPITransfer_Fast:

sts

ldi

USIDR,r16

r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)

r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)

sts

USICR,r16 ; MSB

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16 ; LSB

USICR,r17

lds

r16,USIDR

ret

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17.3.3

SPI Slave Operation Example

The following code demonstrates how to use the USI module as a SPI Slave:

init:

ldi

sts

r16,(1<<USIWM0)|(1<<USICS1)

USICR,r16

...

SlaveSPITransfer:

sts

ldi

sts

USIDR,r16

r16,(1<<USIOIF)

USISR,r16

SlaveSPITransfer_loop:

lds

r16, USISR

sbrs

rjmp

lds

r16, USIOIF

SlaveSPITransfer_loop

r16,USIDR

ret

The code is size optimized using only eight instructions (+ ret). The code example assumes that

the DO is configured as output and USCK pin is configured as input in the DDR Register. The

value stored in register r16 prior to the function is called is transferred to the master device, and

when the transfer is completed the data received from the Master is stored back into the r16

Register.

Note that the first two instructions is for initialization only and needs only to be executed

once.These instructions sets Three-wire mode and positive edge USI Data Register clock. The

loop is repeated until the USI Counter Overflow Flag is set.

17.3.4

Two-wire Mode

The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate lim-

iting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA.

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Figure 17-4. Two-wire Mode Operation, Simplified Diagram

VCC

SDA

SCL

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

HOLD

SCL

Two-wire Clock

Control Unit

SLAVE

SDA

SCL

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

PORTxn

MASTER

Figure 17-4 shows two USI units operating in Two-wire mode, one as Master and one as Slave.

It is only the physical layer that is shown since the system operation is highly dependent of the

communication scheme used. The main differences between the Master and Slave operation at

this level, is the serial clock generation which is always done by the Master, and only the Slave

uses the clock control unit. Clock generation must be implemented in software, but the shift

operation is done automatically by both devices. Note that only clocking on negative edge for

shifting data is of practical use in this mode. The slave can insert wait states at start or end of

transfer by forcing the SCL clock low. This means that the Master must always check if the SCL

line was actually released after it has generated a positive edge.

Since the clock also increments the counter, a counter overflow can be used to indicate that the

transfer is completed. The clock is generated by the master by toggling the USCK pin via the

PORT Register.

The data direction is not given by the physical layer. A protocol, like the one used by the TWI-

bus, must be implemented to control the data flow.

Figure 17-5. Two-wire Mode, Typical Timing Diagram

SDA

1 - 7

8

9

1 - 8

9

1 - 8

9

SCL

S

P

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

A

B

C

D

E

F

Referring to the timing diagram (Figure 17-5.), a bus transfer involves the following steps:

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1. The a start condition is generated by the Master by forcing the SDA low line while the

SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift

Register, or by setting the corresponding bit in the PORT Register to zero. Note that the

USI Data Register bit must be set to one for the output to be enabled. The slave device’s

start detector logic (Figure 17-6.) detects the start condition and sets the USISIF Flag.

The flag can generate an interrupt if necessary.

2. In addition, the start detector will hold the SCL line low after the Master has forced an

negative edge on this line (B). This allows the Slave to wake up from sleep or complete

its other tasks before setting up the USI Data Register to receive the address. This is

done by clearing the start condition flag and reset the counter.

3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave

samples the data and shift it into the USI Data Registerat the positive edge of the SCL

clock.

4. After eight bits are transferred containing slave address and data direction (read or

write), the Slave counter overflows and the SCL line is forced low (D). If the slave is not

the one the Master has addressed, it releases the SCL line and waits for a new start

condition.

5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle

before holding the SCL line low again (i.e., the Counter Register must be set to 14 before

releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables its output. If

the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line)

The slave can hold the SCL line low after the acknowledge (E).

6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given

by the Master (F). Or a new start condition is given.

If the Slave is not able to receive more data it does not acknowledge the data byte it has last

received. When the Master does a read operation it must terminate the operation by force the

acknowledge bit low after the last byte transmitted.

Figure 17-6. Start Condition Detector, Logic Diagram

USISIF

CLOCK

HOLD

D Q

SDA

CLR

SCL

Write( USISIF)

17.3.5

Start Condition Detector

The start condition detector is shown in Figure 17-6. The SDA line is delayed (in the range of 50

to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled

in Two-wire mode.

The start condition detector is working asynchronously and can therefore wake up the processor

from the Power-down sleep mode. However, the protocol used might have restrictions on the

SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time set by

the CKSEL Fuses (see ”Clock Systems and their Distribution” on page 24) must also be taken

into the consideration. Refer to the USISIF bit description on page 134 for further details.

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17.4 Alternative USI Usage

When the USI unit is not used for serial communication, it can be set up to do alternative tasks

due to its flexible design.

17.4.1

17.4.2

17.4.3

17.4.4

Half-duplex Asynchronous Data Transfer

By utilizing the USI Data Register in Three-wire mode, it is possible to implement a more com-

pact and higher performance UART than by software only.

4-bit Counter

The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the

counter is clocked externally, both clock edges will generate an increment.

12-bit Timer/Counter

Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit

counter.

Edge Triggered External Interrupt

By setting the counter to maximum value (F) it can function as an additional external interrupt.

The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature

is selected by the USICS1 bit.

17.4.5

Software Interrupt

The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.

17.5 Register Descriptions

17.5.1

USIDR – USI Data Register

Bit

7

6

5

4

3

2

1

0

0x0F (0x2F)

Read/Write

Initial Value

MSB

R/W

0

LSB

R/W

0

USIDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

When accessing the USI Data Register (USIDR) the Serial Register can be accessed directly. If

a serial clock occurs at the same cycle the register is written, the register will contain the value

written and no shift is performed. A (left) shift operation is performed depending of the

USICS1..0 bits setting. The shift operation can be controlled by an external clock edge, by a

Timer/Counter0 Compare Match, or directly by software using the USICLK strobe bit. Note that

even when no wire mode is selected (USIWM1..0 = 0) both the external data input (DI/SDA) and

the external clock input (USCK/SCL) can still be used by the USI Data Register.

The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch

to the most significant bit (bit 7) of the Data Register. The output latch is open (transparent) dur-

ing the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1),

and constantly open when an internal clock source is used (USICS1 = 0). The output will be

changed immediately when a new MSB written as long as the latch is open. The latch ensures

that data input is sampled and data output is changed on opposite clock edges.

Note that the corresponding Data Direction Register to the pin must be set to one for enabling

data output from the USI Data Register.

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17.5.2

USIBR – USI Buffer Register

Bit

7

6

5

4

3

2

1

0

0x10 (0x30)

Read/Write

Initial Value

MSB

R

LSB

R

USIBR

R

0

R

0

R

0

R

0

R

0

R

0

The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is com-

pleted, and instead of accessing the USI Data Register (the Serial Register) the USI Data Buffer

can be accessed when the CPU reads the received data. This gives the CPU time to handle

other program tasks too as the controlling of the USI is not so timing critical. The USI flags as set

same as when reading the USIDR register.

17.5.3

USISR – USI Status Register

Bit

7

6

5

4

3

2

1

0

0x0E (0x2E)

Read/Write

Initial Value

USISIF

R/W

0

USIOIF

R/W

0

USIPF

R/W

0

USIDC

USICNT3

USICNT2

USICNT1

USICNT0

USISR

R

0

R/W

0

R/W

0

R/W

0

R/W

0

The Status Register contains Interrupt Flags, line Status Flags and the counter value.

• Bit 7 – USISIF: Start Condition Interrupt Flag

When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is

detected. When output disable mode or Three-wire mode is selected and (USICSx = 0b11 &

USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag.

An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global

Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the USISIF

bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode.

A start condition interrupt will wakeup the processor from all sleep modes.

• Bit 6 – USIOIF: Counter Overflow Interrupt Flag

This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An

interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global

Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit.

Clearing this bit will release the counter overflow hold of SCL in Two-wire mode.

A counter overflow interrupt will wakeup the processor from Idle sleep mode.

• Bit 5 – USIPF: Stop Condition Flag

When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected.

The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is

useful when implementing Two-wire bus master arbitration.

• Bit 4 – USIDC: Data Output Collision

This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The

flag is only valid when Two-wire mode is used. This signal is useful when implementing Two-

wire bus master arbitration.

• Bits 3:0 – USICNT3..0: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or

written by the CPU.

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The 4-bit counter increments by one for each clock generated either by the external clock edge

detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe

bits. The clock source depends of the setting of the USICS1..0 bits. For external clock operation

a special feature is added that allows the clock to be generated by writing to the USITC strobe

bit. This feature is enabled by write a one to the USICLK bit while setting an external clock

source (USICS1 = 1).

Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input

(USCK/SCL) are can still be used by the counter.

17.5.4

USICR – USI Control Register

Bit

7

6

5

4

3

2

1

0

0x0D (0x2D)

Read/Write

Initial Value

USISIE

R/W

0

USIOIE

R/W

0

USIWM1

USIWM0

USICS1

R/W

0

USICS0

R/W

0

USICLK

USITC

USICR

R/W

0

R/W

0

W

0

W

0

The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,

and clock strobe.

• Bit 7 – USISIE: Start Condition Interrupt Enable

Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter-

rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be

executed. Refer to the USISIF bit description on page 134 for further details.

• Bit 6 – USIOIE: Counter Overflow Interrupt Enable

Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when

the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed.

Refer to the USIOIF bit description on page 134 for further details.

• Bit 5:4 – USIWM1:0: Wire Mode

These bits set the type of wire mode to be used. Basically only the function of the outputs are

affected by these bits. Data and clock inputs are not affected by the mode selected and will

always have the same function. The counter and USI Data Register can therefore be clocked

externally, and data input sampled, even when outputs are disabled. The relations between

USIWM1:0 and the USI operation is summarized in Table 17-1.

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Table 17-1. Relations between USIWM1..0 and the USI Operation

USIWM1 USIWM0 Description

0

Outputs, clock hold, and start detector disabled. Port pins operates as normal.

Three-wire mode. Uses DO, DI, and USCK pins.

The Data Output (DO) pin overrides the corresponding bit in the PORT Register

in this mode. However, the corresponding DDR bit still controls the data

direction. When the port pin is set as input the pins pull-up is controlled by the

PORT bit.

0

1

The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port

operation. When operating as master, clock pulses are software generated by

toggling the PORT Register, while the data direction is set to output. The USITC

bit in the USICR Register can be used for this purpose.

Two-wire mode. Uses SDA (DI) and SCL (USCK) pins⁽¹⁾.

The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and

uses open-collector output drives. The output drivers are enabled by setting the

corresponding bit for SDA and SCL in the DDR Register.

When the output driver is enabled for the SDA pin, the output driver will force the

line SDA low if the output of the USI Data Register or the corresponding bit in

the PORT Register is zero. Otherwise the SDA line will not be driven (i.e., it is

released). When the SCL pin output driver is enabled the SCL line will be forced

low if the corresponding bit in the PORT Register is zero, or by the start

detector. Otherwise the SCL line will not be driven.

1

0

The SCL line is held low when a start detector detects a start condition and the

output is enabled. Clearing the Start Condition Flag (USISIF) releases the line.

The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on

the SDA and SCL port pin are disabled in Two-wire mode.

Two-wire mode. Uses SDA and SCL pins.

Same operation as for the Two-wire mode described above, except that the SCL

line is also held low when a counter overflow occurs, and is held low until the

Counter Overflow Flag (USIOIF) is cleared.

1

Note:

1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively

to avoid confusion between the modes of operation.

• Bit 3:2 – USICS1:0: Clock Source Select

These bits set the clock source for the USI Data Registerr and counter. The data output latch

ensures that the output is changed at the opposite edge of the sampling of the data input

(DI/SDA) when using external clock source (USCK/SCL). When software strobe or

Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and

therefore the output is changed immediately. Clearing the USICS1:0 bits enables software

strobe option. When using this option, writing a one to the USICLK bit clocks both the USI Data

Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no longer

used as a strobe, but selects between external clocking and software clocking by the USITC

strobe bit.

Table 17-2 on page 137 shows the relationship between the USICS1..0 and USICLK setting and

clock source used for the USI Data Register and the 4-bit counter.

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Table 17-2. Relations between the USICS1..0 and USICLK Setting

USI Data Register Clock

Source

USICS1

USICS0

USICLK

4-bit Counter Clock Source

0

No Clock

Software clock strobe

(USICLK)

Software clock strobe

(USICLK)

0

1

Timer/Counter0 Compare

Match

Timer/Counter0 Compare

Match

X

1

0

1

0

1

0

1

External, positive edge

External, negative edge

External, positive edge

External, negative edge

External, both edges

Software clock strobe (USITC)

• Bit 1 – USICLK: Clock Strobe

Writing a one to this bit location strobes the USI Data Register to shift one step and the counter

to increment by one, provided that the USICS1..0 bits are set to zero and by doing so the soft-

ware clock strobe option is selected. The output will change immediately when the clock strobe

is executed, i.e., in the same instruction cycle. The value shifted into the USI Data Register is

sampled the previous instruction cycle. The bit will be read as zero.

When an external clock source is selected (USICS1 = 1), the USICLK function is changed from

a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the

USITC strobe bit as clock source for the 4-bit counter (see Table 17-2).

• Bit 0 – USITC: Toggle Clock Port Pin

Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0.

The toggling is independent of the setting in the Data Direction Register, but if the PORT value is

to be shown on the pin the DDB2 must be set as output (to one). This feature allows easy clock

generation when implementing master devices. The bit will be read as zero.

When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ-

ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of

when the transfer is done when operating as a master device.

17.5.5

USIPP – USI Pin Position

Bit

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

USIPOS

R/W

0

0x11 (0x31)

Read/Write

Initial Value

USIPP

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bits 7:1 – Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and always reads as zero.

• Bit 0 – USIPOS: USI Pin Position

Setting this bit to one changes the USI pin position. As default pins PB2..PB0 are used for the

USI pin functions, but when writing this bit to one the USIPOS bit is set the USI pin functions are

on pins PA2..PA0.

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18. AC – Analog Comparator

The Analog Comparator compares the input values on the selectable positive pin (AIN0, AIN1 or

AIN2) and selectable negative pin (AIN0, AIN1 or AIN2). When the voltage on the positive pin is

higher than the voltage on the negative pin, the Analog Comparator output, ACO, is set. The

comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can

select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the com-

parator and its surrounding logic is shown in Figure 18-1.

Figure 18-1. Analog Comparator Block Diagram⁽²⁾

BANDGAP

REFERENCE

ACBG

ACM2..1

AIN0

MUX

AIN1

AIN2

ACME

ADEN

ADC MULTIPLEXER

OUTPUT⁽¹⁾

Notes: 1. See Table 18-2 on page 140.

2. Refer to Figure 1-1 on page 2 and Table 12.3.2 on page 65 for Analog Comparator pin

placement.

18.1 Register Description

18.1.1

ACSRA – Analog Comparator Control and Status Register A

Bit

7

6

ACBG

R/W

0

5

ACO

R

4

ACI

R/W

0

3

ACIE

R/W

0

2

ACME

R/W

0

1

ACIS1

R/W

0

ACIS0

R/W

0

0x08 (0x28)

Read/Write

Initial Value

ACD

R/W

0

ACSRA

N/A

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off. This bit

can be set at any time to turn off the Analog Comparator. This will reduce power consumption in

Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be

disabled by clearing the ACIE bit in ACSRA. Otherwise an interrupt can occur when the bit is

changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set an internal 1.1V reference voltage replaces the positive input to the Analog

Comparator. The selection of the internal voltage reference is done by writing the REFS2..0 bits

in ADMUX register. When this bit is cleared, AIN0, AIN1 or AIN2 depending on the ACM2..0 bits

is applied to the positive input of the analog comparator.

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• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The

synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined

by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set

and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-

rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-

parator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the

ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written

logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed

description of this bit, see ”Analog Comparator Multiplexed Input” on page 140.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The

different settings are shown in Table 18-1.

Table 18-1. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle.

Reserved

Comparator Interrupt on Falling Output Edge.

Comparator Interrupt on Rising Output Edge.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by

clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the

bits are changed.

18.2 Analog Comparator Multiplexed Input

When the Analog to Digital Converter (ADC) is configurated as single ended input channel, it is

possible to select any of the ADC10..0 pins to replace the negative input to the Analog Compar-

ator. The ADC multiplexer is used to select this input, and consequently, the ADC must be

switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in

ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX5..0 in ADMUX

select the input pin to replace the negative input to the Analog Comparator, as shown in Table

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18-2. If ACME is cleared or ADEN is set, either AIN0, AIN1 or AIN2 is applied to the negative

input to the Analog Comparator.

Table 18-2. Analog Comparator Multiplexed Input

ACME

0

ADEN

x

MUX5..0

xxxxxx

000000

000001

000010

000011

000100

000101

000110

000111

001000

ACM2..0

000

001

010

011

100

101,110,111

000

01x

Positive Input

AIN0

AIN1

AIN2

AIN0

AIN1

AIN2

AIN0

AIN1

AIN2

AIN0

AIN1

AIN2

AIN0

AIN1

AIN2

AIN0

AIN1

AIN2

AIN0

AIN1

AIN2

AIN0

AIN1

AIN2

AIN0

AIN1

AIN2

AIN0

AIN1

AIN2

Negative Input

AIN1

0

x

AIN2

0

x

AIN0

0

x

AIN2

0

x

AIN0

0

x

AIN1

1

0

AIN1

1

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

ADC8

1

1xx

1

000

01x

1

1xx

1

000

01x

1

1xx

1

000

01x

1

1xx

1

000

01x

1

1xx

1

000

01x

1

1xx

1

000

01x

1

1xx

1

000

01x

1

1xx

1

000

01x

1

1xx

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Table 18-2. Analog Comparator Multiplexed Input (Continued)

ACME

ADEN

MUX5..0

001001

001010

ACM2..0

000

Positive Input

AIN0

Negative Input

ADC9

1

0

01x

AIN1

ADC9

1xx

AIN2

ADC9

000

AIN0

ADC10

01x

AIN1

1xx

AIN2

18.2.1

ACSRB – Analog Comparator Control and Status Register B

Bit

7

HSEL

R/W

0

6

HLEV

R/W

0

5

-

4

-

3

-

2

ACM2

R/W

0

1

ACM1

R/W

0

0x09 (0x29)

Read/Write

Initial Value

ACM0

R/W

0

ACSRB

R

0

R

0

N/A

• Bit 7 – HSEL: Hysteresis Select

When this bit is written logic one, the hysteresis of the Analog Comparator is switched on. The

hysteresis level is selected by the HLEV bit.

• Bit 6 – HLEV: Hysteresis Level

When the hysteresis is enabled by the HSEL bit, the Hysteresis Level, HLEV, bit selects the hys-

teresis level that is either 20mV (HLEV=0) or 50mV (HLEV=1).

• Bit 2:0 – ACM2:ACM0: Analog Comparator Multiplexer

The Analog Comparator multiplexer bits select the positive and negative input pins of the Analog

Comparator. The different settings are shown in Table 18-2.

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19. ADC – Analog to Digital Converter

19.1 Features

• 10-bit Resolution

• 1.0 LSB Integral Non-linearity

•

2 LSB Absolute Accuracy

• 65 - 260 µs Conversion Time

• Up to 15 kSPS at Maximum Resolution

• 11 Multiplexed Single Ended Input Channels

• 16 Differential input pairs

• 15 Differential input pairs with selectable gain

• Temperature sensor input channel

• Optional Left Adjustment for ADC Result Readout

• 0 - V_CCADC Input Voltage Range

• Selectable 1.1V / 2.56V ADC Voltage Reference

• Free Running or Single Conversion Mode

• ADC Start Conversion by Auto Triggering on Interrupt Sources

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Cancele

• Unipolar / Bibolar Input Mode

• Input Polarity Reversal Mode

19.2 Overview

The ATtiny261/461/861 features a 10-bit successive approximation ADC. The ADC is connected

to a 11-channel Analog Multiplexer which allows 16 differential voltage input combinations and

11 single-ended voltage inputs constructed from the pins PA7..PA0 or PB7..PB4. The differential

input is equipped with a programmable gain stage, providing amplification steps of 1x, 8x, 20x or

32x on the differential input voltage before the A/D conversion. The single-ended voltage inputs

refer to 0V (GND).

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. A block diagram of the ADC is shown in Figure 19-1.

Internal reference voltages of nominally 1.1V or 2.56V are provided On-chip. The Internal refer-

ance voltage of 2.56V, can optionally be externally decoupled at the AREF (PA3) pin by a

capacitor, for better noise performance. Alternatively, V_CCcan be used as reference voltage for

single ended channels. There is also an option to use an external voltage reference and turn-off

the internal voltage reference. These options are selected using the REFS2:0 bits of the ADMUX

control register.

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ATtiny261/461/861

Figure 19-1. Analog to Digital Converter Block Schematic

ADC CONVERSION

COMPLETE IRQ

8-BIT DATA BUS

15

0

ADC DATA REGISTER

(ADCH/ADCL)

ADC CTRL. & STATUS

REGISTER B (ADCSRB)

ADC MULTIPLEXER

SELECT (ADMUX)

ADC CTRL. & STATUS

REGISTER A (ADCSRA)

PRESCALER

MUX DECODER

CONVERSION LOGIC

VCC

AREF

SAMPLE & HOLD

COMPARATOR

INTERNAL 2.56/1.1V

REFERENCE

10-BIT DAC

-

+

INTERNAL 1.18V

REFERENCE

AGND

TEMPERATURE

SENSOR

ADC10

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

SINGLE ENDED /

DIFFERENTIAL SELECTION

POS.

INPUT

MUX

ADC

MULTIPLEXER OUTPUT

MUX

+

-

GAIN

AMPLIFIER

NEG.

INPUT

MUX

19.3 Operation

The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-

mation. The minimum value represents GND and the maximum value represents the voltage on

V

_CC, the voltage on the AREF pin or an internal 1.1V / 2.56V voltage reference.

The voltage reference for the ADC may be selected by writing to the REFS2..0 bits in ADMUX.

The VCC supply, the AREF pin or an internal 1.1V / 2.56V voltage reference may be selected as

the ADC voltage reference. Optionally the internal 1.1V / 2.56V voltage reference may be decou-

pled by an external capacitor at the AREF pin to improve noise immunity.

The analog input channel and differential gain are selected by writing to the MUX5..0 bits in

ADMUX. Any of the 11 ADC input pins ADC10..0 can be selected as single ended inputs to the

ADC. The positive and negative inputs to the differential gain amplifier are described in Table

19-4.

If differential channels are selected, the differential gain stage amplifies the voltage difference

between the selected input pair by the selected gain factor, 1x, 8x, 20x or 32x, according to the

setting of the MUX5..0 bits in ADMUX and the GSEL bit in ADCSRB. This amplified value then

becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is

bypassed altogether.

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If the same ADC input pin is selected as both the positive and negative input to the differential

gain amplifier, the remaining offset in the gain stage and conversion circuitry can be measured

directly as the result of the conversion. This figure can be subtracted from subsequent conver-

sions with the same gain setting to reduce offset error to below 1 LSW.

The on-chip temperature sensor is selected by writing the code “111111” to the MUX5..0 bits in

ADMUX register when the ADC11 channel is used as an ADC input.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and

input channel selections will not go into effect until ADEN is set. The ADC does not consume

power when ADEN is cleared, so it is recommended to switch off the ADC before entering power

saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data

registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is

blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes. When ADC

access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will

trigger even if the result is lost.

19.4 Starting a Conversion

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and will be cleared by hardware

when the conversion is completed. If a different data channel is selected while a conversion is in

progress, the ADC will finish the current conversion before performing the channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is

enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is

selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS

bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,

the ADC prescaler is reset and a conversion is started. This provides a method of starting con-

versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new

conversion will not be started. If another positive edge occurs on the trigger signal during con-

version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific

interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus

be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to

trigger a new conversion at the next interrupt event.

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Figure 19-2. ADC Auto Trigger Logic

ADTS[2:0]

PRESCALER

CLK_ADC

START

ADIF

ADATE

SOURCE 1

.

CONVERSION

LOGIC

.

EDGE

DETECTOR

SOURCE n

ADSC

Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon

as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-

stantly sampling and updating the ADC Data Register. The first conversion must be started by

writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive

conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to

one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be

read as one during a conversion, independently of how the conversion was started.

19.5 Prescaling and Conversion Timing

Figure 19-3. ADC Prescaler

ADEN

START

Reset

7-BIT ADC PRESCALER

CK

ADPS0

ADPS1

ADPS2

ADC CLOCK SOURCE

By default, the successive approximation circuitry requires an input clock frequency between 50

kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the

input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.

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The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit

in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously

reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched

on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-

sion and 14.5 ADC clock cycles after the start of an first conversion. When a conversion is

complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion

mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new

conversion will be initiated on the first rising ADC clock edge.

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures

a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold

takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-

tional CPU clock cycles are used for synchronization logic.

In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high. For a summary of conversion times, see Table 19-1.

Figure 19-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)

Conversion

Cycle Number

1

2

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1

2

3

ADC Clock

ADEN

ADSC

ADIF

Sign and MSB of Result

LSB of Result

ADCH

ADCL

MUX and REFS

Update

Conversion

Complete

MUX and REFS

Update

Sample & Hold

Figure 19-5. ADC Timing Diagram, Single Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

3

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

Sign and MSB of Result

LSB of Result

ADCL

Sample & Hold

Conversion

Complete

MUX and REFS

Update

MUX and REFS

Update

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Figure 19-6. ADC Timing Diagram, Auto Triggered Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

Cycle Number

ADC Clock

Trigger

Source

ADATE

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample &

Hold

Prescaler

Reset

Conversion

Complete

Prescaler

Reset

MUX and REFS

Update

Figure 19-7. ADC Timing Diagram, Free Running Conversion

One Conversion

Next Conversion

11

12

13

1

2

3

4

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample & Hold

MUX and REFS

Update

Conversion

Complete

Table 19-1. ADC Conversion Time

Sample & Hold

Condition

(Cycles from Start of Conversion)

Conversion Time (Cycles)

First conversion

13.5

1.5

2

25

13

Normal conversions

Auto Triggered conversions

13.5

19.6 Changing Channel or Reference Selection

The MUX5:0 and REFS2:0 bits in the ADMUX Register are single buffered through a temporary

register to which the CPU has random access. This ensures that the channels and reference

selection only takes place at a safe point during the conversion. The channel and reference

selection is continuously updated until a conversion is started. Once the conversion starts, the

channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-

tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in

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2588B–AVR–11/06

ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after

ADSC is written. The user is thus advised not to write new channel or reference selection values

to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special

care must be taken when updating the ADMUX Register, in order to control which conversion

will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot tell if the next conversion is based

on the old or the new settings. ADMUX can be safely updated in the following ways:

a. When ADATE or ADEN is cleared.

b. During conversion, minimum one ADC clock cycle after the trigger event.

c. After a conversion, before the Interrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

19.6.1

ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure

that the correct channel is selected:

In Single Conversion mode, always select the channel before starting the conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the conversion to complete before changing the channel selection.

In Free Running mode, always select the channel before starting the first conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the first conversion to complete, and then change the channel

selection. Since the next conversion has already started automatically, the next result will reflect

the previous channel selection. Subsequent conversions will reflect the new channel selection.

19.6.2

ADC Voltage Reference

The voltage reference for the ADC (V_REF) indicates the conversion range for the ADC. Single

ended channels that exceed V_REFwill result in codes close to 0x3FF. V_REFcan be selected as

either V_CC, or internal 1.1V / 2.56V voltage reference, or external AREF pin. The first ADC con-

version result after switching voltage reference source may be inaccurate, and the user is

advised to discard this result.

19.7 ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise

induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC

Noise Reduction and Idle mode. To make use of this feature, the following procedure should be

used:

a. Make sure that the ADC is enabled and is not busy converting. Single Conversion

mode must be selected and the ADC conversion complete interrupt must be enabled.

b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion

once the CPU has been halted.

c. If no other interrupts occur before the ADC conversion completes, the ADC interrupt

will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If

another interrupt wakes up the CPU before the ADC conversion is complete, that

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interrupt will be executed, and an ADC Conversion Complete interrupt request will be

generated when the ADC conversion completes. The CPU will remain in active mode

until a new sleep command is executed.

Note that the ADC will not be automatically turned off when entering other sleep modes than Idle

mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-

ing such sleep modes to avoid excessive power consumption.

19.7.1

Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 19-8. An analog

source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard-

less of whether that channel is selected as input for the ADC. When the channel is selected, the

source must drive the S/H capacitor through the series resistance (combined resistance in the

input path).

The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or

less. If such a source is used, the sampling time will be negligible. If a source with higher imped-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources

with slowly varying signals, since this minimizes the required charge transfer to the S/H

capacitor.

Signal components higher than the Nyquist frequency (f_ADC/2) should not be present to avoid

distortion from unpredictable signal convolution. The user is advised to remove high frequency

components with a low-pass filter before applying the signals as inputs to the ADC.

Figure 19-8. Analog Input Circuitry

I_IH

ADCn

1..100 kΩ

C_S/H= 14 pF

I_IL

V_CC/2

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19.7.2

Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

analog measurements. If conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

a. Keep analog signal paths as short as possible. Make sure analog tracks run over the

analog ground plane, and keep them well away from high-speed switching digital

tracks.

b. Use the ADC noise canceler function to reduce induced noise from the CPU.

c. If any port pins are used as digital outputs, it is essential that these do not switch

while a conversion is in progress.

19.7.3

ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and V_REFin 2ⁿsteps

(LSBs). The lowest code is read as 0, and the highest code is read as 2ⁿ-1.

Several parameters describe the deviation from the ideal behavior:

• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at

0.5 LSB). Ideal value: 0 LSB.

Figure 19-9. Offset Error

Output Code

Ideal ADC

Actual ADC

Offset

Error

V_REF

Input Voltage

• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last

transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).

Ideal value: 0 LSB

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Figure 19-10. Gain Error

Gain

Error

Output Code

Ideal ADC

Actual ADC

V_REF

Input Voltage

• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum

deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0

LSB.

Figure 19-11. Integral Non-linearity (INL)

Output Code

Ideal ADC

Actual ADC

V

Input Voltage

REF

• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval

between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.

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Figure 19-12. Differential Non-linearity (DNL)

Output Code

0x3FF

1 LSB

DNL

0x000

0

V_REFInput Voltage

• Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a

range of input voltages (1 LSB wide) will code to the same value. Always 0.5 LSB.

• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to

an ideal transition for any code. This is the compound effect of offset, gain error, differential

error, non-linearity, and quantization error. Ideal value: 0.5 LSB.

19.8 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC

Result Registers (ADCL, ADCH). The form of the conversion result depends on the type of the

conversio as there are three types of conversions: single ended conversion, unipolar differential

conversion and bipolar differential conversion.

19.8.1

Single Ended Conversion

For single ended conversion, the result is

V

⋅ 1024

IN

ADC = --------------------------

V

REF

where V_INis the voltage on the selected input pin and V_REFthe selected voltage reference (see

Table 19-3 on page 154 and Table 19-4 on page 155). 0x000 represents analog ground, and

0x3FF represents the selected voltage reference minus one LSB. The result is presented in one-

sided form, from 0x3FF to 0x000.

19.8.2

Unipolar Differential Conversion

If differential channels and an unipolar input mode are used, the result is

(V

– V

) ⋅ 1024

NEG

POS

-------------------------------------------------------

ADC =

⋅ GAIN

V

REF

where V^POSis the voltage on the positive input pin, VNEG the voltage on the negative input pin,

and V^REFthe selected voltage reference (see Table 19-3 on page 154 and Table 19-4 on page

152

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ATtiny261/461/861

155). The voltage on the positive pin must always be larger than the voltage on the negative pin

or otherwise the voltage difference is saturated to zero. The result is presented in one-sided

form, from 0x000 (0d) to 0x3FF (+1023d). The GAIN is either 1x, 8x, 20x or 32x.

19.8.3

Bipolar Differential Conversion

As default the ADC converter operates in the unipolar input mode, but the bipolar input mode

can be selected by writting the BIN bit in the ADCSRB to one. In the bipolar input mode two-

sided voltage differences are allowed and thus the voltage on the negative input pin can also be

larger than the voltage on the positive input pin. If differential channels and a bipolar input mode

are used, the result is

(V

– V

) ⋅ 512

NEG

POS

----------------------------------------------------

ADC =

⋅ GAIN

V

REF

where V^POSis the voltage on the positive input pin, VNEG the voltage on the negative input pin,

and V^REFthe selected voltage reference. The result is presented in two’s complement form, from

0x200 (-512d) through 0x000 (+0d) to 0x1FF (+511d). The GAIN is either 1x, 8x, 20x or 32x.

However, if the signal is not bipolar by nature (9 bits + sign as the 10th bit), this scheme loses

one bit of the converter dynamic range. Then, if the user wants to perform the conversion with

the maximum dynamic range, the user can perform a quick polarity check of the result and use

the unipolar differential conversion with selectable differential input pair. When the polarity check

is performed, it is sufficient to read the MSB of the result (ADC9 in ADCH). If the bit is one, the

result is negative, and if this bit is zero, the result is positive.

19.9 Temperature Measurement

The temperature measurement is based on an on-chip temperature sensor that is coupled to a

single ended ADC11 channel. Selecting the ADC11 channel by writing the MUX5..0 bits in

ADMUX register to “111111” enables the temperature sensor. The internal 1.1V voltage refer-

ence must also be selected for the ADC voltage reference source in the temperature sensor

measurement. When the temperature sensor is enabled, the ADC converter can be used in sin-

gle conversion mode to measure the voltage over the temperature sensor.

The measured voltage has a linear relationship to the temperature as described in Table 19-2 on

page 153. The voltage sensitivity is approximately 1 mV/°C and the accuracy of the temperature

measurement is +/- 10°C after bandgap calibration.

Table 19-2. Temperature vs. Sensor Output Voltage (Typical Case)

Temperature / °C

-40 °C

+25 °C

+85 °C

Voltage / mV

247 mV

314 mv

382 mV

The values described in Table 19-2 on page 153 are typical values. However, due to the process

variation the temperature sensor output voltage varies from one chip to another. To be capable

of achieving more accurate results the temperature measurement can be calibrated in the appli-

cation software. The software calibration requires that a calibration value is measured and

stored in a register or EEPROM for each chip. The sofware calibration can be done utilizing the

formula:

T = { [ (ADCH << 8) | ADCL ] - TOS } / k

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2588B–AVR–11/06

where ADCn are the ADC data registers, kis a fixed coefficient and T_OSis the temperature sen-

sor offset value determined and stored into EEPROM.

19.10 Register Descriptin

19.10.1 ADMUX – ADC Multiplexer Selection Register

Bit

7

REFS1

R/W

0

6

REFS0

R/W

0

5

ADLAR

R/W

0

4

MUX4

R/W

0

3

MUX3

R/W

0

2

MUX2

R/W

0

1

MUX1

R/W

0

MUX0

R/W

0

0x07 (0x27)

Read/Write

Initial Value

ADMUX

• Bit 7:6 – REFS1:REFS0: Voltage Reference Selection Bits

These bits and the REFS2 bit from the ADC Control and Status Register B (ADCSRB) select the

voltage reference for the ADC, as shown in Table 19-3. If these bits are changed during a

conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is

set). Whenever these bits are changed, the next conversion will take 25 ADC clock cycles. If

active channels are used, using AVCC or an external AREF higher than (AVCC - 1V) is not

recommended, as this will affect ADC accuracy. The internal voltage reference options may not

be used if an external voltage is being applied to the AREF pin.

Table 19-3. Voltage Reference Selections for ADC

REFS2

REFS1

REFS0

Voltage Reference (V_REF) Selection

X

0

V_CCused as Voltage Reference, disconnected from AREF.

External Voltage Reference at AREF pin, Internal Voltage

Reference turned off.

X

0

1

0

1

0

1

Internal 1.1V Voltage Reference.

Reserved.

Internal 2.56V Voltage Reference without external bypass

capacitor, disconnected from AREF.

1

0

1

Internal 2.56V Voltage Reference with external bypass capacitor

at AREF pin.

•

Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-

sions. For a comple te description of this bit, see ”ADCL and ADCH – The ADC Data Register”

on page 158.

• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits

These bits and the MUX5 bit from the ADC Control and Status Register B (ADCSRB) select

which combination of analog inputs are connected to the ADC. In case of differential input, gain

selection is also made with these bits. Selecting the same pin as both inputs to the differential

gain stage enables offset measurements. Selecting the single-ended channel ADC11 enables

the temperature sensor. Refer to Table 19-4 for details. If these bits are changed during a

conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA

is set).

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Table 19-4. Input Channel Selections

Single Ended

Positive

Negative

MUX5..0

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

Input

Differential Input Differential Input Gain

ADC0 (PA0)

ADC1 (PA1)

ADC2 (PA2)

ADC3 (PA4)

ADC4 (PA5)

ADC5 (PA6)

ADC6 (PA7)

ADC7 (PB4)

ADC8 (PB5)

ADC9 (PB6)

ADC10 (PB7)

NA

ADC0 (PA0)

ADC1 (PA1)

ADC2 (PA2)

ADC3 (PA4)

ADC4 (PA5)

ADC5 (PA6)

ADC6 (PA7)

ADC8 (PB5)

ADC9 (PB6)

ADC10 (PB7)

ADC1 (PA1)

ADC3 (PA4)

ADC5 (PA6)

ADC9 (PB6)

20x

1x

NA

N/A

NA

20x

1x

20x

1x

20x

1x

20x

1x

20x

1x

NA

20x

1x

1.1V

0V

N/A

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2588B–AVR–11/06

Table 19-4. Input Channel Selections (Continued)

Single Ended

Input

Positive

Negative

MUX5..0

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

Differential Input Differential Input Gain

ADC0(PA0)

ADC1(PA1

ADC1(PA1)

ADC2(PA2

ADC2(PA2)

ADC0(PA0)

ADC4(PA5)

ADC5(PA6)

ADC6(PA7)

ADC4(PA5)

ADC0(PA0)

ADC1(PA1)

ADC2(PA2)

ADC4(PA5)

ADC5(PA6)

ADC6(PA7)

N/A

ADC1(PA1)

ADC0(PA0)

ADC2(PA2)

ADC1(PA1)

ADC0(PA0)

ADC2(PA2)

ADC5(PA6)

ADC4(PA5)

ADC6(PA7)

ADC5(PA6)

ADC4(PA5)

ADC6(PA7)

ADC0(PA0)

ADC1(PA1)

ADC2(PA2)

ADC4(PA5)

ADC5(PA6)

ADC6(PA7)

N/A

20x/32x

1x/8x

N/A

20x/32x

1x/8x

20x/32x

1x/8x

20x/32x

1x/8x

20x/32x

1x/8x

20x/32x

1x/8x

20x/32x

1x/8x

20x/32x

1x/8x

20x/32x

1x/8x

20x/32x

1x/8x

20x/32x

1x/8x

20x/32x

1x/8x

20x/32x

1x/8x

N/A

20x/32x

N/A

(1)

ADC11

1.

For Temperature Sensor

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ATtiny261/461/861

19.10.2 ADCSRA – ADC Control and Status Register A

Bit

7

6

5

4

3

2

1

0

0x06 (0x26)

Read/Write

Initial Value

ADEN

ADSC

ADATE

ADIF

ADIE

ADPS2

ADPS1

ADPS0

ADCSRA

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the

ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,

write this bit to one to start the first conversion. The first conversion after ADSC has been written

after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,

will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-

tion of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is complete,

it returns to zero. Writing zero to this bit has no effect.

• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-

version on a positive edge of the selected trigger signal. The trigger source is selected by setting

the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the data registers are updated. The ADC

Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is

cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,

ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on

ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions

are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-

rupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the system clock frequency and the input clock

to the ADC.

Table 19-5. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

0

1

0

1

0

1

2

4

8

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2588B–AVR–11/06

Table 19-5. ADC Prescaler Selections (Continued)

ADPS2

ADPS1

ADPS0

Division Factor

1

0

1

0

1

0

1

16

32

64

128

19.10.3 ADCL and ADCH – The ADC Data Register

19.10.3.1 ADLAR = 0

Bit

15

14

13

12

11

10

9

8

0x05 (0x25)

0x04 (0x24)

–

ADC9

ADC8

ADCH

ADCL

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

R

0

Read/Write

Initial Value

0

19.10.3.2

ADLAR = 1

Bit

15

14

13

12

11

10

9

8

0x05 (0x25)

0x04 (0x24)

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADCH

ADCL

ADC1

ADC0

–

5

–

4

–

3

–

2

–

1

–

0

7

R

0

6

R

0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if

the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from

the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result

is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in ”ADC Conversion Result” on

page 152.

19.10.4 ADCSRB – ADC Control and Status Register B

Bit

7

BIN

R/W

0

6

GSEL

R/W

0

5

-

4

3

MUX5

R

2

ADTS2

R/W

0

1

ADTS1

R/W

0

ADTS0

R/W

0

0x03 (0x23)

Read/Write

Initial Value

REFS2

ADCSRB

R/W

0

R

0

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ATtiny261/461/861

• Bits 7– BIN: Bipolar Input Mode

The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected

by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions

are supported and the voltage on the positive input must always be larger than the voltage on

the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode

two-sided conversions are supported and the result is represented in the two’s complement

form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits +

1 sign bit.

• Bits 6 – GSEL: Gain Select

The Gain Select bit selects the 32x gain instead of the 20x gain and the 8x gain instead of the 1x

gain when the Gain Select bit is written to one.

• Bits 5 – Res: Reserved Bit

This bit is a reserv ed bit in the ATtiny261/461/861 and will always read as zero.

• Bits 4 – REFS2: Reference Selection Bit

These bit selects either the voltage reference of 1.1 V or 2.56 V for the ADC, as shown in Table

19-3. If active channels are used, using AVCC or an external AREF higher than (AVCC - 1V) is

not recommended, as this will affect ADC accuracy. The internal voltage reference options may

not be used if an external voltage is being applied to the AREF pin.

• Bits 3 – MUX5: Analog Channel and Gain Selection Bit 5

The MUX5 bit is the MSB of the Analog Channel and Gain Selection bits. Refer to Table 19-4 for

details. If this bit is changed during a conversion, the change will not go into effect until this

conversion is complete (ADIF in ADCSRA is set).

• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger

an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion

will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-

ger source that is cleared to a trigger source that is set, will generate a positive edge on the

trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

Table 19-6. ADC Auto Trigger Source Selections

ADTS2

ADTS1

ADTS0

Trigger Source

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Free Running mode

Analog Comparator

External Interrupt Request 0

Timer/Counter0 Compare Match A

Timer/Counter0 Overflow

Timer/Counter0 Compare Match B

Timer/Counter1 Overflow

Watchdog Interrupt Request

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2588B–AVR–11/06

19.10.5 DIDR0 – Digital Input Disable Register 0

Bit

7

6

5

4

3

2

1

0

0x01 (0x21)

Read/Write

Initial Value

ADC6D

R/W

0

ADC5D

R/W

0

ADC4D

R/W

0

ADC3D

R/W

0

AREFD

R/W

0

ADC2D

R/W

0

ADC1D

R/W

0

ADC0D

R/W

0

DIDR0

• Bits 7:4,2:0 – ADC6D:ADC0D: ADC6:0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

• Bit 3 – AREFD: AREF Digital Input Disable

When this bit is written logic one, the digital input buffer on the AREF pin is disabled. The corre-

sponding PIN register bit will always read as zero when this bit is set. When an analog signal is

applied to the AREF pin and the digital input from this pin is not needed, this bit should be written

logic one to reduce power consumption in the digital input buffer.

19.10.6 DIDR1 – Digital Input Disable Register 1

Bit

0x02 (0x22)

7

6

5

ADC8D

R/W

0

4

ADC7D

R/W

0

3

-

2

1

0

ADC10D

ADC9D

R/W

0

DIDR1

Read/Write

Initial Value

R/W

0

R

0

R

0

R

0

R

0

• Bits 7..4 – ADC10D..ADC7D: ADC10..7 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC10:7 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

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ATtiny261/461/861

20. debugWIRE On-chip Debug System

20.1 Features

• Complete Program Flow Control

• Emulates All On-chip Functions, Both Digital and Analog , except RESET Pin

• Real-time Operation

• Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)

• Unlimited Number of Program Break Points (Using Software Break Points)

• Non-intrusive Operation

• Electrical Characteristics Identical to Real Device

• Automatic Configuration System

• High-Speed Operation

• Programming of Non-volatile Memories

20.2 Overview

The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the

program flow, execute AVR instructions in the CPU and to program the different non-volatile

memories.

20.3 Physical Interface

When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed,

the debugWIRE system within the target device is activated. The RESET port pin is configured

as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the commu-

nication gateway between target and emulator.

Figure 20-1. The debugWIRE Setup

1.8 - 5.5V

VCC

dW

dW(RESET)

GND

Figure 20-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator

connector. The system clock is not affected by debugWIRE and will always be the clock source

selected by the CKSEL Fuses.

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2588B–AVR–11/06

When designing a system where debugWIRE will be used, the following observations must be

made for correct operation:

• Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the

pull-up resistor is optional.

• Connecting the RESET pin directly to V_CCwill not work.

• Capacitors inserted on the RESET pin must be disconnected when using debugWire.

• All external reset sources must be disconnected.

20.4 Software Break Points

debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a

Break Point in AVR Studio^®will insert a BREAK instruction in the Program memory. The instruc-

tion replaced by the BREAK instruction will be stored. When program execution is continued, the

stored instruction will be executed before continuing from the Program memory. A break can be

inserted manually by putting the BREAK instruction in the program.

The Flash must be re-programmed each time a Break Point is changed. This is automatically

handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore

reduce the Falsh Data retention. Devices used for debugging purposes should not be shipped to

end customers.

20.5 Limitations of debugWIRE

The debugWIRE communication pin (dW) is physically located on the same pin as External

Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is

enabled.

The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e.,

when the program in the CPU is running. When the CPU is stopped, care must be taken while

accessing some of the I/O Registers via the debugger (AVR Studio).

A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep

modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should

be disabled when debugWire is not used.

20.6 Register Description

The following section describes the registers used with the debugWire.

20.6.1

DWDR – debugWire Data Register

Bit

7

6

5

4

3

2

1

0

0x20 (0x40)

Read/Write

Initial Value

DWDR[7:0]

DWDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The DWDR Register provides a communication channel from the running program in the MCU

to the debugger. This register is only accessible by the debugWIRE and can therefore not be

used as a general purpose register in the normal operations.

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21. Self-Programming the Flash

The device provides a Self-Programming mechanism for downloading and uploading program

code by the MCU itself. The Self-Programming can use any available data interface and associ-

ated protocol to read code and write (program) that code into the Program memory.

The Program memory is updated in a page by page fashion. Before programming a page with

the data stored in the temporary page buffer, the page must be erased. The temporary page

buffer is filled one word at a time using SPM and the buffer can be filled either before the Page

Erase command or between a Page Erase and a Page Write operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (for example

in the temporary page buffer) before the erase, and then be re-written. When using alternative 1,

the Boot Loader provides an effective Read-Modify-Write feature which allows the user software

to first read the page, do the necessary changes, and then write back the modified data. If alter-

native 2 is used, it is not possible to read the old data while loading since the page is already

erased. The temporary page buffer can be accessed in a random sequence. It is essential that

the page address used in both the Page Erase and Page Write operation is addressing the same

page.

21.0.1

21.0.2

Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “00000011” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will

be ignored during this operation.

• The CPU is halted during the Page Erase operation.

Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The

content of PCWORD in the Z-register is used to address the data in the temporary buffer. The

temporary buffer will auto-erase after a Page Write operation or by writing the CTPB bit in

SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than

one time to each address without erasing the temporary buffer.

If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be

lost.

21.0.3

Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

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The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to

zero during this operation.

• The CPU is halted during the Page Write operation.

21.1 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.

Bit

15

Z15

Z7

7

14

Z14

Z6

6

13

Z13

Z5

5

12

Z12

Z4

4

11

Z11

Z3

3

10

Z10

Z2

2

9

8

ZH (R31)

ZL (R30)

Z9

Z1

1

Z8

Z0

0

Since the Flash is organized in pages (see Table 22-7 on page 171), the Program Counter can

be treated as having two different sections. One section, consisting of the least significant bits, is

addressing the words within a page, while the most significant bits are addressing the pages.

This is shown in Figure 21-1. Note that the Page Erase and Page Write operations are

addressed independently. Therefore it is of major importance that the software addresses the

same page in both the Page Erase and Page Write operation.

The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the

Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.

Figure 21-1. Addressing the Flash During SPM⁽¹⁾

BIT 15

ZPCMSB

ZPAGEMSB

1

0

Z - REGISTER

PCMSB

PAGEMSB

PCWORD

PROGRAM

COUNTER

PCPAGE

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. The different variables used in Figure 21-1 are listed in Table 22-7 on page 171.

21.1.1

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

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21.1.2

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction

is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR, the

value of the Lock bits will be loaded in the destination register. The RFLB and SPMEN bits will

auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within

three CPU cycles or no SPM instruction is executed within four CPU cycles. When RFLB and

SPMEN are cleared, LPM will work as described in the Instruction set Manual.

Bit

Rd

7

6

5

4

3

2

1

0

–

LB2

LB1

The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and

SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the

RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be

loaded in the destination register as shown below. Refer to Table 22-5 on page 170 for a

detailed description and mapping of the Fuse Low byte.

Bit

Rd

7

6

5

4

3

2

1

0

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-

tion is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the

value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.

Refer to Table XXX on page XXX for detailed description and mapping of the Fuse High byte.

Bit

Rd

7

6

5

4

3

2

1

0

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

21.1.3

Preventing Flash Corruption

During periods of low V_CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-

age matches the detection level. If not, an external low V_CCreset protection circuit can be

used. If a reset occurs while a write operation is in progress, the write operation will be

completed provided that the power supply voltage is sufficient.

2. Keep the AVR core in Power-down sleep mode during periods of low V_CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

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21.1.4

Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 21-1 shows the typical pro-

gramming time for Flash accesses from the CPU.

Table 21-1. SPM Programming Time⁽¹⁾

Symbol

Min Programming Time

3.7 ms

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

4.5 ms

Note:

1. Minimum and maximum programming time is per individual operation.

21.2 Register Description

21.2.1

SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Program memory operations.

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

3

2

1

0

0x37 (0x57)

Read/Write

Initial Value

CTPB

R/W

0

RFLB

R/W

0

PGWRT

R/W

0

PGERS

R/W

0

SPMEN

R/W

0

SPMCSR

• Bits 7:5 – Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and always read as zero.

• Bit 4 – CTPB: Clear Temporary Page Buffer

If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be

cleared and the data will be lost.

• Bit 3 – RFLB: Read Fuse and Lock Bits

An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register,

will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destina-

tion register. See ”EEPROM Write Prevents Writing to SPMCSR” on page 164 for details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Write, with the data stored in the temporary buffer. The page address is

taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit

will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four

clock cycles. The CPU is halted during the entire Page Write operation.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The

data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,

or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire

Page Write operation.

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• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special

meaning, see description above. If only SPMEN is written, the following SPM instruction will

store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of

the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,

or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write,

the SPMEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

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22. Memory Programming

This section describes the different methods for Programming the ATtiny261/461/861 memories.

22.1 Program And Data Memory Lock Bits

The ATtiny261/461/861 provides two Lock bits which can be left unprogrammed (“1”) or can be

programmed (“0”) to obtain the additional security listed in Table 22-2. The Lock bits can only be

erased to “1” with the Chip Erase command. The ATtiny261/461/861 has no separate Boot

Loader section. The SPM instruction is enabled for the whole Flash, if the SELFPROGEN fuse is

programmed (“0”), otherwise it is disabled.

Table 22-1. Lock Bit Byte⁽¹⁾

Lock Bit Byte

Bit No

Description

Default Value

7

6

5

4

3

2

1

0

–

1 (unprogrammed)

–

LB2

LB1

Lock bit

Note:

1. “1” means unprogrammed, “0” means programmed

Table 22-2. Lock Bit Protection Modes⁽¹⁾⁽²⁾

Memory Lock Bits Protection Type

LB Mode

LB2

LB1

1

No memory lock features enabled.

Further programming of the Flash and EEPROM is disabled in

High-voltage and Serial Programming mode. The Fuse bits are

locked in both Serial and High-voltage Programming mode.⁽¹⁾

2

1

0

Further programming and verification of the Flash and EEPROM

is disabled in High-voltage and Serial Programming mode. The

Fuse bits are locked in both Serial and High-voltage

Programming mode.⁽¹⁾

3

Notes: 1. Program the Fuse bits before programming the LB1 and LB2.

2. “1” means unprogrammed, “0” means programmed

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22.2 Fuse Bytes

The ATtiny261/461/861 has three Fuse bytes. Table 22-3, Table 22-4 and Table 22-5 describe

briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that

the fuses are read as logical zero, “0”, if they are programmed.

Table 22-3. Fuse Extended Byte

Fuse High Byte

Bit No Description

Default Value

7

6

5

4

3

2

1

0

-

1 (unprogrammed)

-

SELFPRGEN

Self-Programming Enable

Table 22-4. Fuse High Byte

Fuse High Byte

RSTDISBL⁽¹⁾

DWEN⁽²⁾

Bit No Description

Default Value

7

6

External Reset disable

DebugWIRE Enable

1 (unprogrammed)

Enable Serial Program and Data

Downloading

0 (programmed, SPI prog.

enabled)

SPIEN⁽³⁾

WDTON⁽⁴⁾

EESAVE

6

4

3

Watchdog Timer always on

1 (unprogrammed)

EEPROM memory is preserved

through the Chip Erase

1 (unprogrammed, EEPROM

not preserved)

BODLEVEL2⁽⁵⁾

BODLEVEL1⁽⁵⁾

BODLEVEL0⁽⁵⁾

2

1

0

Brown-out Detector trigger level

1 (unprogrammed)

Notes: 1. See ”Alternate Functions of Port B” on page 61 for description of RSTDISBL and DWEN

Fuses.

2. DWEN must be unprogrammed when Lock Bit security is required. See Section “22.1” on page

168.

3. The SPIEN Fuse is not accessible in SPI Programming mode.

4. See ”WDTCR – Watchdog Timer Control Register” on page 44 for details.

5. See Table 23-4 on page 189 for BODLEVEL Fuse decoding.

6. When programming the RSTDISBL Fuse, High-voltage Serial programming has to be used to

change fuses to perform further programming.

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Table 22-5. Fuse Low Byte

Fuse Low Byte

CKDIV8⁽¹⁾

CKOUT⁽²⁾

SUT1

Bit No Description

Default Value

7

6

5

4

3

2

1

0

Divide clock by 8

0 (programmed)

Clock Output Enable

Select start-up time

Select Clock source

1 (unprogrammed)

1 (unprogrammed)⁽³⁾

0 (programmed)⁽³⁾

0 (programmed)⁽⁴⁾

1 (unprogrammed)⁽⁴⁾

0 (programmed)⁽⁴⁾

SUT0

CKSEL3

CKSEL2

CKSEL1

CKSEL0

Notes: 1. See ”System Clock Prescaler” on page 31 for details.

2. The CKOUT Fuse allows the system clock to be output on PORTB5. See “Clock Output Buffer”

on page 30 for details.

3. The default value of SUT1..0 results in maximum start-up time for the default clock source.

See Table 7-7 on page 28 for details.

4. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8.0 MHz. See Table 7-6

on page 28 for details.

The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if

Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.

22.2.1

Latching of Fuses

The fuse values are latched when the device enters programming mode and changes of the

fuse values will have no effect until the part leaves Programming mode. This does not apply to

the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on

Power-up in Normal mode.

22.3 Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This

code can be read in both serial and High-voltage Programming mode, also when the device is

locked. The three bytes reside in a separate address space. The ATtiny261/461/861signature

bytes are given in Table 22-6.

Table 22-6. Device ID

Signature Bytes Address

Parts

0x000

0x1E

0x001

0x91

0x92

0x93

0x002

0x0C

0x08

ATtiny261

ATtiny461

ATtiny861

0x0D

22.4 Calibration Byte

Signature area of the ATtiny261/461/861 has one byte of calibration data for the internal RC

Oscillator. This byte resides in the high byte of address 0x000. During reset, this byte is auto-

matically written into the OSCCAL Register to ensure correct frequency of the calibrated RC

Oscillator.

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22.5 Page Size

Table 22-7. No. of Words in a Page and No. of Pages in the Flash

Device

ATtiny261

ATtiny461

ATtiny861

Flash Size

Page Size PCWORD No. of Pages PCPAGE PCMSB

1K words (2K bytes)

2K words (4K bytes)

4K words (8K bytes)

16 words

32 words

PC[3:0]

PC[4:0]

64

PC[9:4]

PC[10:5]

PC[11:5]

9

10

11

128

Table 22-8. No. of Words in a Page and No. of Pages in the EEPROM

EEPROM

Device

ATtiny261

ATtiny461

ATtiny861

Size

Page Size

4 bytes

PCWORD

EEA[1:0]

No. of Pages

PCPAGE

EEAMSB

128 bytes

256 bytes

512 bytes

64

EEA[6:2]

EEA[7:2]

EEA[8:2]

6

7

8

4 bytes

128

22.6 Parallel Programming Parameters, Pin Mapping, and Commands

This section describes how to parallel program and verify Flash Program memory, EEPROM

Data memory, Memory Lock bits, and Fuse bits in the ATtiny261/461/861. Pulses are assumed

to be at least 250 ns unless otherwise noted.

22.6.1

Signal Names

In this section, some pins of the ATtiny261/461/861 are referenced by signal names describing

their functionality during parallel programming, see Figure 22-1 and Table 22-9. Pins not

described in the following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.

The bit coding is shown in Table 22-11.

When pulsing WR or OE, the command loaded determines the action executed. The different

Commands are shown in Table 22-12.

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Figure 22-1. Parallel Programming

+5V

WR

PB0

PB1

VCC

XA0

AVCC

XA1/BS2

PB2

PB3

PA7 - PA0

DATA

PAGEL/BS1

AL1/PB4

XT

OE

RDY/BSY

+12 V

PB5

PB6

RESET

GND

Table 22-9. Pin Name Mapping

Signal Name in

Programming Mode

Name

I/O

Function

WR

PB0

PB1

I

Write Pulse (Active low).

XTAL Action Bit 0

XA0

XTAL Action Bit 1. Byte Select 2 (“0” selects low byte, “1”

selects 2’nd high byte).

XA1/BS2

PB2

I

Byte Select 1 (“0” selects low byte, “1” selects high byte).

Program Memory and EEPROM Data Page Load.

PAGEL/BS1

OE

PB3

PB5

I

Output Enable (Active low).

0: Device is busy programming, 1: Device is ready for new

command.

RDY/BSY

DATA I/O

PB6

O

I/O

PA7-PA0

Bi-directional Data bus (Output when OE is low).

Table 22-10. Pin Values Used to Enter Programming Mode

PAGEL/BS1

XA1/BS2

XA0

Symbol

Value

Prog_enable[3]

Prog_enable[2]

Prog_enable[1]

Prog_enable[0]

0

WR

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Table 22-11. XA1 and XA0 Coding

XA1

XA0

Action when XTAL1 is Pulsed

0

1

0

1

0

1

Load Flash or EEPROM Address (High or low address byte determined by BS1).

Load Data (High or Low data byte for Flash determined by BS1).

Load Command

No Action, Idle

Table 22-12. Command Byte Bit Coding

Command Byte

1000 0000

0100 0000

0010 0000

0001 0000

0001 0001

0000 1000

0000 0100

0000 0010

0000 0011

Command Executed

Chip Erase

Write Fuse bits

Write Lock bits

Write Flash

Write EEPROM

Read Signature Bytes and Calibration byte

Read Fuse and Lock bits

Read Flash

Read EEPROM

22.7 Parallel Programming

22.7.1

Enter Programming Mode

The following algorithm puts the device in parallel programming mode:

1. Apply 4.5 - 5.5V between V_CCand GND.

2. Set RESET to “0” and toggle XTAL1 at least six times.

3. Set the Prog_enable pins listed in Table 22-10 on page 172 to “0000” and wait at least

100 ns.

4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V

has been applied to RESET, will cause the device to fail entering programming mode.

5. Wait at least 50 µs before sending a new command.

22.7.2

Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient

programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the

EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address high byte needs only be loaded before programming or reading a new 256 word

window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes

reading.

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22.7.3

Chip Erase

The Chip Erase will erase the Flash and EEPROM⁽¹⁾memories plus Lock bits. The Lock bits are

not reset until the program memory has been completely erased. The Fuse bits are not

changed. A Chip Erase must be performed before the Flash and/or EEPROM are

reprogrammed.

Note:

1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a new command.

22.7.4

Programming the Flash

The Flash is organized in pages, see Table 22-7 on page 171. When programming the Flash,

the program data is latched into a page buffer. This allows one page of program data to be pro-

grammed simultaneously. The following procedure describes how to program the entire Flash

memory:

A. Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address low byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte (0x00 - 0xFF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. This selects high data byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the data byte.

1. E. Latch Data

2. Set BS1 to “1”. This selects high data byte.

3. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 22-3 for signal

waveforms)

F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.

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While the lower bits in the address are mapped to words within the page, the higher bits address

the pages within the FLASH. This is illustrated in Figure 22-2 on page 175. Note that if less than

eight bits are required to address words in the page (pagesize < 256), the most significant bit(s)

in the address low byte are used to address the page when performing a Page Write.

G. Load Address High byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

H. Program Page

1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY

goes low.

2. Wait until RDY/BSY goes high (See Figure 22-3 for signal waveforms).

I. Repeat B through H until the entire Flash is programmed or until all data has been

programmed.

J. End Page Programming

1. 1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are

reset.

Figure 22-2. Addressing the Flash Which is Organized in Pages⁽¹⁾

PCMSB

PAGEMSB

PROGRAM

COUNTER

PCPAGE

PCWORD

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. PCPAGE and PCWORD are listed in Table 22-7 on page 171.

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Figure 22-3. Programming the Flash Waveforms⁽¹⁾

F

A

B

C

D

E

B

C

D

E

G

H

0x10

ADDR. LOW

DATA LOW

DATA HIGH

ADDR. LOW DATA LOW

DATA HIGH

ADDR. HIGH

XX

DATA

XA1/BS2

XA0

PAGEL/BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

Note:

1. “XX” is don’t care. The letters refer to the programming description above.

22.7.5

Programming the EEPROM

The EEPROM is organized in pages, see Table 22-8 on page 171. When programming the

EEPROM, the program data is latched into a page buffer. This allows one page of data to be

programmed simultaneously. The programming algorithm for the EEPROM data memory is as

follows (refer to ”Programming the Flash” on page 174 for details on Command, Address and

Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. C: Load Data (0x00 - 0xFF).

5. E: Latch data (give PAGEL a positive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page

1. Set BS to “0”.

2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY

goes low.

3. Wait until to RDY/BSY goes high before programming the next page (See Figure 22-4 for

signal waveforms).

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Figure 22-4. Programming the EEPROM Waveforms

K

A

G

B

C

E

B

C

E

L

0x11

ADDR. HIGH

ADDR. LOW

DATA

ADDR. LOW

DATA

XX

DATA

XA1/BS2

XA0

PAGEL/BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

22.7.6

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to ”Programming the Flash” on

page 174 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

5. Set BS to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

22.7.7

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to ”Programming the Flash”

on page 174 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.

5. Set OE to “1”.

22.7.8

Programming the Fuse Low Bits

The algorithm for programming the Fuse Low bits is as follows (refer to ”Programming the Flash”

on page 174 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

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22.7.9

Programming the Fuse High Bits

The algorithm for programming the Fuse High bits is as follows (refer to ”Programming the

Flash” on page 174 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS1 to “0”. This selects low data byte.

22.7.10 Programming the Extended Fuse Bits

The algorithm for programming the Extended Fuse bits is as follows (refer to ”Programming the

Flash” on page 174 for details on Command and Data loading):

1. 1. A: Load Command “0100 0000”.

2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.

4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. 5. Set BS2 to “0”. This selects low data byte.

Figure 22-5. Programming the FUSES Waveforms

Write Fuse Low byte

Write Fuse high byte

Write Extended Fuse byte

A

C

A

C

A

C

0x40

DATA

XX

0x40

DATA

XX

0x40

DATA

XX

DATA

XA1/BS2

XA0

PAGEL/BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

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22.7.11 Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to ”Programming the Flash” on

page 174 for details on Command and Data loading):

1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed

(LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any

External Programming mode.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

22.7.12 Reading the Fuse and Lock Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to ”Programming the Flash”

on page 174 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be

read at DATA (“0” means programmed).

3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be

read at DATA (“0” means programmed).

4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now

be read at DATA (“0” means programmed).

5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at

DATA (“0” means programmed).

6. Set OE to “1”.

Figure 22-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

0

Fuse Low Byte

Extended Fuse Byte

Lock Bits

0

1

0

DATA

BS2

BS1

Fuse High Byte

1

BS2

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22.7.13 Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to ”Programming the Flash” on

page 174 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte (0x00 - 0x02).

3. Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA.

4. Set OE to “1”.

22.7.14 Reading the Calibration Byte

The algorithm for reading the Calibration byte is as follows (refer to ”Programming the Flash” on

page 174 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, 0x00.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4. Set OE to “1”.

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22.8 Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-

put). After RESET is set low, the Programming Enable instruction needs to be executed first

before program/erase operations can be executed. NOTE, in Table 22-13 on page 181, the pin

mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal

SPI interface.

Figure 22-7. Serial Programming and Verify⁽¹⁾

+1.8 - 5.5V

VCC

MOSI

MISO

SCK

RESET

GND

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

CLKI pin.

Table 22-13. Pin Mapping Serial Programming

Symbol

MOSI

MISO

SCK

Pins

PB0

PB1

PB2

I/O

Description

Serial Data in

Serial Data out

Serial Clock

I

O

I

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

High: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

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22.8.1

Serial Programming Algorithm

When writing serial data to the ATtiny261/461/861, data is clocked on the rising edge of SCK.

When reading data from the ATtiny261/461/861, data is clocked on the falling edge of SCK. See

Figure 23-7 and Figure 23-8 for timing details.

To program and verify the ATtiny261/461/861 in the Serial Programming mode, the following

sequence is recommended (see four byte instruction formats in Table 22-15):

1. Power-up sequence:

Apply power between V_CCand GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

3. The serial programming instructions will not work if the communication is out of synchro-

nization. When in sync. the second byte (0x53), will echo back when issuing the third

byte of the Programming Enable instruction. Whether the echo is correct or not, all four

bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a

positive pulse and issue a new Programming Enable command.

4. The Flash is programmed one page at a time. The memory page is loaded one byte at a

time by supplying the 5 LSB of the address and data together with the Load Program

memory Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program memory

Page is stored by loading the Write Program memory Page instruction with the 6 MSB of

the address. If polling (RDY/BSY) is not used, the user must wait at least t_{WD_FLASH}before

issuing the next page. (See Table 22-14.) Accessing the serial programming interface

before the Flash write operation completes can result in incorrect programming.

5. A: The EEPROM array is programmed one byte at a time by supplying the address and

data together with the appropriate Write instruction. An EEPROM memory location is first

automatically erased before new data is written. If polling (RDY/BSY) is not used, the

user must wait at least t_{WD_EEPROM}before issuing the next byte. (See Table 22-14.) In a

chip erased device, no 0xFFs in the data file(s) need to be programmed.

B: The EEPROM array is programmed one page at a time. The Memory page is loaded

one byte at a time by supplying the 2 LSB of the address and data together with the Load

EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading

the Write EEPROM Memory Page Instruction with the 6 MSB of the address. When using

EEPROM page access only byte locations loaded with the Load EEPROM Memory Page

instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is

not used, the used must wait at least t_{WD_EEPROM}before issuing the next page (See Table

22-8). In a chip erased device, no 0xFF in the data file(s) need to be programmed.

6. Any memory location can be verified by using the Read instruction which returns the con-

tent at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence normal

operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn V_CCpower off.

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Table 22-14. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol

Minimum Wait Delay

4.5 ms

t_{WD_FLASH}

t_{WD_EEPROM}

t_{WD_ERASE}

t_{WD_FUSE}

4.0 ms

4.5 ms

22.8.2

Serial Programming Instruction set

Table 22-15 on page 183 and Figure 22-8 on page 184 describes the Instruction set.

Table 22-15. Serial Programming Instruction Set

Instruction Format

Instruction/Operation

Byte 1

$AC

Byte 2

Byte 3

$00

Byte4

$00

Programming Enable

$53

$80

$00

Chip Erase (Program Memory/EEPROM)

Poll RDY/BSY

$AC

$00

$F0

$00

data byte out

Load Instructions

Load Extended Address byte⁽¹⁾

Load Program Memory Page, High byte

Load Program Memory Page, Low byte

Load EEPROM Memory Page (page access)

Read Instructions

$4D

$48

$40

$C1

$00

adr MSB

$00

Extended adr

adr LSB

$00

high data byte in

low data byte in

data byte in

adr LSB

0000 000aa

Read Program Memory, High byte

Read Program Memory, Low byte

Read EEPROM Memory

Read Lock bits

$28

$20

$A0

$58

$30

$50

$58

$50

$38

adr MSB

$00

adr LSB

00aa aaaa

$00

high data byte out

low data byte out

data byte out

$00

Read Signature Byte

$00

0000 000aa

$00

Read Fuse bits

$00

Read Fuse High bits

$08

$00

Read Extended Fuse Bits

$08

$00

Read Calibration Byte

$00

Write Instructions⁽⁶⁾

Write Program Memory Page

Write EEPROM Memory

Write EEPROM Memory Page (page access)

Write Lock bits

$4C

$C0

$C2

$AC

adr MSB

$00

adr LSB

00aa aaaa

00aa aa00

$00

data byte in

$00

$E0

data byte in

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Table 22-15. Serial Programming Instruction Set (Continued)

Instruction Format

Instruction/Operation

Write Fuse bits

Byte 1

$AC

Byte 2

Byte 3

$00

Byte4

$A0

$A8

$A4

data byte in

Write Fuse High bits

Write Extended Fuse Bits

$AC

$00

$AC

$00

Notes: 1. Not all instructions are applicable for all parts.

2. a = address

3. Bits are programmed ‘0’, unprogrammed ‘1’.

4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .

5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size.

6. Instructions accessing program memory use a word address. This address may be random within the page range.

7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.

If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until

this bit returns ‘0’ before the next instruction is carried out.

Within the same page, the low data byte must be loaded prior to the high data byte.

After data is loaded to the page buffer, program the EEPROM page, see Figure 22-8 on page

184.

Figure 22-8. Serial Programming Instruction example

Serial Programming Instruction

Load Program Memory Page (High/Low Byte)/

Load EEPROM Memory Page (page access)

Write Program Memory Page/

Write EEPROM Memory Page

Byte 1

Byte 2

Byte 3

Byte 4

Byte 1

Byte 2

Byte 3

Byte 4

Adr MSB

Adr LSB

Adr MSB

Adr LSB

Bit 15 B

0

Bit 15 B

0

Page Buffer

Page Offset

Page 0

Page 1

Page 2

Page Number

Page N-1

Program Memory/

EEPROM Memory

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ATtiny261/461/861

23. Electrical Characteristics

23.1 Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to V_CC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V_CCand GND Pins................................ 200.0 mA

23.2 DC Characteristics

T_A= -40°C to 85°C, V_CC= 1.8V to 5.5V (unless otherwise noted)⁽¹⁾

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

Except XTAL1 and RESET

V_IL

Input Low-voltage

-0.5

0.2V_CC

V

Except XTAL1 and RESET

(3)

V_IH

Input High-voltage

Input Low-voltage

Input High-voltage

0.7V_CC

-0.5

V_CC+0.5

0.1V_CC

V

XTAL1 pin, External

Clock Selected

V_IL1

XTAL1 pin, External

Clock Selected

V_IH1

0.8V_CC

V_CC+0.5

V_IL2

V_IH2

V_IL3

V_IH3

Input Low-voltage

Input High-voltage

Input Low-voltage

Input High-voltage

RESET pin

-0.5

0.9V_CC

-0.5

0.2V_CC

V_CC+0.5

0.2V_CC

V

(3)

RESET pin

RESET pin as I/O

0.7V_CC

V_CC+0.5

Output Low Voltage⁽⁴⁾

(Except Reset pin)

I_OL= 10 mA, V_CC= 5V

I_OL= 5 mA, V_CC= 3V

0.6

0.5

V

V_OL

V_OH

I_IL

Output High-voltage⁽⁵⁾

(Except Reset pin)

I

_OH= -10 mA, V_CC= 5V

4.3

2.5

V

I_OH= -5 mA, V_CC= 3V

Input Leakage

Current I/O Pin

Vcc = 5.5V, pin low

(absolute value)

<0.05

1

µA

Input Leakage

Current I/O Pin

Vcc = 5.5V, pin high

(absolute value)

I_IH

R_RST

R_PU

Reset Pull-up Resistor

I/O Pin Pull-up Resistor

30

20

60

50

kΩ

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T_A= -40°C to 85°C, V_CC= 1.8V to 5.5V (unless otherwise noted)⁽¹⁾(Continued)

Symbol

Parameter

Condition

Min.

Typ.

0.4

2

Max.

0.6

3

Units

mA

µA

Active 1MHz, V_CC= 2V⁽⁶⁾

Active 4MHz, V_CC= 3V⁽⁶⁾

Active 8MHz, V_CC= 5V⁽⁶⁾

Idle 1MHz, V_CC= 2V⁽⁶⁾

Idle 4MHz, V_CC= 3V⁽⁶⁾

Idle 8MHz, V_CC= 5V⁽⁶⁾

WDT enabled, V_CC= 3V⁽⁷⁾

WDT disabled, V_CC= 3V⁽⁷⁾

6

9

Power Supply Current

0.1

0.4

1.5

4

0.3

1

I_CC

3

10

2

Power-down mode

0.15

µA

Notes: 1. Typical values at 25 °C. Maximum values are characterized values and not test limits in production.

2. “Max” means the highest value where the pin is guaranteed to be read as low.

3. “Min” means the lowest value where the pin is guaranteed to be read as high.

4. Although each I/O port can sink more than the test conditions (10 mA at V_CC= 5V, 5 mA at V_CC= 3V) under steady state

conditions (non-transient), the following must be observed:

1] The sum of all IOL, for all ports, should not exceed 60 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

5. Although each I/O port can source more than the test conditions (10 mA at V_CC= 5V, 5 mA at V_CC= 3V) under steady state

conditions (non-transient), the following must be observed:

1] The sum of all IOH, for all ports, should not exceed 60 mA.

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

6. Values using methods described in ”Minimizing Power Consumption” on page 35. Power Reduction is enabled (PRR =

0xFF) and there is no I/O drive.

7. BOD Disabled.

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23.3 Speed Grades

Figure 23-1. Maximum Frequency vs. V_CC

10 MHz

Safe Operating Area

4 MHz

1.8V

2.7V

5.5V

Figure 23-2. Maximum Frequency vs. V_CC

20 MHz

10 MHz

Safe Operating Area

2.7V

4.5V

5.5V

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23.4 Clock Characteristics

23.4.1

Calibrated Internal RC Oscillator Accuracy

Table 23-1. Calibration Accuracy of Internal RC Oscillator

Frequency

V_CC

Temperature

Calibration Accuracy

Factory

Calibration

8.0 MHz

3V

25°C

10%

User

Calibration

1.8V - 5.5V⁽¹⁾

2.7V - 5.5V⁽²⁾

7.3 - 8.1 MHz

-40°C - 85°C

1%

Notes: 1. Voltage range for ATtiny261V/461V/861V.

2. Voltage range for ATtiny261/461/861.

23.4.2

External Clock Drive Waveforms

Figure 23-3. External Clock Drive Waveforms

V_IH1

V_IL1

23.4.3

External Clock Drive

Table 23-2. External Clock Drive

V_CC= 1.8 - 5.5V

V_CC= 2.7 - 5.5V

V_CC= 4.5 - 5.5V

Symbol

1/t_CLCL

t_CLCL

Parameter

Min.

Max.

Min.

0

Max.

Min.

0

Max.

Units

MHz

ns

Clock Frequency

0

4

10

20

Clock Period

250

100

40

50

20

t_CHCX

t_CLCX

High Time

ns

Low Time

40

ns

t_CLCH

Rise Time

2.0

2

1.6

2

0.5

2

μs

t_CHCL

Fall Time

μs

Δt_CLCL

Change in period from one clock cycle to the next

%

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23.5 System and Reset Characteristics

Table 23-3. Reset, Brown-out and Internal Voltage Characteristics⁽¹⁾

Symbol

Parameter

Condition

Min

Typ

Max

Units

Power-on Reset Threshold

Voltage (rising)

T_A= -40 - 85°C

0.7

1.0

1.4

V

V_POT

Power-on Reset Threshold

Voltage (falling)⁽²⁾

T_A= -40 - 85°C

0.6

0.9

1.3

0.9 V_CC

2.5

V

RESET Pin Threshold

Voltage

V_RST

t_RST

V_HYST

t_BOD

V_BG

t_BG

V_CC= 3V

0.2 V_CC

Minimum pulse width on

RESET Pin

V_CC= 3V

µs

mV

µs

V

Brown-out Detector

Hysteresis

50

2

Min Pulse Width on Brown-

out Reset

V_CC= 2.7V,

Bandgap reference voltage

1.0

1.1

40

15

1.2

70

T_A= 25°C

Bandgap reference start-up

time

V_CC= 2.7V,

T_A= 25°C

µs

µA

Bandgap reference current

consumption

V_CC= 2.7V,

T_A= 25°C

I_BG

Notes: 1. Values are guidelines only. Actual values are TBD.

2. The Power-on Reset will not work unless the supply voltage has been below V_POT(falling)

Table 23-4. BODLEVEL Fuse Coding⁽¹⁾

BODLEVEL [2..0] Fuses

Min V_BOT

Typ V_BOT

Max V_BOT

Units

111

110

101

100

011

010

001

000

BOD Disabled

1.7

2.5

4.1

1.8

2.7

4.3

2.0

2.9

4.5

V

Reserved

Note:

1. V_BOTmay be below nominal minimum operating voltage for some devices. For devices where

this is the case, the device is tested down to V_CC= V_BOTduring the production test. This guar-

antees that a Brown-out Reset will occur before V_CCdrops to a voltage where correct

operation of the microcontroller is no longer guaranteed.

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23.6 ADC Characteristics – Preliminary Data

Table 23-5. ADC Characteristics, Single Ended Channels. -40°C - 85°C

Symbol

Parameter

Condition

Min⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

Units

Resolution

Single Ended Conversion

10

Bits

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

2

3

LSB

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 1 MHz

Absolute accuracy (Including

INL, DNL, quantization error,

gain and offset error)

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

1.5

2.5

LSB

ADC clock = 200 kHz

Noise Reduction Mode

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 1 MHz

Noise Reduction Mode

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

Integral Non-linearity (INL)

Differential Non-linearity (DNL)

Gain Error

1

LSB

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

0.5

2.5

1.5

ADC clock = 200 kHz

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

Offset Error

ADC clock = 200 kHz

Conversion Time

Free Running Conversion

13

50

260

1000

V_REF

µs

kHz

V

Clock Frequency

V_IN

Input Voltage

GND

Input Bandwidth

38.5

1.1

kHz

V

V_INT

Internal Voltage Reference

Analog Input Resistance

1.0

1.2

R_AIN

100

MΩ

Note:

1. Values are preliminary.

190

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23.7 Parallel Programming Characteristics

Figure 23-4. Parallel Programming Timing, Including some General Timing Requirements

t_XLWL

t_XHXL

XTAL1

t_DVXH

t_XLDX

Data & Contol

(DATA, XA0, XA1/BS2, PAGEL/BS1)

t_BVPH

t_PLBXt_BVWL

t_WLBX

t_WLWH

WR

t_PLWL

WLRL

RDY/BSY

t_WLRH

Figure 23-5. Parallel Programming Timing, Loading Sequence with Timing Requirements⁽¹⁾

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLXH

XTAL1

PAGEL/BS1

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1/BS2

Note:

1. The timing requirements shown in Figure 23-4 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to load-

ing operation.

191

2588B–AVR–11/06

Figure 23-6. Parallel Programming Timing, Reading Sequence (within the Same Page) with

Timing Requirements⁽¹⁾

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLOL

XTAL1

t_BVDV

PAGEL/BS1

t_OLDV

OE

t_OHDZ

ADDR1 (Low Byte)

DATA (High Byte)

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

XA0

XA1/BS2

Note:

1. The timing requirements shown in Figure 23-4 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to read-

ing operation.

192

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Table 23-6. Parallel Programming Characteristics, V_CC= 5V 10%

Symbol

V_PP

Parameter

Min

Typ

Max

12.5

250

Units

V

Programming Enable Voltage

Programming Enable Current

Data and Control Valid before XTAL1 High

XTAL1 Low to XTAL1 High

XTAL1 Pulse Width High

Data and Control Hold after XTAL1 Low

XTAL1 Low to WR Low

11.5

I_PP

μA

ns

μs

ms

ns

t_DVXH

t_XLXH

t_XHXL

t_XLDX

t_XLWL

t_BVPH

t_PHPL

t_PLBX

t_WLBX

t_PLWL

t_BVWL

t_WLWH

t_WLRL

t_WLRH

t_{WLRH_CE}

t_XLOL

t_BVDV

t_OLDV

t_OHDZ

67

200

150

67

0

BS1 Valid before PAGEL High

PAGEL Pulse Width High

BS1 Hold after PAGEL Low

BS2/1 Hold after WR Low

PAGEL Low to WR Low

67

150

67

150

0

BS1 Valid to WR Low

WR Pulse Width Low

WR Low to RDY/BSY Low

WR Low to RDY/BSY High⁽¹⁾

WR Low to RDY/BSY High for Chip Erase⁽¹⁾

XTAL1 Low to OE Low

1

4.5

9

3.7

7.5

0

BS1 Valid to DATA valid

0

250

OE Low to DATA Valid

OE High to DATA Tri-stated

Note:

1. t_WLRHis valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits

commands.

1.

t_{WLRH_CE}is valid for the Chip Erase command.

193

2588B–AVR–11/06

23.8 Serial Programming Characteristics

Figure 23-7. Serial Programming Waveforms

SERIAL DATA INPUT

(MOSI)

MSB

LSB

SERIAL DATA OUTPUT

(MISO)

MSB

SERIAL CLOCK INPUT

(SCK)

SAMPLE

Figure 23-8. Serial Programming Timing

MOSI

t_OVSH

t_SLSH

t_SHOX

SCK

t_SHSL

MISO

t_SLIV

Table 23-7. Serial Programming Characteristics, T_A= -40°C to 85°C, V_CC= 1.8 - 5.5V (Unless

Otherwise Noted)

Symbol

1/t_CLCL

t_CLCL

Parameter

Min

0

Typ

Max

Units

MHz

ns

Oscillator Frequency (ATtiny261/461/861V)

Oscillator Period (ATtiny261/461/861V)

4

250

Oscillator Frequency (ATtiny261/461/861L, VCC =

2.7 - 5.5V)

1/t_CLCL

t_CLCL

1/t_CLCL

t_CLCL

0

100

0

10

20

MHz

ns

Oscillator Period (ATtiny261/461/861L, VCC = 2.7 -

5.5V)

Oscillator Frequency (ATtiny261/461/861, V_CC= 4.5V

- 5.5V)

MHz

ns

Oscillator Period (ATtiny261/461/861, V_CC= 4.5V -

5.5V)

50

t_SHSL

t_SLSH

t_OVSH

t_SHOX

t_SLIV

SCK Pulse Width High

SCK Pulse Width Low

MOSI Setup to SCK High

MOSI Hold after SCK High

SCK Low to MISO Valid

2 t_CLCL*

ns

2 t_CLCL

*

t_CLCL

2 t_CLCL

TBD

Note:

1. 2 t_CLCLfor f_ck< 12 MHz, 3 t_CLCLfor f_ck>= 12 MHz

194

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ATtiny261/461/861

24. Typical Characteristics

The data contained in this section is largely based on simulations and characterization of similar

devices in the same process and design methods. Thus, the data should be treated as indica-

tions of how the part will behave.

The following charts show typical behavior. These figures are not tested during manufacturing.

All current consumption measurements are performed with all I/O pins configured as inputs and

with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock

source.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage, operating

frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera-

ture. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as C_L*V_CC*f where

C_L= load capacitance, V_CC= operating voltage and f = average switching frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to

function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog Timer

enabled and Power-down mode with Watchdog Timer disabled represents the differential cur-

rent drawn by the Watchdog Timer.

24.1 Active Supply Current

Figure 24-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz)

ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MHZ

1,2

5.5 V

5.0 V

1

0,8

0,6

0,4

0,2

0

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

1

Frequency (MHz)

195

2588B–AVR–11/06

Figure 24-2. Active Supply Current vs. Frequency (1 - 20 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

16

14

12

10

8

5.5 V

5.0 V

4.5 V

4.0 V

6

4

2

0

3.3 V

2.7 V

1.8 V

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 24-3. Active Supply Current vs. V_CC(Internal RC Oscillator, 8 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 8 MHz

7

85 ˚C

25 ˚C

6

5

4

3

2

1

0

-40 ˚C

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

196

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2588B–AVR–11/06

ATtiny261/461/861

Figure 24-4. Active Supply Current vs. V_CC(Internal RC Oscillator, 1 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 1 MHz

1,6

1,4

1,2

1

85 ˚C

25 ˚C

-40 ˚C

0,8

0,6

0,4

0,2

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

Figure 24-5. Active Supply Current vs. V_CC(Internal RC Oscillator, 128 kHz)

ACTIVE SUPPLY CURRENT vs. V

CC

INTERNAL RC OSCILLATOR, 128 kHz

0,3

0,25

0,2

85 ˚C

-40 ˚C

25 ˚C

0,15

0,1

0,05

0

1,5

2

2,5

3

3,5

_CC(V)

4

4,5

5

5,5

V

197

2588B–AVR–11/06

24.2 Idle Supply Current

Figure 24-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz)

IDLE SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MHz

0,3

0,25

0,2

5.5 V

5.0 V

4.5 V

4.0 V

0,15

0,1

3.3 V

2.7 V

1.8 V

0,05

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

1

Frequency (MHz)

Figure 24-7. Idle Supply Current vs. Frequency (1 - 20 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

4,5

4

3,5

3

5.5 V

5.0 V

4.5 V

2,5

2

4.0 V

1,5

3.3 V

1

2.7 V

0,5

1.8 V

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

198

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Figure 24-8. Idle Supply Current vs. V_CC(Internal RC Oscillator, 8 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 8 MHz

2,5

2

85 ˚C

25 ˚C

-40 ˚C

1,5

1

0,5

0

1,5

2

2,5

3

3,5

_CC(V)

4

4,5

5

5,5

V

Figure 24-9. Idle Supply Current vs. V_CC(Internal RC Oscillator, 1 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 1 MHz

0,7

0,6

0,5

0,4

0,3

0,2

0,1

0

85 ˚C

25 ˚C

-40 ˚C

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

199

2588B–AVR–11/06

Figure 24-10. Idle Supply Current vs. V_CC(Internal RC Oscillator, 128 kHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 128 kHz

0,2

85 ˚C

0,18

0,16

0,14

0,12

0,1

25 ˚C

0,08

0,06

0,04

0,02

0

-40 ˚C

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

24.3 Supply Current of I/O modules

The tables and formulas below can be used to calculate the additional current consumption for

the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules

are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on

page 37 for details.

Table 24-1. Additional Current Consumption for the different I/O modules (absolute values)

PRR bit

Typical numbers

_CC= 2V, F = 1MHz

V

V_CC= 3V, F = 4MHz

423 uA

V_CC= 5V, F = 8MHz

1787 uA

PRTIM1

PRTIM0

PRUSI

65 uA

7 uA

39 uA

165 uA

5 uA

25 uA

457 uA

PRADC

18 uA

111 uA

102 uA

Table 24-2. Additional Current Consumption (percentage) in Active and Idle mode

Additional Current consumption

compared to Active with external

clock (see Figure 24-1 on page

195 and Figure 24-2 on page 196)

Additional Current consumption

compared to Idle with external

clock (see Figure 24-6 on page

198 and Figure 24-7 on page 198)

PRR bit

PRTIM1

PRTIM0

PRUSI

26.9 %

2.6 %

1.7 %

7.1 %

103.7 %

10.0 %

6.5 %

PRADC

27.3 %

It is possible to calculate the typical current consumption based on the numbers from Table 24-1

for other V_CCand frequency settings than listed in Table 24-2.

200

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Example

Calculate the expected current consumption in idle mode with TIMER0, ADC, and USI enabled

at V_CC= 2.0V and F = 1MHz. From Table 24-2, third column, we see that we need to add 10%

for the TIMER0, 27.3 % for the ADC, and 6.5 % for the USI module. Reading from Figure 24-6

on page 198, we find that the idle current consumption is ~0,085 mA at V_CC= 2.0V and F=1MHz.

The total current consumption in idle mode with TIMER0, ADC, and USI enabled, gives:

ICCtotal ≈ 0,085mA • (1 + 0,10 + 0,273 + 0,065) ≈ 0,122mA

24.4 Power-down Supply Current

Figure 24-11. Power-down Supply Current vs. V_CC(Watchdog Timer Disabled)

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER DISABLED

1,6

1,4

1,2

1

85 ˚C

0,8

0,6

0,4

0,2

0

-40 ˚C

25 ˚C

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

Figure 24-12. Power-down Supply Current vs. V_CC(Watchdog Timer Enabled)

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER ENABLED

10

-40 ˚C

9

8

7

6

5

4

3

2

1

0

85 ˚C

25 ˚C

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

201

2588B–AVR–11/06

24.5 Pin Pull-up

Figure 24-13. I/O Pin pull-up Resistor Current vs. Input Voltage (V_CC= 1.8V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_CC= 1.8V

60

50

40

30

20

10

25 ˚C

85 ˚C

-40 ˚C

0

0,2

0,4

0,6

0,8

1

1,2

1,4

1,6

1,8

2

V_OP(V)

Figure 24-14. I/O Pin pull-up Resistor Current vs. Input Voltage (V_CC= 2.7V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_CC= 2.7V

90

80

70

60

50

40

30

20

10

0

25 ˚C

85 ˚C

-40 ˚C

0

0,5

1

1,5

2

2,5

3

V_OP(V)

202

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Figure 24-15. I/O Pin pull-up Resistor Current vs. Input Voltage (V_CC= 5V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_CC= 5V

160

140

120

100

80

60

40

25 ˚C

85 ˚C

-40 ˚C

20

0

1

2

3

4

5

6

V_OP(V)

Figure 24-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 1.8V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V_CC= 1.8V

40

35

30

25

20

15

10

25 ˚C

5

-40 ˚C

85 ˚C

0

0,2

0,4

0,6

0,8

1

1,2

1,4

1,6

1,8

2

V_RESET(V)

203

2588B–AVR–11/06

Figure 24-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 2.7V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V_CC= 2.7V

70

60

50

40

30

20

25 ˚C

10

-40 ˚C

85 ˚C

0

0,5

1

1,5

2

2,5

3

V_RESET(V)

Figure 24-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 5V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V_CC= 5V

120

100

80

60

40

25 ˚C

20

0

-40 ˚C

85 ˚C

0

1

2

3

4

5

6

V_RESET(V)

204

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

24.6 Pin Driver Strength

Figure 24-19. I/O Pin Output Voltage vs. Sink Current (V_CC= 3V)

I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

V_CC= 3V

0,9

0,8

0,7

0,6

0,5

0,4

0,3

0,2

0,1

0

85 ˚C

25 ˚C

-40 ˚C

0

5

10

15

20

25

I_OL(mA)

Figure 24-20. I/O Pin Output Voltage vs. Sink Current (V_CC= 5V)

I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

V_CC= 5V

0,6

85 ˚C

0,5

0,4

0,3

0,2

0,1

0

25 ˚C

-40 ˚C

0

5

10

15

20

25

I_OL(mA)

205

2588B–AVR–11/06

Figure 24-21. I/O Pin Output Voltage vs. Source Current (V_CC= 3V)

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

V_CC= 3V

3,1

2,9

2,7

2,5

-40 ˚C

2,3

25 ˚C

2,1

85 ˚C

1,9

1,7

1,5

0

5

10

15

20

25

I_OH(mA)

Figure 24-22. I/O Pin Output Voltage vs. Source Current (V_CC= 5V)

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

V_CC= 5V

5

4,8

4,6

-40 ˚C

25 ˚C

4,4

85 ˚C

4,2

4

0

5

10

15

20

25

I_OH(mA)

206

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

24.7 Pin Threshold and Hysteresis

Figure 24-23. I/O Pin Input Threshold Voltage vs. V_CC(V_IH, I/O Pin Read as ‘1’)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_CC

VIH, IO PIN READ AS '1'

3,5

3

-40 ˚C

25 ˚C

85 ˚C

2,5

2

1,5

1

0,5

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

Figure 24-24. I/O Pin Input Threshold Voltage vs. V_CC(V_IL, I/O Pin Read as ‘0’)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_CC

VIL, IO PIN READ AS '0'

3

85 ˚C

2,5

2

25 ˚C

-40 ˚C

1,5

1

0,5

0

1,5

2

2,5

3

3,5

_CC(V)

4

4,5

5

5,5

V

207

2588B–AVR–11/06

Figure 24-25. I/O Pin Input Hysteresis vs. V_CC

I/O PIN INPUT HYSTERESIS vs. V_CC

0,7

0,6

0,5

0,4

0,3

0,2

0,1

0

-40 ˚C

25 ˚C

85 ˚C

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

Figure 24-26. Reset Input Threshold Voltage vs. V_CC(V_IH, Reset Read as ‘1’)

RESET INPUT THRESHOLD VOLTAGE vs. V_CC

VIH, RESET READ AS '1'

3

85 ˚C

25 ˚C

2,5

2

-40 ˚C

1,5

1

0,5

0

1,5

2

2,5

3

3,5

_CC(V)

4

4,5

5

5,5

V

208

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Figure 24-27. Reset Input Threshold Voltage vs. V_CC(V_IL, Reset Read as ‘0’)

RESET PIN AS I/O THRESHOLD VOLTAGE vs. V_CC

VIL, RESET READ AS '0'

2,5

2

85 ˚C

25 ˚C

-40 ˚C

1,5

1

0,5

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

Figure 24-28. Reset Pin input Hysteresis vs. V_CC

RESET PIN INPUT HYSTERESIS vs. V_CC

1

0,9

0,8

0,7

0,6

0,5

0,4

0,3

0,2

0,1

0

85 ˚C

25 ˚C

-40 ˚C

1,5

2

2,5

3

3,5

_CC(V)

4

4,5

5

5,5

V

209

2588B–AVR–11/06

24.8 BOD Threshold and Analog Comparator Offset

Figure 24-29. BOD Threshold vs. Temperature (BOD Level is 4.3V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL is 4.3V

4,5

4,45

4,4

4,35

4,3

Rising V_CC

Falling V_CC

4,25

4,2

4,15

4,1

-60

-40

-20

0

20

40

60

80

100

Temperature (C)

Figure 24-30. BOD Threshold vs. Temperature (BOD Level is 2.7V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL is 2.7V

2,9

2,85

2,8

Rising V_CC

2,75

2,7

2,65

2,6

Falling V_CC

2,55

2,5

-60

-40

-20

0

20

40

60

80

100

Temperature (C)

210

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Figure 24-31. BOD Threshold vs. Temperature (BOD Level is 1.8V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL is 1.8V

2

1,95

1,9

1,85

1,8

Rising V_CC

Falling V_CC

1,75

1,7

1,65

1,6

-60

-40

-20

0

20

40

60

80

100

Temperature (C)

24.9 Internal Oscillator Speed

Figure 24-32. Watchdog Oscillator Frequency vs. V_CC

WATCHDOG OSCILLATOR FREQUENCY vs. V_CC

0,138

0,136

0,134

0,132

0,13

-40 ˚C

25 ˚C

0,128

0,126

0,124

0,122

0,12

85 ˚C

0,118

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

211

2588B–AVR–11/06

Figure 24-33. Calibrated 8.0 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs. V_CC

9

8,8

8,6

8,4

8,2

8

85 ˚C

25 ˚C

7,8

7,6

7,4

7,2

7

-40 ˚C

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

Figure 24-34. Calibrated 8.0 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

9

8,8

8,6

5.0 V

8,4

8,2

3.0 V

8

7,8

7,6

7,4

7,2

7

-60

-40

-20

0

20

40

60

80

100

Temperature

212

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Figure 24-35. Calibrated 8.0 MHz RC Oscillator Frequency vs. OSCCAL Value

CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

18

85 ˚C

16

14

12

10

8

25 ˚C

-40 ˚C

6

4

2

0

16

32

48

64

80

96 112 128 144 160 176 192 208 224 240 256

OSCCAL (X1)

24.10 Current Consumption of Peripheral Units

Figure 24-36. ADC Current vs. V_CC(AREF = AV_CC

)

ADC CURRENT vs. V_CC

AREF = AV_CC

1000

900

800

700

600

500

400

300

200

100

0

25 ˚C

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

213

2588B–AVR–11/06

Figure 24-37. AREF External Reference Current vs. V_CC

AREF EXTERNAL REFERENCE CURRENT vs. V_CC

180

25 ˚C

150

120

90

60

30

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

Figure 24-38. Analog Comparator vs. V_CC

ANALOG COMPARATOR vs. V_CC

160

140

120

100

80

25 ˚C

60

40

20

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

214

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Figure 24-39. Brownout Detector Current vs. V_CC

BROWNOUT DETECTOR CURRENT vs. V_CC

30

25

20

15

10

5

85 ˚C

25 ˚C

-40 ˚C

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

Figure 24-40. Programming Current vs. V_CC

PROGRAMMING CURRENT vs. V_CC

16000

14000

12000

10000

8000

6000

4000

2000

0

25 ˚C

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

215

2588B–AVR–11/06

Figure 24-41. Watchdog Timer Current vs. V_CC

WATCHDOG TIMER CURRENT vs. V_CC

10

9

8

7

6

5

4

3

2

1

0

-40 ˚C

85 ˚C

25 ˚C

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

24.11 Current Consumption in Reset and Reset Pulsewidth

Figure 24-42. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz, Excluding Current

Through the Reset Pull-up)

RESET SUPPLY CURRENT vs. Low Frequency

0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP

0,14

5.5 V

0,12

5.0 V

0,1

4.5 V

4.0 V

0,08

3.3 V

0,06

2.7 V

0,04

1.8 V

0,02

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

1

Frequency (MHz)

216

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Figure 24-43. Reset Supply Current vs. Frequency (1 - 20 MHz, Excluding Current Through the

Reset Pull-up)

RESET SUPPLY CURRENT vs. V_CC

1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

2,5

5.5 V

5.0 V

2

4.5 V

1,5

4.0 V

1

3.3 V

0,5

2.7 V

1.8 V

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 24-44. Minimum Reset Pulse Width vs. V_CC

MINIMUM RESET PULSE WIDTH vs. V_CC

2500

2000

1500

1000

500

85 ˚C

25 ˚C

-40 ˚C

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

217

2588B–AVR–11/06

25. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

SREG

SPH

I

–

T

–

H

–

S

–

V

–

N

Z

C

page 9

page 12

SP10

SP2

SP9

SP1

SP8

SP0

SPL

SP7

SP6

SP5

SP4

SP3

Reserved

GIMSK

GIFR

–

INT1

INTF1

OCIE1D

OCF1D

–

INT0

INTF0

OCIE1A

OCF1A

–

PCIE1

PCIF

PCIE0

–

page 51

–

TIMSK

TIFR

OCIE1B

OCF1B

–

OCIE0A

OCF0A

CTPB

OCIE0B

OCF0B

RFLB

PRTIM1

SM0

TOIE1

TOV1

PGWRT

PRTIM0

–

TOIE0

TOV0

PGERS

PRUSI

ISC01

EXTRF

CS01

TICIE0

ICF0

page 86, page 123

page 87, page 124

page 166

page 35

SPMCSR

PRR

SPMEN

PRADC

ISC00

PORF

CS00

MCUCR

MCUSR

TCCR0B

TCNT0L

OSCCAL

TCCR1A

TCCR1B

TCNT1

OCR1A

OCR1B

OCR1C

OCR1D

PLLCSR

CLKPR

TCCR1C

TCCR1D

TC1H

–

PUD

SE

–

SM1

–

page 37, page 68, page 50

page 44,

page 70

–

WDRF

PSR0

BORF

CS02

–

TSM

Timer/Counter0 Counter Register Low Byte

Oscillator Calibration Register

page 85

page 32

COM1A1

PWM1X

COM1A0

PSR1

COM1B1

DTPS11

COM1B0

DTPS10

FOC1A

CS13

FOC1B

CS12

PWM1A

CS11

PWM1B

CS10

page 113

page 166

page 121

page 122

page 123

page 89

Timer/Counter1 Counter Register

Timer/Counter1 Output Compare Register A

Timer/Counter1 Output Compare Register B

Timer/Counter1 Output Compare Register C

Timer/Counter1 Output Compare Register D

LSM

CLKPCE

COM1A1S

FPIE1

PCKE

PLLE

CLKPS1

FOC1D

WGM11

TC19

PLOCK

CLKPS0

PWM1D

WGM10

TC18

CLKPS3

COM1D1

FPAC1

CLKPS2

COM1D0

FPF1

page 32

COM1A0S

FPEN1

COM1B1S

FPNC1

COM1B0S

FPES1

page 117

page 119

page 121

page 124

page 52

DT1

DT1H3

PCINT7

PCINT15

WDIF

DT1H2

PCINT6

PCINT14

WDIE

DT1H1

PCINT5

PCINT13

WDP3

DT1H0

PCINT4

PCINT12

WDCE

DT1L3

PCINT3

PCINT11

WDE

DT1L2

PCINT2

PCINT10

WDP2

DT1L1

PCINT1

PCINT9

WDP1

DT1L0

PCMSK0

PCMSK1

WDTCR

DWDR

EEARH

EEARL

EEDR

PCINT0

PCINT8

WDP0

page 52

page 44

DWDR[7:0]

page 35

EEAR8

EEAR0

page 21

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

page 21

EEPROM Data Register

page 22

EECR

–

EEPM1

PORTA5

DDA5

EEPM0

PORTA4

DDA4

EERIE

PORTA3

DDA3

EEMPE

PORTA2

DDA2

EEPE

PORTA1

DDA1

EERE

PORTA0

DDA0

page 22

PORTA

DDRA

PORTA7

DDA7

PORTA6

DDA6

page 68

PINA

PINA7

PORTB7

DDB7

PINA6

PORTB6

DDB6

PINA5

PINA4

PINA3

PINA2

PINA1

PINA0

page 68

PORTB

DDRB

PORTB5

DDB5

PORTB4

DDB4

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

page 68

PINB

PINB7

TCW0

PINB6

ICEN0

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

page 68

TCCR0A

TCNT0H

OCR0A

OCR0B

USIPP

ICNC0

ICES0

ACIC0

WGM00

page 84

Timer/Counter0 Counter Register High Byte

Timer/Counter0 Output Compare Register A

Timer/Counter0 Output Compare Register B

page 85

USIPOS

page 137

page 134

page 133

page 134

page 135

page 23

USIBR

USIDR

USISR

USICR

GPIOR2

GPIOR1

GPIOR0

ACSRB

ACSRA

ADMUX

ADCSRA

ADCH

USI Buffer Register

USI Data Register

USISIF

USISIE

USIOIF

USIOIE

USIPF

USIDC

USICNT3

USICS1

USICNT2

USICS0

USICNT1

USICLK

USICNT0

USITC

USIWM1

USIWM0

General Purpose I/O Register 2

General Purpose I/O Register 1

General Purpose I/O Register 0

page 23

HSEL

ACD

HLEV

ACBG

REFS0

ADSC

ACM2

ACME

MUX2

ADPS2

ACM1

ACIS1

MUX1

ADPS1

ACM0

ACIS0

MUX0

ADPS0

page 141

page 138

page 154

page 157

page 158

page 160

page 120

ACO

ACI

MUX4

ADIF

ACIE

MUX3

ADIE

REFS1

ADEN

ADLAR

ADATE

ADC Data Register High Byte

ADC Data Register Low Byte

ADCL

ADCSRB

DIDR1

BIN

ADC10D

ADC6D

–

GSEL

ADC9D

ADC5D

-

REFS2

ADC7D

ADC3D

OC1OE4

MUX5

ADTS2

ADTS1

ADTS0

ADC8D

ADC4D

OC1OE5

DIDR0

AREFD

ADC2D

ADC1D

ADC0D

TCCR1E

OC1OE3

OC1OE2

OC1OE1

OC1OE0

218

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

219

2588B–AVR–11/06

26. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd ⊕ Rr

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

DEC

TST

Rd

Decrement

Rd ← Rd − 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

CLR

SER

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

LSL

LSR

ROL

I/O(P,b) ← 0

None

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Logical Shift Right

Rotate Left Through Carry

220

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ROR

Rd

Rotate Right Through Carry

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

1

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Rd

s

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(z) ← R1:R0

Rd, P

P, Rr

Rr

Rd ← P

1

2

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/Timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

221

2588B–AVR–11/06

27. Ordering Information

27.1 ATtiny261

Speed (MHz)⁽³⁾

Power Supply

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATtiny261V-10MU

ATtiny261V-10PU

ATtiny261V-10SU

32M1-A

20P3

Industrial

(-40°C to 85°C)

10

1.8 - 5.5V

2.7 - 5.5V

20S2

ATtiny261-20MU

ATtiny261-20PU

ATtiny261-20SU

32M1-A

20P3

Industrial

(-40°C to 85°C)

20

20S2

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V_CC,see Figure 23.3 on page 187

Package Type

32M1-A

20P3

32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)

20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20S2

20-lead, 0.300" Wide, Plastic Gull Wing Smal Outline Package (SOIC)

222

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

27.2 ATtiny461

Speed (MHz)⁽³⁾

Power Supply

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATtiny461V-10MU

ATtiny461V-10PU

ATtiny461V-10SU

32M1-A

20P3

Industrial

(-40°C to 85°C)

10

20

1.8 - 5.5V

20S2

ATtiny461-20MU

ATtiny461-20PU

ATtiny461-20SU

32M1-A

20P3

Industrial

(-40°C to 85°C)

2.7 - 5.5V

20S2

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V_CC,see Figure 23.3 on page 187

Package Type

32M1-A

20P3

32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)

20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20S2

20-lead, 0.300" Wide, Plastic Gull Wing Smal Outline Package (SOIC)

223

2588B–AVR–11/06

27.3 ATtiny861

Speed (MHz)⁽³⁾

Power Supply

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATtiny861V-10MU

ATtiny861V-10PU

ATtiny861V-10SU

32M1-A

20P3

Industrial

(-40°C to 85°C)

10

20

1.8 - 5.5V

20S2

ATtiny861-20MU

ATtiny861-20PU

ATtiny861-20SU

32M1-A

20P3

Industrial

(-40°C to 85°C)

2.7 - 5.5V

20S2

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V_CC,see Figure 23.3 on page 187

Package Type

32M1-A

20P3

32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)

20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20S2

20-lead, 0.300" Wide, Plastic Gull Wing Smal Outline Package (SOIC)

224

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

28. Packaging Information

28.1 32M1-A

D

D1

1

2

0

Pin 1 ID

3

SIDE VIEW

E1

E

TOP VIEW

A3

A1

A2

A

K

COMMON DIMENSIONS

0.08

C

(Unit of Measure = mm)

P

D2

MIN

0.80

–

MAX

1.00

0.05

1.00

NOM

0.90

NOTE

SYMBOL

A

A1

A2

A3

b

0.02

1

2

3

P

–

0.65

Pin #1 Notch

(0.20 R)

0.20 REF

0.23

E2

0.18

2.95

0.30

3.25

D

5.00 BSC

4.75 BSC

3.10

K

D1

D2

E

5.00 BSC

4.75BSC

3.10

e

b

L

E1

E2

e

BOTTOM VIEW

0.50 BSC

0.40

L

0.30

–

0.50

0.60

P

–

o

–

12

0

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

K

0.20

–

8/19/04

DRAWING NO. REV.

32M1-A

TITLE

2325 Orchard Parkway

San Jose, CA 95131

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,

3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

D

R

225

2588B–AVR–11/06

28.2 20P3

D

1

E1

A

SEATING PLANE

A1

L

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

C

MIN

–

MAX

5.334

–

NOM

NOTE

SYMBOL

eC

A

–

eB

A1

D

0.381

25.493

7.620

6.096

0.356

1.270

2.921

0.203

–

25.984 Note 2

8.255

E

E1

B

7.112 Note 2

0.559

B1

L

1.551

Notes:

1. This package conforms to JEDEC reference MS-001, Variation AD.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

3.810

C

0.356

eB

eC

e

10.922

0.000

1.524

2.540 TYP

1/12/04

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

20P3

C

R

226

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

28.3 20S2

227

2588B–AVR–11/06

29. Errata

29.1 Errata ATtiny261

The revision letter in this section refers to the revision of the ATtiny261 device.

29.1.1

Rev A

No known errata.

29.2 Errata ATtiny461

The revision letter in this section refers to the revision of the ATtiny461 device.

29.2.1

29.2.2

Rev B

Rev A

Yield improvement. No known errata.

No known errata.

29.3 Errata ATtiny861

The revision letter in this section refers to the revision of the ATtiny861 device.

29.3.1

29.3.2

Rev B

Rev A

No known errata.

Not sampled.

228

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

30. Datasheet Revision History

30.1 Rev. 2588A – 11/06

1.

2.

Updated ”Ordering Information” on page 222.

Updated ”Packaging Information” on page 225.

30.2 Rev. 2588A – 10/06

1.

Initial Revision.

229

2588B–AVR–11/06

230

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

Table of Contents

Features ..................................................................................................... 1

1

2

Pin Configurations ................................................................................... 2

1.1 Disclaimer .................................................................................................................2

Overview ................................................................................................... 3

2.1 Block Diagram ..........................................................................................................3

2.2 Pin Descriptions ........................................................................................................4

3

4

5

Resources ................................................................................................. 6

About Code Examples ............................................................................. 7

AVR CPU Core .......................................................................................... 8

5.1 Overview ...................................................................................................................8

5.2 ALU – Arithmetic Logic Unit ......................................................................................9

5.3 Status Register .........................................................................................................9

5.4 General Purpose Register File ...............................................................................11

5.5 Stack Pointer ..........................................................................................................12

5.6 Instruction Execution Timing ..................................................................................13

5.7 Reset and Interrupt Handling ..................................................................................13

6

7

AVR Memories ........................................................................................ 16

6.1 In-System Re-programmable Flash Program Memory ...........................................16

6.2 SRAM Data Memory ...............................................................................................16

6.3 EEPROM Data Memory .........................................................................................17

6.4 I/O Memory .............................................................................................................21

6.5 Register Description ...............................................................................................21

System Clock and Clock Options ......................................................... 24

7.1 Clock Systems and their Distribution ......................................................................24

7.2 Clock Sources ........................................................................................................26

7.3 Default Clock Source ..............................................................................................26

7.4 External Clock ........................................................................................................26

7.5 High Frequency PLL Clock - PLLCLK ....................................................................27

7.6 Calibrated Internal RC Oscillator ............................................................................28

7.7 128 kHz Internal Oscillator .....................................................................................29

7.8 Low-frequency Crystal Oscillator ............................................................................29

7.9 Crystal Oscillator ....................................................................................................29

i

2588B–AVR–11/06

7.10 Clock Output Buffer ..............................................................................................31

7.11 System Clock Prescaler .......................................................................................31

7.12 Register Description .............................................................................................32

8

Power Management and Sleep Modes ................................................. 34

8.1 Sleep Modes ...........................................................................................................34

8.2 Idle Mode ................................................................................................................34

8.3 ADC Noise Reduction Mode ...................................................................................35

8.4 Power-down Mode ..................................................................................................35

8.5 Standby Mode ........................................................................................................35

8.6 Power Reduction Register ......................................................................................35

8.7 Minimizing Power Consumption .............................................................................35

8.8 Register Description ...............................................................................................37

9

System Control and Reset .................................................................... 39

9.1 Internal Voltage Reference .....................................................................................42

9.2 Watchdog Timer .....................................................................................................42

9.3 Timed Sequences for Changing the Configuration of the Watchdog Timer ...........43

9.4 Register Description ...............................................................................................44

10 Interrupts ................................................................................................ 48

10.1 Interrupt Vectors in ATtiny261/461/861 ................................................................48

11 External Interrupts ................................................................................. 50

11.1 Register Description .............................................................................................50

12 I/O Ports .................................................................................................. 53

12.1 Overview ...............................................................................................................53

12.2 Ports as General Digital I/O ..................................................................................54

12.3 Alternate Port Functions .......................................................................................58

12.4 Register Description .............................................................................................68

13 Timer/Counter0 Prescaler ..................................................................... 69

13.1 Register Description .............................................................................................70

14 Timer/Counter0 ....................................................................................... 72

14.1 Features ...............................................................................................................72

14.2 Overview ...............................................................................................................72

14.3 Timer/Counter Clock Sources ..............................................................................73

14.4 Counter Unit .........................................................................................................73

14.5 Modes of Operation ..............................................................................................74

ii

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

14.6 Input Capture Unit ................................................................................................76

14.7 Output Compare Unit ............................................................................................77

14.8 Timer/Counter Timing Diagrams ..........................................................................78

14.9 Accessing Registers in 16-bit Mode .....................................................................80

14.10 Register Description ...........................................................................................84

15 Timer/Counter1 Prescaler ..................................................................... 88

15.1 Register Description .............................................................................................89

16 Timer/Counter1 ....................................................................................... 91

16.1 Features ...............................................................................................................91

16.2 Overview ...............................................................................................................91

16.3 Counter Unit .........................................................................................................95

16.4 Output Compare Unit ............................................................................................96

16.5 Dead Time Generator ...........................................................................................98

16.6 Compare Match Output Unit .................................................................................99

16.7 Modes of Operation ............................................................................................101

16.8 Timer/Counter Timing Diagrams ........................................................................107

16.9 Fault Protection Unit ...........................................................................................108

16.10 Accessing 10-Bit Registers ...............................................................................110

16.11 Register Description .........................................................................................113

17 USI – Universal Serial Interface .......................................................... 126

17.1 Features .............................................................................................................126

17.2 Overview .............................................................................................................126

17.3 Functional Descriptions ......................................................................................127

17.4 Alternative USI Usage ........................................................................................133

17.5 Register Descriptions .........................................................................................133

18 AC – Analog Comparator .................................................................... 138

18.1 Register Description ...........................................................................................138

18.2 Analog Comparator Multiplexed Input ................................................................139

19 ADC – Analog to Digital Converter ..................................................... 142

19.1 Features .............................................................................................................142

19.2 Overview .............................................................................................................142

19.3 Operation ............................................................................................................143

19.4 Starting a Conversion .........................................................................................144

19.5 Prescaling and Conversion Timing .....................................................................145

iii

2588B–AVR–11/06

19.6 Changing Channel or Reference Selection ........................................................147

19.7 ADC Noise Canceler ..........................................................................................148

19.8 ADC Conversion Result ......................................................................................152

19.9 Temperature Measurement ................................................................................153

19.10 Register Descriptin ...........................................................................................154

20 debugWIRE On-chip Debug System .................................................. 161

20.1 Features .............................................................................................................161

20.2 Overview .............................................................................................................161

20.3 Physical Interface ...............................................................................................161

20.4 Software Break Points ........................................................................................162

20.5 Limitations of debugWIRE ..................................................................................162

20.6 Register Description ...........................................................................................162

21 Self-Programming the Flash ............................................................... 163

21.1 Addressing the Flash During Self-Programming ................................................164

21.2 Register Description ...........................................................................................166

22 Memory Programming ......................................................................... 168

22.1 Program And Data Memory Lock Bits ................................................................168

22.2 Fuse Bytes ..........................................................................................................169

22.3 Signature Bytes ..................................................................................................170

22.4 Calibration Byte ..................................................................................................170

22.5 Page Size ...........................................................................................................171

22.6 Parallel Programming Parameters, Pin Mapping, and Commands ....................171

22.7 Parallel Programming .........................................................................................173

22.8 Serial Downloading .............................................................................................181

23 Electrical Characteristics .................................................................... 185

23.1 Absolute Maximum Ratings* ..............................................................................185

23.2 DC Characteristics ..............................................................................................185

23.3 Speed Grades ....................................................................................................187

23.4 Clock Characteristics ..........................................................................................188

23.5 System and Reset Characteristics .....................................................................189

23.6 ADC Characteristics – Preliminary Data .............................................................190

23.7 Parallel Programming Characteristics ................................................................191

23.8 Serial Programming Characteristics ...................................................................194

24 Typical Characteristics ........................................................................ 195

iv

ATtiny261/461/861

2588B–AVR–11/06

ATtiny261/461/861

24.1 Active Supply Current .........................................................................................195

24.2 Idle Supply Current .............................................................................................198

24.3 Supply Current of I/O modules ...........................................................................200

24.4 Power-down Supply Current ...............................................................................201

24.5 Pin Pull-up ..........................................................................................................202

24.6 Pin Driver Strength .............................................................................................205

24.7 Pin Threshold and Hysteresis .............................................................................207

24.8 BOD Threshold and Analog Comparator Offset .................................................210

24.9 Internal Oscillator Speed ....................................................................................211

24.10 Current Consumption of Peripheral Units .........................................................213

24.11 Current Consumption in Reset and Reset Pulsewidth .....................................216

25 Register Summary ............................................................................... 218

26 Instruction Set Summary ..................................................................... 220

27 Ordering Information ........................................................................... 222

27.1 ATtiny261 ...........................................................................................................222

27.2 ATtiny461 ...........................................................................................................223

27.3 ATtiny861 ...........................................................................................................224

28 Packaging Information ........................................................................ 225

28.1 32M1-A ...............................................................................................................225

28.2 20P3 ...................................................................................................................226

28.3 20S2 ...................................................................................................................227

29 Errata ..................................................................................................... 228

29.1 Errata ATtiny261 .................................................................................................228

29.2 Errata ATtiny461 .................................................................................................228

29.3 Errata ATtiny861 .................................................................................................228

30 Datasheet Revision History ................................................................. 229

30.1 Rev. 2588A – 11/06 ............................................................................................229

30.2 Rev. 2588A – 10/06 ............................................................................................229

Table of Contents....................................................................................... i

v

2588B–AVR–11/06

Atmel Corporation

Atmel Operations

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Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

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intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

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2588B–AVR–11/06


型号：	ATTINY261_0611
厂家：	ATMEL
描述：	8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash 8位微控制器与2/4 / 8K字节的系统内可编程闪存闪存微控制器
文件：	总236页 (文件大小：2209K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATTINY261_0611 [ATMEL]

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