ATTINY25_06 [ATMEL]
8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash; 8位微控制器与2/4 / 8K字节的系统内可编程闪存
| 型号： | ATTINY25_06 |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| 文件： | 总24页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85)
Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85)
Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM (ATtiny25/45/85)
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
• Peripheral Features
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
2 High Frequency PWM Outputs with Separate Output Compare Registers
Programmable Dead Time Generator
– USI – Universal Serial Interface with Start Condition Detector
– 10-bit ADC
4 Single Ended Channels
ATtiny25/V*
ATtiny45/V
ATtiny85/V*
2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
Temperature Measurement
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
Summary
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
• I/O and Packages
*Preliminary
– Six Programmable I/O Lines
– 8-pin PDIP, 8-pin SOIC and 20-pad QFN/MLF
• Operating Voltage
– 1.8 - 5.5V for ATtiny25/45/85V
– 2.7 - 5.5V for ATtiny25/45/85
• Speed Grade
– ATtiny25/45/85V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny25/45/85: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
• Industrial Temperature Range
• Low Power Consumption
– Active Mode:
1 MHz, 1.8V: 300 μA
– Power-down Mode:
0.1μA at 1.8V
2586JS–AVR–12/06
1. Pin Configurations
Figure 1-1. Pinout ATtiny25/45/85
PDIP/SOIC
(PCINT5/RESET/ADC0/dW) PB5
1
2
3
4
8
7
6
5
VCC
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
GND
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
QFN/MLF
1
15
(PCINT5/RESET/ADC0/dW) PB5
VCC
2
3
4
5
14
13
12
11
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
DNC
DNC
DNC
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
2
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
2. Overview
The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
8-BIT DATABUS
CALIBRATED
INTERNAL
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
VCC
GND
MCU CONTROL
REGISTER
PROGRAM
FLASH
SRAM
MCU STATUS
REGISTER
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER0
X
Y
Z
INSTRUCTION
DECODER
TIMER/
COUNTER1
UNIVERSAL
SERIAL
INTERFACE
CONTROL
LINES
ALU
INTERRUPT
UNIT
STATUS
REGISTER
PROGRAMMING
LOGIC
DATA
EEPROM
OSCILLATORS
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
ADC /
ANALOG COMPARATOR
PORT B DRIVERS
RESET
PB0-PB5
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
3
2586JS–AVR–12/06
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32
general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high
speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software select-
able power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Inter-
rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
2.2
Pin Descriptions
2.2.1
VCC
Supply voltage.
2.2.2
2.2.3
GND
Ground.
Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on
page 61.
On the ATtiny25 device the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged
in the ATtiny15 compatibility mode for supporting the backward compatibility with ATtiny15.
2.2.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 23-3 on page
170. Shorter pulses are not guaranteed to generate a reset.
4
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
5
2586JS–AVR–12/06
4. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F
0x3E
0x3D
0x3C
0x3B
0x3A
0x39
0x38
0x37
0x36
0x35
0x34
0x33
0x32
0x31
0x30
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
0x15
0x14
0x13
0x12
0x11
0x10
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
SREG
I
–
T
–
H
–
S
–
V
–
N
–
Z
C
page 7
page 10
page 10
SPH
SP9
SP1
SP8
SP0
SPL
SP7
SP6
SP5
SP4
SP3
SP2
Reserved
GIMSK
GIFR
–
–
–
–
–
–
–
INT0
INTF0
OCIE1A
OCF1A
–
PCIE
PCIF
–
–
–
–
–
page 51
page 52
–
–
–
–
–
TIMSK
OCIE1B
OCF1B
–
OCIE0A
OCF0A
CTPB
OCIE0B
OCF0B
RFLB
TOIE1
TOV1
PGWRT
TOIE0
TOV0
PGERS
–
–
page 84/page 106
page 84
TIFR
SPMCSR
Reserved
MCUCR
MCUSR
TCCR0B
TCNT0
OSCCAL
TCCR1
TCNT1
OCR1A
OCR1C
GTCCR
OCR1B
TCCR0A
OCR0A
OCR0B
PLLCSR
CLKPR
DT1A
SPMEN
page 148
BODS
–
PUD
–
SE
–
SM1
SM0
BODSE
BORF
CS02
ISC01
EXTRF
CS01
ISC00
PORF
CS00
page 37,page 51, page 65,
page 44,
–
–
WDRF
WGM02
FOC0A
FOC0B
–
page 82
Timer/Counter0
page 83
Oscillator Calibration Register
page 31
CTC1
PWM1A
COM1A1
COM1A0
CS13
CS12
CS11
CS10
page 92, page 103
page 94, page 105
page 94, page 105
Timer/Counter1
Timer/Counter1 Output Compare Register A
Timer/Counter1 Output Compare Register C
page 95, page 106
page 79, page 93, page
TSM
PWM1B
COM1B1
Timer/Counter1 Output Compare Register B
COM0B1 COM0B0
COM1B0
FOC1B
FOC1A
PSR1
PSR0
page 95
page 79
COM0A1
COM0A0
–
WGM01
WGM00
Timer/Counter0 – Output Compare Register A
Timer/Counter0 – Output Compare Register B
page 83
page 84
LSM
CLKPCE
DT1AH3
DT1BH3
-
–
–
–
–
PCKE
CLKPS2
DT1AL2
DT1BL2
-
PLLE
PLOCK
CLKPS0
DT1AL0
DT1BL0
DTPS10
page 97, page 107
page 32
–
–
–
CLKPS3
DT1AL3
DT1BL3
-
CLKPS1
DT1AL1
DT1BL1
DTPS11
DT1AH2
DT1BH2
-
DT1AH1
DT1BH1
-
DT1AH0
DT1BH0
-
page 109
page 110
page 109
page 145
page 44
DT1B
DTPS1
DWDR
DWDR[7:0]
WDTCR
PRR
WDIF
–
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
PRUSI
WDP0
PRADC
EEAR8
EEAR0
PRTIM1
PRTIM0
page 36
EEARH
EEARL
EEDR
page 19
EEAR7
–
EEAR6
–
EEAR5
EEPM1
EEAR4
EEAR3
EEAR2
EEMPE
EEAR1
EEPE
page 19
EEPROM Data Register
page 19
EECR
EEPM0
EERIE
EERE
page 20
Reserved
Reserved
Reserved
PORTB
DDRB
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTB5
DDB5
PORTB4
DDB4
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
page 65
page 65
PINB
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 65
PCMSK
DIDR0
PCINT5
ADC0D
PCINT4
ADC2D
PCINT3
ADC3D
PCINT2
ADC1D
PCINT1
AIN1D
PCINT0
AIN0D
page 52
page 125, page 143
page 9
GPIOR2
GPIOR1
GPIOR0
USIBR
General Purpose I/O Register 2
General Purpose I/O Register 1
General Purpose I/O Register 0
USI Buffer Register
page 9
page 9
page 119
page 118
page 119
page 120
USIDR
USI Data Register
USISR
USISIF
USISIE
USIOIF
USIOIE
USIPF
USIDC
USICNT3
USICS1
USICNT2
USICS0
USICNT1
USICLK
USICNT0
USITC
USICR
USIWM1
USIWM0
Reserved
Reserved
Reserved
Reserved
ACSR
–
–
–
–
ACD
REFS1
ADEN
ACBG
REFS0
ADSC
ACO
ACI
REFS2
ADIF
ACIE
MUX3
ADIE
–
ACIS1
MUX1
ADPS1
ACIS0
MUX0
ADPS0
page 124
page 138
ADMUX
ADCSRA
ADCH
ADLAR
ADATE
MUX2
ADPS2
page 140
ADC Data Register High Byte
ADC Data Register Low Byte
page 141
ADCL
page 141
ADCSRB
Reserved
Reserved
Reserved
BIN
ACME
IPR
–
–
ADTS2
ADTS1
ADTS0
page 124, page 142
–
–
–
6
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
7
2586JS–AVR–12/06
5. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
CBR
INC
Rd ← Rd ⊕ Rr
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
Z,N,V
DEC
TST
Rd
Decrement
Rd ← Rd − 1
Z,N,V
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
CLR
SER
Rd
Z,N,V
Rd
Set Register
None
BRANCH INSTRUCTIONS
RJMP
IJMP
k
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
RCALL
ICALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
Subroutine Return
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
k
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
CBI
LSL
LSR
ROL
I/O(P,b) ← 0
None
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Logical Shift Right
Rotate Left Through Carry
8
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd
Rd
s
Arithmetic Shift Right
Swap Nibbles
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S
V
V
T
S ← 0
V ← 1
V ← 0
T ← 1
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
None
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/Timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
9
2586JS–AVR–12/06
6. Ordering Information
6.1
ATtiny25
Speed (MHz)(3)
Power Supply
Ordering Code(2)
Package(1)
Operational Range
ATtiny25V-10PU
ATtiny25V-10SU
ATtiny25V-10MU
8P3
Industrial
(-40°C to 85°C)
10
20
1.8 - 5.5V
8S2
20M1
ATtiny25-20PU
ATtiny25-20SU
ATtiny25-20MU
8P3
Industrial
(-40°C to 85°C)
2.7 - 5.5V
8S2
20M1
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC,see Figure 23.3 on page 168
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
20M1
10
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
6.2
ATtiny45
Speed (MHz)(3)
Power Supply
Ordering Code(2)
Package(1)
Operational Range
ATtiny45V-10PU
ATtiny45V-10SU
ATtiny45V-10MU
8P3
Industrial
(-40°C to 85°C)
10
20
1.8 - 5.5V
8S2
20M1
ATtiny45-20PU
ATtiny45-20SU
ATtiny45-20MU
8P3
Industrial
(-40°C to 85°C)
2.7 - 5.5V
8S2
20M1
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC,see Figure 23.3 on page 168
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
20M1
11
2586JS–AVR–12/06
6.3
ATtiny85
Speed (MHz)(3)
Power Supply
Ordering Code(2)
Package(1)
Operational Range
ATtiny85V-10PU
ATtiny85V-10SU
ATtiny85V-10MU
8P3
Industrial
(-40°C to 85°C)
10
20
1.8 - 5.5V
8S2
20M1
ATtiny85-20PU
ATtiny85-20SU
ATtiny85-20MU
8P3
Industrial
(-40°C to 85°C)
2.7 - 5.5V
8S2
20M1
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC,see Figure 23.3 on page 168
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
20M1
12
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
7. Packaging Information
7.1
8P3
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
13
2586JS–AVR–12/06
7.2
8S2
C
1
E
E1
L
N
θ
TOP VIEW
END VIEWW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0°
MAX
2.16
0.25
0.48
0.35
5.35
5.40
8.26
0.85
8°
NOM
NOTE
SYMBOL
A1
A
A1
b
5
5
C
D
E1
E
D
2, 3
L
SIDE VIEW
θ
e
1.27 BSC
4
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/7/06
TITLE
DRAWING NO.
REV.
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
2325 Orchard Parkway
San Jose, CA 95131
8S2
D
R
14
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
7.3
20M1
D
1
2
Pin 1 ID
SIDE VIEW
E
3
TOP VIEW
A2
A1
D2
A
0.08
C
1
2
Pin #1
Notch
(0.20 R)
COMMON DIMENSIONS
(Unit of Measure = mm)
3
E2
MIN
0.70
–
MAX
0.80
0.05
b
NOM
0.75
NOTE
SYMBOL
A
A1
A2
b
0.01
L
0.20 REF
0.23
0.18
2.45
2.45
0.35
0.30
2.75
2.75
0.55
e
D
4.00 BSC
2.60
D2
E
BOTTOM VIEW
4.00 BSC
2.60
E2
e
0.50 BSC
0.40
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
Note:
L
10/27/04
DRAWING NO. REV.
20M1
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
A
R
15
2586JS–AVR–12/06
8. Errata
8.1
Errata ATtiny25
The revision letter in this section refers to the revision of the ATtiny25 device.
8.1.1
8.1.2
Rev C
Rev B
No known errata
• Reading EEPROM at low frequency may not work for frequencies below 900 kHz
1. Reading EEPROM at low frequency may not work for frequencies below 900 kHz
Reading data from the EEPROM at low internal clock frequency may result in wrong data
read.
Problem Fix/Workaround
Avoid using the EEPROM at clock frequency below 900kHz.
8.1.3
Rev A
Not sampled.
16
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
8.2
Errata ATtiny45
The revision letter in this section refers to the revision of the ATtiny45 device.
8.2.1
8.2.2
Rev E
Rev D
No known errata
• Reading EEPROM at low frequency may not work for frequencies below 900 kHz
1. Reading EEPROM at low frequency may not work for frequencies below 900 kHz
Reading data from the EEPROM at low internal clock frequency may result in wrong data
read.
Problem Fix/Workaround
Avoid using the EEPROM at clock frequency below 900kHz.
8.2.3
Rev B and C
• PLL not locking
• EEPROM read from application code does not work in Lock Bit Mode 3
• Reading EEPROM at low frequency may not work for frequencies below 900 kHz
• Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly
1. PLL not locking
When at frequencies below 6.0 MHz, the PLL will not lock
Problem fix / Workaround
When using the PLL, run at 6.0 MHz or higher.
2. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does
not work from the application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from
EEPROM.
3. Reading EEPROM at low frequency may not work for frequencies below 900 kHz
Reading data from the EEPROM at low internal clock frequency may result in wrong data
read.
Problem Fix/Workaround
Avoid using the EEPROM at clock frequency below 900kHz.
4. Timer Counter 1 PWM output generation on OC1B – XOC1B does not work correctly
Timer Counter1 PWM output OC1B-XOC1B does not work correctly. Only in the case when
the control bits, COM1B1 and COM1B0 are in the same mode as COM1A1 and COM1A0,
respectively, the OC1B-XOC1B output works correctly.
Problem Fix/Work around
The only workaround is to use same control setting on COM1A(1:0) and COM1B(1:0) con-
trol bits, see table 14-4 in the data sheet. The problem has been fixed for Tiny45 rev D.
17
2586JS–AVR–12/06
8.2.4
Rev A
• Too high power down power consumption
• DebugWIRE looses communication when single stepping into interrupts
• PLL not locking
• EEPROM read from application code does not work in Lock Bit Mode 3
• Reading EEPROM at low frequency may not work for frequencies below 900 kHz
1. Too high power down power consumption
Three situations will lead to a too high power down power consumption. These are:
– An external clock is selected by fuses, but the I/O PORT is still enabled as an output.
– The EEPROM is read before entering power down.
– VCC is 4.5 volts or higher.
Problem fix / Workaround
– When using external clock, avoid setting the clock pin as Output.
– Do not read the EEPROM if power down power consumption is important.
– Use VCC lower than 4.5 Volts.
2. DebugWIRE looses communication when single stepping into interrupts
When receiving an interrupt during single stepping, debugwire will loose
communication.
Problem fix / Workaround
– When singlestepping, disable interrupts.
– When debugging interrupts, use breakpoints within the interrupt routine, and run into
the interrupt.
3. PLL not locking
When at frequencies below 6.0 MHz, the PLL will not lock
Problem fix / Workaround
When using the PLL, run at 6.0 MHz or higher.
4. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does
not work from the application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from
EEPROM.
5. Reading EEPROM at low frequency may not work for frequencies below 900 kHz
Reading data from the EEPROM at low internal clock frequency may result in wrong data
read.
Problem Fix/Workaround
Avoid using the EEPROM at clock frequency below 900kHz.
18
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
8.3
Errata ATtiny85
The revision letter in this section refers to the revision of the ATtiny85 device.
8.3.1
8.3.2
Rev B
Rev A
No known errata.
• Reading EEPROM at low frequency may not work for frequencies below 900 kHz
1. Reading EEPROM at low frequency may not work for frequencies below 900 kHz
Reading data from the EEPROM at low internal clock frequency may result in wrong data
read.
Problem Fix/Workaround
Avoid using the EEPROM at clock frequency below 900kHz.
19
2586JS–AVR–12/06
9. Datasheet Revision History
9.1
Rev. 2586J-12/06
1.
2.
Updated ”Low Power Consumption” on page 1.
Updated description of instruction length in “Architectural Overview” ,
starting on page 6.
3.
4.
Updated Flash size in ”In-System Re-programmable Flash Program
Memory” on page 14.
Updated cross-references in sections “Atomic Byte Programming” ,
“Erase” and “Write” , starting on page 16.
5.
6.
Updated ”Atomic Byte Programming” on page 16.
Updated ”Internal PLL for Fast Peripheral Clock Generation - clkPCK”
on page 23.
7.
8.
9.
Replaced single clocking system figure with two: Figure 7-2 and Figure
7-3 on page 23.
Updated Table 7-1 on page 24, Table 7-4 on page 26 and Table 7-6 on
page 28.
Updated ”Calibrated Internal RC Oscillator” on page 27.
Updated Table 7-11 on page 29.
10.
11.
12.
13.
14.
15.
16.
17.
18.
Updated ”OSCCAL – Oscillator Calibration Register” on page 31.
Updated ”CLKPR – Clock Prescale Register” on page 32.
Updated ”Power-down Mode” on page 35.
Updated “Bit 0” in ”PRR – Power Reduction Register” on page 38.
Added footnote to Table 9-3 on page 46.
Updated Table 12-5 on page 64.
Deleted “Bits 7, 2” in ”MCUCR – MCU Control Register” on page 65.
Updated and moved section “Timer/Counter0 Prescaler and Clock
Sources”, now located on page 67.
19.
20.
Updated ”Timer/Counter1 Initialization for Asynchronous Mode” on
page 89.
Updated bit description in ”PLLCSR – PLL Control and Status Register”
on page 97 and ”PLLCSR – PLL Control and Status Register” on page
107.
21.
Added recommended maximum frequency in”Prescaling and Conver-
sion Timing” on page 129.
22.
23.
24.
Updated Figure 19-8 on page 134 .
Updated ”Temperature Measurement” on page 138.
Updated Table 19-3 on page 139.
20
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
25.
Updated bit R/W descriptions in:
”TIMSK – Timer/Counter Interrupt Mask Register” on page 84,
”TIFR – Timer/Counter Interrupt Flag Register” on page 84,
”TIMSK – Timer/Counter Interrupt Mask Register” on page 95,
”TIFR – Timer/Counter Interrupt Flag Register” on page 96,
”PLLCSR – PLL Control and Status Register” on page 97,
”TIMSK – Timer/Counter Interrupt Mask Register” on page 106,
”TIFR – Timer/Counter Interrupt Flag Register” on page 106,
”PLLCSR – PLL Control and Status Register” on page 107 and
”DIDR0 – Digital Input Disable Register 0” on page 143.
Added limitation to ”Limitations of debugWIRE” on page 145.
Updated ”DC Characteristics” on page 166.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
Updated Table 23-4 on page 170.
Updated Figure 23-6 on page 173.
Updated Table 23-7 on page 173.
Updated Table 24-1 on page 179.
Updated Table 24-2 on page 179.
Updated Table 24-26, Table 24-27 and Table 24-28, starting on page 188.
Updated Table 24-29, Table 24-30 and Table 24-31, starting on page 189.
Updated Table 24-33 on page 191.
Updated Table 24-40, Table 24-41, Table 24-42 and Table 24-43, starting
on page 195.
9.2
Rev. 2586I-09/06
1.
2.
3.
All Characterization data moved to ”Electrical Characteristics” on page
166.
All Register Descriptions are gathered up in seperate sections in the
end of each chapter.
Updated Table 13-3 on page 80, Table 13-6 on page 81, Table 13-8 on
page 82 and Table 22-4 on page 152.
4.
5.
6.
7.
8.
9.
Updated ”Calibrated Internal RC Oscillator” on page 27.
Updated Note in Table 8-1 on page 34.
Updated ”System Control and Reset” on page 39.
Updated Register Description in ”I/O Ports” on page 53.
Updated Features in ”USI – Universal Serial Interface” on page 111.
Updated Code Example in ”SPI Master Operation Example” on page 113
and ”SPI Slave Operation Example” on page 115.
Updated ”Analog Comparator Multiplexed Input” on page 123.
Updated Figure 19-1 on page 127.
10.
11.
12.
13.
Updated ”Signature Bytes” on page 153.
Updated ”Electrical Characteristics” on page 166.
21
2586JS–AVR–12/06
9.3
9.4
Rev. 2586H-06/06
1.
2.
3.
Updated ”Calibrated Internal RC Oscillator” on page 27.
Updated Table 7.12.1 on page 31.
Added Table 23-1 on page 169.
Rev. 2586G-05/06
1.
Updated ”Internal PLL for Fast Peripheral Clock Generation - clkPCK”
on page 23.
2.
3.
4.
5.
6.
7.
8.
9.
Updated ”Default Clock Source” on page 25.
Updated ”Low-frequency Crystal Oscillator” on page 27.
Updated ”Calibrated Internal RC Oscillator” on page 27.
Updated ”Clock Output Buffer” on page 30.
Updated ”Power Management and Sleep Modes” on page 34.
Added ”BOD Disable” on page 34.
Updated Figure 18-1 on page 123.
Updated ”Bit 6 – ACBG: Analog Comparator Bandgap Select” on page
124.
10.
11.
Added note for Table 19-2 on page 129.
Updated ”Register Summary” on page 199.
9.5
9.6
Rev. 2586F-04/06
1.
2.
3.
Updated ”Digital Input Enable and Sleep Modes” on page 57.
Updated Table 22-15 on page 163.
Updated ”Ordering Information” on page 203.
Rev. 2586E-03/06
1.
2.
3.
4.
5.
Updated Features in ”Analog to Digital Converter” on page 126.
Updated Operation in ”Analog to Digital Converter” on page 126.
Updated Table 19-3 on page 139.
Updated Table 19-2 on page 138.
Updated ”Errata” on page 209.
9.7
Rev. 2586D-02/06
1.
Updated Table 7-4 on page 26, Table 7-5 on page 27, Table 7-9 on page
29, Table 7-12 on page 30, Table 7-11 on page 29, Table 10-1 on page
48,Table 19-4 on page 139, Table 22-15 on page 163, Table 23-5 on page
171.
2.
3.
Updated ”Timer/Counter1 in PWM Mode” on page 89.
Updated text ”Bit 2 - TOV1: Timer/Counter1 Overflow Flag” on page 96.
22
ATtiny25/45/85
2586JS–AVR–12/06
ATtiny25/45/85
4.
5.
6.
7.
8.
9.
Updated values in ”DC Characteristics” on page 166.
Updated ”Register Summary” on page 199.
Updated ”Ordering Information” on page 203.
Updated Rev B and C in ”Errata ATtiny45” on page 210.
All references to power-save mode are removed.
Updated Register Adresses.
9.8
9.9
Rev. 2586C-06/05
1.
2.
3.
4.
5.
6.
Updated ”Features” on page 1.
Updated Figure 1-1 on page 2.
Updated Code Examples on page 17 and page 18.
Moved “Temperature Measurement” to Section 19.9 page 138.
Updated ”Register Summary” on page 199.
Updated ”Ordering Information” on page 203.
Rev. 2586B-05/05
1.
CLKI added, instances of EEMWE/EEWE renamed EEMPE/EEPE,
removed some TBD.
Removed “Preliminary Description” from ”Temperature Measurement”
on page 138.
2.
3.
4.
Updated ”Features” on page 1.
Updated Figure 1-1 on page 2 and Figure 9-1 on page 39.
Updated Table 8-2 on page 38, Table 12-4 on page 64, Table 12-5 on
page 64
5.
6.
7.
8.
9.
Updated ”Serial Programming Instruction set” on page 157.
Updated SPH register in ”Instruction Set Summary” on page 201.
Updated ”DC Characteristics” on page 166.
Updated ”Ordering Information” on page 203.
Updated ”Errata” on page 209.
9.10 Rev. 2586A-02/05
1.
Initial revision.
23
2586JS–AVR–12/06
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
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Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
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Biometrics/Imaging/Hi-Rel MPU/
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Avenue de Rochepleine
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
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38521 Saint-Egreve Cedex, France
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Fax: (33) 4-76-58-34-80
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
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ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
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Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
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