ATSAM3N1BB-MU [ATMEL]
AT91SAM ARM-based Flash MCU; AT91SAM基于ARM的闪存微控制器
| 型号： | ATSAM3N1BB-MU |
| 厂家： | 
ATMEL |
| 描述： | AT91SAM ARM-based Flash MCU |
| 文件： | 总60页 (文件大小：1335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Core
– ARM® Cortex®-M3 revision 2.0 running at up to 48 MHz
– Thumb®-2 instruction
– 24-bit SysTick Counter
– Nested Vector Interrupt Controller
• Pin-to-pin compatible with SAM7S legacy products (48- and 64-pin versions) and
SAM3S (48-, 64- and 100-pin versions)
• Memories
– From 16 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,
single plane
– From 4 to 24 Kbytes embedded SRAM
AT91SAM
ARM-based
Flash MCU
– 16 Kbytes ROM with embedded bootloader routines (UART) and IAP routines
• System
– Embedded voltage regulator for single supply operation
– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe
operation
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure
Detection and optional low power 32.768 kHz for RTC or device clock
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default
frequency for device startup. In-application trimming access for frequency
adjustment
SAM3N Series
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– One PLL up to 130 MHz for device clock
– Up to 10 peripheral DMA (PDC) channels
• Low Power Modes
Summary
– Sleep and Backup modes, down to 3 µA in Backup mode
– Ultra low power RTC
• Peripherals
– Up to 2 USARTs with RS-485 and SPI mode support. One USART (USART0) has
ISO7816, IrDA® and PDC support in addition
– Two 2-wire UARTs
– 2 Two Wire Interface (I2C compatible), 1 SPI
– Up to 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and
PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for
Stepper Motor
– 4-channel 16-bit PWM
– 32-bit Real-time Timer and RTC with calendar and alarm features
– Up to 16 channels, 384 KSPS 10-bit ADC
– One 500 KSPS 10-bit DAC
• I/O
– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
– Three 32-bit Parallel Input/Output Controllers
• Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm
– 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm
11011BS–ATARM–22-Feb-12
1. SAM3N Description
Atmel's SAM3N series is a member of a family of Flash microcontrollers based on the high per-
formance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 48 MHz
and features up to 256 Kbytes of Flash and up to 24 Kbytes of SRAM. The peripheral set
includes 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, as well as 1 PWM timer, 6x general purpose
16-bit timers, an RTC, a 10-bit ADC and a 10-bit DAC.
The SAM3N series is ready for capacitive touch thanks to the QTouch library, offering an easy
way to implement buttons, wheels and sliders.
The SAM3N device is an entry-level general purpose microcontroller. That makes the SAM3N
the ideal starting point to move from 8- /16-bit to 32-bit microcontrollers.
It operates from 1.62V to 3.6V and is available in 48-pin, 64-pin and 100-pin QFP, 48-pin and
64-pin QFN, and 100-pin BGA packages.
The SAM3N series is the ideal migration path from the SAM3S for applications that require a
reduced BOM cost. The SAM3N series is pin-to-pin compatible with the SAM3S series. Its
aggressive price point and high level of integration pushes its scope of use far into cost-sensi-
tive, high-volume applications.
2
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
1.1
Configuration Summary
The SAM3N4/2/1/0/00 differ in memory size, package and features list. Table 1-1 summarizes
the configurations of the 9 devices.
Table 1-1.
Configuration Summary
Number
of PIOs
PDC
Device
Flash
SRAM
Package
ADC
Timer
Channels USART DAC
LQFP48
QFN48
SAM3N4A
SAM3N4B
SAM3N4C
SAM3N2A
SAM3N2B
SAM3N2C
SAM3N1A
SAM3N1B
SAM3N1C
SAM3N0A
SAM3N0B
SAM3N0C
SAM3N00A
SAM3N00B
256 Kbytes
24 Kbytes
24 Kbytes
24 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
4 KBytes
4 KBytes
34
47
79
34
47
79
34
47
79
34
47
79
34
47
8 channels
6(1)
8
1
2
2
1
2
2
1
2
2
1
2
2
1
2
_
1
1
_
1
1
_
1
1
_
1
1
_
1
LQFP64
QFN64
256 Kbytes
256 Kbytes
128 Kbytes
128 Kbytes
128 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
16 Kbytes
16 Kbytes
10 channels
16 channels
8 channels
10 channels
16 channels
8 channels
10 channels
16 channels
8 channels
10 channels
16 channels
8 channels
10 channels
6(2)
10
10
8
LQFP100
BGA100
6
LQFP48
QFN48
6(1)
6((2)
6
LQFP64
QFN64
10
10
8
LQFP100
BGA100
LQFP48
QFN48
6(1)
6(2)
6
LQFP64
QFN64
10
10
8
LQFP100
BGA100
LQFP48
QFN48
6(1)
6(2)
6
LQFP64
QFN64
10
10
8
LQFP100
BGA100
LQFP48
QFN48
6(1)
6(2)
LQFP64
QFN64
10
Notes: 1. Only two TC channels are accessible through the PIO.
2. Only three TC channels are accessible through the PIO.
3
11011BS–ATARM–22-Feb-12
2. SAM3N Block Diagram
Figure 2-1. SAM3N 100-pin version Block Diagram
System Controller
TST
Voltage
Regulator
PCK0-PCK2
PMC
JTAG & Serial Wire
OSC
3-20 MHz
XIN
XOUT
In-Circuit Emulator
FLASH
SRAM
WDT
RC OSC
12/8/4 MHz
24-bit
N
V
I
SM
SysTick Counter
256 KBytes
128 KBytes
64 KBytes
24 KBytes
16 KBytes
8 KBytes
Cortex-M3 Processor
Fmax 48 MHz
ROM
16 KBytes
C
SUPC
OSC 32k
RC 32k
PLL
XIN32
XOUT32
I/D
S
ERASE
3- layer AHB Bus Matrix Fmax 48 MHz
RTT
RTC
POR
VDDIO
RSTC
NRST
Peripheral
Bridge
PIOA
PIOB
PIOC
VDDCORE
URXD0
UTXD0
TCLK[0:2]
Timer Counter A
UART0
UART1
PDC
PDC
TIOA[0:2]
TIOB[0:2]
TC[0..2]
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
USART0
USART1
TCLK[3:5]
Timer Counter B
TC[3..5]
TIOA[3:5]
TIOB[3:5]
NPCS0
NPCS1
NPCS2
NPCS3
MISO
PDC
SPI
PWM
PWM[0:3]
MOS
SPCK
PDC
TWCK0
TWD0
TWI0
TWI1
ADTRG
AD[0..15]
10-bit ADC
10-bit DAC
PDC
PDC
TWCK1
TWD1
ADVREF
DAC0
DATRG
4
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
Figure 2-2. SAM3N 64-pin version Block Diagram
System Controller
TST
Voltage
Regulator
PCK0-PCK2
PMC
JTAG & Serial Wire
OSC
3-20 MHz
XIN
XOUT
In-Circuit Emulator
FLASH
SRAM
WDT
RC OSC
12/8/4 MHz
24-bit
N
V
I
SM
SysTick Counter
256 KBytes
128 KBytes
64 KBytes
24 KBytes
16 KBytes
8 KBytes
Cortex-M3 Processor
Fmax 48 MHz
ROM
16 KBytes
C
SUPC
OSC 32k
RC 32k
PLL
XIN32
XOUT32
I/D
S
ERASE
3-layer AHB Bus Matrix Fmax 48 MHz
RTT
RTC
POR
VDDIO
RSTC
NRST
Peripheral
Bridge
PIOA
PIOB
VDDCORE
URXD0
UTXD0
TCLK[0:2]
Timer Counter A
UART0
UART1
PDC
PDC
TIOA[0:2]
TIOB[0:2]
TC[0..2]
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
USART0
USART1
Timer Counter B
TC[3..5]
NPCS0
NPCS1
NPCS2
NPCS3
MISO
PDC
SPI
PWM
PWM[0:3]
MOS
SPCK
PDC
TWCK0
TWD0
TWI0
TWI1
ADTRG
AD[0..9]
10-bit ADC
10-bit DAC
PDC
PDC
TWCK1
TWD1
ADVREF
DAC0
DATRG
5
11011BS–ATARM–22-Feb-12
Figure 2-3. SAM3N 48-pin version Block Diagramz
System Controller
TST
Voltage
Regulator
PCK0-PCK2
PMC
JTAG & Serial Wire
OSC
3-20 MHz
XIN
XOUT
In-Circuit Emulator
FLASH
SRAM
WDT
RC OSC
12/8/4 MHz
24-bit
256 KBytes
128 KBytes
64 KBytes
32 KBytes
16 KBytes
N
V
I
SM
SysTick Counter
24 KBytes
16 KBytes
8 KBytes
4 KBytes
Cortex-M3 Processor
Fmax 48 MHz
ROM
16 KBytes
C
SUPC
OSC 32k
RC 32k
PLL
XIN32
XOUT32
I/D
S
ERASE
3-layer AHBBusMatrixFmax48 MHz
RTT
RTC
POR
VDDIO
RSTC
NRST
Peripheral
Bridge
PIOA
PIOB
VDDCORE
URXD0
UTXD0
TCLK[0..1]
Timer Counter A
UART0
UART1
PDC
PDC
TIOA[0..1]
TIOB[0..1]
TC[0..1]
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
Timer Counter B
TC[3..5]
USART0
NPCS0
NPCS1
NPCS2
NPCS3
MISO
PDC
SPI
PWM
PWM[0:3]
MOS
SPCK
PDC
ADTRG
AD[0..7]
TWCK0
TWD0
TWI0
TWI1
10-bit ADC
PDC
ADVREF
TWCK1
TWD1
6
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
3. Signal Description
Table 3-1 gives details on the signal name classified by peripheral.
Table 3-1.
Signal Description List
Active
Level
Voltage
Reference Comments
Signal Name
Function
Type
Power Supplies
VDDIO
VDDIN
Peripherals I/O Lines Power Supply
Power
Power
1.62V to 3.6V
1.8V to 3.6V(3)
Voltage Regulator, ADC and DAC Power
Supply
VDDOUT
VDDPLL
Voltage Regulator Output
Power
Power
1.8V Output
Oscillator and PLL Power Supply
1.65 V to 1.95V
1.65V to 1.95V
Power the core, the embedded memories
and the peripherals
VDDCORE
GND
Power
Connectedexternally
to VDDOUT
Ground
Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
Output
Input
Reset State:
- PIO Input
XOUT
XIN32
Main Oscillator Output
Slow Clock Oscillator Input
- Internal Pull-up
disabled
- Schmitt Trigger
enabled(1)
XOUT32
Slow Clock Oscillator Output
Programmable Clock Output
Output
VDDIO
Reset State:
- PIO Input
- Internal Pull-up
enabled
PCK0 - PCK2
Output
- Schmitt Trigger
enabled(1)
ICE and JTAG
TCK/SWCLK
TDI
Test Clock/Serial Wire Clock
Test Data In
Input
Input
Reset State:
- SWJ-DP Mode
- Internal pull-up
disabled
Test Data Out/Trace Asynchronous Data
Out
TDO/TRACESWO
TMS/SWDIO
JTAGSEL
Output
Input / I/O
Input
VDDIO
- Schmitt Trigger
enabled(1)
Test Mode Select /Serial Wire
Input/Output
Permanent Internal
pull-down
JTAG Selection
High
7
11011BS–ATARM–22-Feb-12
Table 3-1.
Signal Description List (Continued)
Active
Level
Voltage
Reference Comments
Signal Name
Function
Type
Flash Memory
Reset State:
- Erase Input
Flash and NVM Configuration Bits Erase
Command
- Internal pull-down
enabled
ERASE
Input
High
VDDIO
- Schmitt Trigger
enabled(1)
Reset/Test
Permanent Internal
pull-up
NRST
TST
Microcontroller Reset
Test Mode Select
I/O
Low
VDDIO
Permanent Internal
pull-down
Input
VDDIO
Universal Asynchronous Receiver Transceiver - UARTx
URXDx
UTXDx
UART Receive Data
Input
UART Transmit Data
Output
PIO Controller - PIOA - PIOB - PIOC
PA0 - PA31
PB0 - PB14
Parallel IO Controller A
Parallel IO Controller B
I/O
I/O
Reset State:
- PIO or System
IOs(2)
VDDIO
- Internal pull-up
enabled
PC0 - PC31
Parallel IO Controller C
I/O
- Schmitt Trigger
enabled(1)
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
TXDx
RXDx
RTSx
CTSx
USARTx Serial Clock
I/O
I/O
USARTx Transmit Data
USARTx Receive Data
USARTx Request To Send
USARTx Clear To Send
Input
Output
Input
Timer/Counter - TC
TCLKx
TIOAx
TIOBx
TC Channel x External Clock Input
TC Channel x I/O Line A
Input
I/O
TC Channel x I/O Line B
I/O
Pulse Width Modulation Controller- PWMC
PWM Waveform Output for channel x Output
PWMx
8
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
Table 3-1.
Signal Description List (Continued)
Active
Level
Voltage
Reference Comments
Signal Name
Function
Type
Serial Peripheral Interface - SPI
MISO
Master In Slave Out
Master Out Slave In
SPI Serial Clock
I/O
I/O
I/O
MOSI
SPCK
SPI_NPCS0
SPI Peripheral Chip Select 0
SPI Peripheral Chip Select
I/O
Low
Low
SPI_NPCS1 -
SPI_NPCS3
Output
Two-Wire Interface- TWIx
TWDx
TWIx Two-wire Serial Data
TWIx Two-wire Serial Clock
I/O
I/O
TWCKx
Analog
Analog
ADVREF
ADC and DAC Reference
10-bit Analog-to-Digital Converter - ADC
AD0 - AD15
ADTRG
Analog Inputs
ADC Trigger
Analog
Input
VDDIO
VDDIO
Digital-to-Analog Converter Controller- DACC
DAC0
DACC channel analog output
DACC Trigger
Analog
Input
DATRG
Fast Flash Programming Interface
PGMEN0-PGMEN2
PGMM0-PGMM3
PGMD0-PGMD15
PGMRDY
Programming Enabling
Programming Mode
Programming Data
Programming Ready
Data Direction
Input
Input
I/O
Output
Output
Input
Input
Input
High
Low
Low
VDDIO
PGMNVALID
PGMNOE
Programming Read
Programming Clock
Programming Command
PGMCK
PGMNCMD
Low
Notes: 1. Schmitt Triggers can be disabled through PIO registers.
2. Some PIO lines are shared with System IOs.
3. See Section 5.3 “Typical Powering Schematics” for restriction on voltage range of Analog Cells.
9
11011BS–ATARM–22-Feb-12
4. Package and Pinout
SAM3N4/2/1/0/00 series is pin-to-pin compatible with SAM3S products. Furthermore
SAM3N4/2/1/0/00 devices have new functionalities referenced in italic inTable 4-1, Table 4-3
and Table 4-4.
4.1
SAM3N4/2/1/0/00C Package and Pinout
4.1.1
100-lead LQFP Package Outline
Figure 4-1. Orientation of the 100-lead LQFP Package
75
51
76
50
100
26
1
25
4.1.2
100-ball TFBGA Package Outline
The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its
dimensions are 9 x 9 x 1.1 mm.
Figure 4-2. Orientation of the 100-ball TFBGA Package
TOP VIEW
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K
BALL A1
10
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
4.1.3
100-Lead LQFP Pinout
Table 4-1.
100-lead LQFP SAM3N4/2/1/0/00C Pinout
1
2
ADVREF
GND
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
GND
VDDIO
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
TDI/PB4
PA6/PGMNOE
PA5/PGMRDY
PC28
76 TDO/TRACESWO/PB5
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
JTAGSEL
PC18
3
PB0/AD4
PC29/AD13
PB1/AD5
PC30/AD14
PB2/AD6
PC31/AD15
PB3/AD7
VDDIN
PA16/PGMD4
PC7
4
TMS/SWDIO/PB6
PC19
5
PA15/PGMD3
PA14/PGMD2
PC6
PA4/PGMNCMD
VDDCORE
PA27
6
PA31
7
PC20
8
PA13/PGMD1
PA24
PC8
TCK/SWCLK/PB7
PC21
9
PA28
10
11
PC5
NRST
VDDCORE
PC22
VDDOUT
VDDCORE
PC4
TST
12
13
14
15
16
17
18
19
20
21
22
PA17/PGMD5/AD0
PC26
PC9
ERASE/PB12
PB10
PA25
PA29
PA18/PGMD6/AD1
PA21/AD8
PA26
PA30
PB11
PC3
PC10
PC23
VDDCORE
PC27
PA12/PGMD0
PA11/PGMM3
PC2
PA3
VDDIO
PA2/PGMEN2
PC11
PC24
PA19/PGMD7/AD2
PC15/AD11
PA22/AD9
PB13/DAC0
PC25
PA10/PGMM2
GND
VDDIO
GND
GND
PC13/AD10
PA23
PA9/PGMM1
PC1
PC14
PB8/XOUT
PB9/PGMCK/XIN
PA1/PGMEN1
PA8/XOUT32/
PGMM0
23
PC12/AD12
48
73
PC16
98
VDDIO
PA7/XIN32/
PGMNVALID
24
25
PA20/AD3
PC0
49
50
74
75
PA0/PGMEN0
PC17
99
PB14
VDDIO
100
VDDPLL
11
11011BS–ATARM–22-Feb-12
4.1.4
100-ball TFBGA Pinout
Table 4-2.
A1
100-ball TFBGA SAM3N4/2/1/0/00C Pinout
PB1
PC29
VDDIO
PB9
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
PB7
PC16
PA1
F1
F2
PA18
PC26
VDDOUT
GND
H6
H7
H8
H9
H10
J1
PC4
PA11
PC1
A2
A3
F3
A4
PC17
PA0
F4
PA6
A5
PB8
F5
VDDIO
PA27
PB4
A6
PB13
PB11
PB10
PB6
PB3
F6
PC15
PC0
A7
PB0
F7
PC8
J2
A8
PC24
PC22
GND
GND
VDDCORE
PA2
F8
PA28
J3
PA16
PC6
A9
F9
TST
J4
A10
B1
JTAGSEL
PC30
ADVREF
GNDANA
PB14
PC21
PC20
PA31
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
H5
PC9
J5
PA24
PA25
PA10
GND
VDDCORE
VDDIO
PA22
PC13
PC12
PA20
PC5
PA21
J6
B2
PC27
PA15
J7
B3
J8
B4
PC11
PC14
PA17
PC31
VDDIN
GND
GND
NRST
PA29
PA30
PC10
PA3
VDDCORE
VDDCORE
PA26
J9
B5
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
B6
B7
PA12
B8
PC19
PC18
PB5
PC28
PA4
B9
B10
C1
PA5
PB2
PA19
PC3
C2
VDDPLL
PC25
PC23
PB12
PA23
PC2
C3
PC7
PA9
C4
PA14
PA8
C5
PA13
PA7
12
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
4.2
SAM3N4/2/1/0/00B Package and Pinout
Figure 4-3. Orientation of the 64-pad QFN Package
64
49
48
1
16
33
32
17
TOP VIEW
Figure 4-4. Orientation of the 64-lead LQFP Package
48
33
49
32
64
17
1
16
13
11011BS–ATARM–22-Feb-12
4.2.1
64-Lead LQFP and QFN Pinout
64-pin version SAM3N devices are pin-to-pin compatible with SAM3S products. Furthermore,
SAM3N products have new functionalities shown in italic in Table 4-3.
Table 4-3.
64-pin SAM3N4/2/1/0/00B Pinout
1
2
3
4
5
6
7
8
ADVREF
GND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
33
34
35
36
37
38
39
40
41
42
43
44
45
46
TDI/PB4
PA6/PGMNOE
PA5/PGMRDY
PA4/PGMNCMD
PA27/PGMD15
PA28
49
50
51
52
53
54
55
56
57
58
59
60
61
62
TDO/TRACESWO/PB5
JTAGSEL
VDDIO
PB0/AD4
PB1AD5
PB2/AD6
PB3/AD7
VDDIN
PA16/PGMD4
PA15/PGMD3
PA14/PGMD2
PA13/PGMD1
PA24/PGMD12
VDDCORE
TMS/SWDIO/PB6
PA31
TCK/SWCLK/PB7
VDDCORE
ERASE/PB12
PB10
NRST
VDDOUT
TST
9
PA17/PGMD5/AD0
PA18/PGMD6/AD1
PA21/PGMD9/AD8
VDDCORE
PA25/PGMD13
PA26/PGMD14
PA12/PGMD0
PA11/PGMM3
PA10/PGMM2
PA9/PGMM1
PA29
PB11
10
11
12
13
14
PA30
VDDIO
PA3
PB13/DAC0
GND
PA2/PGMEN2
VDDIO
PA19/PGMD7/AD2
PA22/PGMD10/AD9
XOUT/PB8
XIN/PGMCK/PB9
GND
PA8/XOUT32/PGMM
0
15
PA23/PGMD11
31
32
47
48
PA1/PGMEN1
PA0/PGMEN0
63
64
PB14
PA7/XIN32/XOUT32/
PGMNVALID
16
PA20/PGMD8/AD3
VDDPLL
Note:
The bottom pad of the QFN package must be connected to ground.
14
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
4.3
SAM3N4/2/1/0/00A Package and Pinout
Figure 4-5. Orientation of the 48-pad QFN Package
48
37
1
36
12
25
13
24
TOP VIEW
Figure 4-6. Orientation of the 48-lead LQFP Package
36
25
37
24
13
48
1
12
15
11011BS–ATARM–22-Feb-12
4.3.1
48-Lead LQFP and QFN Pinout
Table 4-4.
48-pin SAM3N4/2/1/0/00A Pinout
TDO/TRACESWO/
PB5
1
ADVREF
13
VDDIO
25
TDI/PB4
37
2
3
4
5
6
7
8
GND
14
15
16
17
18
19
20
21
22
PA16/PGMD4
PA15/PGMD3
PA14/PGMD2
PA13/PGMD1
VDDCORE
26
27
28
29
30
31
32
33
34
PA6/PGMNOE
PA5/PGMRDY
PA4/PGMNCMD
NRST
38
39
40
41
42
43
44
45
46
JTAGSEL
TMS/SWDIO/PB6
TCK/SWCLK/PB7
VDDCORE
PB0/AD4
PB1/AD5
PB2/AD6
PB3/AD7
VDDIN
TST
ERASE/PB12
PB10
PA12/PGMD0
PA11/PGMM3
PA10/PGMM2
PA9/PGMM1
PA3
VDDOUT
PA2/PGMEN2
VDDIO
PB11
9
PA17/PGMD5/AD0
PA18/PGMD6/AD1
XOUT/PB8
10
GND
XIN/P/PB9/GMCK
PA8/XOUT32/PG
MM0
11
PA19/PGMD7/AD2
PA20/AD3
23
24
35
36
PA1/PGMEN1
PA0/PGMEN0
47
48
VDDIO
PA7/XIN32/PGMN
VALID
12
VDDPLL
Note:
The bottom pad of the QFN package must be connected to ground.
16
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
5. Power Considerations
5.1
Power Supplies
The SAM3N product has several types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the embedded memories and the
peripherals. Voltage ranges from 1.62V and 1.95V.
• VDDIO pins: Power the Peripherals I/O lines, Backup part, 32 kHz crystal oscillator and
oscillator pads. Voltage ranges from 1.62V and 3.6V
• VDDIN pin: Voltage Regulator, ADC and DAC Power Supply. Voltage ranges from 1.8V to
3.6V for the Voltage Regulator
• VDDPLL pin: Powers the PLL, the Fast RC and the 3 to 20 MHz oscillators. Voltage ranges
from 1.62V and 1.95V.
5.2
Voltage Regulator
The SAM3N embeds a voltage regulator that is managed by the Supply Controller.
This internal regulator is intended to supply the internal core of SAM3N. It features two different
operating modes:
• In Normal mode, the voltage regulator consumes less than 700 µA static current and draws
60 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current
depending on the required load current. In Wait Mode quiescent current is only 7 µA.
• In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT)
is driven internally to GND. The default output voltage is 1.80V and the start-up time to reach
Normal mode is less than100 µs.
For adequate input and output power supply decoupling/bypassing, refer to the Voltage Regula-
tor section in the Electrical Characteristics section of the datasheet.
5.3
Typical Powering Schematics
The SAM3N supports a 1.62V-3.6V single supply mode. The internal regulator input connected
to the source and its output feeds VDDCORE. Figure 5-1 shows the power schematics.
As VDDIN powers the voltage regulator and the ADC/DAC, when the user does not want to use
the embedded voltage regulator, it can be disabled by software via the SUPC (note that it is dif-
ferent from Backup mode).
17
11011BS–ATARM–22-Feb-12
Figure 5-1. Single Supply
VDDIO
I/Os.
Main Supply
(1.8V-3.6V)
ADC, DAC
VDDIN
VDDOUT
Voltage
Regulator
VDDCORE
VDDPLL
Figure 5-2. Core Externally Supplied
VDDIO
VDDIN
Main Supply
(1.62V-3.6V)
I/Os.
Can be the
same supply
ADC, DAC
ADC, DAC Supply
(3V-3.6V)
VDDOUT
Voltage
Regulator
VDDCORE
VDDCORE Supply
(1.62V-1.95V)
VDDPLL
Note:
Restrictions
With Main Supply < 3V, ADC and DAC are not usable.
With Main Supply >= 3V, all peripherals are usable.
Figure 5-3 below provides an example of the powering scheme when using a backup battery.
Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch
off the external regulator by driving the PIO line at low level (PIO is input, pull-up enabled after
backup reset). External wake-up of the system can be from a push button or any signal. See
Section 5.6 “Wake-up Sources” for further details.TFBGA
18
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
Figure 5-3. Core Externally Supplied (backup battery)
ADC, DAC Supply
(3V-3.6V)
VDDIO
Backup
Battery
I/Os.
+
-
ADC, DAC
VDDIN
Main Supply
VDDOUT
IN
OUT
Voltage
Regulator
3.3V
LDO
VDDCORE
ON/OFF
VDDPLL
PIOx (Output)
WAKEUPx
External wakeup signal
Note: The two diodes provide a “switchover circuit” (for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
5.4
Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator,
the main crystal oscillator or the PLL. The power management controller can be used to adapt
the frequency and to disable the peripheral clocks.
5.5
Low Power Modes
The various low-power modes of the SAM3N are described below:
5.5.1
Backup Mode
The purpose of backup mode is to achieve the lowest power consumption possible in a system
that is performing periodic wakeups to carry out tasks but not requiring fast startup time
(<0.1ms). Total current consumption is 3 µA typical.
The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz
oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The
regulator and the core supply are off.
Backup mode is based on the Cortex-M3 deep sleep mode with the voltage regulator disabled.
The SAM3N can be awakened from this mode through WUP0-15 pins, the supply monitor (SM),
the RTT or RTC wake-up event.
Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the System Con-
trol Register of the Cortex-M3 set to 1. (See the Power management description in The ARM
Cortex M3 Processor section of the product datasheet).
Exit from Backup mode happens if one of the following enable wake-up events occurs:
• WKUPEN0-15 pins (level transition, configurable debouncing)
19
11011BS–ATARM–22-Feb-12
• Supply Monitor alarm
• RTC alarm
• RTT alarm
5.5.2
Wait Mode
The purpose of the wait mode is to achieve very low power consumption while maintaining the
whole device in a powered state for a startup time of less than 10 µs. Current Consumption in
Wait mode is typically 15 µA (total current consumption) if the internal voltage regulator is used
or 8 µA if an external regulator is used.
In this mode, the clocks of the core, peripherals and memories are stopped. However, the core,
peripherals and memories power supplies are still powered. From this mode, a fast start up is
available.
This mode is entered via Wait for Event (WFE) instructions with LPM = 1 (Low Power Mode bit in
PMC_FSMR). The Cortex-M3 is able to handle external or internal events in order to wake up
the core (WFE). By configuring the WUP0-15 external lines as fast startup wake-up pins (refer to
Section 5.7 “Fast Start-Up”). RTC or RTT Alarm wake-up events can be used to wake up the
CPU (exit from WFE).
Entering Wait Mode:
• Select the 4/8/12 MHz fast RC oscillator as Main Clock
• Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR)
• Execute the Wait-For-Event (WFE) instruction of the processor
Note:
Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN
bit and the effective entry in Wait mode. Depending on the user application, Waiting for
MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired
instructions.
5.5.3
Sleep Mode
The purpose of sleep mode is to optimize power consumption of the device versus response
time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. The
current consumption in this mode is application dependent.
This mode is entered via Wait for Interrupt (WFI) or Wait for Event (WFE) instructions with
LPM = 0 in PMC_FSMR.
The processor can be woke up from an interrupt if WFI instruction of the Cortex M3 is used, or
from an event if the WFE instruction is used to enter this mode.
20
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
5.5.4
Low Power Mode Summary Table
The modes detailed above are the main low power modes. Each part can be set to on or off sep-
arately and wake up sources can be individually configured. Table 5-1 below shows a summary
of the configurations of the low power modes.
Table 5-1.
Low Power Mode Configuration Summary
SUPC,
32 kHz
Oscillator
RTC RTT
Backup
Registers,
POR
Core
PIO State
Memory
(Backup
Region)
Potential Wake Up Core at while in Low PIO State Consumption Wake Up
(2) (3)
Mode
Regulator Peripherals Mode Entry
Sources
Wake Up Power Mode at Wake Up
Time(1)
PIOA &
PIOB &
PIOC
Inputs with
pull ups
WUP0-15 pins
BOD alarm
RTC alarm
RTT alarm
WFE
OFF
Backup
Mode
Previous
state saved
ON
ON
OFF
Reset
3 µA typ(4)
< 0.1 ms
+SLEEPDEEP
(Not powered)
bit = 1
Any Event from: Fast
startup through
WUP0-15 pins
RTC alarm
WFE
Powered
Wait
Mode
+SLEEPDEEP
bit = 0
Clocked Previous
back state saved
ON
ON
Unchanged 5 µA/15 µA (5) < 10 µs
(Not clocked)
+LPM bit = 1
RTT alarm
Entry mode = WFI
Interrupt Only; Entry
mode = WFE Any
Enabled Interrupt
WFE or WFI
Powered(7)
Sleep
Mode
+SLEEPDEEP and/or Any Event
Clocked Previous
(6)
(6)
ON
Unchanged
bit = 0
from: Fast start-up back state saved
(Not clocked)
through WUP0-15
pins
+LPM bit = 0
RTC alarm
RTT alarm
Notes: 1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works
with the 4/8/12 MHz Fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up
time is defined as the time taken for wake up until the first instruction is fetched.
2. The external loads on PIOs are not taken into account in the calculation.
3. Supply Monitor current consumption is not included.
4. Total Current consumption.
5. 5 µA on VDDCORE, 15 µA for total current consumption (using internal voltage regulator), 8 µA for total current consumption
(without using internal voltage regulator).
6. Depends on MCK frequency.
7. In this mode the core is supplied and not clocked but some peripherals can be clocked.
21
11011BS–ATARM–22-Feb-12
5.6
Wake-up Sources
The wake-up events allow the device to exit backup mode. When a wake-up event is detected,
the Supply Controller performs a sequence which automatically reenables the core power sup-
ply and the SRAM power supply, if they are not already enabled.
Figure 5-4. Wake-up Source
BODEN
brown_out
rtc_alarm
RTCEN
RTTEN
Core
Supply
Restart
rtt_alarm
WKUPT0
WKUPEN0
WKUPEN1
WKUPIS0
WKUPIS1
Falling/Rising
Edge
Detector
WKUP0
WKUP1
WKUPDBC
Debouncer
SLCK
WKUPS
WKUPT1
Falling/Rising
Edge
Detector
WKUPT15
WKUPEN15
WKUPIS15
Falling/Rising
Edge
WKUP15
Detector
22
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
5.7
Fast Start-Up
The SAM3N allows the processor to restart in a few microseconds while the processor is in wait
mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs
(WKUP0 to 15 + SM + RTC + RTT).
The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast start-
up signal to the Power Management Controller. As soon as the fast start-up signal is asserted,
the PMC automatically restarts the embedded 4 MHz fast RC oscillator, switches the master
clock on this 4 MHz clock and reenables the processor clock.
Figure 5-5. Fast Start-Up Sources
RTCEN
rtc_alarm
RTTEN
rtt_alarm
fast_restart
FSTT0
Falling/Rising
Edge
Detector
WKUP0
FSTT15
Falling/Rising
Edge
WKUP15
Detector
23
11011BS–ATARM–22-Feb-12
6. Input/Output Lines
The SAM3N has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO)
and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the
PIO controllers. The same PIO line can be used whether in IO mode or by the multiplexed
peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs.
6.1
General Purpose I/O Lines
GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such
as pull-up or pull-down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing
or input change interrupt. Programming of these modes is performed independently for each I/O
line through the PIO controller user interface. For more details, refer to the product PIO control-
ler section.
The input output buffers of the PIO lines are supplied through VDDIO power supply rail.
The SAM3N embeds high speed pads able to handle up to 45 MHz for SPI clock lines and 35
MHz on other lines. See AC Characteristics Section in the Electrical Characteristics Section of
the datasheet for more details. Typical pull-up and pull-down value is 100 kΩ for all I/Os.
Each I/O line also embeds an ODT (On-Die Termination), (see Figure 6-1). It consists of an
internal series resistor termination scheme for impedance matching between the driver output
(SAM3N) and the PCB trace impedance preventing signal reflection. The series resistor helps to
reduce I/O switching current (di/dt) thereby reducing in turn, EMI. It also decreases overshoot
and undershoot (ringing) due to inductance of interconnect between devices or between boards.
In conclusion ODT helps diminish signal integrity issues.
Figure 6-1. On-Die Termination
Z0 ~ Zout + Rodt
ODT
36 Ohms Typ.
Rodt
Receiver
SAM3 Driver with
PCB Trace
Zout ~ 10 Ohms
Z0 ~ 50 Ohms
6.2
System I/O Lines
System I/O lines are pins used by oscillators, test mode, reset and JTAG to name but a few.
Described below are the SAM3N system I/O lines shared with PIO lines:
These pins are software configurable as general purpose I/O or system pins. At startup the
default function of these pins is always used.
24
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
Table 6-1.
SYSTEM_IO
bit number
System I/O Configuration Pin List.
Default function
after reset
Constraints for
normal start
Other function
Configuration
Low Level at
startup(1)
12
ERASE
PB12
In Matrix User Interface Registers
7
6
5
4
-
TCK/SWCLK
PB7
PB6
-
-
-
-
-
-
-
-
(Refer to the System I/O
Configuration Register in the Bus
Matrix section of the product
datasheet.)
TMS/SWDIO
TDO/TRACESWO
PB5
TDI
PA7
PA8
PB9
PB8
PB4
XIN32
XOUT32
XIN
See footnote (2) below
See footnote (3) below
-
-
-
XOUT
Notes: 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the
user application sets PB12 into PIO mode.
2. In the product Datasheet Refer to: Slow Clock Generator of the Supply Controller section.
3. In the product Datasheet Refer to: 3 to 20 MHZ Crystal Oscillator information in the PMC section.
6.2.1
Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on
a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference
and reset state, refer to Table 3-1 on page 7.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging
probe. Please refer to the Debug and Test Section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins
when the debug port is not needed in the end application. Mode selection between SWJ-DP
mode (System IO mode) and general IO mode is performed through the AHB Matrix Special
Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing
and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left uncon-
nected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire
Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous
trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and
JTAG-DP switching, please refer to the Debug and Test Section.
25
11011BS–ATARM–22-Feb-12
6.3
6.4
Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming
mode of the SAM3N series. The TST pin integrates a permanent pull-down resistor of about 15
kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming
mode, see the Fast Flash Programming Interface (FFPI) section. For more on the manufacturing
and test mode, refer to the “Debug and Test” section of the product datasheet.
NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low
to provide a reset signal to the external components or asserted low externally to reset the
microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT
and Supply Controller). There is no constraint on the length of the reset pulse and the reset con-
troller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up
resistor to VDDIO of about 100 kΩ . By default, the NRST pin is configured as an input.
6.5
ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased
state (all bits read as logic level 1). It integrates a pull-down resistor of about 100 kΩ to GND, so
that it can be left unconnected for normal operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high
during less than 100 ms, it is not taken into account. The pin must be tied high during more than
220 ms to perform a Flash erase operation.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE
pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of
this pin must be low to prevent unwanted erasing. Please refer to Section 11.2 “Peripheral Sig-
nals Multiplexing on I/O Lines” on page 42. Also, if the ERASE pin is used as a standard I/O
output, asserting the pin to low does not erase the Flash.
26
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
7. Processor and Architecture
7.1
ARM Cortex-M3 Processor
• Version 2.0
• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit.
• Harvard processor architecture enabling simultaneous instruction fetch with data load/store.
• Three-stage pipeline.
• Single cycle 32-bit multiply.
• Hardware divide.
• Thumb and Debug states.
• Handler and Thread modes.
• Low latency ISR entry and exit.
7.2
7.3
APB/AHB Bridge
The SAM3N4/2/1/0/00 product embeds one peripheral bridge:
The peripherals of the bridge are clocked by MCK.
Matrix Masters
The Bus Matrix of the SAM3N product manages 3 masters, which means that each master can
perform an access concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decodings.
Table 7-1.
List of Bus Matrix Masters
Cortex-M3 Instruction/Data
Master 0
Master 1
Master 2
Cortex-M3 System
Peripheral DMA Controller (PDC)
7.4
Matrix Slaves
The Bus Matrix of the SAM3N product manages 4 slaves. Each slave has its own arbiter, allow-
ing a different arbitration per slave.
Table 7-2.
Slave 0
List of Bus Matrix Slaves
Internal SRAM
Slave 1
Internal ROM
Slave 2
Internal Flash
Slave 3
Peripheral Bridge
27
11011BS–ATARM–22-Feb-12
7.5
Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired, and shown as “-” in Table 7-3.
Table 7-3.
SAM3N Master to Slave Access
Masters
0
1
2
PDC
X
Slaves
Cortex-M3 I/D Bus
Cortex-M3 S Bus
0
1
2
3
Internal SRAM
Internal ROM
-
X
X
-
X
-
X
Internal Flash
-
-
Peripheral Bridge
X
X
7.6
Peripheral DMA Controller
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
• Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-4.
Peripheral DMA Controller
Instance name
TWI0
Channel T/R
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Receive
Receive
Receive
Receive
100 & 64 Pins
48 Pins
x
x
x
x
x
x
x
x
x
x
x
x
UART0
USART0
DAC
x
N/A
x
SPI
TWI0
x
UART0
USART0
ADC
x
x
x
SPI
x
28
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
7.7
Debug and Test Features
• Debug access to all memory and registers in the system, including Cortex-M3 register bank
when the core is running, halted, or held in reset.
• Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
• Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and
system profiling
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• IEEE1149.1 JTAG Boundary-can on All Digital Pins
29
11011BS–ATARM–22-Feb-12
8. Product Mapping
Figure 8-1. SAM3N4/2/1/0/00 Product Mapping
Code
Address Memory Space
Peripherals
Reserved
System Controller
Reserved
0x40000000
0x40004000
0x40008000
0x4000C000
0x40010000
+0x40
0x00000000
0x400E0000
0x400E0200
0x400E0400
0x400E0600
0x400E0740
0x400E0800
0x400E0A00
0x400E0C00
0x400E0E00
0x400E1000
0x400E1200
0x400E1400
+0x10
0x00000000
0x00400000
0x00800000
0x00C00000
0x1FFFFFFF
Boot Memory
Code
MATRIX
PMC
Internal Flash
Internal ROM
Reserved
Reserved
SPI
1 MByte
bit band
region
0x20000000
0x20100000
21
5
8
SRAM
Reserved
UART0
CHIPID
0x22000000
0x24000000
TC0
TC0
TC0
TC1
TC1
TC1
Undefined
TC0
TC1
23
24
25
26
27
28
19
20
31
32 MBytes
bit band alias
UART1
EEFC
9
6
+0x80
0x40000000
0x60000000
0xA0000000
0xE0000000
0xFFFFFFFF
TC2
0x40014000
+0x40
Peripherals
Reserved
Reserved
TC3
Reserved
TC4
PIOA
PIOB
11
12
13
1
+0x80
TC5
0x40018000
0x4001C000
0x40020000
0x40024000
0x40028000
0x4002C000
0x40038000
0x4003C000
0x40040000
0x40044000
0x40048000
0x400E0000
0x400E2600
0x40100000
TWI0
TWI1
PWM
PIOC
1 MByte
bit band
region
SYSC
RSTC
SUPC
RTT
SYSC
SYSC
SYSC
SYSC
SYSC
+0x30
System
USART0
USART1
14
15
3
4
2
+0x50
WDT
+0x60
RTC
Reserved
+0x90
offset
block
peripheral
ADC
GPBR
Reserved
29
30
0x400E1600
0x4007FFFF
ID
DACC
Reserved
Reserved
Reserved
System Controller
Reserved
Reserved
0x40200000
0x40400000
32 MBytes
bit band alias
Reserved
0x60000000
30
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
9. Memories
9.1
Embedded Memories
9.1.1
Internal SRAM
The SAM3N4 product embeds a total of 24-Kbytes high-speed SRAM.
The SAM3N2 product embeds a total of 16-Kbytes high-speed SRAM.
The SAM3N1 product embeds a total of 8-Kbytes high-speed SRAM.
The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000.
The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 and 0x23FF
FFFF.
RAM size must be configurable by calibration fuses.
9.1.2
Internal ROM
The SAM3N product embeds an Internal ROM, which contains the SAM Boot Assistant
(SAM-BA), In Application Programming routines (IAP) and Fast Flash Programming Interface
(FFPI).
At any time, the ROM is mapped at address 0x0080 0000.
9.1.3
Embedded Flash
9.1.3.1
Flash Overview
The Flash of the SAM3N4 (256 Kbytes) is organized in one bank of 1024 pages of 256 bytes
(Single plane).
The Flash of the SAM3N2 (128 Kbytes) is organized in one bank of 512 pages of 256 bytes (Sin-
gle Plane).
The Flash of the SAM3N1 (64 Kbytes) is organized in one bank of 256 pages of 256 bytes (Sin-
gle plane).
The Flash contains a 128-byte write buffer, accessible through a 32-bit interface.
9.1.3.2
9.1.3.3
Flash Power Supply
The Flash is supplied by VDDCORE.
Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller (EEFC) manages accesses performed by the mas-
ters of the system. It enables reading the Flash and writing the write buffer. It also contains a
User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32-
bit internal bus. Its 128-bit wide memory interface increases performance.
The user can choose between high performance or lower current consumption by selecting
either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking
sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system
about the Flash organization, thus making the software generic.
31
11011BS–ATARM–22-Feb-12
9.1.3.4
9.1.3.5
Flash Speed
Lock Regions
The user needs to set the number of wait states depending on the frequency used.
For more details, refer to the AC Characteristics sub section in the product Electrical Character-
istics Section.
Several lock bits used to protect write and erase operations on lock regions. A lock region is
composed of several consecutive pages, and each lock region has its associated lock bit.
Table 9-1.
Lock bit number
Product
Number of lock bits
Lock region size
16 kbytes (64 pages)
16 kbytes (64 pages)
16 kbytes (64 pages)
SAM3N4
SAM3N2
SAM3N1
16
8
4
If a locked-region’s erase or program command occurs, the command is aborted and the EEFC
triggers an interrupt.
The lock bits are software programmable through the EEFC User Interface. The command “Set
Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
9.1.3.6
Security Bit Feature
The SAM3N features a security bit, based on a specific General Purpose NVM bit (GPNVM bit
0). When the security is enabled, any access to the Flash, either through the ICE interface or
through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of
the code programmed in the Flash.
This security bit can only be enabled, through the command “Set General Purpose NVM Bit 0” of
the EEFC User Interface. Disabling the security bit can only be achieved by asserting the
ERASE pin at 1, after a full Flash erase is performed. When the security bit is deactivated, all
accesses to the Flash are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal
operation. However, it is safer to connect it directly to GND for the final application.
9.1.3.7
9.1.3.8
Calibration Bits
NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are
factory configured and cannot be changed by the user. The ERASE pin has no effect on the cal-
ibration bits.
Unique Identifier
Each device integrates its own 128-bit unique identifier. These bits are factory configured and
cannot be changed by the user. The ERASE pin has no effect on the unique identifier.
32
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
9.1.3.9
Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial
JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang program-
ming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered
when TST and PA0 and PA1are tied low.
9.1.3.10
SAM-BA Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the
on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART0.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
9.1.3.11
GPNVM Bits
The SAM3N features three GPNVM bits that can be cleared or set respectively through the com-
mands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.
.
Table 9-2.
General-purpose Non volatile Memory Bits
GPNVMBit[#]
Function
Security bit
0
1
Boot mode selection
9.1.4
Boot Strategies
The system always boots at address 0x0. To ensure a maximum boot possibilities the memory
layout can be changed via GPNVM.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the
Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-
pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface.
Setting the GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the
ROM. Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by
default.
33
11011BS–ATARM–22-Feb-12
10. System Controller
The System Controller is a set of peripherals, which allow handling of key elements of the sys-
tem, such as power, resets, clocks, time, interrupts, watchdog, etc...
See the System Controller block diagram in Figure 10-1 on page 35.
34
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
Figure 10-1. System Controller Block Diagram
VDDIO
VDDOUT
vr_on
vr_mode
Software Controlled
Voltage Regulator
VDDIN
Supply
Controller
Zero-Power
Power-on Reset
VDDIO
PIOx
bod_on
Supply
PIOA/B/C
Monitor
brown_out
(Backup)
WKUP0 - WKUP15
ADx
General Purpose
Backup Registers
ADC
DAC
ADVREF
DAC0
rtc_nreset
SLCK
SLCK
RTC
RTT
rtc_alarm
rtt_nreset
rtt_alarm
osc32k_xtal_en
osc32k_sel
core_nreset
XIN32
Xtal 32 kHz
Oscillator
Slow Clock
SLCK
bod_core_on
Brownout
XOUT32
Detector
(Core)
lcore_brown_out
Embedded
32 kHz RC
Oscillator
osc32k_rc_en
SRAM
Backup Power Supply
core_nreset
Peripherals
VDDCORE
proc_nreset
periph_nreset
ice_nreset
Matrix
Reset
Peripheral
Bridge
Controller
NRST
Cortex-M3
Flash
FSTT0 - FSTT15
SLCK
Embedded
12/8/4 MHz
RC
Main Clock
MAINCK
Master Clock
MCK
Oscillator
Power
Management
Controller
XIN
Xtal
Oscillator
XOUT
PLL
Watchdog
Timer
SLCK
Core Power Supply
FSTT0 - FSTT15 are possible Fast Startup Sources, generated by WKUP0-WKUP15 Pins, but are not physical pins.
35
11011BS–ATARM–22-Feb-12
10.1 System Controller and Peripherals Mapping
Please refer to Figure 8-1, "SAM3N4/2/1/0/00 Product Mapping" on page 30.
All the peripherals are in the bit band region and are mapped in the bit band alias region.
10.2 Power-on-Reset, Brownout and Supply Monitor
The SAM3N embeds three features to monitor, warn and/or reset the chip:
• Power-on-Reset on VDDIO
• Brownout Detector on VDDCORE
• Supply Monitor on VDDIO
10.2.1
10.2.2
Power-on-Reset
The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but
also during power down. If VDDIO goes below the threshold voltage, the entire chip is reset. For
more information, refer to the Electrical Characteristics section of the datasheet.
Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by soft-
ware through the Supply Controller (SUPC_MR). It is especially recommended to disable it
during low-power modes such as wait or sleep modes.
If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more infor-
mation, refer to the Supply Controller (SUPC) and Electrical Characteristics sections of the
datasheet.
10.2.3
Supply Monitor on VDDIO
The Supply Monitor monitors VDDIO. It is inactive by default. It can be activated by software and
is fully programmable with 16 steps for the threshold (between 1.9V to 3.4V). It is controlled by
the Supply Controller (SUPC). A sample mode is possible. It allows to divide the supply monitor
power consumption by a factor of up to 2048. For more information, refer to the SUPC and Elec-
trical Characteristics sections of the datasheet.
10.3 Reset Controller
The Reset Controller is based on a Power-on-Reset cell, and a Supply Monitor on VDDCORE.
The Reset Controller is capable to return to the software the source of the last reset, either a
general reset, a wake-up reset, a software reset, a user reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin input/output. It
is capable to shape a reset signal for the external devices, simplifying to a minimum connection
of a push-button on the NRST pin to implement a manual reset.
The configuration of the Reset Controller is saved as supplied on VDDIO.
10.4 Supply Controller (SUPC)
The Supply Controller controls the power supplies of each section of the processor and the
peripherals (via Voltage regulator control)
The Supply Controller has its own reset circuitry and is clocked by the 32 kHz slow clock
generator.
36
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell.
The zero-power power-on reset allows the Supply Controller to start properly, while the soft-
ware-programmable brownout detector allows detection of either a battery discharge or main
voltage loss.
The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC
oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal
oscillator and select it as the Slow Clock source.
The Supply Controller starts up the device by sequentially enabling the internal power switches
and the Voltage Regulator, then it generates the proper reset signals to the core power supply.
It also enables to set the system in different low power modes and to wake it up from a wide
range of events.
10.5 Clock Generator
The Clock Generator is made up of:
• One Low Power 32768Hz Slow Clock Oscillator with bypass mode
• One Low-Power RC Oscillator
• One 3-20 MHz Crystal or Ceramic resonator Oscillator, which can be bypassed
• One Fast RC Oscillator factory programmed, 3 output frequencies can be selected: 4, 8 or 12
MHz. By default 4 MHz is selected.
• One 60 to 130 MHz programmable PLL, capable to provide the clock MCK to the processor
and to the peripherals. The input frequency of PLL is from 3.5 to 20 MHz.
Figure 10-2. Clock Generator Block Diagram
Clock Generator
XTALSEL
On Chip 32 kHz
RC OSC
Slow Clock
SLCK
XIN32
Slow Clock
Oscillator
XOUT32
XIN
3-20 MHz
Main
Oscillator
Main Clock
MAINCK
XOUT
On Chip
12/8/4 MHz
RC OSC
MAINSEL
PLLA Clock
PLLACK
PLL and
Divider A
Status
Power
Control
Management
Controller
37
11011BS–ATARM–22-Feb-12
10.6 Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
• the Processor Clock HCLK
• the Free running processor clock FCLK
• the Cortex SysTick external clock
• the Master Clock MCK, in particular to the Matrix and the memory interfaces
• independent peripheral clocks, typically at the frequency of MCK
• three programmable clock outputs: PCK0, PCK1 and PCK2
The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The
unused oscillator is disabled automatically so that power consumption is optimized.
By default, at startup the chip runs out of the Master Clock using the Fast RC Oscillator running
at 4 MHz.
The user can trim by software the 8 and 12 MHz RC Oscillator frequency.
Figure 10-3. SAM3N4/2/1/0/00 Power Management Controller Block Diagram
Processor
Clock
Controller
HCK
int
Sleep Mode
Divider
/8
SystTick
FCLK
Master Clock Controller
SLCK
MAINCK
PLLCK
Prescaler
/1,/2,/4,..,/64
MCK
Peripherals
Clock Controller
periph_clk[..]
ON/OFF
Programmable Clock Controller
ON/OFF
SLCK
MAINCK
PLLCK
Prescaler
/1,/2,/4,..,/64
pck[..]
The SysTick calibration value is fixed at 6000 which allows the generation of a time base of 1 ms
with SysTick clock at 6 MHz (48 MHz/8)
10.7 Watchdog Timer
• 16-bit key-protected only-once-Programmable Counter
• Windowed, prevents the processor to be in a dead-lock on the watchdog access
38
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
10.8 SysTick Timer
10.9 Real-time Timer
• 24-bit down counter
• Self-reload capability
• Flexible System timer
• Real-time Timer, allowing backup of time with different accuracies
– 32-bit Free-running back-up Counter
– Integrates a 16-bit programmable prescaler running on slow clock
– Alarm register capable to generate a wake-up of the system through the Shut Down
Controller
10.10 Real Time Clock
• Low power consumption
• Full asynchronous design
• Two hundred year calendar
• Programmable Periodic Interrupt
• Alarm and update parallel load
• Control of alarm and update Time/Calendar Data In
10.11 General Purpose Backup Registers
• Eight 32-bit general-purpose backup registers
10.12 Nested Vectored Interrupt Controller
• Thirty Two maskable external interrupts
• Sixteen priority levels
• Processor state automatically saved on interrupt entry, and restored on
• Dynamic reprioritization of interrupts
• Priority grouping
– selection of pre-empting interrupt levels and non pre-empting interrupt levels
• Support for tail-chaining and late arrival of interrupts
– back-to-back interrupt processing without the overhead of state saving and
restoration between interrupts.
• Processor state automatically saved on interrupt entry and restored on interrupt exit, with no
instruction overhead
39
11011BS–ATARM–22-Feb-12
10.13 Chip Identification
• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.
Table 10-1. SAM3N Chip ID Register
Chip Name
CHIPID_CIDR
0x29540960
0x29590760
0x29580560
0x29440960
0x29490760
0x29480560
0x29340960
0x29390760
0x29380560
CHIPID_EXID
ATSAM3N4C (Rev A)
ATSAM3N2C (Rev A)
ATSAM3N1C (Rev A)
ATSAM3N4B (Rev A)
ATSAM3N2B (Rev A)
ATSAM3N1B (Rev A)
ATSAM3N4A (Rev A)
ATSAM3N2A (Rev A)
ATSAM3N1A (Rev A)
• JTAG ID: 0x05B2E03F
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
10.14 UART
• Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
10.15 PIO Controllers
• 3 PIO Controllers, PIOA, PIOB and PIOC (100-pin version only) controlling a maximum of 79
I/O Lines
• Each PIO Controller controls up to 32 programmable I/O Lines
• Fully programmable through Set/Clear Registers
Table 10-2. PIO available according to pin count
Version
PIOA
48 pin
64 pin
100 pin
32
21
13
-
32
15
-
PIOB
15
PIOC
32
• Multiplexing of four peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
– Input change, rising edge, falling edge, low level and level interrupt
– Debouncing and Glitch filter
40
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
– Multi-drive option enables driving in open drain
– Programmable pull up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
• Selection of the drive level
• Synchronous output, provides Set and Clear of several I/O lines in a single write
11. Peripherals
11.1 Peripheral Identifiers
Table 11-1 defines the Peripheral Identifiers of the SAM3N4/2/1/0/00. A peripheral identifier is
required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller
and for the control of the peripheral clock with the Power Management Controller.
Table 11-1. Peripheral Identifiers
Instance ID
Instance Name
NVIC Interrupt
PMC Clock Control Instance Description
Supply Controller
0
1
SUPC
RSTC
RTC
RTT
WDT
PMC
EEFC
-
X
X
X
X
X
X
X
-
Reset Controller
2
Real Time Clock
3
Real Time Timer
4
Watchdog Timer
5
Power Management Controller
6
Enhanced Flash Controller
Reserved
7
8
UART0
UART1
-
X
X
-
X
X
-
UART 0
9
UART 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Reserved
PIOA
PIOB
PIOC
USART0
USART1
-
X
X
X
X
X
-
X
X
X
X
X
-
Parallel I/O Controller A
Parallel I/O Controller B
Parallel I/O Controller C
USART 0
USART 1
Reserved
-
-
-
Reserved
-
-
-
Reserved
TWI0
TWI1
SPI
X
X
X
-
X
X
X
-
Two Wire Interface 0
Two Wire Interface 1
Serial Peripheral Interface
Reserved
-
TC0
TC1
X
X
X
X
Timer/Counter 0
Timer/Counter 1
41
11011BS–ATARM–22-Feb-12
Table 11-1. Peripheral Identifiers (Continued)
Instance ID
Instance Name
TC2
NVIC Interrupt
PMC Clock Control Instance Description
25
26
27
28
29
30
31
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Timer/Counter 2
TC3
Timer/Counter 3
TC4
Timer/Counter 4
TC5
Timer/Counter 5
ADC
Analog-to-Digital Converter
Digital-to-Analog Converter
Pulse Width Modulation
DACC
PWM
11.2 Peripheral Signals Multiplexing on I/O Lines
The SAM3N product features 2 PIO controllers (48-pin and 64-pin version) or 3 PIO controllers
(100-pin version), PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set.
The SAM3N 64-pin and 100-pin PIO Controller controls up to 32 lines (see Table 10-2, “PIO
available according to pin count,” on page 40). Each line can be assigned to one of three periph-
eral functions: A, B or C. The multiplexing tables in the following paragraphs define how the I/O
lines of the peripherals A, B and C are multiplexed on the PIO Controllers. The column “Com-
ments” has been inserted in this table for the user’s own comments; it may be used to track how
pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within the tables.
42
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
11.2.1
PIO Controller A Multiplexing
Table 11-2. Multiplexing on PIO Controller A (PIOA)
I/O Line
PA0
Peripheral A
PWM0
PWM1
PWM2
TWD0
TWCK0
RXD0
Peripheral B
TIOA0
TIOB0
SCK0
Peripheral C
Extra Function
WKUP0
System Function
Comments
High drive
High drive
High drive
High drive
PA1
WKUP1
PA2
DATRG
WKUP2
PA3
NPCS3
TCLK0
NPCS3
PCK0
PA4
WKUP3
WKUP4
PA5
PA6
TXD0
PA7
RTS0
PWM3
ADTRG
NPCS1
NPCS2
PWM0
PWM1
PWM2
PWM3
TIOA1
TIOB1
PCK1
XIN32
PA8
CTS0
WKUP5
WKUP6
XOUT32
PA9
URXD0
UTXD0
NPCS0
MISO
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
WKUP7
MOSI
SPCK
WKUP8
WKUP14
WKUP15
AD0
PCK2
AD1
AD2/WKUP9
AD3/WKUP10
AD8
RXD1
TXD1
SCK1
RTS1
CTS1
PCK1
NPCS3
PWM0
PWM1
PWM2
TIOA2
TIOB2
TCLK1
TCLK2
NPCS2
PCK2
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
AD9
WKUP11
NPCS1
43
11011BS–ATARM–22-Feb-12
11.2.2
PIO Controller B Multiplexing
Table 11-3. Multiplexing on PIO Controller B (PIOB)
I/O Line
PB0
Peripheral A
PWM0
Peripheral B
Peripheral C
Extra Function
AD4
System Function
Comments
PB1
PWM1
AD5
PB2
URXD1
UTXD1
TWD1
NPCS2
PCK2
AD6/WKUP12
AD7
PB3
PB4
PWM2
TDI
TDO/
TRACESWO
PB5
TWCK1
WKUP13
PB6
PB7
TMS/SWDIO
TCK/SWCLK
XOUT
PB8
PB9
XIN
PB10
PB11
PB12
PB13
PB14
ERASE
PCK0
DAC0
64/100-pin versions
64/100-pin versions
NPCS1
PWM3
44
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
11.2.3
PIO Controller C Multiplexing
I/O Line
PC0
Peripheral A
Peripheral B
Peripheral C
Extra Function
System Function Comments
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
PC1
PC2
PC3
PC4
NPCS1
PC5
PC6
PC7
NPCS2
PWM0
PWM1
PWM2
PWM3
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
AD12
AD10
PCK2
AD11
PCK0
PCK1
PWM0
PWM1
PWM2
PWM3
PWM0
TIOA3
TIOB3
TCLK3
TIOA4
TIOB4
TCLK4
TIOA5
TIOB5
TCLK5
AD13
AD14
AD15
45
11011BS–ATARM–22-Feb-12
12. Embedded Peripherals Overview
12.1 Serial Peripheral Interface (SPI)
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
12.2 Two Wire Interface (TWI)
• Master, Multi-Master and Slave Mode Operation
• Compatibility with Atmel two-wire interface, serial memory and I2C compatible devices
• One, two or three bytes for slave address
• Sequential read/write operations
• Bit Rate: Up to 400 kbit/s
• General Call Supported in Slave Mode
• Connecting to PDC channel capabilities optimizes data transfers in Master Mode only (for
TWI0 only)
– One channel for the receiver, one channel for the transmitter
– Next buffer support
12.3 Universal Asynchronous Receiver Transceiver (UART)
• Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
46
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
– Support for two PDC channels with connection to receiver and transmitter (for
UART0 only)
12.4 USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards (Only on USART0)
– NACK handling, error counter with repetition and iteration limit
• SPI Mode
– Master or Slave
– Serial Clock programmable Phase and Polarity
– SPI Serial Clock (SCK) Frequency up to MCK/4
• IrDA modulation and demodulation (Only on USART0)
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
• PDC support (for USART0 only)
12.5 Timer Counter (TC)
• Six 16-bit Timer Counter Channels
• Wide range of functions including:
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
47
11011BS–ATARM–22-Feb-12
– Two multi-purpose input/output signals
• Two global registers that act on all three TC Channels
• Quadrature decoder
– Advanced line filtering
– Position/revolution/speed
• 2-bit Gray Up/Down Counter for Stepper Motor
12.6 Pulse Width Modulation Controller (PWM)
• Four channels, one 16-bit counter per channel
• Common clock generator, providing thirteen different clocks
– One Modulo n counter providing eleven clocks
– Two independent linear dividers working on modulo n counter outputs
• Independent channel programming
– Independent enable/disable commands
– Independent clock selection
– Independent period and duty cycle, with double buffering
– Programmable selection of the output waveform polarity
12.7 10-bit Analog-to-Digital Converter
• Up to 16-channel ADC
• 10-bit 384 Ksamples/sec. or 8-bit 583 Ksamples/sec. Successive Approximation Register
ADC
•
2 LSB Integral Non Linearity, 1 LSB Differential Non Linearity
• Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs
• External voltage reference for better accuracy on low voltage inputs
• Individual enable and disable of each channel
• Multiple trigger source
– Hardware or software trigger
– External trigger pin
– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
• Sleep Mode and conversion sequencer
– Automatic wakeup on trigger and back to sleep mode after conversions of all
enabled channels
12.8 Digital-to-Analog Converter (DAC)
• 1 channel 10-bit DAC
• Up to 500 ksamples/s conversion rate
• Flexible conversion range
• Multiple trigger sources
• One PDC channel
48
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
13. Package Drawings
The SAM3N series devices are available in LQFP, QFN and TFBGA packages.
Figure 13-1. 100-lead LQFP Package Drawing
Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
49
11011BS–ATARM–22-Feb-12
Figure 13-2. 100-ball TFBGA Package Drawing
50
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
Figure 13-3. 64- and 48-lead LQFP Package Drawing
51
11011BS–ATARM–22-Feb-12
Table 13-1. 48-lead LQFP Package Dimensions (in mm)
Millimeter
Inch
Symbol
Min
–
Nom
Max
1.60
0.15
1.45
Min
–
Nom
Max
0.063
0.006
0.057
A
A1
A2
D
–
–
0.05
1.35
–
1.40
0.002
0.053
–
0.055
0.354 BSC
0.276 BSC
0.354 BSC
0.276 BSC
–
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
–
D1
E
E1
R2
R1
q
0.08
0.08
0°
0.20
–
0.003
0.003
0°
0.008
–
–
–
3.5°
7°
3.5°
7°
θ1
θ2
θ3
c
0°
–
–
0°
–
–
11°
11°
0.09
0.45
12°
13°
13°
0.20
0.75
11°
12°
13°
13°
0.008
0.030
12°
11°
12°
–
0.004
0.018
–
L
0.60
0.024
0.039 REF
–
L1
S
1.00 REF
–
0.20
0.17
–
0.008
0.007
–
b
0.20
0.27
0.008
0.020 BSC.
0.217
0.217
0.011
e
0.50 BSC.
5.50
D2
E2
5.50
Tolerances of Form and Position
0.20
aaa
bbb
ccc
ddd
0.008
0.008
0.003
0.003
0.20
0.08
0.08
52
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
Table 13-2. 64-lead LQFP Package Dimensions (in mm)
Millimeter
Inch
Symbol
Min
–
Nom
Max
1.60
0.15
1.45
Min
–
Nom
Max
0.063
0.006
0.057
A
A1
A2
D
–
–
0.05
1.35
–
0.002
0.053
–
0.055
0.472 BSC
0.383 BSC
0.472 BSC
0.383 BSC
–
1.40
12.00 BSC
D1
E
10.00 BSC
12.00 BSC
E1
R2
R1
q
10.00 BSC
0.08
0.08
0°
–
–
0.20
–
0.003
0.003
0°
0.008
–
–
3.5°
–
7°
3.5°
7°
θ1
θ2
θ3
c
0°
–
0°
–
–
11°
11°
0.09
0.45
12°
13°
13°
0.20
0.75
11°
12°
13°
13°
0.008
0.030
12°
11°
12°
–
0.004
0.018
–
L
0.60
1.00 REF
–
0.024
0.039 REF
–
L1
S
0.20
0.17
–
0.008
0.007
–
b
0.20
0.50 BSC.
7.50
7.50
0.27
0.008
0.020 BSC.
0.285
0.285
0.011
e
D2
E2
Tolerances of Form and Position
0.20
aaa
bbb
ccc
ddd
0.008
0.008
0.003
0.003
0.20
0.08
0.08
53
11011BS–ATARM–22-Feb-12
Figure 13-4. 48-pad QFN Package Drawing
54
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
Table 13-3. 48-pad QFN Package Dimensions (in mm)
Millimeter
Inch
Symbol
Min
–
Nom
–
Max
090
Min
–
Nom
–
Max
0.035
0.002
0.028
A
A1
A2
A3
b
–
–
0.050
0.70
–
–
–
0.65
–
0.026
0.008 REF
0.008
0.276 bsc
0.220
0.276 bsc
0.220
0.016
0.020 bsc
–
0.20 REF
0.20
0.18
5.45
0.23
5.75
0.007
0.215
0.009
0.226
D
7.00 bsc
5.60
D2
E
7.00 bsc
5.60
E2
L
5.45
0.35
5.75
0.45
0.215
0.014
0.226
0.018
0.40
e
0.50 bsc
–
R
0.09
–
0.004
–
Tolerances of Form and Position
0.10
aaa
bbb
ccc
0.004
0.004
0.002
0.10
0.05
55
11011BS–ATARM–22-Feb-12
Figure 13-5. 64-pad QFN Package Drawing
56
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
14. Ordering Information
Table 14-1.
Flash
Temperature
Ordering Code
MRL
(Kbytes)
Package
Package Type
Operating Range
Industrial
-40°C to 85°C
ATSAM3N4CA-AU
A
256
256
256
256
256
256
128
128
128
128
128
128
64
LQFP100
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Industrial
-40°C to 85°C
ATSAM3N4CA-CU
ATSAM3N4BA-AU
ATSAM3N4BA-MU
ATSAM3N4AA-AU
ATSAM3N4AA-MU
ATSAM3N2CA-AU
ATSAM3N2CA-CU
ATSAM3N2BA-AU
ATSAM3N2BA-MU
ATSAM3N2AA-AU
ATSAM3N2AA-MU
ATSAM3N1CA-AU
ATSAM3N1CB-AU
ATSAM3N1CA-CU
ATSAM3N1CB-CU
ATSAM3N1BA-AU
ATSAM3N1BB-AU
ATSAM3N1BA-MU
ATSAM3N1BB-MU
A
A
A
A
A
A
A
A
A
A
A
A
B
A
B
A
B
A
B
TFBGA100
LQFP64
QFN64
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
LQFP48
QFN48
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
LQFP100
TFBGA100
LQFP64
QFN64
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
LQFP48
QFN48
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
LQFP100
LQFP100
TFBGA100
TFBGA100
LQFP64
LQFP64
QFN 64
Industrial
-40°C to 85°C
64
Industrial
-40°C to 85°C
64
Industrial
-40°C to 85°C
64
Industrial
-40°C to 85°C
64
Industrial
-40°C to 85°C
64
Industrial
-40°C to 85°C
64
Industrial
-40°C to 85°C
64
QFN 64
57
11011BS–ATARM–22-Feb-12
Table 14-1.
Ordering Code
Flash
(Kbytes)
Temperature
Operating Range
MRL
Package
Package Type
Industrial
-40°C to 85°C
ATSAM3N1AA-AU
ATSAM3N1AB-AU
ATSAM3N1AA-MU
ATSAM3N1AB-MU
ATSAM3N0CA-AU
ATSAM3N0CA-CU
ATSAM3N0BA-AU
ATSAM3N0BA-MU
ATSAM3N0AA-AU
ATSAM3N0AA-MU
ATSAM3N00BA-AU
ATSAM3N00BA-MU
ATSAM3N00AA-AU
ATSAM3N00AA-MU
A
64
64
64
64
32
32
32
32
32
32
16
16
16
16
LQFP48
Green
Industrial
-40°C to 85°C
B
A
B
A
A
A
A
A
A
A
A
A
A
LQFP48
QFN48
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
QFN48
Industrial
-40°C to 85°C
LQFP100
TFBGA100
LQFP64
QFN64
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
LQFP48
QFN48
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
LQFP64
QFN64
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
LQFP48
QFN48
Industrial
-40°C to 85°C
58
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
Revision History
Doc. Rev.
Change
11011BS
Comments
Request Ref.
Overview:
All mentions of 100-ball LFBGA changed into 100-ball TFBGA
8044
Section 8. “Product Mapping”, Heading was ‘Memories’. Changed to ‘Product Mapping’
Section 4.1.4 “100-ball TFBGA Pinout”, whole pinout table updated
Updated package dimensions in ‘Features’
7685
7201
7965
Change
Doc. Rev
Comments
Request Ref.
11011AS
First issue
59
11011BS–ATARM–22-Feb-12
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Atmel Asia
Atmel Europe
Le Krebs
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Unit 1-5 & 16, 19/F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
Hong Kong
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-en-
Yvelines Cedex
France
Tel: (852) 2245-6100
Fax: (852) 2722-1369
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11
Product Contact
Web Site
www.atmel.com
www.atmel.com/AT91SAM
Technical Support
AT91SAM Support
Atmel techincal support
Sales Contacts
www.atmel.com/contacts/
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
© 2010 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, SAM-BA® and others are registered trademarks or
trademarks of Atmel Corporation or its subsidiaries. ARM®, ARM®Powered logo, Thumb® and others are registered trademarks or trademarks of
ARM Ltd. Other terms and product names may be trademarks of others.
11011BS–ATARM–22-Feb-12
相关型号：
©2020 ICPDF网 联系我们和版权申明