ATMEGA2561V-8MI [ATMEL]
RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, 9 X 9 MM, 1 MM HEIGHT, 0.50 MM PITCH, MO-220VMMD, MLF-64;型号: | ATMEGA2561V-8MI |
厂家: | ATMEL |
描述: | RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, 9 X 9 MM, 1 MM HEIGHT, 0.50 MM PITCH, MO-220VMMD, MLF-64 闪存 微控制器 |
文件: | 总35页 (文件大小:467K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 135 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
• Non-volatile Program and Data Memories
– 64K/128K/256K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
8-bit
Microcontroller
with
64K/128K/256K
Bytes In-System
Programmable
Flash
– 4K Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 8K Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
– Real Time Counter with Separate Oscillator
– Four 8-bit PWM Channels
– Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits
(ATmega1281/2561, ATmega640/1280/2560)
– Output Compare Modulator
– 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560)
– Two/Four Programmable Serial USART (ATmega1281/2561,ATmega640/1280/2560)
– Master/Slave SPI Serial Interface
ATmega640/V
ATmega1280/V
ATmega1281/V
ATmega2560/V
ATmega2561/V
– Byte Oriented 2-wire Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
• I/O and Packages
– 54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560)
– 64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561)
– 100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560)
– RoHS/Fully Green
Preliminary
Summary
• Temperature Range:
– -40°C to 85°C Industrial
• Ultra-Low Power Consumption
– Active Mode: 1 MHz, 1.8V: 510 µA
– Power-down Mode: 0.1 µA at 1.8V
• Speed Grade (see “Maximum speed vs. VCC” on page 377):
– ATmega640V/ATmega1280V/ATmega1281V:
0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V
– ATmega2560V/ATmega2561V:
0 - 2 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V
– ATmega640/ATmega1280/ATmega1281:
0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V
– ATmega2560/ATmega2561:
0 - 16 MHz @ 4.5 - 5.5V
2549KS–AVR–01/07
Pin Configurations
Figure 1. TQFP-pinout ATmega640/1280/2560
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
100
(OC0B) PG5
(RXD0/PCINT8) PE0
(TXD0) PE1
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA3 (AD3)
2
PA4 (AD4)
INDEX CORNER
3
PA5 (AD5)
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
4
PA6 (AD6)
5
PA7 (AD7)
6
PG2 (ALE)
7
PJ6 (PCINT15)
PJ5 (PCINT14)
PJ4 (PCINT13)
PJ3 (PCINT12)
PJ2 (XCK3/PCINT11)
PJ1 (TXD3/PCINT10)
PJ0 (RXD3/PCINT9)
GND
8
(CLKO/ICP3/INT7) PE7
VCC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
(RXD2) PH0
(TXD2) PH1
ATmega640/1280/2560
(XCK2) PH2
(OC4A) PH3
VCC
(OC4B) PH4
PC7 (A15)
(OC4C) PH5
PC6 (A14)
(OC2B) PH6
PC5 (A13)
(SS/PCINT0) PB0
(SCK/PCINT1) PB1
(MOSI/PCINT2) PB2
(MISO/PCINT3) PB3
(OC2A/PCINT4) PB4
(OC1A/PCINT5) PB5
(OC1B/PCINT6) PB6
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PG1 (RD)
PG0 (WR)
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
Figure 2. CBGA-pinout ATmega640/1280/2560
Top view
Bottom view
1
2
3
4
5
6
7
8
9
10
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
K
Table 1. CBGA-pinout ATmega640/1280/2560.
1
2
3
PF0
4
5
6
7
8
9
10
A
B
C
D
E
F
GND
AVCC
PE2
PE3
PE7
VCC
GND
PB3
PH7
PB7
AREF
PG5
PE0
PE4
PH0
PH4
PB1
PB4
PG3
PG4
PF2
PF3
PF4
PE6
PH3
PB0
PB5
PL1
PL0
GND
PF5
PF6
PF7
PH2
PH5
PL4
PL2
PL3
PK0
PK1
PK2
PA4
PJ6
PD1
PD0
PL7
PL6
PL5
PK3
PK4
PK5
PA5
PJ5
PJ1
PD5
PD4
PD3
PD2
PK6
PK7
PJ7
PA6
PJ4
PJ0
PC5
PC4
PC1
PD6
GND
PA0
PA1
PA7
PJ3
VCC
PA2
PA3
PG2
PJ2
PF1
PE1
PE5
PH1
PH6
PB2
RESET
PB6
VCC
PC7
PC6
PC3
PC0
PD7
GND
VCC
PC2
PG1
PG0
G
H
J
XTAL2
XTAL1
K
3
2549KS–AVR–01/07
Figure 3. Pinout ATmega1281/2561
1
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PG2 (ALE)
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
(OC0B) PG5
2
3
(RXD0/PCINT8/PDI) PE0
(TXD0/PDO) PE1
INDEX CORNER
4
(XCK0/AIN0) PE2
5
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
6
7
8
ATmega1281/2561
9
(ICP3/CLKO/INT7) PE7
(SS/PCINT0) PB0
(SCK/PCINT1) PB1
(MOSI/PCINT2) PB2
(MISO/PCINT3) PB3
(OC2A/PCINT4) PB4
(OC1A/PCINT5) PB5
(OC1B/PCINT6) PB6
10
11
12
13
14
15
16
PC0 (A8)
PG1 (RD)
PG0 (WR)
Note:
The large center pad underneath the QFN/MLF package is made of metal and internally
connected to GND. It should be soldered or glued to the board to ensure good mechani-
cal stability. If the center pad is left unconnected, the package might loosen from the
board.
Disclaimer
Typical values contained in this datasheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min.
and Max values will be available after the device is characterized.
4
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
Overview
The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing
speed.
Block Diagram
Figure 4. Block Diagram
PF7..0
PK7..0
PJ7..0
PE7..0
VCC
Power
Supervision
POR / BOD &
RESET
RESET
PORT F (8)
PORT K (8)
PORT J (8)
PORT E (8)
Watchdog
Timer
GND
Analog
Comparator
A/D
Converter
Watchdog
Oscillator
JTAG
USART 0
USART 3
USART 1
USART 2
XTAL1
Oscillator
Circuits /
Clock
Internal
Bandgap reference
16bit T/C 3
EEPROM
Generation
16bit T/C 5
16bit T/C 4
16bit T/C 1
XTAL2
CPU
PORT A (8)
PORT G (6)
PA7..0
FLASH
SRAM
PG5..0
PC7..0
XRAM
TWI
SPI
8bit T/C 0
8bit T/C 2
PORT C (8)
NOTE:
Shaded parts only available
in the 100-pin version.
Complete functionality for
the ADC, T/C4, and T/C5 only
available in the 100-pin version.
PORT D (8)
PORT B (8)
PORT H (8)
PORT L (8)
PD7..0
PB7..0
PH7..0
PL7..0
5
2549KS–AVR–01/07
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K
bytes of In-System Programmable Flash with Read-While-Write capabilities, 4K bytes
EEPROM, 8K bytes SRAM, 54/86 general purpose I/O lines, 32 general purpose work-
ing registers, Real Time Counter (RTC), six flexible Timer/Counters with compare
modes and PWM, 4 USARTs, a byte oriented 2-wire Serial Interface, a 16-channel, 10-
bit ADC with optional differential input stage with programmable gain, programmable
Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant
JTAG test interface, also used for accessing the On-chip Debug system and program-
ming and six software selectable power saving modes. The Idle mode stops the CPU
while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscilla-
tor, disabling all other chip functions until the next interrupt or Hardware Reset. In
Power-save mode, the asynchronous timer continues to run, allowing the user to main-
tain a timer base while the rest of the device is sleeping. The ADC Noise Reduction
mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to min-
imize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low power consumption. In Extended Standby mode, both the main
Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the application Flash memory. Soft-
ware in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.
The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program
and system development tools including: C compilers, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.
6
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
Comparison Between ATmega1281/2561 and ATmega640/1280/2560
Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size
and number of pins. Table 2 summarizes the different configurations for the six devices.
Table 2. Configuration Summary
General
Purpose I/O pins
16 bits resolution
PWM channels
Serial
USARTs
ADC
Channels
Device
Flash
64KB
EEPROM
4KB
RAM
8KB
8KB
8KB
8KB
8KB
ATmega640
ATmega1280
ATmega1281
ATmega2560
ATmega2561
86
86
54
86
54
12
12
6
4
4
2
4
2
16
16
8
128KB
128KB
256KB
256KB
4KB
4KB
4KB
12
6
16
8
4KB
Pin Descriptions
VCC
Digital supply voltage.
Ground.
GND
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 91.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 92.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port
C
also serves the functions of special features of the
ATmega640/1280/1281/2560/2561 as listed on page 95.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
7
2549KS–AVR–01/07
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 97.
Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 99.
Port F (PF7..PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port F output
buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, Port F pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port F pins are tri-stated when a reset condition becomes
active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resis-
tors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset
occurs.
Port F also serves the functions of the JTAG interface.
Port G (PG5..PG0)
Port H (PH7..PH0)
Port J (PJ7..PJ0)
Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G
output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port G pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
Port G also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 105.
Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port H output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port H pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port H also serves the functions of various special features of the
ATmega640/1280/2560 as listed on page 107.
Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port J output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port J pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port J also serves the functions of various special features of the
ATmega640/1280/2560 as listed on page 109.
Port K (PK7..PK0)
Port K serves as analog inputs to the A/D Converter.
8
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port K output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port K pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port K pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port K also serves the functions of various special features of the
ATmega640/1280/2560 as listed on page 111.
Port L (PL7..PL0)
Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port L output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port L pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port L pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port L also serves the functions of various special features of the
ATmega640/1280/2560 as listed on page 113.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
26 on page 58. Shorter pulses are not guaranteed to generate a reset.
XTAL1
XTAL2
AVCC
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier.
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be con-
nected to VCC through a low-pass filter.
AREF
This is the analog reference pin for the A/D Converter.
Resources
A comprehensive set of development tools and application notes, and datasheets are
available for download on http://www.atmel.com/avr.
9
2549KS–AVR–01/07
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x1FF)
...
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UDR3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(0x13F)
(0x13E)
(0x13D)
(0x13C)
(0x13B)
(0x13A)
(0x139)
(0x138)
(0x137)
(0x136)
(0x135)
(0x134)
(0x133)
(0x132)
(0x131)
(0x130)
(0x12F)
(0x12E)
(0x12D)
(0x12C)
(0x12B)
(0x12A)
(0x129)
(0x128)
(0x127)
(0x126)
(0x125)
(0x124)
(0x123)
(0x122)
(0x121)
(0x120)
(0x11F)
(0x11E)
(0x11D)
(0x11C)
(0x11B)
(0x11A)
(0x119)
(0x118)
(0x117)
(0x116)
(0x115)
(0x114)
(0x113)
(0x112)
(0x111)
(0x110)
(0x10F)
(0x10E)
(0x10D)
(0x10C)
(0x10B)
(0x10A)
(0x109)
(0x108)
(0x107)
(0x106)
(0x105)
(0x104)
(0x103)
(0x102)
USART3 I/O Data Register
- USART3 Baud Rate Register High Byte
page 227
page 231
page 231
UBRR3H
UBRR3L
Reserved
UCSR3C
UCSR3B
UCSR3A
Reserved
Reserved
OCR5CH
OCR5CL
OCR5BH
OCR5BL
OCR5AH
OCR5AL
ICR5H
-
-
-
USART3 Baud Rate Register Low Byte
-
-
-
UPM31
UDRIE3
UDRE3
-
-
-
USBS3
TXEN3
DOR3
-
-
-
UCSZ30
RXB83
U2X3
-
-
UMSEL31
UMSEL30
UPM30
UCSZ31
UCPOL3
page 244
page 243
page 242
RXCIE3
TXCIE3
RXEN3
UCSZ32
TXB83
RXC3
TXC3
FE3
UPE3
MPCM3
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer/Counter5 - Output Compare Register C High Byte
Timer/Counter5 - Output Compare Register C Low Byte
Timer/Counter5 - Output Compare Register B High Byte
Timer/Counter5 - Output Compare Register B Low Byte
Timer/Counter5 - Output Compare Register A High Byte
Timer/Counter5 - Output Compare Register A Low Byte
Timer/Counter5 - Input Capture Register High Byte
Timer/Counter5 - Input Capture Register Low Byte
Timer/Counter5 - Counter Register High Byte
page 167
page 167
page 167
page 167
page 167
page 167
page 168
page 168
page 165
page 165
ICR5L
TCNT5H
TCNT5L
Reserved
TCCR5C
TCCR5B
TCCR5A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PORTL
Timer/Counter5 - Counter Register Low Byte
-
-
-
-
-
-
-
-
FOC5A
FOC5B
FOC5C
-
-
-
-
-
page 164
page 162
page 160
ICNC5
ICES5
-
WGM53
WGM52
CS52
CS51
CS50
COM5A1
COM5A0
COM5B1
COM5B0
COM5C1
COM5C0
WGM51
WGM50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTL7
DDL7
PINL7
PORTK7
DDK7
PINK7
PORTJ7
DDJ7
PINJ7
PORTH7
PORTL6
DDL6
PINL6
PORTK6
DDK6
PINK6
PORTJ6
DDJ6
PINJ6
PORTH6
PORTL5
DDL5
PINL5
PORTK5
DDK5
PINK5
PORTJ5
DDJ5
PINJ5
PORTH5
PORTL4
DDL4
PINL4
PORTK4
DDK4
PINK4
PORTJ4
DDJ4
PINJ4
PORTH4
PORTL3
DDL3
PINL3
PORTK3
DDK3
PINK3
PORTJ3
DDJ3
PINJ3
PORTH3
PORTL2
DDL2
PINL2
PORTK2
DDK2
PINK2
PORTJ2
DDJ2
PINJ2
PORTH2
PORTL1
DDL1
PINL1
PORTK1
DDK1
PINK1
PORTJ1
DDJ1
PINJ1
PORTH1
PORTL0
DDL0
PINL0
PORTK0
DDK0
PINK0
PORTJ0
DDJ0
PINJ0
PORTH0
page 118
page 118
page 118
page 118
page 118
page 118
page 118
page 118
page 118
page 117
DDRL
PINL
PORTK
DDRK
PINK
PORTJ
DDRJ
PINJ
PORTH
10
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x101)
(0x100)
(0xFF)
(0xFE)
(0xFD)
(0xFC)
(0xFB)
(0xFA)
(0xF9)
(0xF8)
(0xF7)
(0xF6)
(0xF5)
(0xF4)
(0xF3)
(0xF2)
(0xF1)
(0xF0)
(0xEF)
(0xEE)
(0xED)
(0xEC)
(0xEB)
(0xEA)
(0xE9)
(0xE8)
(0xE7)
(0xE6)
(0xE5)
(0xE4)
(0xE3)
(0xE2)
(0xE1)
(0xE0)
(0xDF)
(0xDE)
(0xDD)
(0xDC)
(0xDB)
(0xDA)
(0xD9)
(0xD8)
(0xD7)
(0xD6)
(0xD5)
(0xD4)
(0xD3)
(0xD2)
(0xD1)
(0xD0)
(0xCF)
(0xCE)
(0xCD)
(0xCC)
(0xCB)
(0xCA)
(0xC9)
(0xC8)
(0xC7)
(0xC6)
(0xC5)
(0xC4)
(0xC3)
(0xC2)
(0xC1)
(0xC0)
DDRH
DDH7
DDH6
DDH5
DDH4
DDH3
DDH2
DDH1
DDH0
page 117
page 117
PINH
PINH7
PINH6
PINH5
PINH4
PINH3
PINH2
PINH1
PINH0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UDR2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2 I/O Data Register
- USART2 Baud Rate Register High Byte
page 227
page 231
page 231
UBRR2H
UBRR2L
Reserved
UCSR2C
UCSR2B
UCSR2A
Reserved
UDR1
-
-
-
USART2 Baud Rate Register Low Byte
-
-
UMSEL20
TXCIE2
TXC2
-
-
-
-
-
-
-
UMSEL21
RXCIE2
RXC2
-
UPM21
UDRIE2
UDRE2
-
UPM20
RXEN2
FE2
USBS2
TXEN2
DOR2
-
UCSZ21
UCSZ22
UPE2
-
UCSZ20
RXB82
U2X2
-
UCPOL2
TXB82
MPCM2
-
page 244
page 243
page 242
-
USART1 I/O Data Register
- USART1 Baud Rate Register High Byte
page 227
page 231
page 231
UBRR1H
UBRR1L
Reserved
UCSR1C
UCSR1B
UCSR1A
Reserved
UDR0
-
-
-
USART1 Baud Rate Register Low Byte
-
-
UMSEL10
TXCIE1
TXC1
-
-
-
-
-
-
-
UMSEL11
RXCIE1
RXC1
-
UPM11
UDRIE1
UDRE1
-
UPM10
RXEN1
FE1
USBS1
TXEN1
DOR1
-
UCSZ11
UCSZ12
UPE1
-
UCSZ10
RXB81
U2X1
-
UCPOL1
TXB81
MPCM1
-
page 244
page 243
page 242
-
USART0 I/O Data Register
- USART0 Baud Rate Register High Byte
page 227
page 231
page 231
UBRR0H
UBRR0L
Reserved
UCSR0C
UCSR0B
UCSR0A
-
-
-
USART0 Baud Rate Register Low Byte
-
-
-
-
-
-
-
-
UMSEL01
RXCIE0
RXC0
UMSEL00
TXCIE0
TXC0
UPM01
UDRIE0
UDRE0
UPM00
RXEN0
FE0
USBS0
TXEN0
DOR0
UCSZ01
UCSZ02
UPE0
UCSZ00
RXB80
U2X0
UCPOL0
TXB80
MPCM0
page 244
page 243
page 243
11
2549KS–AVR–01/07
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xBF)
(0xBE)
(0xBD)
(0xBC)
(0xBB)
(0xBA)
(0xB9)
(0xB8)
(0xB7)
(0xB6)
(0xB5)
(0xB4)
(0xB3)
(0xB2)
(0xB1)
(0xB0)
(0xAF)
(0xAE)
(0xAD)
(0xAC)
(0xAB)
(0xAA)
(0xA9)
(0xA8)
(0xA7)
(0xA6)
(0xA5)
(0xA4)
(0xA3)
(0xA2)
(0xA1)
(0xA0)
(0x9F)
(0x9E)
(0x9D)
(0x9C)
(0x9B)
(0x9A)
(0x99)
(0x98)
(0x97)
(0x96)
(0x95)
(0x94)
(0x93)
(0x92)
(0x91)
(0x90)
(0x8F)
(0x8E)
(0x8D)
(0x8C)
(0x8B)
(0x8A)
(0x89)
(0x88)
(0x87)
(0x86)
(0x85)
(0x84)
(0x83)
(0x82)
(0x81)
(0x80)
(0x7F)
(0x7E)
Reserved
Reserved
TWAMR
TWCR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TWAM6
TWINT
TWAM5
TWEA
TWAM4
TWSTA
TWAM3
TWSTO
TWAM2
TWWC
TWAM1
TWEN
TWAM0
page 274
page 271
page 273
page 273
page 272
page 271
-
TWIE
TWDR
2-wire Serial Interface Data Register
TWAR
TWA6
TWS7
TWA5
TWS6
TWA4
TWS5
TWA3
TWS4
TWA2
TWS3
TWA1
TWA0
TWGCE
TWPS0
TWSR
-
TWPS1
TWBR
2-wire Serial Interface Bit Rate Register
Reserved
ASSR
-
-
-
-
-
AS2
-
-
-
-
-
-
EXCLK
-
TCN2UB
OCR2AUB
-
OCR2BUB
-
TCR2AUB
-
TCR2BUB
-
page 188
Reserved
OCR2B
-
Timer/Counter2 Output Compare Register B
Timer/Counter2 Output Compare Register A
Timer/Counter2 (8 Bit)
page 195
page 195
page 195
page 194
page 195
OCR2A
TCNT2
TCCR2B
TCCR2A
Reserved
Reserved
OCR4CH
OCR4CL
OCR4BH
OCR4BL
OCR4AH
OCR4AL
ICR4H
FOC2A
FOC2B
-
-
WGM22
CS22
CS21
CS20
COM2A1
COM2A0
COM2B1
COM2B0
-
-
-
-
-
-
WGM21
WGM20
-
-
-
-
-
-
-
-
-
-
-
-
Timer/Counter4 - Output Compare Register C High Byte
Timer/Counter4 - Output Compare Register C Low Byte
Timer/Counter4 - Output Compare Register B High Byte
Timer/Counter4 - Output Compare Register B Low Byte
Timer/Counter4 - Output Compare Register A High Byte
Timer/Counter4 - Output Compare Register A Low Byte
Timer/Counter4 - Input Capture Register High Byte
Timer/Counter4 - Input Capture Register Low Byte
Timer/Counter4 - Counter Register High Byte
page 167
page 167
page 166
page 166
page 166
page 166
page 168
page 168
page 165
page 165
ICR4L
TCNT4H
TCNT4L
Reserved
TCCR4C
TCCR4B
TCCR4A
Reserved
Reserved
OCR3CH
OCR3CL
OCR3BH
OCR3BL
OCR3AH
OCR3AL
ICR3H
Timer/Counter4 - Counter Register Low Byte
-
-
-
-
-
-
-
-
FOC4A
FOC4B
FOC4C
-
-
-
-
-
page 164
page 162
page 160
ICNC4
ICES4
-
WGM43
WGM42
CS42
CS41
CS40
COM4A1
COM4A0
COM4B1
COM4B0
COM4C1
COM4C0
WGM41
WGM40
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer/Counter3 - Output Compare Register C High Byte
Timer/Counter3 - Output Compare Register C Low Byte
Timer/Counter3 - Output Compare Register B High Byte
Timer/Counter3 - Output Compare Register B Low Byte
Timer/Counter3 - Output Compare Register A High Byte
Timer/Counter3 - Output Compare Register A Low Byte
Timer/Counter3 - Input Capture Register High Byte
Timer/Counter3 - Input Capture Register Low Byte
Timer/Counter3 - Counter Register High Byte
page 166
page 166
page 166
page 166
page 166
page 166
page 168
page 168
page 165
page 165
ICR3L
TCNT3H
TCNT3L
Reserved
TCCR3C
TCCR3B
TCCR3A
Reserved
Reserved
OCR1CH
OCR1CL
OCR1BH
OCR1BL
OCR1AH
OCR1AL
ICR1H
Timer/Counter3 - Counter Register Low Byte
-
-
-
-
-
-
-
-
FOC3A
FOC3B
FOC3C
-
-
-
-
-
page 164
page 162
page 160
ICNC3
ICES3
-
WGM33
WGM32
CS32
CS31
CS30
COM3A1
COM3A0
COM3B1
COM3B0
COM3C1
COM3C0
WGM31
WGM30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer/Counter1 - Output Compare Register C High Byte
Timer/Counter1 - Output Compare Register C Low Byte
Timer/Counter1 - Output Compare Register B High Byte
Timer/Counter1 - Output Compare Register B Low Byte
Timer/Counter1 - Output Compare Register A High Byte
Timer/Counter1 - Output Compare Register A Low Byte
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
Timer/Counter1 - Counter Register High Byte
page 166
page 166
page 166
page 166
page 166
page 166
page 168
page 168
page 165
page 165
ICR1L
TCNT1H
TCNT1L
Reserved
TCCR1C
TCCR1B
TCCR1A
DIDR1
Timer/Counter1 - Counter Register Low Byte
-
-
-
-
-
-
-
-
FOC1A
ICNC1
COM1A1
-
FOC1B
ICES1
COM1A0
-
FOC1C
-
-
-
-
-
page 164
page 162
page 160
page 278
page 300
-
WGM13
COM1B0
-
WGM12
COM1C1
-
CS12
COM1C0
-
CS11
WGM11
AIN1D
ADC1D
CS10
WGM10
AIN0D
ADC0D
COM1B1
-
DIDR0
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
12
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x7D)
(0x7C)
DIDR2
ADMUX
ADCSRB
ADCSRA
ADCH
ADC15D
REFS1
-
ADC14D
REFS0
ACME
ADC13D
ADLAR
-
ADC12D
MUX4
-
ADC11D
MUX3
MUX5
ADIE
ADC10D
MUX2
ADC9D
MUX1
ADC8D
MUX0
page 300
page 294
(0x7B)
ADTS2
ADPS2
ADTS1
ADPS1
ADTS0
ADPS0
page 277,295,,299
page 297
(0x7A)
ADEN
ADSC
ADATE
ADIF
(0x79)
ADC Data Register High byte
ADC Data Register Low byte
page 298
(0x78)
ADCL
page 298
(0x77)
Reserved
Reserved
XMCRB
XMCRA
TIMSK5
TIMSK4
TIMSK3
TIMSK2
TIMSK1
TIMSK0
PCMSK2
PCMSK1
PCMSK0
EICRB
-
-
-
-
-
-
-
-
(0x76)
-
-
-
-
-
-
-
-
-
(0x75)
XMBK
-
-
-
XMM2
SRW10
OCIE5B
OCIE4B
OCIE3B
OCIE2B
OCIE1B
OCIE0B
PCINT18
PCINT10
PCINT2
ISC50
ISC10
PCIE2
-
XMM1
SRW01
OCIE5A
OCIE4A
OCIE3A
OCIE2A
OCIE1A
OCIE0A
PCINT17
PCINT9
PCINT1
ISC41
ISC01
PCIE1
-
XMM0
SRW00
TOIE5
TOIE4
TOIE3
TOIE2
TOIE1
TOIE0
PCINT16
PCINT8
PCINT0
ISC40
ISC00
PCIE0
-
page 36
page 34
page 169
page 169
page 169
page 197
page 169
page 135
page 81
page 81
page 82
page 79
page 78
page 80
(0x74)
SRE
SRL2
SRL1
ICIE5
ICIE4
ICIE3
-
SRL0
SRW11
OCIE5C
OCIE4C
OCIE3C
-
(0x73)
-
-
-
(0x72)
-
-
-
(0x71)
-
-
-
(0x70)
-
-
-
(0x6F)
-
-
ICIE1
-
-
OCIE1C
-
(0x6E)
-
-
-
(0x6D)
PCINT23
PCINT15
PCINT7
ISC71
ISC31
-
PCINT22
PCINT14
PCINT6
ISC70
ISC30
-
PCINT21
PCINT13
PCINT5
ISC61
ISC21
-
PCINT20
PCINT12
PCINT4
ISC60
ISC20
-
PCINT19
PCINT11
PCINT3
ISC51
ISC11
-
(0x6C)
(0x6B)
(0x6A)
(0x69)
EICRA
(0x68)
PCICR
(0x67)
Reserved
OSCCAL
PRR1
-
-
-
-
-
(0x66)
Oscillator Calibration Register
page 48
page 56
page 55
(0x65)
-
-
PRTIM5
PRTIM4
PRTIM3
PRUSART3
PRUSART2
PRUSART1
(0x64)
PRR0
PRTWI
PRTIM2
PRTIM0
-
PRTIM1
PRSPI
PRUSART0
PRADC
(0x63)
Reserved
Reserved
CLKPR
WDTCSR
SREG
-
-
-
-
-
-
-
-
(0x62)
-
-
-
-
-
-
-
-
(0x61)
CLKPCE
-
-
-
CLKPS3
CLKPS2
CLKPS1
CLKPS0
page 48
page 66
page 12
page 14
page 14
page 15
page 15
(0x60)
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
I
T
H
S
V
N
Z
C
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
EIND
-
-
-
-
-
-
-
EIND0
RAMPZ
Reserved
Reserved
Reserved
SPMCSR
Reserved
MCUCR
MCUSR
SMCR
-
-
-
-
-
-
RAMPZ1
RAMPZ0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PGERS
-
-
SPMEN
-
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
page 340
-
-
-
-
-
-
JTD
-
-
PUD
-
WDRF
SM2
-
-
BORF
SM1
-
IVSEL
EXTRF
SM0
-
IVCE
PORF
SE
page 66,76,115,314
page 314
-
-
-
JTRF
-
-
-
-
page 51
Reserved
OCDR
-
OCDR7
ACD
-
-
-
OCDR5
ACO
-
-
OCDR4
ACI
-
OCDR6
ACBG
-
OCDR3
ACIE
-
OCDR2
ACIC
-
OCDR1
ACIS1
-
OCDR0
ACIS0
-
page 307
page 277
ACSR
Reserved
SPDR
-
SPI Data Register
page 208
page 207
page 206
page 34
page 34
SPSR
SPIF
SPIE
WCOL
-
-
-
-
-
SPI2X
SPR0
SPCR
SPE
DORD
MSTR
CPOL
CPHA
SPR1
GPIOR2
GPIOR1
Reserved
OCR0B
OCR0A
TCNT0
TCCR0B
TCCR0A
GTCCR
EEARH
EEARL
EEDR
General Purpose I/O Register 2
General Purpose I/O Register 1
-
-
-
-
-
-
-
-
Timer/Counter0 Output Compare Register B
Timer/Counter0 Output Compare Register A
Timer/Counter0 (8 Bit)
page 134
page 134
page 134
page 133
page 130
page 173, 198
page 32
FOC0A
COM0A1
TSM
FOC0B
-
-
WGM02
CS02
CS01
CS00
COM0A0
COM0B1
COM0B0
-
-
-
-
WGM01
PSRASY
WGM00
-
-
-
-
-
-
PSRSYNC
-
EEPROM Address Register High Byte
EEPROM Address Register Low Byte
EEPROM Data Register
page 32
page 32
EECR
-
-
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
page 32
GPIOR0
EIMSK
General Purpose I/O Register 0
page 34
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
page 79
EIFR
INTF7
INTF6
INTF5
INTF4
INTF3
INTF2
INTF1
INTF0
page 80
13
2549KS–AVR–01/07
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
PCIFR
TIFR5
TIFR4
TIFR3
TIFR2
TIFR1
TIFR0
PORTG
DDRG
PING
-
-
-
-
-
-
-
PCIF2
OCF5B
OCF4B
OCF3B
OCF2B
OCF1B
OCF0B
PORTG2
DDG2
PCIF1
OCF5A
OCF4A
OCF3A
OCF2A
OCF1A
OCF0A
PORTG1
DDG1
PCIF0
TOV5
page 81
page 169
page 170
page 170
page 197
page 170
page 135
page 117
page 117
page 117
page 116
page 117
page 117
page 116
page 116
page 116
page 116
page 116
page 116
page 116
page 116
page 116
page 115
page 115
page 115
page 115
page 115
page 115
ICF5
-
OCF5C
OCF4C
OCF3C
-
-
-
ICF4
-
TOV4
-
-
ICF3
-
TOV3
-
-
-
-
TOV2
-
-
ICF1
-
OCF1C
-
TOV1
-
-
-
-
TOV0
-
-
PORTG5
DDG5
PING5
PORTF5
DDF5
PINF5
PORTE5
DDE5
PINE5
PORTD5
DDD5
PIND5
PORTC5
DDC5
PINC5
PORTB5
DDB5
PINB5
PORTA5
DDA5
PINA5
PORTG4
DDG4
PING4
PORTF4
DDF4
PINF4
PORTE4
DDE4
PINE4
PORTD4
DDD4
PIND4
PORTC4
DDC4
PINC4
PORTB4
DDB4
PINB4
PORTA4
DDA4
PINA4
PORTG3
DDG3
PING3
PORTF3
DDF3
PORTG0
DDG0
-
-
-
-
PING2
PORTF2
DDF2
PING1
PORTF1
DDF1
PING0
PORTF0
DDF0
PORTF
DDRF
PINF
PORTF7
DDF7
PINF7
PORTE7
DDE7
PINE7
PORTD7
DDD7
PIND7
PORTC7
DDC7
PINC7
PORTB7
DDB7
PINB7
PORTA7
DDA7
PINA7
PORTF6
DDF6
PINF6
PORTE6
DDE6
PINE6
PORTD6
DDD6
PIND6
PORTC6
DDC6
PINC6
PORTB6
DDB6
PINB6
PORTA6
DDA6
PINA6
PINF3
PORTE3
DDE3
PINF2
PINF1
PINF0
PORTE0
DDE0
PORTE
DDRE
PINE
PORTE2
DDE2
PORTE1
DDE1
PINE3
PORTD3
DDD3
PINE2
PINE1
PINE0
PORTD0
DDD0
PORTD
DDRD
PIND
PORTD2
DDD2
PORTD1
DDD1
PIND3
PORTC3
DDC3
PIND2
PIND1
PIND0
PORTC0
DDC0
PORTC
DDRC
PINC
PORTC2
DDC2
PORTC1
DDC1
PINC3
PORTB3
DDB3
PINC2
PINC1
PINC0
PORTB0
DDB0
PORTB
DDRB
PINB
PORTB2
DDB2
PORTB1
DDB1
PINB3
PORTA3
DDA3
PINB2
PINB1
PINB0
PORTA0
DDA0
PORTA
DDRA
PINA
PORTA2
DDA2
PORTA1
DDA1
PINA3
PINA2
PINA1
PINA0
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-
isters, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis-
ters as data space using LD and ST instructions, $20 must be added to these addresses. The
ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported within
the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
14
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADC
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
ADIW
SUB
SUBI
SBC
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
SBCI
SBIW
AND
ANDI
OR
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
Rd ← Rd ⊕ Rr
Z,N,V
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
CBR
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
INC
Z,N,V
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
TST
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Z,N,V
CLR
Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
SER
Rd
Set Register
None
MUL
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
Z,C
MULS
MULSU
FMUL
FMULS
FMULSU
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z,C
Z,C
Z,C
Z,C
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
PC ← PC + k + 1
PC ← Z
None
None
None
None
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ←(EIND:Z)
EIJMP
JMP
Extended Indirect Jump to (Z)
Direct Jump
2
k
k
PC ← k
3
RCALL
ICALL
EICALL
CALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
PC ← Z
4
4
PC ←(EIND:Z)
Extended Indirect Call to (Z)
Direct Subroutine Call
Subroutine Return
4
k
PC ← k
5
PC ← STACK
5
RETI
Interrupt Return
PC ← STACK
5
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
15
2549KS–AVR–01/07
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRVS
BRVC
BRIE
BRID
k
k
k
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
1/2
1/2
1/2
1/2
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
None
None
None
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CBI
I/O(P,b) ← 0
None
LSL
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S
V
V
T
S ← 0
V ← 1
V ← 0
T ← 1
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
LD
LDD
LD
Rd ← (Z)
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
LD
LDD
LDS
ST
Rd ← (k)
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
ELPM
ELPM
(k) ← Rr
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Extended Load Program Memory
Extended Load Program Memory
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
R0 ← (RAMPZ:Z)
Rd ← (RAMPZ:Z)
Rd, Z
16
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ELPM
SPM
IN
Rd, Z+
Extended Load Program Memory
Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1
None
3
-
Store Program Memory
In Port
(Z) ← R1:R0
Rd ← P
None
None
None
None
None
Rd, P
P, Rr
Rr
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
None
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
Note:
EICALL and EIJMP do not exist in ATmega640/1280/1281.
ELPM does not exist in ATmega640.
17
2549KS–AVR–01/07
Ordering Information
ATmega640
Speed (MHz)(2)
Power Supply
Ordering Code
Package(1)(3)
Operation Range
ATmega640V-8AU
ATmega640V-8CU
100A
8
1.8 - 5.5V
Industrial (-40°C to 85°C)
100C1
ATmega640-16AU
ATmega640-16CU
100A
16
2.7 - 5.5V
Industrial (-40°C to 85°C)
100C1
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. See “Maximum speed vs. VCC” on page 377.
3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
Package Type
64A
64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
64-pad, 9 x 9 x 1.0 mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)
100-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
100-ball, Chip Ball Grid Array (CBGA)
64M2
100A
100C1
18
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
ATmega1281
Speed (MHz)(2)
Power Supply
Ordering Code
Package(1)(3)
Operation Range
ATmega1281V-8AU
ATmega1281V-8MU
64A
64M2
Industrial
(-40°C to 85°C)
8
1.8 - 5.5V
ATmega1281-16AU
ATmega1281-16MU
64A
64M2
Industrial
(-40°C to 85°C)
16
2.7 - 5.5V
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. See “Maximum speed vs. VCC” on page 377.
3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
Package Type
64A
64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
64-pad, 9 x 9 x 1.0 mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)
100-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
100-ball, Chip Ball Grid Array (CBGA)
64M2
100A
100C1
19
2549KS–AVR–01/07
ATmega1280
Speed (MHz)(2)
Power Supply
Ordering Code
Package(1)(3)
Operation Range
ATmega1280V-8AU
ATmega1280V-8CU
100A
8
1.8 - 5.5V
Industrial (-40°C to 85°C)
100C1
ATmega1280-16AU
ATmega1280-16AU
100A
16
2.7 - 5.5V
Industrial (-40°C to 85°C)
100C1
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. See “Maximum speed vs. VCC” on page 377.
3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
Package Type
64A
64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
64-pad, 9 x 9 x 1.0 mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)
100-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
100-ball, Chip Ball Grid Array (CBGA)
64M2
100A
100C1
20
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
ATmega2561
Speed (MHz)(2)
Power Supply
Ordering Code
Package(1)(3)
Operation Range
ATmega2561V-8AU
ATmega2561V-8MU
64A
64M2
Industrial
(-40°C to 85°C)
8
1.8 - 5.5V
ATmega2561-16AU
ATmega2561-16MU
64A
64M2
Industrial
(-40°C to 85°C)
16
4.5 - 5.5V
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. See “Maximum speed vs. VCC” on page 377.
3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
Package Type
64A
64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
64-pad, 9 x 9 x 1.0 mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)
100-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
100-ball, Chip Ball Grid Array (CBGA)
64M2
100A
100C1
21
2549KS–AVR–01/07
ATmega2560
Speed (MHz)(2)
Power Supply
Ordering Code
Package(1)(3)
Operation Range
ATmega2560V-8AU
ATmega2560V-8CU
100A
8
1.8 - 5.5V
Industrial (-40°C to 85°C)
100C1
ATmega2560-16AU
ATmega2560-16CU
100A
16
4.5 - 5.5V
Industrial (-40°C to 85°C)
100C1
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. See “Maximum speed vs. VCC” on page 377.
3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
Package Type
64A
64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
64-pad, 9 x 9 x 1.0 mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)
100-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
100-ball, Chip Ball Grid Array (CBGA)
64M2
100A
100C1
22
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
Packaging Information
100A
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.17
0.09
0.45
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
14.10 Note 2
0.27
C
–
0.20
3. Lead coplanarity is 0.08 mm maximum.
L
–
0.75
e
0.50 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
100A
C
R
23
2549KS–AVR–01/07
100C1
0.12
Z
E
Marked A1 Identifier
SIDE VIEW
D
A
TOP VIEW
A1
Øb
e
A1 Corner
0.90 TYP
10
8
7
6
9
5
4
3
2
1
A
B
C
D
0.90 TYP
COMMON DIMENSIONS
E
F
(Unit of Measure = mm)
D1
MIN
1.10
0.30
8.90
8.90
7.10
7.10
0.35
MAX
1.20
0.40
9.10
9.10
7.30
7.30
0.45
NOM
–
NOTE
SYMBOL
G
e
A
H
I
A1
D
0.35
J
9.00
E
9.00
E1
D1
E1
Øb
e
7.20
7.20
BOTTOM VIEW
0.40
0.80 TYP
5/25/06
DRAWING NO. REV.
100C1
TITLE
2325 Orchard Parkway
San Jose, CA 95131
100C1, 100-ball, 9 x 9 x 1.2 mm Body, Ball Pitch 0.80 mm
Chip Array BGA Package (CBGA)
A
R
24
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
64A
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.30
0.09
0.45
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
14.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
64A
B
R
25
2549KS–AVR–01/07
64M2
D
Marked Pin# 1 ID
E
SEATING PLANE
C
A1
TOP VIEW
A
K
0.08
C
L
Pin #1 Corner
SIDE VIEW
D2
Pin #1
Triangle
Option A
1
2
3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.80
–
MAX
1.00
0.05
0.30
9.10
7.80
9.10
NOM
0.90
0.02
0.25
9.00
7.65
9.00
NOTE
SYMBOL
E2
Option B
Option C
A
Pin #1
Chamfer
(C 0.30)
A1
b
0.18
8.90
7.50
8.90
D
D2
E
K
Pin #1
Notch
(0.20 R)
e
b
E2
e
7.50
7.65
0.50 BSC
0.40
7.80
BOTTOM VIEW
L
0.35
0.20
0.45
0.40
K
0.27
1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
2. Dimension and tolerance conform to ASMEY14.5M-1994.
Note:
5/25/06
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
64M2, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,
7.65 mm Exposed Pad, Micro Lead Frame Package (MLF)
64M2
D
R
26
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
Errata
ATmega640 rev. A
• Inaccurate ADC conversion in differential mode with 200x gain
• High current consumption in sleep mode
1. Inaccurate ADC conversion in differential mode with 200x gain
With AVCC < 3.6V, random conversions will be inaccurate. Typical absolute accu-
racy may reach 64 LSB.
Problem Fix/Workaround
None
2. High current consumption in sleep mode.
If a pending interrupt cannot wake the part up from the selected sleep mode, the
current consumption will increase during sleep when executing the SLEEP instruc-
tion directly after a SEI instruction.
Problem Fix/Workaround
Before entering sleep, interrupts not used to wake the part from the sleep mode
should be disabled.
ATmega1280 rev. A
• Inaccurate ADC conversion in differential mode with 200x gain
• High current consumption in sleep mode
1. Inaccurate ADC conversion in differential mode with 200x gain
With AVCC < 3.6V, random conversions will be inaccurate. Typical absolute accu-
racy may reach 64 LSB.
Problem Fix/Workaround
None
2. High current consumption in sleep mode.
If a pending interrupt cannot wake the part up from the selected sleep mode, the
current consumption will increase during sleep when executing the SLEEP instruc-
tion directly after a SEI instruction.
Problem Fix/Workaround
Before entering sleep, interrupts not used to wake the part from the sleep mode
should be disabled.
27
2549KS–AVR–01/07
ATmega1281 rev. A
• Inaccurate ADC conversion in differential mode with 200x gain
• High current consumption in sleep mode
1. Inaccurate ADC conversion in differential mode with 200x gain
With AVCC < 3.6V, random conversions will be inaccurate. Typical absolute accu-
racy may reach 64 LSB.
Problem Fix/Workaround
None
2. High current consumption in sleep mode.
If a pending interrupt cannot wake the part up from the selected sleep mode, the
current consumption will increase during sleep when executing the SLEEP instruc-
tion directly after a SEI instruction.
Problem Fix/Workaround
Before entering sleep, interrupts not used to wake the part from the sleep mode
should be disabled.
ATmega2560 rev. E
ATmega2560 rev. D
ATmega2560 rev. C
No known errata.
Not sampled.
• High current consumption in sleep mode
1. High current consumption in sleep mode.
If a pending interrupt cannot wake the part up from the selected sleep mode, the
current consumption will increase during sleep when executing the SLEEP instruc-
tion directly after a SEI instruction.
Problem Fix/Workaround
Before entering sleep, interrupts not used to wake the part from the sleep mode
should be disabled.
ATmega2560 rev. B
Not sampled.
28
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
ATmega2560 rev. A
• Non-Read-While-Write area of flash not functional
• Part does not work under 2.4 volts
• Incorrect ADC reading in differential mode
• Internal ADC reference has too low value
• IN/OUT instructions may be executed twice when Stack is in external RAM
• EEPROM read from application code does not work in Lock Bit Mode 3
1. Non-Read-While-Write area of flash not functional
The Non-Read-While-Write area of the flash is not working as expected. The prob-
lem is related to the speed of the part when reading the flash of this area.
Problem Fix/Workaround
- Only use the first 248K of the flash.
- If boot functionality is needed, run the code in the Non-Read-While-Write area at
maximum 1/4th of the maximum frequency of the device at any given voltage. This
is done by writing the CLKPR register before entering the boot section of the code
2. Part does not work under 2.4 volts
The part does not execute code correctly below 2.4 volts
Problem Fix/Workaround
Do not use the part at voltages below 2.4 volts.
3. Incorrect ADC reading in differential mode
The ADC has high noise in differential mode. It can give up to 7 LSB error.
Problem Fix/Workaround
Use only the 7 MSB of the result when using the ADC in differential mode.
4. Internal ADC reference has too low value
The internal ADC reference has a value lower than specified
Problem Fix/Workaround
- Use AVCC or external reference
- The actual value of the reference can be measured by applying a known voltage to
the ADC when using the internal reference. The result when doing later conversions
can then be calibrated.
5. IN/OUT instructions may be executed twice when Stack is in external RAM
If either an IN or an OUT instruction is executed directly before an interrupt occurs
and the stack pointer is located in external ram, the instruction will be executed
twice. In some cases this will cause a problem, for example:
- If reading SREG it will appear that the I-flag is cleared.
- If writing to the PIN registers, the port will toggle twice.
- If reading registers with interrupt flags, the flags will appear to be cleared.
Problem Fix/Workaround
There are two application work-arounds, where selecting one of them, will be omit-
ting the issue:
- Replace IN and OUT with LD/LDS/LDD and ST/STS/STD instructions
- Use internal RAM for stack pointer.
29
2549KS–AVR–01/07
6. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM
read does not work from the application code.
Problem Fix/Workaround
Do not set Lock Bit Protection Mode 3 when the application code needs to read from
EEPROM.
ATmega2561 rev. E
ATmega2561 rev. D
ATmega2561 rev. C
No known errata.
Not sampled.
• High current consumption in sleep mode
1. High current consumption in sleep mode.
If a pending interrupt cannot wake the part up from the selected sleep mode, the
current consumption will increase during sleep when executing the SLEEP instruc-
tion directly after a SEI instruction.
Problem Fix/Workaround
Before entering sleep, interrupts not used to wake the part from the sleep mode
should be disabled.
ATmega2561 rev. B
ATmega2561 rev. A
Not sampled.
• Non-Read-While-Write area of flash not functional
• Part does not work under 2.4 Volts
• Incorrect ADC reading in differential mode
• Internal ADC reference has too low value
• IN/OUT instructions may be executed twice when Stack is in external RAM
• EEPROM read from application code does not work in Lock Bit Mode 3
1. Non-Read-While-Write area of flash not functional
The Non-Read-While-Write area of the flash is not working as expected. The prob-
lem is related to the speed of the part when reading the flash of this area.
Problem Fix/Workaround
- Only use the first 248K of the flash.
- If boot functionality is needed, run the code in the Non-Read-While-Write area at
maximum 1/4th of the maximum frequency of the device at any given voltage. This
is done by writing the CLKPR register before entering the boot section of the code.
30
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
2. Part does not work under 2.4 volts
The part does not execute code correctly below 2.4 volts
Problem Fix/Workaround
Do not use the part at voltages below 2.4 volts.
3. Incorrect ADC reading in differential mode
The ADC has high noise in differential mode. It can give up to 7 LSB error.
Problem Fix/Workaround
Use only the 7 MSB of the result when using the ADC in differential mode
4. Internal ADC reference has too low value
The internal ADC reference has a value lower than specified
Problem Fix/Workaround
- Use AVCC or external reference
- The actual value of the reference can be measured by applying a known voltage to
the ADC when using the internal reference. The result when doing later conversions
can then be calibrated.
5. IN/OUT instructions may be executed twice when Stack is in external RAM
If either an IN or an OUT instruction is executed directly before an interrupt occurs
and the stack pointer is located in external ram, the instruction will be executed
twice. In some cases this will cause a problem, for example:
- If reading SREG it will appear that the I-flag is cleared.
- If writing to the PIN registers, the port will toggle twice.
- If reading registers with interrupt flags, the flags will appear to be cleared.
Problem Fix/Workaround
There are two application workarounds, where selecting one of them, will be omit-
ting the issue:
- Replace IN and OUT with LD/LDS/LDD and ST/STS/STD instructions
- Use internal RAM for stack pointer.
6. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM
read does not work from the application code.
Problem Fix/Workaround
Do not set Lock Bit Protection Mode 3 when the application code needs to read from
EEPROM.
31
2549KS–AVR–01/07
Datasheet Revision
History
Please note that the referring page numbers in this section are referring to this docu-
ment.The referring revision in this section are referring to the document revision.
Rev. 2549K-01/07
1.
2.
3.
4.
5.
6:
7.
Updated Table 1 on page 3.
Updated “Pin Descriptions” on page 7.
Updated “Stack Pointer” on page 14.
Updated “Bit 1 – EEPE: EEPROM Programming Enable” on page 33.
Updated Assembly code example in “Watchdog Timer” on page 62.
Updated “EIMSK – External Interrupt Mask Register” on page 79.
Updated Bit description in “PCIFR – Pin Change Interrupt Flag Register”
on page 81.
8.
9.
Updated code example in “USART Initialization” on page 215.
Updated Figure 120 on page 288.
10. Updated “DC Characteristics” on page 374.
Rev. 2549J-09/06
1.
2.
Updated “Calibrated Internal RC Oscillator” on page 44.
Updated code example in “Moving Interrupts Between Application and
Boot Section” on page 74.
3.
4.
5.
6.
Updated “Timer/Counter Prescaler” on page 190.
Updated “Device Identification Register” on page 309.
Updated “Signature Bytes” on page 345.
Updated “Instruction Set Summary” on page 421.
Rev. 2549I-07/06
1.
2.
Updated Table 74 on page 130, Table 77 on page 131, Table 79 on page
132, Table 82 on page 149, Table 84 on page 161, Table 85 on page 161,
Table 89 on page 191, Table 92 on page 192 and Table 94 on page 193.
Updated “Fast PWM Mode” on page 151.
Rev. 2549H-06/06
Rev. 2549G-06/06
1.
2.
3.
Updated “Calibrated Internal RC Oscillator” on page 44.
Updated “OSCCAL – Oscillator Calibration Register” on page 48.
Added Table 172 on page 384.
1.
2.
3.
4.
5.
6.
7.
Updated “Features” on page 1.
Added Figure 2 on page 3, Table 1 on page 3.
Updated “Calibrated Internal RC Oscillator” on page 44.
Updated “Power Management and Sleep Modes” on page 50.
Updated note for Table 30 on page 67.
Updated Figure 121 on page 289 and Figure 122 on page 289.
Updated “Setting the Boot Loader Lock Bits by SPM” on page 330.
32
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
ATmega640/1280/1281/2560/2561
8.
9.
Updated “Ordering Information” on page 18.
Added Package information “100C1” on page 24.
10. Updated “Errata” on page 27.
Rev. 2549F-04/06
Rev. 2549E-04/06
1.
Updated Figure 15 on page 28, Figure 16 on page 29 and Figure 17 on
page 29.
Updated Table 88 on page 191 and Table 89 on page 191.
Updated Features in “ADC – Analog to Digital Converter” on page 279.
Updated “Fuse Bits” on page 343.
2.
3.
4.
1.
2.
3.
4.
Updated “Features” on page 1.
Updated Table 27 on page 60.
Updated note for Table 27 on page 60.
Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page
277.
5.
5.
6.
Updated “Prescaling and Conversion Timing” on page 282.
Updated “Maximum speed vs. VCC” on page 377.
Updated “Ordering Information” on page 18.
Rev. 2549D-12/05
1.
2.
3.
Advanced Information Status changed to Preliminary.
Changed number of I/O Ports from 51 to 54.
Updatet typos in “TCCR0A – Timer/Counter Control Register A” on page
130.
4.
5.
6.
Updated Features in “ADC – Analog to Digital Converter” on page 279.
Updated Operation in“ADC – Analog to Digital Converter” on page 279
Updated Stabilizing Time in “Changing Channel or Reference Selection”
on page 286.
7.
8.
9.
Updated Figure 113 on page 280, Figure 121 on page 289, Figure 122 on
page 289.
Updated Text in “ADCSRB – ADC Control and Status Register B” on page
295.
Updated Note for Table 4 on page 41, Table 51 on page 99, Table 128 on
page 294 and Table 131 on page 299.
10. Updated Table 170 on page 382 and Table 171 on page 383.
11. Updated “Filling the Temporary Buffer (Page Loading)” on page 329.
12. Updated “Typical Characteristics” on page 390.
13. Updated “Packaging Information” on page 23.
14. Updated “Errata” on page 27.
Rev. 2549C-09/05
1.
2.
3.
Updated Speed Grade in section “Features” on page 1.
Added “Resources” on page 9.
Updated “SPI – Serial Peripheral Interface” on page 199. In Slave mode,
low and high period SPI clock must be larger than 2 CPU cycles.
33
2549KS–AVR–01/07
4.
5.
6.
7.
Updated “Bit Rate Generator Unit” on page 251.
Updated “Maximum speed vs. VCC” on page 377.
Updated “Ordering Information” on page 18.
Updated “Packaging Information” on page 23. Package 64M1 replaced by
64M2.
8.
Updated “Errata” on page 27.
Rev. 2549B-05/05
Rev. 2549A-03/05
1.
2.
3.
4.
JTAG ID/Signature for ATmega640 updated: 0x9608.
Updated Table 43 on page 94.
Updated “Serial Programming Instruction set” on page 359.
Updated “Errata” on page 27.
1.
Initial version.
34
ATmega640/1280/1281/2560/2561
2549KS–AVR–01/07
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
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2549KS–AVR–01/07
相关型号:
ATMEGA2561V-8MU-SL383
Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, 9 X 9 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, MO-220VMMD, MLF-64
ATMEL
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