ATLV7AI [ATMEL]
Field Programmable Gate Array, 4400 Gates, CMOS, PQFP100, 1MM HEIGHT, PLASTIC, VQFP-100;
| 型号： | ATLV7AI |
| 厂家： | 
ATMEL |
| 描述： | Field Programmable Gate Array, 4400 Gates, CMOS, PQFP100, 1MM HEIGHT, PLASTIC, VQFP-100 栅 |
| 文件： | 总7页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Specifically Designed for Battery Powered Applications
1.0 - 3.0 Volts and will Operate from 0.7 to 5.5 Volts
• Static Current Drain of <75 nA at 1.0 Volts
• 200 MHz Maximum Toggle Frequency for Flip Flop at 1.5 Volts
• 1.0 µ Drawn Gate Length CMOS Gate Arrays
• All Package Styles Offered Including TQFP and TAB
• Improved Product Testability Using Serial Scan, Boundary Scan,
and JTAG
ATLV Series
Ultra Low
Voltage
• Second Source Existing ASIC Design in Atmel's ATLV via Design
Translation. Improved Performance and Lower Cost
Description
Gate Arrays
The ATLV Series CMOS gate arrays employ 1.0 µ-drawn, double-level metal,
Si-gate, CMOS technology processed in Atmel's U.S.-based, advanced
manufacturing facility. The arrays utilize an enhanced channelless architecture
which results in greater than 50 percent usable gates.
ATLV2
ATLV3
ATLV5
ATLV7
ATLV10
ATLV15
ATLV20
ATLV35
Atmel's flexible design system uses industry design standards and is compatible
with popular CAD/CAE software and hardware packages. The customer can
start designing with the ATLV series today using existing CAD/CAE tools.
ATLV Array Organization
(1)
(2)
Device
Number
Raw
Gates
Routable
Gates
Max Pin
Count
Max I/O
Pins
Gate
Speed
ATLV2
ATLV3
2,000
3,000
1,400
1,600
2,800
4,400
6,600
8,000
12,000
18,000
44
68
36
60
1.3 ns
1.3 ns
1.3 ns
1.3 ns
1.3 ns
1.3 ns
1.3 ns
1.3 ns
ATLV5
5,000
84
76
ATLV7
7,000
100
120
144
160
208
92
ATLV10
ATLV15
ATLV20
ATLV35
10,000
15,000
22,000
35,000
112
136
152
192
Notes: 1. Absolute maximum I/O pins is maximum pin count minus 8. Additional power
and ground pins are assumed to be required to support simultaneous
switching outputs as pin count increases.
2. Nominal 2 input nand gate with a fan out of 2 at 1.5 volts, room temperature.
0261B
ATLV Design
Design Options
Schematic Capture
Design Systems Supported
Schematic capture and simulation are performed by the
customer using an Atmel supplied macro cell library. The
customer can also receive complete back annotation delay
data for post-route simulation.
Atmel supports the major CAE/CAD software systems
with complete macro cell libraries (symbols, timing and
function), as well as utilities for checking the netlist and
accuratepre-routedelaysimulations. AtmelusesCadence’s
Verilog-XL as our golden simulator. Design systems
which are supported include Cadence, Viewlogic, Mentor,
and Synopsys.
VHDL/Verilog-HDL
Atmel can accept Register Transfer level (RTL) designs for
VHDL (MIL-STD-454, IEEE STD 1076) or Verilog-HDL
format. Atmel fully supports Synopsys for VHDL simula-
tion as well as synthesis. Design via VHDL or Verilog-
HDL is the preferred method of performing a gate array
design.
Design Flow
While Atmel provides four options for implementing a gate
array design, they all have the same basic flow. Data base
acceptance is the first milestone. This is when Atmel
receives and accepts the complete design data base.
Preliminary design review is where the performance of the
design is set based on the Cadence simulation. Final design
reviewisthelastreviewofthedesignbeforemakingmasks.
Thebackannotationdataisincorporatedintothesimulations.
Afterfinaldesignreviewmasksarereleasedandprototypes
in ceramic packages are delivered.
ASIC Design Translation
Atmel has successfully translated dozens of existing de-
signs from most major ASIC vendors (LSI Logic, Oki,
NEC, Fujitsu and others) into our gate arrays. These
designs have been optimized for speed, gate count, modi-
fied to add logic or memory, or replicated for a pin-for-pin
compatible, drop-in replacement.
ATLV Gate Array Design Flow
Design
Gate Array
Atmel Cell
Synthesis FPGA/EPLD
Customer
Design
Atmel
Library
-VHDL
-Verilog-HDL
Conversions
Translation
Data Base Acceptance
Atmel
Atmel
Simulation
and Verification
Customer
Preliminary Design Review
Atmel
Atmel
Atmel
Physical Design, Simulation
and Verification
Final Design Review
Prototype Delivery
Customer
Customer
Atmel
2
ATLV
ATLV
FPGA and EPLD Conversions
Atmel has successfully translated existing FPGA/EPLD
designs from most major vendors (Xilinx, Actel, Altera,
AMD & Atmel) into our gate arrays. The design can be
optimized for speed or power consumption, modified to
addlogicormemoryorreplicatedforapin-for-pincompat-
ible, drop-in replacement. Atmel frequently combines
several devices onto a single gate array.
at the transistor level and verified through measurements
made on fabricated test arrays. The symbols for the ATLV
cell library are compatible with Atmel's ATL (1.0 µ 3.3
and 5.0 V) and ATL80 (0.8 µ 3.3 and 5.0 V) cell libraries.
Existing designs can be easily migrated to the ATLV
series. Characterization has been performed over
commercial temperature and 1.0 to 3.0 volts, to ensure
that the simulation accurately predicts the performance
of the finished product. Atmel is continually expanding
the ATLV series cell library with both soft and hard
macros. Check with your sales representative for the most
recent additions.
ATLV Series Cell Library
Atmel’s ATLV series gate arrays use cells from an
accurately modeled and highly flexible library. The cell
library contains over 120 hard-wired data path elements
and has been characterized via extensive SPICE modeling
Cell Guide
Buffers and Inverters
1x Buffer
1x Inverter
2x Buffer
Dual 1x Inverter
Quad 1x Inverter
Quad Tri-state Inverter
2x Inverter
2x Buffer with Enable
2x Buffer with Enable Low
3x Buffer
4x Buffer
8x Buffer
12x Buffer
Dual 2x Inverter
2x Tri-state Inverter
3x Inverter
16x Buffer
4x Inverter
Delay Buffer 2.0 ns
Delay Buffer 3.5 ns
Delay Buffer 8.0 ns
8x Inverter
10x Inverter
AND, NAND, OR, NOR Gates
2 input AND
3 input AND
4 input AND
5 input AND
2 input NAND
Dual 2-input NAND
3 input NAND
4 input NAND
5 input NAND
6 input NAND
8 input NAND
2 input NOR
Dual 2 input NOR
3 input NOR
4 input NOR
5 input NOR
8 input NOR
2 input OR
3 input OR
4 input OR
Multiplexers
2:1 MUX
4:1 MUX
Inverting 2:1 MUX w/o Buffered Inputs
Inverting 2:1 MUX w/o Buffered Inputs
2:1 MUX with Enable Low
4:1 MUX w/o Buffered Inputs
4:1 MUX w/o Buffered Inputs
8:1 MUX
Quad 2:1 MUX with Enable
Quad 2:1 MUX
8:1 MUX with Enable Low
Inverting 3:1 MUX w/o Buffered Inputs
Inverting 3:1 MUX w/o Buffered Inputs
3
Cell Guide
AND/OR, OR/AND Gates
3 input AND OR INVERT
4 input AND OR INVERT
6 input AND OR INVERT
3 input OR AND INVERT
4 input OR AND INVERT
8 input OR AND INVERT
Exclusive OR/NOR Gates
1 bit Adder
1 bit Adder with Buffered Outputs
7 input Carry Lookahead
2 input Exclusive OR
2 input Exclusive NOR
Decoders
2:4 Decoder
3:8 Decoder with Low Enable
2:4 Decoder with Low Enable
Flip-flops/Latches
D Flip-flop
LATCH
D Flip-flop with Clear/Preset
D Flip-flop with Clear
D Flip-flop with Reset
D Flip-flop with Set
D Flip-flop with Set/Reset
JK Flip-flop
LATCH with Complementary Outputs
LATCH with Inverted Gate Signal
QUAD LATBG with Common Gate Signal
QUAD Inverting LATCH
LATCH with Reset
LATCH with Set
JK Flip-flop with Clear/Preset
JK Flip-flop with Clear
LATCH with Set and Reset
Scan Cells
Set-scan Register
Set-scan Register with Set
Set-scan Register with Clear and Preset
Set-scan Register with Reset
Set-scan Register with Set and Reset
I/O Options
Input, Output, Bidirectional, Tristate Output, Internal Clock Driver and Oscillator
Output Drive Value Programmable from 0.5 mA to 6 mA in 0.5 mA increments with Slew Rate Control
CMOS Operation
Testable NAND Gate on Input (Bidirectional, Input)
Inverting and Non-inverting Input Buffers (Bidirectional, Input)
Pullup Resistor - 10K Ω to 310K Ω
Pulldown Resistor - 3.5K Ω to 108.5K Ω
4
ATLV
ATLV
CMOS Input Interface Characteristics
Interface
Logic High
0.90 V
Logic Low
0.1 V
Switchpoint
V /2 Typical
DD
CMOS
DD
DD
Absolute Maximum Ratings*
Operating Temperature .......................-40°C to +85°C
Storage Temperature ........................-65°C to +150°C
Voltage on Any Pin
*NOTICE: Stresses beyond those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
ratingonlyandfunctionaloperationofthedeviceattheseoranyother
conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
1
with Respect to Ground ....................-2.0 V to +5.5 V
Notes:
1. Minimum voltage is -0.6 V dc which may undershoot to -2.0 V
for pulses of less than 20 ns. Maximum output pin voltage is
Maximum Operating Voltage...............................5.5 V
V
+ 0.75V dc which may overshoot to +7.0 V for pulses of less
DD
than 20 ns.
1.5 Volt DC Characteristics
Applicable over recommended operating range from T = -40°C to +85°C, V
= 1.0 V to 3.0 V (unless otherwise noted)
DD
a
Symbol
Parameter
Test Condition
V =V , V =1.8 V
Min
Typ
Max
Units
-5
-5
I
IH
Input Leakage High
1 x 10
10
µA
IN
DD
DD
I
IL
Input Leakage Low
(no pull-up)
V =V , V =1.8 V
-10
-10
-1 x 10
µA
IN
SS
DD
-5
I
Output Leakage (no pull-up)
Output Short Circuit Current
V =V or V , V =3.6 V
1 x 10
10
µA
OZ
IN
DD
SS
DD
I
V
V
=1.8 V, V
=1.8 V, V
=V
=V
5
-60
25
-25
60
-5
mA
mA
OS
DD
DD
OUT
OUT
DD
SS
(2)
(3 x Buffer)
V
CMOS Input Low Voltage
0.2 x V
V
IL
DD
DD
V
CMOS Input High Voltage
CMOS Switching Threshold
Output Low Voltage
0.8 x V
V
V
V
IH
DD
V
V
=1.5 V, 25°C
0.75
T
DD
V
I
=as rated
OL
0.2 x V
OL
Output buffer has
V
=1.5 V
DD
12 stages of drive capability
with 0.5 mA I per stage.
OL
V
Output High Voltage
Output buffer has
I
V
=as rated
0.8 x V
DD
V
OH
OH
=1.5 V
DD
12 stages of drive capability
with -0.5 mA I
per stage.
OH
I
Static Current
Input Leakage Low
(no pull-up)
1.0 V
3.0 V
< 75
< 1.0
nA
µA
DD
Note: 2. This is the specification for the 3 x Output Buffer. Output short circuit current for other outputs will scale accordingly. Not more
than one output shorted at a time, for a maximum of one second, is allowed.
5
AC Characteristics
Delay vs V
Delay vs Fanout
DD
2
4
3.5
3
1.5
1
2.5
2
1.5
1
0.5
0
0.5
0
2
4
6
8
16
1.2
1.5
2.0
Volts
2.5
3.0
Fanout
Volts V
1.5
NAND2 - 2 input NAND
Temp = 25°C
FO = 2
DD
NAND2 - 2 input NAND
Temp = 25°C
Delay vs Temperature
Current Drain vs Voltage
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2
1.5
1
0.5
0
0.5 1.0 1.5 2.0 2.5 3.0
(Volts)
-30
0
25
50
V
Temperature (°C)
DD
Volts V
Temp = 25°C
1.5
DD
NAND2 - 2 input NAND
FO = 2
6
ATLV
ATLV
I/O Buffer DC Characteristics
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
C
Capacitance Input Buffer (Die)
Capacitance Output Buffer (Die)
Capacitance Bi-Directional
1.5 V
1.5 V
1.5 V
2.4
5.6
6.6
pF
pF
pF
IN
C
OUT
C
I/O
I/O Buffers
• Programmable output drive
By following a set of design rules, Test Compiler can
automatically insert the scan cells and generate test vectors
providing greater than 95% fault coverage. This is the
easiest andleastexpensivemethodfordesigningtestability
into a gate array design.
0.5 to 6 mA I , -4.5 to -6 mA I for 1.5 V)
• 3000 volts ESD protection
OL
OH
The ATLV series input/output ring contains the I/O buffer
circuitry capable of sourcing and sinking currents up to 6
mA, and responds to CMOS logic levels. I/O locations
on this ring can accommodate bidirectional cells.
Advanced Packaging
Atmel supports a wide variety of standard packages for
the ATLV series, but also offers its ATLV series gate
arrays in packages that are custom designed to maintain
the performance obtained in the silicon. All of Atmel's
standard packages have been characterized for thermal and
electrical performance.
Design for Testability
Atmel supports a full range of Design-for-Test improve-
ment techniques which reduce design and prototype debug
time, production test time, and board & system test time.
These techniques can also improve system level test and
diagnostic capability.
When a standard package can’t meet a customer's needs,
Atmel's package design center can develop a package to
precisely fit the application. The company has delivered
custom-designed packages in a wide variety of
configurations, including Tape Automated Bonding (TAB)
packages. Atmel's domestic packaging facility
manufactures commercial, industrial and Class B.
The ATLV arrays support the Joint Test Action Group
(JTAG) boundary scan architecture. The required soft and
hardmacrostoimplementIEEE1149.1compliantarchitec-
ture are available in our macro cell library. Use of JTAG
allows for scan testing with only 4-5 additional pins re-
quired.
Atmel can also provide automatic high fault coverage test
pattern generation (ATPG) via Synopsys Test Compiler.
Packaging Options
Package Type
Pin Count
PQFP
TQFP
PLCC
CPGA
CQFP
BGA
44, 52, 64, 80, 100, 120, 128, 132, 144, 160, 184, 208, 240, 304
44, 48, 52, 64, 80, 100, 120, 128, 144, 160, 176, 216
20, 28, 32, 44, 52, 68, 84
64, 68, 84, 100, 124, 144, 155, 180, 223, 224, 299, 391
64, 68, 84, 100, 120, 132, 144, 160, 224, 340
121, 169, 225
Cadence, Mentor, Synopsys, Verilog-XL, Viewlogic, and Xilinx may be registered trademarks of others.
7
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