ATFS40-CC [ATMEL]
Support Device; 支持器件
| 型号： | ATFS40-CC |
| 厂家： | 
ATMEL |
| 描述： | Support Device |
| 文件： | 总14页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Designed to Store Configurator Programs for Field Programmable System Level
Integrated Circuits (FPSLICs)
• In-System Programmable (ISP) via 2-wire Bus
• Spare Memory Available for System Parameters Storage
• Low-power CMOS EEPROM Process
• Available in 6 mm x 6 mm x 1 mm 8-lead LAP Package (Pin Compatible Across Product
Family)
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Available in 3.3V 10% LV
• Low-power Standby Mode
• High-reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for
Commercial Parts (at 70°C)
Support Device
ATFS05
ATFS10
ATFS40
Description
The FPSLIC Support Devices provide an easy-to-use, cost-effective configuration
memory for programming Field Programmable System Level Integrated Circuits by
using a simple serial-access procedure to configure one or more FPSLIC devices.
See Table 1 for a list of supported FPSLIC devices.
The FPSLIC Support Device can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Advance
Table 1. ATFS FPSLIC Support Devices
Information
FPSLIC Device
AT94K05
FPSLIC Support Device Configuration Data
Spare Memory
35624 Bits
ATFS05
ATFS10
ATFS40
226520 Bits
430488 Bits
815382 Bits
AT94K10
93800 Bits
AT94K40
233194 Bits
Pin Configurations
8-lead LAP
DATA 1
CLK 2
8 VCC
7 SER_EN
6 CEO (A2)
5 GND
RESET/OE 3
CE 4
Rev. 3017C–FPSLI–07/02
Block Diagram
SER_EN
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
ROW
ADDRESS
COUNTER
EEPROM
CELL
MATRIX
ROW
DECODER
BIT
COUNTER
COLUMN
DECODER
POWER ON
RESET
TC
CLK
RESET/OE
CE
CEO(A2)
DATA
Device Description
The control signals for the FPSLIC Support Device (CE, RESET/OE and CCLK) inter-
face directly with the FPSLIC control signals. All FPSLIC devices can control the entire
configuration process and retrieve data from the FPSLIC Support Device without requir-
ing an external intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and
enable the address counter. When RESET/OE is driven Low, the configuration
EEPROM resets its address counter and tri-states its DATA pin. The CE pin also con-
trols the output of the FPSLIC Support Device. If CE is held High after the RESET/OE
reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is
subsequently driven High, the counter and the DATA output pin are enabled. When
RESET/OE is driven Low again, the address counter is reset and the DATA output pin is
tri-stated, regardless of the state of CE.
When the FPSLIC Support Device has driven out all of its data and CEO is driven Low,
the device tri-states the DATA pin to avoid contention with other FPSLIC Support
Devices. Upon power-up, the address counter is automatically reset.
2
ATFS05/10/40
3017C–FPSLI–07/02
ATFS05/10/40
Pin Description
8 LAP
Pin
Name
DATA
I/O
Description
1
I/O
Tri-state DATA output for configuration. Open-collector bi-directional pin for programming.
Clock input. Used to increment the internal address and bit counter for reading and programming.
2
CLK
I
I
3
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver.
4
CE
I
Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the
address counter and enables the data output driver. A High level on CE disables both the
address and bit counters and forces the device into a low-power standby mode. Note that this
pin will not enable/disable the device in the 2-wire Serial Programming mode ( SER_EN Low).
5
6
7
GND
A2
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
I
I
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
SER_EN
VCC
Serial enable must be held High during FPSLIC loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to VCC
.
8
+3.3V power supply pin
3
3017C–FPSLI–07/02
FPSLIC Master Serial The I/O and logic functions of the FPSLIC devices are established by a configuration
program. The program is loaded either automatically upon power-up, or on command,
Mode Summary
depending on the state of the mode pins. In Master Mode, the FPSLIC automatically
loads the configuration program from an external memory. The FPSLIC Support Device
has been designed for compatibility with the Master Mode.
Control of
Configuration
Most connections between the FPSLIC device and the FPSLIC Support Device are sim-
ple and self-explanatory:
•
•
The DATA output of the FPSLIC Support Device drives DIN of the FPSLIC devices.
The master FPSLIC CCLK output drives the CLK input of the FPSLIC Support
Device.
•
SER_EN must be connected to VCC (except during ISP).
Programming Mode
Standby Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial bus. The programming is done at VCC supply only.
Programming super voltages are generated inside the chip.
The FPSLIC Support Device enters a low-power standby mode whenever CE is
asserted High. In this mode, the ATFS05 consumes less than 50 µA of current at 3.3V.
The output remains in a high-impedance state regardless of the state of the OE input.
4
ATFS05/10/40
3017C–FPSLI–07/02
ATFS05/10/40
Example Circuits
Figure 1. FPSLIC Support Device for Programming FPSLIC Devices
VCC
AT94K
FPSLIC Support Device
DATA
CLK
SER_EN
RESET
DATA0
CCLK
CON
RESET
CE
RESET/OE
M2
M1
M0
INIT
GND
The FPSLIC’s bi-directional CON pin drives the CE input of the FPSLIC Support Device, while the RESET/OE input is
driven by the FPSLIC’s bi-directional INIT pin. This connection works under all normal circumstances, even when the user
aborts the configuration before CON has gone High. A Low level on the RESET/OE input, during FPSLIC reset, clears the
FPSLIC Support Device’s internal address pointer so that the reconfiguration starts at the beginning.
The spare memory can be accessed by in-system programming the ATFS through a two-wire serial interface built in the
FPSLIC device. For more information, refer to the “C Code for Interfacing the FPSLIC AVR Core to AT17 Series Configura-
tion Memories” application note, available on the Atmel web site (www.atmel.com).
Figure 2. In-System Programming of FPSLIC Support Devices
VCC VCC
4.7 k
4.7 k
2
DATA 1
VCC
4
CLK 3
6
5
7
9
8
10
GND
FPSLIC Support Device
AT94K
SER_EN
DATA0
CCLK
CON
SER_EN
RESET
DATA
CLK
RESET
CE
INIT
M2
M1
M0
RESET/OE
GND
5
3017C–FPSLI–07/02
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground ..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
Operating Conditions
ATFS05/10/40
Symbol
Description
Min
Max
Units
Commercial
Supply voltage relative to GND
3.0
3.6
V
-0°C to +70°C
VCC
Industrial
Supply voltage relative to GND
3.0
3.6
V
-40°C to +85°C
6
ATFS05/10/40
3017C–FPSLI–07/02
ATFS05/10/40
DC Characteristics – ATFS05
VCC = 3.3V 10%
Symbol
VIH
Description
Min
2.0
0
Max
VCC
0.8
Units
V
High-level Input Voltage
VIL
Low-level Input Voltage
V
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -2.5 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +3 mA)
Supply Current, Active Mode
2.4
V
Commercial
Industrial
0.4
V
2.4
-10
V
0.4
5
V
mA
µA
µA
µA
Input or Output Leakage Current (VIN = VCC or GND)
10
50
100
Commercial
Industrial
ICCS
Supply Current, Standby Mode
DC Characteristics – ATFS10/40
VCC = 3.3V 10%
Symbol
VIH
Description
Min
2.0
0.0
2.4
Max
Units
V
High-level Input Voltage
VCC
0.8
VIL
Low-level Input Voltage
V
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -2.5 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +3 mA)
Supply Current, Active Mode
V
Commercial
Industrial
0.4
V
2.4
-10
V
0.4
5
V
mA
µA
µA
µA
Input or Output Leakage Current (VIN = VCC or GND)
10
Commercial
Industrial
100
100
ICCS
Supply Current, Standby Mode
7
3017C–FPSLI–07/02
AC Characteristics
CE
TSCE
THCE
TSCE
RESET/OE
CLK
THOE
TLC
THC
TOH
TOE
TCAC
TDF
TCE
DATA
TOH
AC Characteristics When Cascading
RESET/OE
CE
CLK
T
CDF
LAST BIT
FIRST BIT
DATA
CEO
T
T
OOE
T
OCE
OCK
T
OCE
8
ATFS05/10/40
3017C–FPSLI–07/02
ATFS05/10/40
AC Characteristics for ATFS05
VCC = 3.3V 10%
Commercial
Industrial
Symbol
Description
Min
Max
Min
Max
55
Units
ns
(1)
TOE
OE to Data Delay
50
60
75
(1)
TCE
CE to Data Delay
60
ns
(1)
TCAC
CLK to Data Delay
80
ns
TOH
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
0
0
ns
(2)
TDF
55
55
ns
TLC
25
25
35
0
25
25
60
0
ns
THC
CLK High Time
ns
TSCE
THCE
THOE
FMAX
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time from CLK (to guarantee proper counting)
OE High Time (guarantees counter is reset)
Maximum Input Clock Frequency
ns
ns
25
10
25
10
ns
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
AC Characteristics for ATFS05 when Cascading
VCC = 3.3V 10%
Commercial
Industrial
Symbol
Description
Min
Max
60
Min
Max
60
Units
ns
(1)
TCDF
CLK to Data Float Delay
Maximum Input Clock Frequency
FMAX
8
8
MHz
Note:
1. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
9
3017C–FPSLI–07/02
AC Characteristics for ATFS10/40
VCC = 3.3V 10%
Commercial
Industrial
Symbol Description
Min
Max
Min
Max
Units
ns
(1)
TOE
TCE
OE to Data Delay
50
55
55
55
60
60
(1)
(1)
CE to Data Delay
ns
TCAC
TOH
CLK to Data Delay
ns
Data Hold From CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
0
0
ns
(2)
TDF
50
50
ns
TLC
25
25
30
0
25
25
35
0
ns
THC
TSCE
THCE
CLK High Time
ns
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time from CLK (to guarantee proper counting)
OE High Time (guarantees counter is reset)
MAX Input Clock Frequency
ns
ns
THOE
FMAX
25
15
25
10
ns
MHz
Notes: 1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
AC Characteristics for ATFS10/40 when Cascading
VCC = 3.3V 10%
Commercial
Industrial
Max
50
Symbol
Description
Min
Max
50
Min
Units
ns
(1)
TCDF
CLK to Data Float Delay
MAX Input Clock Frequency
FMAX
12.5
10
MHz
Note:
1. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
10
ATFS05/10/40
3017C–FPSLI–07/02
ATFS05/10/40
Thermal Resistance Coefficients(1)
θJA [°C/W]
Device
Package Type
θ
JC [°C/W]
Airflow = 0 ft/min
ATFS05
ATFS10/40
Leadless Array Package (LAP)
Leadless Array Package (LAP)
8CN4
8CN4
45
45
115.71
135.71
Note:
1. For more information refer to the “Thermal Characteristics of Atmel’s Packages” application note, available on the Atmel web
site.
11
3017C–FPSLI–07/02
Ordering Information
Ordering Code
Package
Operation Range
ATFS05-CC
ATFS10-CC
ATFS40-CC
8CN4
8CN4
8CN4
Commercial
(0°C to 70°C)
ATFS05-CI
ATFS10-CI
ATFS40-CI
8CN4
8CN4
8CN4
Industrial
(-40°C to 85°C)
Package Type
8CN4
8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP)
12
ATFS05/10/40
3017C–FPSLI–07/02
ATFS05/10/40
Packaging Information
8CN4 – LAP
Marked Pin1 Indentifier
E
A
D
A1
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
7
1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
2
3
MIN
0.94
0.30
0.45
5.89
4.89
MAX
1.14
0.38
0.55
6.09
6.09
NOM
1.04
NOTE
SYMBOL
A
6
5
A1
b
0.34
b
0.50
1
4
D
5.99
E
5.99
e1
L
e
1.27 BSC
1.10 REF
1.00
e1
L
Bottom View
0.95
1.25
1.05
1.35
1
1
L1
1.30
Note: 1. Metal Pad Dimensions.
11/14/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP)
A
8CN4
R
13
3017C–FPSLI–07/02
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FAQ
Available on web site
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3017C–FPSLI–07/02
xM
Other terms and product names may be the trademarks of others.
相关型号：
ATFS40CC
1865552 X 1 CONFIGURATION MEMORY, DSO8, 6 X 6 MM, 1.04 MM HEIGHT, 1.27 MM PITCH, LAP-8
ATMEL
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