ATF20V8B-7PC [ATMEL]
High- Performance EE PLD; 高性能EE PLD
| 型号： | ATF20V8B-7PC |
| 厂家： | 
ATMEL |
| 描述： | High- Performance EE PLD |
| 文件： | 总17页 (文件大小：761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Industry Standard Architecture
– Emulates Many 24-Pin PALs®
– Low Cost Easy-to-Use Software Tools
• High-Speed Electrically Erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-Pin Delay
• Several Power Saving Options
Device
ICC, Stand-By
50 mA
ICC, Active
55 mA
ATF20V8B
ATF20V8BQ
ATF20V8BQL
High-
35 mA
40 mA
Performance
EE PLD
5 mA
20 mA
• CMOS and TTL Compatible Inputs and Outputs
• Input and I/O Pull-Up Resistors
• Advanced Flash Technology
– Reprogrammable
– 100% Tested
• High Reliability CMOS Process
– 20 Year Data Retention
ATF20V8B
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Commercial and Industrial Temperature Ranges
• Dual-in-Line and Surface Mount Packages in Standard Pinouts
Block Diagram
TSSOP Top View
Pin Configurations
CLK/IN
IN
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
IN
2
Pin Name Function
IN
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
IN
4
IN
5
CLK
I
Clock
IN
6
IN
7
IN
8
Logic Inputs
IN
9
IN
10
11
12
IN
I/O
OE
*
Bidirectional Buffers
Output Enable
No Internal Connection
+5V Supply
GND
OE/IN
DIP/SOIC
PLCC Top View
VCC
Rev. 0407E–05/98
Description
The ATF20V8B is a high performance CMOS (Electrically
Erasable) Programmable Logic Device (PLD) which utilizes
Atmel’s proven electrically erasable Flash memory technol-
ogy. Speeds down to 7.5 ns and power dissipation as low
as 10 mA are offered. All speed ranges are specified over
the full 5V ± 10% range for industrial temperature ranges,
and 5V ± 5% for commercial temperature ranges.
these options significantly reduces total system power and
enhances system reliability.
The ATF20V8Bs incorporate a superset of the generic
architectures, which allows direct replacement of the 20R8
family and most 24-pin combinatorial PLDs. Eight outputs
are each allocated eight product terms. Three different
modes of operation, configured automatically with soft-
ware, allow highly complex logic functions to be realized.
Several low power options allow selection of the best solu-
tion for various types of power-limited applications. Each of
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.Maxi-
mum output pin voltage is VCC + 0.75V DC which
may overshoot to 7.0V for pulses of less than 20
ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
DC and AC Operating Conditions
Commercial
0°C - 70°C
5V ± 5%
Industrial
-40°C - 85°C
5V ± 10%
Operating Temperature (Case)
VCC Power Supply
ATF20V8B
2
ATF20V8B
DC Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
Input or I/O Low
Leakage Current
IIL
0 ≤ VIN ≤ VIL(MAX)
-35
-100
µA
Input or I/O High
Leakage Current
IIH
3.5 ≤ VIN ≤ VCC
10
µA
Com.
Ind.
60
60
60
60
35
5
90
100
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
B-7, -10
Com.
Ind.
VCC = MAX,
VIN = MAX,
Outputs Open
B-15, -25
BQ-10
Power Supply
ICC
90
Current, Standby
Com.
Com.
Ind.
55
10
BQL-15, -25
5
15
Com.
Ind.
80
80
60
60
40
20
20
110
125
90
B-7, -10
VCC = MAX,
Outputs Open,
f = 15 MHz
Clocked Power
Supply Current
ICC2
Com.
Ind.
B-15, -25
BQ-10
105
55
Com.
Com.
Ind.
35
BQL-15, -25
40
Output Short
IOS(1)
VOUT = 0.5V
-130
mA
Circuit Current
VIL
VIH
Input Low Voltage
Input High Voltage
-0.5
2.0
0.8
V
V
VCC + 0.75
Com.,
Ind.
IOL = 24 mA
IOL = 16 mA
IOH = -4.0 mA
0.5
0.5
V
V
V
VIN = VIH or VIL,
VCC = MIN
VOL
Output Low Voltage
VIN = VIH or VIL,
VCC = MIN
VOH
Output High Voltage
2.4
Note:
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
3
AC Waveforms(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics(1)
-7
-10
-15
-25
Symbol
Parameter
Min
Max
7.5
7
Min
Max
Min
Max
Min
Max
Units
ns
8 outputs switching
1 output switching
3
3
10
3
15
3
25
Input or Feedback to
Non-Registered Output
tPD
ns
tCF
tCO
Clock to Feedback
Clock to Output
3
6
7
8
10
12
ns
2
5
5
2
2
10
2
ns
Input or Feedback
Setup Time
tS
7.5
12
15
ns
tH
tP
Hold Time
0
8
4
0
12
6
0
16
8
0
ns
ns
Clock Period
24
12
tW
Clock Width
ns
External Feedback 1/(tS + tCO
)
100
125
125
68
74
83
45
50
62
37
40
41
MHz
MHz
MHz
FMAX
Internal Feedback 1/(tS + tCF
No Feedback 1/(tP)
)
Input to Output
Enable — Product Term
tEA
tER
3
2
9
9
3
2
10
10
3
2
15
15
3
2
20
20
ns
ns
Input to Output
Disable —Product Term
tPZX
tPXZ
OE pin to Output Enable
OE pin to Output Disable
2
6
6
2
10
10
2
15
15
2
20
20
ns
ns
1.5
1.5
1.5
1.5
Note:
1. See ordering information for valid part numbers and speed grades.
ATF20V8B
4
ATF20V8B
Input Test Waveforms and
Measurement Levels
Output Test Loads
Commercial
tR, tF < 5 ns (10% to 90%)
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
Max
8
Units
pF
Conditions
VIN = 0V
CIN
COUT
Note:
5
6
8
pF
VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The registers in the ATF20V8Bs are designed to reset dur-
ing power up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times
must be met before driving the clock pin high, and
3. The clock must remain stable during tPR
.
Parameter Description
Typ
600 1,000
3.8 4.5
Max
Units
ns
tPR
Power-Up Reset Time
Power-Up Reset Voltage
Preload of Registered Outputs
VRST
V
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF20V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. For further information, see the Configurable
Logic Databook, section titled, “CMOS PLD Programming
Hardware and Software Support.”
5
Input and I/O Pull-Ups
All ATF20V8B family members have internal input and I/O
pull-up resistors. Therefore, whenever inputs or I/Os are
not being driven externally, they will float to VCC. This
ensures that all logic array inputs are at known states.
These are relatively weak active pull-ups that can easily be
overdriven by TTL-compatible drivers (see input and I/O
diagrams below).
Input Diagram
I/O Diagram
Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the
ATF20V8B architecture. Eight configurable macrocells can
be configured as a registered output, combinatorial I/O,
combinatorial output, or dedicated input.
subsets can be found in each of the configuration modes
described in the following pages. The user can download
the listed subset device JEDEC programming file to the
PLD programmer, and the ATF20V8B can be configured to
act like the chosen device. Check with your programmer
manufacturer for this capability.
The ATF20V8B can be configured in one of three different
modes. Each mode makes the ATF20V8B look like a dif-
ferent device. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The deter-
mining factors would be the usage of register versus com-
binatorial outputs and dedicated outputs versus outputs
with output enable control.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A Security
Fuse, when programmed, protects the content of the
ATF20V8B. Eight bytes (64 fuses) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision, or date. The User Signature
is accessible regardless of the state of the Security Fuse.
The ATF20V8B universal architecture can be programmed
to emulate many 24-pin PAL devices. These architectural
ATF20V8B
6
ATF20V8B
Compiler Mode Selection
Registered
Complex
P20V8C
Simple
Auto Select
ABEL, Atmel-ABEL
CUPL
P20V8R
P20V8
P20V8
G20V8MS
GAL20V8_R(1)
“Registered”
P20V8
G20V8MA
GAL20V8_C7(1)
“Complex”
P20V8
G20V8
G20V8A
GAL20V8
GAL20V8
P20V8
LOG/iC
GAL20V8_C8(1)
“Simple”
P20V8
OrCAD-PLD
PLDesigner
Tango-PLD
G20V8
G20V8
G20V8
G20V8
Note:
1. Only applicable for version 3.4 or lower.
ATF20V8B Registered Mode
PAL Device Emulation / PAL Replacement
The registered mode is used if one or more registers are
required. Each macrocell can be configured as either a reg-
istered or combinatorial output or I/O, or as an input. For a
registered output or I/O, the output is enabled by the OE
pin, and the register is clocked by the CLK pin. Eight prod-
uct terms are allocated to the sum term. For a combinato-
rial output or I/O, the output enable is controlled by a
product term, and seven product terms are allocated to the
sum term. When the macrocell is configured as an input,
the output enable is permanently disabled.
Any register usage will make the compiler select this mode.
The following registered devices can be emulated using
this mode:
20R8 20RP8
20R6 20RP6
20R4 20RP4
Registered Mode Operation
7
Registered Mode Logic Diagram
ATF20V8B
8
ATF20V8B
ATF20V8B Complex Mode
PAL Device Emulation/PAL Replacement
In the Complex Mode, combinatorial output and I/O func-
tions are possible. Pins 1 and 11 are regular inputs to the
array. Pins 13 through 18 have pin feedback paths back to
the AND-array, which makes full I/O capability possible.
Pins 12 and 19 (outermost macrocells) are outputs only.
They do not have input capability. In this mode, each mac-
rocell has seven product terms going to the sum term and
one product term enabling the output.
Combinatorial applications with an OE requirement will
make the compiler select this mode. The following devices
can be emulated using this mode:
20L8
20H8
20P8
Complex Mode Operation
ATF20V8B Simple Mode
PAL Device Emulation / PAL Replacement
In the Simple Mode, 8 product terms are allocated to the
sum term. Pins 15 and 16 (center macrocells) are perma-
nently configured as combinatorial outputs. Other macro-
cells can be either inputs or combinatorial outputs with pin
feedback to the AND-array. Pins 1 and 11 are regular
inputs.
The compiler selects this mode when all outputs are combi-
natorial without OE control. The following simple PALs can
be emulated using this mode:
14L8 14H8 14P8
16L6 18H6 16P6
18L4 18H4 18P4
20L2 20H2 20P2
Simple Mode Option
9
Complex Mode Logic Diagram
ATF20V8B
10
ATF20V8B
Simple Mode Logic Diagram
11
ATF20V8B
12
ATF20V8B
13
ATF20V8B
14
ATF20V8B
Ordering Information
tPD (ns)
tS (ns)
tCO (ns)
Ordering Code
Package
Operation Range
7.5
5
5
ATF20V8B-7JC
ATF20V8B-7PC
ATF20V8B-7SC
ATF20V8B-7XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
10
15
25
7.5
12
15
7
ATF20V8B-10JC
ATF20V8B-10PC
ATF20V8B-10SC
ATF20V8B-10XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF20V8B-10JI
ATF20V8B-10PI
ATF20V8B-10SI
ATF20V8B-10XI
28J
Industrial
24P3
24S
24X
(-40°C to 85°C)
10
ATF20V8B-15JC
ATF20V8B-15PC
ATF20V8B-15SC
ATF20V8B-15XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF20V8B-15JI
ATF20V8B-15PI
ATF20V8B-15SI
ATF20V8B-15XI
28J
Industrial
24P3
24S
24X
(-40°C to 85°C)
12
ATF20V8B-25JC
ATF20V8B-25PC
ATF20V8B-25SC
ATF20V8B-25XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF20V8B-25JI
ATF20V8B-25PI
ATF20V8B-25SI
ATF20V8B-25XI
28J
Industrial
24P3
24S
24X
(-40°C to 85°C)
(continued)
Package Type
28J
28-Lead, Plastic J-Leaded Chip Carrier (PLCC)
24P3
24S
24-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
24X
15
Ordering Information
tPD (ns)
tS (ns)
tCO (ns)
Ordering Code
Package
Operation Range
10
7.5
7
ATF20V8BQ-10JC
ATF20V8BQ-10PC
ATF20V8BQ-10XC
28J
Commercial
24P3
24X
(0°C to 70°C)
15
25
12
15
10
12
ATF20V8BQL-15JC
ATF20V8BQL-15PC
ATF20V8BQL-15SC
ATF20V8BQL-15XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF20V8BQL-25JC
ATF20V8BQL-25PC
ATF20V8BQL-25SC
ATF20V8BQL-25XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF20V8BQL-25JI
ATF20V8BQL-25PI
ATF20V8BQL-25SI
ATF20V8BQL-25XI
28J
Industrial
24P3
24S
24X
(-40°C to 85°C)
Package Type
28J
28-Lead, Plastic J-Leaded Chip Carrier (PLCC)
24P3
24S
24-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
24X
ATF20V8B
16
ATF20V8B
Packaging Information
28J, 28-Lead, Plastic J-Leaded Chip Carrier (PLCC)
24P3, 24-Lead, 0.300" Wide, Plastic Dual Inline
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AB
Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 AF
.045(1.14) X 30° - 45°
1.27(32.3)
1.25(31.7)
.045(1.14) X 45° PIN NO. 1
IDENTIFY
.012(.305)
.008(.203)
PIN
1
.430(10.9)
.390(9.91)
.021(.533)
.013(.330)
.266(6.76)
.250(6.35)
SQ
.456(11.6)
.450(11.4)
SQ
.032(.813)
.026(.660)
.495(12.6)
.485(12.3)
.090(2.29)
SQ
MAX
1.100(27.94) REF
.200(5.06)
MAX
.005(.127)
MIN
.050(1.27) TYP
.043(1.09)
.300(7.62) REF SQ
.020(.508)
.120(3.05)
.090(2.29)
SEATING
PLANE
.180(4.57)
.165(4.19)
.070(1.78)
.020(.508)
.023(.584)
.014(.356)
.151(3.84)
.125(3.18)
.065(1.65)
.040(1.02)
.110(2.79)
.090(2.29)
.022(.559) X 45° MAX (3X)
.325(8.26)
.300(7.62)
0
15
REF
.012(.305)
.008(.203)
.400(10.2) MAX
24S, 24-Lead, 0.300" Wide, Plastic Gull Wing Small
Outline (SOIC)
24X, 24-Lead, 4.4 mm Wide, Plastic Thin Shrink
Small Outline (TSSOP)
Dimensions in Inches and (Millimeters)
Dimensions in Millimeters and (Inches)
.020(.508)
.013(.330)
.299(7.60) .420(10.7)
.291(7.39) .393(9.98)
PIN 1 ID
.050(1.27) BSC
.616(15.6)
.105(2.67)
.598(15.2)
.092(2.34)
.012(.305)
.003(.076)
.013(.330)
.009(.229)
.050(1.27)
0
REF
.015(.381)
8
17
相关型号：
ATF20V8B/BQ/BQL
ATF20V8B/BQ/BQL [Updated 4/01. 18 Pages] 300 gate electrically erasable PLD. 24 pins
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