ATF16V8CZ-15SL [ATMEL]
Flash PLD, 15ns, CMOS, PDSO20, 0.300 INCH, PLASTIC, MS-013, SOIC-20;
| 型号： | ATF16V8CZ-15SL |
| 厂家： | 
ATMEL |
| 描述： | Flash PLD, 15ns, CMOS, PDSO20, 0.300 INCH, PLASTIC, MS-013, SOIC-20 光电二极管 |
| 文件： | 总26页 (文件大小：585K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Industry-standard Architecture
– Emulates Many 20-pin PALs
– Low-cost Easy-to-use Software Tools
• High-speed Electrically-erasable Programmable Logic Devices
– 12 ns Maximum Pin-to-pin Delay
• Low-power - 5 µA (Typ) Standby Current
• CMOS and TTL Compatible Inputs and Outputs
– Input and I/O Pin Keeper Circuits
• Advanced Flash Technology
High-
– Reprogrammable
performance
EE PLD
– 100% Tested
• High-reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
ATF16V8CZ
– 200 mA Latchup Immunity
• Commercial and Industrial Temperature Ranges
• Dual-in-line and Surface Mount Packages in Standard Pinouts
• PCI-compliant
• Green (Pb/Halide-free/RoHS Compliant) Package Options Available
1. Description
The ATF16V8CZ is a high-performance EECMOS programmable logic device that uti-
lizes Atmel’s proven electrically-erasable Flash memory technology. Speeds down to
12 ns and a 5 µA (Typ) edge-sensing power-down mode are offered. All speed ranges
are specified over the full 5V ±10% range for industrial temperature ranges; 5V ±5%
for commercial range 5-volt devices.
The ATF16V8CZ incorporates a superset of the generic architectures, which allows
direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight out-
puts are each allocated eight product terms. Three different modes of operation,
configured automatically with software, allow highly complex logic functions to be
realized.
The ATF16V8CZ can significantly reduce total system power, thereby enhancing sys-
tem reliability and reducing power supply costs. When all the inputs and internal
nodes are not switching, supply current drops to less than 5 µA typically. This auto-
matic power-down feature (or sleep mode) allows for power savings in slow clock
systems and asynchronous applications. Also, the pin-keeper circuits eliminate the
need for internal pull-up resistors along with their attendant power consumption.
0453H–PLD–7/05
Figure 1-1. Block Diagram
2. Pin Configuration and Pinouts
Table 2-1.
Pinouts - All Pinouts Top View
Pin Name
Function
CLK
I
Clock
Logic Inputs
Bi-directional Buffers
Output Enable
+5V Supply
I/O
OE
VCC
Figure 2-1. TSSOP
I/CLK
I1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I2
I/O
I3
I/O
I4
I/O
I5
I/O
I6
I/O
I7
I/O
I8
I/O
GND
I9/OE
Figure 2-2. DIP/SOIC
I/CLK
1
2
3
4
5
6
7
8
9
20 VCC
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I/O
12 I/O
I1
I2
I3
I4
I5
I6
I7
I8
GND 10
11 I9/OE
2
ATF16V8CZ
0453H–PLD–7/05
ATF16V8CZ
Figure 2-3. PLCC
I3
I4
I5
I6
I7
4
5
6
7
8
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
3. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
4. DC and AC Operating Conditions
Commercial
Industrial
-40°C - 85°C
5V ±10%
Operating Temperature (Ambient)
VCC Power Supply
0°C - 70°C
5V ±5%
4.1
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
-10
10
Units
µA
IIL
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
0 ≤ VIN ≤ VIL(Max)
3.5 ≤ VIN ≤ VCC
IIH
µA
Com
Ind.
95
mA
mA
µA
15 MHz, VCC = Max,
VIN = 0, VCC, Outputs Open
ICC1
Power Supply Current
105
Com.
Ind
5
5
Power Supply Current,
Standby Mode
0 MHz, VCC = Max,
VIN = 0, VCC, Outputs Open
(1)
ICC
µA
V
OUT = 0.5V;
IOS
Output Short Circuit Current
-150
mA
VCC= 5V; TA = 25°C
VIL
VIH
Input Low Voltage
Input High Voltage
Min < VCC < Max
-0.5
2.0
0.8
V
V
VCC+1
VCC = Min, All Outputs
IOL = -16 mA
VOL
Output Low Voltage
Com, Ind.
0.5
V
3
0453H–PLD–7/05
4.1
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
VCC = Min
IOL = -3.2 mA
VOH
Output High Voltage
2.4
V
Com.
24
12
4
IOL
Output Low Current
Output High Current
VCC = Min
mA
mA
Ind.
IOH
VCC = Min
Com., Ind.
Note:
1. All ICC parameters measured with outputs open. Data is based on Atmel test patterns. Reading may vary with pattern.
4
ATF16V8CZ
0453H–PLD–7/05
ATF16V8CZ
4.2
AC Waveforms(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
4.3
AC Characteristics
-12
-15
Symbol Parameter
Min
Max
12
6
Min
Max
15
8
Units
ns
tPD
tCF
tCO
tS
Input or Feedback to Non-registered Output
Clock to Feedback
3
3
ns
Clock to Output
2
10
0
8
2
12
0
10
ns
Input or Feedback Setup Time
Input Hold Time
ns
tH
ns
tP
Clock Period
12
6
16
8
ns
tW
Clock Width
ns
External Feedback 1/(tS + tCO
)
55
62
83
12
15
12
12
45
50
62
15
15
15
15
MHz
MHz
MHz
ns
fMAX
Internal Feedback 1/(tS + tCF
)
No Feedback 1/(tP)
tEA
Input to Output Enable – Product Term
Input to Output Disable – Product Term
OE pin to Output Enable
3
2
3
2
tER
ns
tPZX
tPXZ
2
2
ns
OE pin to Output Disable
1.5
1.5
ns
5
0453H–PLD–7/05
4.4
Input Test Waveforms
4.4.1
Input Test Waveforms and Measurement Levels
tR, tF < 1.5 ns (10% to 90%)
4.4.2
Output Test Loads
Note:
Similar devices are tested with slightly different loads. These load differences may affect output
signals' delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible
devices.
4.4.3
Pin Capacitance
Table 4-1.
Pin Capacitance (f = 1 MHz, T = 25°C(1))
Typ
5
Max
8
Units
pF
Conditions
VIN = 0V
CIN
COUT
6
8
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%
tested.
6
ATF16V8CZ
0453H–PLD–7/05
ATF16V8CZ
4.5
Power-up Reset
The ATF16V8CZ’s registers are designed to reset during power-up. At a point delayed slightly
from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered out-
put state will always be high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how VCC actually rises in the system, the following conditions are
required:
1. The VCC rise must be monotonic, from below 0.7V,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock term high, and
3. The signals from which the clock is derived must remain stable during tPR
.
Parameter
tPR
Description
Typ
600
3.8
Max
Units
ns
Power-up Reset Time
Power-up Reset Voltage
1,000
4.5
VRST
V
4.6
Preload of Registered Outputs
The ATF16V8CZ’s registers are provided with circuitry to allow loading of each register with
either a high or a low. This feature will simplify testing since any state can be forced into the reg-
isters to control test sequencing. A JEDEC file with preload is generated when a source file with
vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automati-
cally by approved programmers.
5. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF16V8CZ fuse patterns.
Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature
remains accessible.
The security fuse should be programmed last, as its effect is immediate.
7
0453H–PLD–7/05
6. Input and I/O Pin-keeper Circuits
The ATF16V8CZ contains internal input and I/O pin-keeper circuits. These circuits allow each
ATF16V8CZ pin to hold its previous value even when it is not being driven by an external source
or by the device’s output buffer. This helps insure that all logic array inputs are at known, valid
logic levels. This reduces system power by preventing pins from floating to indeterminate levels.
By using pin-keeper circuits rather than pull-up resistors, there is no DC current required to hold
the pins in either logic state (high or low).
These pin-keeper circuits are implemented as weak feedback inverters, as shown in the Input
Diagram below. These keeper circuits can easily be overdriven by standard TTL- or CMOS-com-
patible drivers. The typical overdrive current required is 40 µA.
Figure 6-1. Input Diagram
Figure 6-2. I/O Diagram
8
ATF16V8CZ
0453H–PLD–7/05
ATF16V8CZ
7. Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the ATF16V8CZ architecture. Eight config-
urable macrocells can be configured as a registered output, combinatorial I/O, combinatorial
output, or dedicated input.
The ATF16V8CZ can be configured in one of three different modes. Each mode makes the
ATF16V8CZ look like a different device. Most PLD compilers can choose the right mode auto-
matically. The user can also force the selection by supplying the compiler with a mode selection.
The determining factors would be the usage of register versus combinatorial outputs and dedi-
cated outputs versus outputs with output enable control.
The ATF16V8CZ universal architecture can be programmed to emulate many 20-pin PAL
devices. These architectural subsets can be found in each of the configuration modes described
in the following pages. The user can download the listed subset device JEDEC programming file
to the PLD programmer, and the ATF16V8CZ can be configured to act like the chosen device.
Check with your programmer manufacturer for this capability.
Unused product terms are automatically disabled by the compiler to decrease power consump-
tion. A security fuse, when programmed, protects the content of the ATF16V8CZ. Eight bytes
(64 fuses) of User Signature are accessible to the user for purposes such as storing project
name, part number, revision, or date. The User Signature is accessible regardless of the state of
the security fuse.
Table 7-1.
Compiler Mode Selection
Registered
P16C8R
Complex
P16V8C
Simple
P16V8AS
G16V8AS
GAL16V8_C8(1)
“Simple”
Auto Select
P16V8
ABEL, Atmel-ABEL
CUPL
G16V8MS
GAL16V8_R(1)
“Registered”
P16V8R
G16V8MA
GAL16V8_C7(1)
“Complex”
P16V8C
G16V8A
GAL16V8
GAL16V8A
P16V8A
LOG/iC
OrCAD-PLD
PLDesigner
Tango-PLD
P16V8C
G16V8R
G16V8C
G16V8AS
G16V8
Notes: 1. Only applicable for version 3.4 or lower.
9
0453H–PLD–7/05
8. Macrocell Configuration
Software compilers support the three different OMC modes as different device types. These
device types are listed in the table below. Most compilers have the ability to automatically select
the device type, generally based on the register usage and output enable (OE) usage. Register
usage on the device forces the software to choose the registered mode. All combinatorial out-
puts with OE controlled by the product term will force the software to choose the complex mode.
The software will choose the simple mode only when all outputs are dedicated combinatorial
without OE control. The different device types listed in the table can be used to override the
automatic device selection by the software. For further details, refer to the compiler software
manuals.
When using compiler software to configure the device, the user must pay special attention to the
following restrictions in each mode.
In registered mode pin 1 and pin 11 are permanently configured as clock and output enable,
respectively. These pins cannot be configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin
19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have
the feedback option in this mode.
In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing
so, the two inner most pins (pins 15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
8.1
ATF16V8CZ Registered Mode
PAL Device Emulation/PAL Replacement. The registered mode is used if one or more regis-
ters are required. Each macrocell can be configured as either a registered or combinatorial
output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin,
and the register is clocked by the CLK pin. Eight product terms are allocated to the sum term.
For a combinatorial output or I/O, the output enable is controlled by a product term, and seven
product terms are allocated to the sum term. When the macrocell is configured as an input, the
output enable is permanently disabled.
Any register usage will make the compiler select this mode. The following registered devices can
be emulated using this mode:
16R8
16R6
16R4
16RP8
16RP6
16RP4
10
ATF16V8CZ
0453H–PLD–7/05
ATF16V8CZ
Figure 8-1. Registered Configuration for Registered Mode(1)(2)
Notes: 1. Pin 1 controls common CLK for the registered outputs.
Pin 11 controls common OE for the registered outputs.
Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture control bits and checks for proper pin
usage automatically.
Figure 8-2. Combinatorial Configuration for Registered Mode(1)(2)
Notes: 1. Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture control bits and checks for proper pin
usage automatically.
11
0453H–PLD–7/05
Figure 8-3. Registered Mode Logic Diagram
12
ATF16V8CZ
0453H–PLD–7/05
ATF16V8CZ
8.2
ATF16V8CZ Complex Mode
PAL Device Emulation/PAL Replacement. In the complex mode, combinatorial output and I/O
functions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin
feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19
(outermost macrocells) are outputs only. They do not have input capability. In this mode, each
macrocell has seven product terms going to the sum term and one product term enabling the
output.
Combinatorial applications with an OE requirement will make the compiler select this mode. The
following devices can be emulated using this mode:
16L8
16H8
16P8
Figure 8-4. Complex Mode Option
9. ATF16V8CZ Simple Mode
PAL Device Emulation/PAL Replacement. In the Simple Mode, 8 product terms are allocated
to the sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinato-
rial outputs. Other macrocells can be either inputs or combinatorial outputs with pin feedback to
the AND-array. Pins 1 and 11 are regular inputs.
The compiler selects this mode when all outputs are combinatorial without OE control. The fol-
lowing simple PALs can be emulated using this mode:
10L8 10H8 10P8
12L6 12H6 12P6
14L4 14H4 14P4
16L2 16H2 16P2
13
0453H–PLD–7/05
Figure 9-1. Simple Mode Option
0
1
14
ATF16V8CZ
0453H–PLD–7/05
ATF16V8CZ
Figure 9-2. Complex Mode Logic Diagram
15
0453H–PLD–7/05
Figure 9-3. Simple Mode Logic Diagram
16
ATF16V8CZ
0453H–PLD–7/05
ATF16V8CZ
9.1
Test Characterization Data
17
0453H–PLD–7/05
18
ATF16V8CZ
0453H–PLD–7/05
ATF16V8CZ
19
0453H–PLD–7/05
10. Ordering Information
10.1 Standard Package Options
tPD
tS
tCO
(ns)
(ns)
(ns)
Ordering Code
Package
Operation Range
ATF16V8CZ-12JC
ATF16V8CZ-12PC
ATF16V8CZ-12SC
ATF16V8CZ-12XC
20J
20P3
20S
Commercial
12
15
10
12
12
8
(0°C to 70°C)
20X
ATF16V8CZ-15JC
ATF16V8CZ-15PC
20J
20P3
20S
Commercial
10
10
(0°C to 70°C)
ATF16V8CZ-15SC
ATF16V8CZ-15XC
20X
ATF16V8CZ-15JI
ATF16V8CZ-15PI
20J
20P3
20S
Industrial
(-40°C to 85°C)
ATF16V8CZ-15SI
ATF16V8CZ-15XI
20X
Note:
Shaded parts are being obsoleted in Q3-05 and being replaced by Green parts.
10.2 Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade
from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%.
10.3 Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
tS
tCO
(ns)
(ns)
(ns)
Ordering Code
Package
Operation Range
ATF16V8CZ-15JU
ATF16V8CZ-15PU
ATF16V8CZ-15SU
ATF16V8CZ-15XU
20J
20P3
20S
Industrial
15
12
10
(-40°C to 85°C)
20X
Package Type
20J
20-lead, Plastic J-leaded Chip Carrier (PLCC)
20P3
20S
20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC)
20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
20X
20
ATF16V8CZ
0453H–PLD–7/05
ATF16V8CZ
11. Package Information
11.1 20J – PLCC
PIN NO. 1
1.14(0.045) X 45˚
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
2.286
0.508
9.779
8.890
9.779
8.890
7.366
0.660
0.330
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
A1
A2
D
–
–
–
–
10.033
D1
E
–
9.042 Note 2
10.033
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
D2/E2
B
–
9.042 Note 2
8.382
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
20J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
21
0453H–PLD–7/05
11.2 20P3 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
MIN
–
MAX
5.334
–
NOM
NOTE
SYMBOL
eC
A
–
–
–
–
–
–
–
–
–
–
–
eB
A1
D
0.381
24.892
7.620
6.096
0.356
1.270
2.921
0.203
–
26.924 Note 2
8.255
E
E1
B
7.112 Note 2
0.559
B1
L
1.551
Notes:
1. This package conforms to JEDEC reference MS-001, Variation AD.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
3.810
C
0.356
eB
eC
e
10.922
0.000
1.524
2.540 TYP
1/23/04
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
20P3
D
R
22
ATF16V8CZ
0453H–PLD–7/05
ATF16V8CZ
11.3 20S – SOIC
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
JEDEC Standard MS-013
0.51(0.020)
0.33(0.013)
10.65 (0.419)
10.00 (0.394)
7.60 (0.2992)
7.40 (0.2914)
PIN 1 ID
PIN 1
1.27 (0.050) BSC
13.00 (0.5118)
12.60 (0.4961)
2.65 (0.1043)
2.35 (0.0926)
0.30(0.0118)
0.10 (0.0040)
0.32 (0.0125)
0.23 (0.0091)
0º ~ 8º
1.27 (0.050)
0.40 (0.016)
10/23/03
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
20S, 20-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC)
20S
B
R
23
0453H–PLD–7/05
11.4 20X – TSSOP
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
JEDEC Standard MO-153 AC
INDEX MARK
PIN
1
6.50 (0.256)
6.25 (0.246)
4.50 (0.177)
4.30 (0.169)
6.60 (.260)
6.40 (.252)
1.20 (0.047) MAX
0.65 (.0256) BSC
0.15 (0.006)
0.05 (0.002)
SEATING
PLANE
0.30 (0.012)
0.19 (0.007)
0.20 (0.008)
0.09 (0.004)
0º ~ 8º
0.75 (0.030)
0.45 (0.018)
10/23/03
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
20X, (Formerly 20T), 20-lead, 4.4 mm Body Width,
Plastic Thin Shrink Small Outline Package (TSSOP)
20X
C
R
24
ATF16V8CZ
0453H–PLD–7/05
ATF16V8CZ
12. Revision History
12.1 0453H
1. Green Package options added in 2005.
25
0453H–PLD–7/05
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
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ATF16V8C_13
Industry-standard architecture Emulates Many 20-pin PALs Low-cost, easy to use software tools
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