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ATF16V8BQL-25SC [ATMEL]

High- Performance Flash PLD; 高性能闪存PLD
ATF16V8BQL-25SC
型号： ATF16V8BQL-25SC
厂家： ATMEL    ATMEL
描述：

High- Performance Flash PLD
高性能闪存PLD

闪存
文件： 总17页 (文件大小：639K)
中文：  中文翻译
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Features  
• Industry Standard Architecture  
– Emulates Many 20-Pin PALs®  
– Low Cost Easy-to-Use Software Tools  
• High-Speed Electrically Erasable Programmable Logic Devices  
– 7.5 ns Maximum Pin-to-Pin Delay  
• Several Power Saving Options  
Device  
ICC, Stand-By  
50 mA  
ICC, Active  
55 mA  
ATF16V8B  
ATF16V8BQ  
ATF16V8BQL  
High-  
35 mA  
40 mA  
Performance  
Flash PLD  
5 mA  
20 mA  
• CMOS and TTL Compatible Inputs and Outputs  
– Input and I/O Pull-Up Resistors  
• Advanced Flash Technology  
– Reprogrammable  
– 100% Tested  
• High Reliability CMOS Process  
– 20 Year Data Retention  
ATF16V8B  
– 100 Erase/Write Cycles  
– 2,000V ESD Protection  
– 200 mA Latchup Immunity  
• Commercial, and Industrial Temperature Ranges  
• Dual-in-Line and Surface Mount Packages in Standard Pinouts  
Block Diagram  
TSSOP Top View  
Pin Configurations  
I/CLK  
I1  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
I/O  
Pin Name  
Function  
I2  
I/O  
I3  
I/O  
CLK  
I
Clock  
I4  
I/O  
I5  
I/O  
I6  
I/O  
Logic Inputs  
Bidirectional Buffers  
Output Enable  
+5 V Supply  
I7  
I/O  
I8  
I/O  
GND  
I9/OE  
I/O  
OE  
VCC  
DIP/SOIC  
PLCC Top View  
Rev. 0364E–07/98  
Description  
The ATF16V8B is a high performance CMOS (Electrically  
Erasable) Programmable Logic Device (PLD) which utilizes  
Atmel’s proven electrically erasable Flash memory technol-  
ogy. Speeds down to 7.5 ns are offered. All speed ranges  
are specified over the full 5V ± 10% range for industrial  
temperature ranges, and 5V ± 5% for commercial tempera-  
ture ranges.  
these options significantly reduces total system power and  
enhances system reliability.  
The ATF16V8Bs incorporate a superset of the generic  
architectures, which allows direct replacement of the 16R8  
family and most 20-pin combinatorial PLDs. Eight outputs  
are each allocated eight product terms. Three different  
modes of operation, configured automatically with soft-  
ware, allow highly complex logic functions to be realized.  
Several low power options allow selection of the best solu-  
tion for various types of power-limited applications. Each of  
Absolute Maximum Ratings*  
Temperature Under Bias.................................-55oC to +125oC  
*NOTICE:  
Stresses beyond those listed under “Absolute  
Maximum Ratings” may cause permanent dam-  
age to the device. This is a stress rating only and  
functional operation of the device at these or any  
other conditions beyond those indicated in the  
operational sections of this specification is not  
implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device  
reliability.  
Storage Temperature......................................-65oC to +150oC  
Voltage on Any Pin with  
Respect to Ground .......................................-2.0 V to +7.0 V(1)  
Voltage on Input Pins  
with Respect to Ground  
During Programming...................................-2.0 V to +14.0 V(1)  
Note:  
1. Minimum voltage is -0.6V DC, which may under-  
shoot to -2.0V for pulses of less than 20 ns. Max-  
imum output pin voltage is VCC + 0.75V DC,  
which may overshoot to 7.0V for pulses of less  
than 20 ns.  
Programming Voltage with  
Respect to Ground .....................................-2.0 V to +14.0 V(1)  
DC and AC Operating Conditions  
Commercial  
0oC - 70oC  
5V ± 5%  
Industrial  
-40oC - 85oC  
5V ± 10%  
Operating Temperature (Case)  
VCC Power Supply  
ATF16V8B  
2
ATF16V8B  
DC Characteristics  
Symbol  
Parameter  
Condition  
Min  
Typ  
Max  
Units  
Input or I/O Low  
Leakage Current  
IIL  
0 ≤ VIN ≤ VIL(MAX)  
-35  
-100  
µA  
Input or I/O High  
Leakage Current  
IIH  
3.5 ≤ VIN ≤ VCC  
10  
µA  
Com.  
Ind.  
55  
55  
50  
50  
35  
5
85  
95  
75  
80  
55  
10  
15  
90  
100  
85  
95  
55  
35  
40  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
B-7, -10  
Com.  
Ind.  
VCC = MAX,  
VIN = MAX,  
Outputs Open  
B-15, -25  
BQ-10  
Power Supply  
Current, Standby  
ICC  
Com.  
Com.  
Ind.  
BQL-15, -25  
5
Com.  
Ind.  
60  
60  
55  
55  
40  
20  
20  
B-7, -10  
Com.  
Ind.  
V
CC = MAX,  
B-15, -25  
BQ-10  
Clocked Power  
Supply Current  
ICC2  
Outputs Open,  
f=15 MHz  
Com.  
Com.  
Ind.  
BQL-15, -25  
Output Short  
Circuit Current  
(1)  
IOS  
VOUT = 0.5 V  
-130  
mA  
VIL  
VIH  
Input Low Voltage  
Input High Voltage  
-0.5  
2.0  
0.8  
V
V
VCC+0.75  
VIN=VIH or VIL,  
VCC=MIN  
IOL = -24 mA  
Com., Ind.  
VOL  
VOH  
Output High Voltage  
Output High Voltage  
0.5  
V
V
VIN=VIH or VIL,  
VCC=MIN  
IOH = -4.0 mA  
2.4  
Note:  
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.  
3
AC Waveforms(1)  
Note:  
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise specified.  
AC Characteristics(1)  
-7(2)  
Min Max Min Max Min Max Min Max Units  
-10  
-15  
-25  
Symbol  
Parameter  
8 outputs switching  
1 output switching  
3
7.5  
7
3
10  
3
15  
3
25  
ns  
ns  
ns  
ns  
Input or Feedback to  
Non-Registered Output  
tPD  
tCF  
tCO  
Clock to Feedback  
Clock to Output  
3
6
7
8
10  
12  
2
5
5
2
2
10  
2
Input or Feedback  
Setup Time  
tS  
7.5  
12  
15  
ns  
tH  
tP  
Hold Time  
0
8
4
0
12  
6
0
16  
8
0
ns  
ns  
Clock Period  
24  
12  
tW  
Clock Width  
ns  
External Feedback 1/(tS+tCO  
Internal Feedback 1/(tS + tCF  
No Feedback 1/(tP)  
)
100  
125  
125  
68  
74  
83  
45  
50  
62  
37  
40  
41  
MHz  
MHz  
MHz  
FMAX  
)
Input to Output Enable —  
Product Term  
tEA  
tER  
3
2
9
9
3
2
10  
10  
3
2
15  
15  
3
2
20  
20  
ns  
ns  
Input to Output Disable —  
Product Term  
tPZX  
tPXZ  
OE pin to Output Enable  
OE pin to Output Disable  
2
6
6
2
10  
10  
2
15  
15  
2
20  
20  
ns  
ns  
1.5  
1.5  
1.5  
1.5  
Notes: 1. See ordering information for valid part numbers and speed grades.  
2. Recommend ATF16V8C-7.  
ATF16V8B  
4
ATF16V8B  
Input Test Waveforms and  
Measurement Levels:  
Output Test Loads:  
Commercial  
tR, tF < 5 ns (10% to 90%)  
Pin Capacitance  
f = 1 MHz, T = 25°C(1)  
Typ  
Max  
8
Units  
pF  
Conditions  
VIN = 0 V  
CIN  
COUT  
Note:  
5
6
8
pF  
VOUT = 0 V  
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.  
Power Up Reset  
The registers in the ATF16V8Bs are designed to reset dur-  
ing power up. At a point delayed slightly from VCC crossing  
VRST, all registers will be reset to the low state. As a result,  
the registered output state will always be high on power-up.  
This feature is critical for state machine initialization. How-  
ever, due to the asynchronous nature of reset and the  
uncertainty of how VCC actually rises in the system, the fol-  
lowing conditions are required:  
1) The VCC rise must be monotonic,  
2) After reset occurs, all input and feedback setup times  
must be met before driving the clock pin high, and  
3) The clock must remain stable during tPR  
.
Parameter  
Description  
Typ  
Max  
Units  
Power-Up  
Reset Time  
Preload of Registered Outputs  
tPR  
600  
1,000  
ns  
The ATF16V8B’s registers are provided with circuitry to  
allow loading of each register with either a high or a low.  
This feature will simplify testing since any state can be  
forced into the registers to control test sequencing. A  
JEDEC file with preload is generated when a source file  
with vectors is compiled. Once downloaded, the JEDEC file  
preload sequence will be done automatically by most of the  
approved programmers after the programming.  
Power-Up  
Reset Voltage  
VRST  
3.8  
4.5  
V
Security Fuse Usage  
A single fuse is provided to prevent unauthorized copying  
of the ATF16V8B fuse patterns. Once programmed, fuse  
verify and preload are inhibited. However, the 64-bit User  
Signature remains accessible.  
The security fuse should be programmed last, as its effect  
is immediate.  
5
Electronic Signature Word  
There are 64 bits of programmable memory that are always  
available to the user, even if the device is secured. These  
bits can be used for user-specific data.  
Input and I/O Pull-Ups  
All ATF16V8B family members have internal input and I/O  
pull-up resistors. Therefore, whenever inputs or I/Os are  
not being driven externally, they will float to VCC. This  
ensures that all logic array inputs are at known states.  
These are relatively weak active pull-ups that can easily be  
overdriven by TTL-compatible drivers (see input and I/O  
diagrams below).  
Programming/Erasing  
Programming/erasing is performed using standard PLD  
programmers. See CMOS PLD Programming Hardware  
and Software Support for information on software/program-  
ming.  
Input Diagram  
I/O Diagram  
Functional Logic Diagram Description  
The Logic Option and Functional Diagrams describe the  
ATF16V8B architecture. Eight configurable macrocells can  
be configured as a registered output, combinatorial I/O,  
combinatorial output, or dedicated input.  
subsets can be found in each of the configuration modes  
described in the following pages. The user can download  
the listed subset device JEDEC programming file to the  
PLD programmer, and the ATF16V8B can be configured to  
act like the chosen device. Check with your programmer  
manufacturer for this capability.  
The ATF16V8B can be configured in one of three different  
modes. Each mode makes the ATF16V8B look like a differ-  
ent device. Most PLD compilers can choose the right  
mode automatically. The user can also force the selection  
by supplying the compiler with a mode selection. The deter-  
mining factors would be the usage of register versus com-  
binatorial outputs and dedicated outputs versus outputs  
with output enable control.  
Unused product terms are automatically disabled by the  
compiler to decrease power consumption. A Security Fuse,  
when programmed, protects the content of the ATF16V8B.  
Eight bytes (64 fuses) of User Signature are accessible to  
the user for purposes such as storing project name, part  
number, revision, or date. The User Signature is accessible  
regardless of the state of the Security Fuse.  
The ATF16V8B universal architecture can be programmed  
to emulate many 20-pin PAL devices. These architectural  
Compiler Mode Selection  
Registered  
Complex  
Simple  
Auto Select  
P16V8  
ABEL, Atmel-ABEL  
CUPL  
P16V8R  
P16V8C  
P16V8AS  
G16V8AS  
GAL16V8_C8(1)  
“Simple”  
G16V8MS  
GAL16V8_R(1)  
“Registered”  
P16V8R  
G16V8MA  
GAL16V8_C7(1)  
“Complex”  
P16V8C  
G16V8  
LOG/iC  
GAL16V8  
GAL16V8A  
P16V8A  
G16V8  
OrCAD-PLD  
PLDesigner  
Tango-PLD  
P16V8C  
G16V8R  
G16V8C  
G16V8AS  
Note:  
1. Only applicable for version 3.4 or lower.  
ATF16V8B  
6
ATF16V8B  
In simple mode all feedback paths of the output pins are  
routed via the adjacent pins. In doing so, the two inner most  
pins (pins 15 and 16) will not have the feedback option as  
these pins are always configured as dedicated combinato-  
rial output.  
Macrocell Configuration  
Software compilers support the three different OMC  
modes as different device types. Most compilers have the  
ability to automatically select the device type, generally  
based on the register usage and output enable (OE) usage.  
Register usage on the device forces the software to choose  
the registered mode. All combinatorial outputs with OE  
controlled by the product term will force the software to  
choose the complex mode. The software will choose the  
simple mode only when all outputs are dedicated combina-  
torial without OE control. The different device types can be  
used to override the automatic device selection by the soft-  
ware. For further details, refer to the compiler software  
manuals.  
ATF16V8B Registered Mode  
PAL Device Emulation / PAL Replacement  
The registered mode is used if one or more registers are  
required. Each macrocell can be configured as either a reg-  
istered or combinatorial output or I/O, or as an input. For a  
registered output or I/O, the output is enabled by the OE  
pin, and the register is clocked by the CLK pin. Eight prod-  
uct terms are allocated to the sum term. For a combinato-  
rial output or I/O, the output enable is controlled by a  
product term, and seven product terms are allocated to the  
sum term. When the macrocell is configured as an input,  
the output enable is permanently disabled.  
When using compiler software to configure the device, the  
user must pay special attention to the following restrictions  
in each mode.  
In registered mode pin 1 and pin 11 are permanently con-  
figured as clock and output enable, respectively. These  
pins cannot be configured as dedicated inputs in the regis-  
tered mode.  
Any register usage will make the compiler select this mode.  
The following registered devices can be emulated using  
this mode:  
In complex mode pin 1 and pin 11 become dedicated  
inputs and use the feedback paths of pin 19 and pin 12  
respectively. Because of this feedback path usage, pin 19  
and pin 12 do not have the feedback option in this mode.  
16R8 16RP8  
16R6 16RP6  
16R4 16RP4  
Registered Configuration for  
Registered Mode(1)(2)  
Combinatorial Configuration for  
Registered Mode(1)(2)  
Notes: 1. Pin 1 cotrols common CLK for the registered out-  
puts. Pin 11 controls common OE for the registered  
outputs. Pin 1 and Pin 11 are permanently config-  
ured as CLK and OE.  
Notes: 1. Pin 1 and Pin 11 are permanently configured as  
CLK and OE.  
2. The development software configures all the archi-  
tecture control bits and checks for proper pin usage  
automatically.  
2. The development software configures all the archi-  
tecture control bits and checks for proper pin usage  
automatically.  
7
Registered Mode Logic Diagram  
ATF16V8B  
8
ATF16V8B  
ATF16V8B Complex Mode  
PAL Device Emulation/PAL Replacement  
rocell has seven product terms going to the sum term and  
one product term enabling the output.  
In the Complex Mode, combinatorial output and I/O func-  
tions are possible. Pins 1 and 11 are regular inputs to the  
array. Pins 13 through 18 have pin feedback paths back to  
the AND-array, which makes full I/O capability possible.  
Pins 12 and 19 (outermost macrocells) are outputs only.  
They do not have input capability. In this mode, each mac-  
Combinatorial applications with an OE requirement will  
make the compiler select this mode. The following devices  
can be emulated using this mode:  
16L8  
16H8  
16P8  
Complex Mode Option  
The compiler selects this mode when all outputs are combi-  
natorial without OE control. The following simple PALs can  
be emulated using this mode:  
ATF16V8B Simple Mode  
PAL Device Emulation / PAL Replacement  
In the Simple Mode, 8 product terms are allocated to the  
sum term. Pins 15 and 16 (center macrocells) are perma-  
nently configured as combinatorial outputs. Other macro-  
cells can be either inputs or combinatorial outputs with pin  
feedback to the AND-array. Pins 1 and 11 are regular  
inputs.  
10L8  
12L6  
14L4  
16L2  
10H8  
12H6  
14H4  
16H2  
10P8  
12P6  
14P4  
16P2  
Simple Mode Option  
* - Pins 15 and 16 are always enabled.  
9
Complex Mode Logic Diagram  
ATF16V8B  
10  
ATF16V8B  
Simple Mode Logic Diagram  
11  
SUPPLY CURRENT vs. INPUT FREQUENCY  
SUPPLY CURRENT vs. INPUT FREQUENCY  
ATF16V8BL/BQL (VCC = 5V, TA = 25C)  
ATF16V8B/BQ (VCC = 5V, TA = 25C)  
75  
75  
ATF16V8BL  
ATF16V8B  
I
C
C
I
C
C
50  
50  
ATF16V8BQL  
ATF16V8BQ  
m
A
m
25  
0
25  
A
0
0
20  
40  
60  
80  
100  
0
25  
50  
75  
100  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
SUPPLY CURRENT vs. SUPPLY VOLTAGE  
ATF16V8B/BQ (TA = 25C)  
65  
ATF16V8B  
55  
I
C
C
ATF16V8BQ  
45  
35  
25  
m
A
4.50  
4.75  
5.00  
5.25  
5.50  
SUPPLY VOLTAGE (V)  
OUTPUT SOURCE CURRENT  
vs. SUPPLY VOLTAGE (TA = 25C)  
-10  
-12  
-14  
-16  
-18  
-20  
-22  
-24  
I
O
H
m
A
4.5  
4.7  
4.9  
5.1  
5.3  
5.5  
SUPPLY VOLTAGE (V)  
ATF16V8B  
12  
ATF16V8B  
NORMALIZED TPD  
vs. SUPPLY VOLTAGE (TA=25°C)  
1.3  
1.15  
1
N
O
R
M
ATF16V8B/BQ  
T
P
D
ATF16V8BQL  
0.85  
0.7  
4.50  
4.75  
5.00  
5.25  
5.50  
SUPPLY VOLTAGE (V)  
NORMALIZED TCO  
vs. SUPPLY VOLTAGE(TA=25°C)  
1.3  
1.15  
1
N
O
R
M
ATF16V8B/BQ  
ATF16V8BQL  
T
C
O
0.85  
0.7  
4.50  
4.75  
5.00  
5.25  
5.50  
SUPPLY VOLTAGE (V)  
13  
ATF16V8B  
14  
ATF16V8B  
Ordering Information  
tPD  
tS  
tCO  
(ns)  
(ns)  
(ns)  
Ordering Code  
Package  
Operation Range  
7.5  
5
5
ATF16V8B-7JC(1)  
ATF16V8B-7PC(1)  
ATF16V8B-7SC(1)  
ATF16V8B-7XC(1)  
20J  
Commercial  
20P3  
20S  
20X  
(0°C to 70°C)  
10  
7.5  
7
ATF16V8B-10JC  
ATF16V8B-10PC  
ATF16V8B-10SC  
ATF16V8B-10XC  
20J  
Commercial  
20P3  
20S  
20X  
(0°C to 70°C)  
ATF16V8B-10JI  
ATF16V8B-10PI  
ATF16V8B-10SI  
ATF16V8B-10XI  
20J  
Industrial  
20P3  
20S  
20X  
(-40°C to 85°C)  
15  
12  
10  
ATF16V8B-15JC  
ATF16V8B-15PC  
ATF16V8B-15SC  
ATF16V8B-15XC  
20J  
Commercial  
20P3  
20S  
20X  
(0°C to 70°C)  
ATF16V8B-15JI  
ATF16V8B-15PI  
ATF16V8B-15SI  
ATF16V8B-15XI  
20J  
Industrial  
20P3  
20S  
20X  
(-40°C to 85°C)  
25  
15  
12  
ATF16V8B-25JC  
ATF16V8B-25PC  
ATF16V8B-25SC  
ATF16V8B-25XC  
20J  
Commercial  
20P3  
20S  
20X  
(0°C to 70°C)  
ATF16V8B-25JI  
ATF16V8B-25PI  
ATF16V8B-25SI  
ATF16V8B-25XI  
20J  
Industrial  
20P3  
20S  
20X  
(-40°C to 85°C)  
Note:  
1. Recommend ATF16V8C-7.  
15  
Ordering Information  
tPD  
tS  
tCO  
(ns)  
(ns)  
(ns)  
Ordering Code  
Package  
Operation Range  
10  
15  
25  
7.5  
12  
15  
7
ATF16V8BQ-10JC  
ATF16V8BQ-10PC  
ATF16V8BQ-10SC  
ATF16V8BQ-10XC  
20J  
Commercial  
20P3  
20S  
20X  
(0°C to 70°C)  
10  
12  
ATF16V8BQL-15JC  
ATF16V8BQL-15PC  
ATF16V8BQL-15SC  
ATF16V8BQL-15XC  
20J  
Commercial  
20P3  
20S  
20X  
(0°C to 70°C)  
ATF16V8BQL-25JC  
ATF16V8BQL-25PC  
ATF16V8BQL-25SC  
ATF16V8BQL-25XC  
20J  
Commercial  
20P3  
20S  
20X  
(0°C to 70°C)  
ATF16V8BQL-25JI  
ATF16V8BQL-25PI  
ATF16V8BQL-25SI  
ATF16V8BQL-25XI  
20J  
Industrial  
20P3  
20S  
20X  
(-40°C to 85°C)  
Package Type  
20J  
20-Lead, Plastic J-Leaded Chip Carrier (PLCC)  
20P3  
20S  
20-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)  
20-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)  
20X  
20-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)  
ATF16V8B  
16  
ATF16V8B  
Packaging Information  
20J, 20-Lead, Plastic J-Leaded Chip Carrier (PLCC)  
20P3, 20-Lead, 0.300" Wide, Plastic Dual Inline  
Dimensions in Inches and (Millimeters)  
JEDEC STANDARD MS-018 AA  
Package (PDIP)  
Dimensions in Inches and (Millimeters)  
JEDEC STANDARD MS-001 AD  
1.060(26.9)  
.980(24.9)  
PIN  
1
.280(7.11)  
.240(6.10)  
.090(2.29)  
.900(22.86) REF  
MAX  
.210(5.33)  
MAX  
.005(.127)  
MIN  
SEATING  
PLANE  
.015(.381) MIN  
.150(3.81)  
.115(2.92)  
.022(.559)  
.014(.356)  
.070(1.78)  
.045(1.13)  
.110(2.79)  
.090(2.29)  
.325(8.26)  
.300(7.62)  
0
15  
REF  
.014(.356)  
.008(.203)  
.430(10.92) MAX  
20S, 20-Lead, 0.300" Wide, Plastic Gull Wing Small  
Outline (SOIC)  
20X, 20-Lead, 4.4 mm Wide, Plastic Thin Shrink  
Small Outline (TSSOP)  
Dimensions in Inches and (Millimeters)  
Dimensions in Millimeters and (Inches)  
0.020 (0.508)  
0.013 (0.330)  
0.30(0.012)  
0.18(0.007)  
0.420 (10.7)  
0.393 (9.98)  
0.299 (7.60)  
0.291 (7.39)  
PIN 1  
4.48(.176) 6.50(.256)  
4.30(.169) 6.25(.246)  
PIN 1 ID  
.050 (1.27) BSC  
0.65(.0256) BSC  
6.60(.260)  
0.513 (13.0)  
0.497 (12.6)  
0.105 (2.67)  
0.092 (2.34)  
6.40(.252)  
1.10(0.043) MAX  
0.15(.006)  
0.05(.002)  
0.012 (0.305)  
0.003 (0.076)  
0.18(.007)  
0.09(.003)  
0
8
REF  
0.013 (0.330)  
0.009 (0.229)  
0.70(.028)  
0
REF  
0.50(.020)  
0.035 (0.889)  
0.015 (0.381)  
8
17  

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