ATF1502SE-5 [ATMEL]
Family Datasheet; 系列数据表Features
• 2nd Generation EE PROM-based Complex Programmable Logic Devices
– VCCIO of 5.0V or 3.3V with 3.3V Operation being 5V Tolerant
– 32 - 256 Macrocells with Enhanced Features
– Pin-compatible with Industry Standard Devices
– Speeds to 5 ns Maximum Pin-to-pin Delay
– Registered Operation to 250 MHz
• Enhanced Macrocells with Logic Doubling™ Features
– Bury Either Register or COM while Using the Other for Output
– Dual Independent Feedback Allows Multiple Latch Functions per Macrocell
– 5 Product Terms per Macrocell, expandable to 40 per Macrocell with Cascade
Logic, Plus 15 more with Foldback Logic
ATF15xxSE
Family
Datasheet
– D/T/Latch Configurable Flip-flops plus Transparent Latches
– Global and/or per Macrocell Register Control Signals
– Global and/or per Macrocell Output Enable
– Programmable Output Slew Rate per Macrocell
– Programmable Output Open Collector Option per Macrocell
– Fast Registered Input from Product Term
• Enhanced Connectivity
ATF1502SE(L)
ATF1504SE(L)
ATF1508SE(L)
ATF1516SE(L)
– Single Level Switch Matrix for Maximum Routing Options
– Up to 40 Inputs per Logic Block
• Advanced Power Management Features
– ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and
I/O for µA Level Standby Current for “L” Versions
– Pin-controlled 1 mA Standby Mode
– Reduced-power Option per Macrocell
– Automatic Power Down of Unused Macrocells
– Programmable Pin-keeper Inputs and I/Os
• Available in Commercial and Industrial Temperature Ranges
• Available in All Popular Packages Including PLCC, PQFP and TQFP
• EE PROM Technology
Preliminary
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993
– Pull-up Option on JTAG Pins TMS and TDI
• IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG
• PCI-compliant
• Security Fuse Feature
Rev. 2401D–PLD–09/02
General
Description
Beginning with the introduction of the 100% connected ATF1500 with 32 enhanced macrocells
in 1996, Atmel’s CPLD products have delivered extra IO connectivity and logic reusability.
Atmel’s commitment to efficient, flexible architecture has continued with the current Atmel
ATF15xxSE Family of industry-standard, pin-compatible CPLDs. Atmel’s Logic Doubling
architecture consists of wider fan-in, additional routing and clock options, combined with
sophisticated, proprietary device fitters, extend CPLD place and route efficiency. Atmel
enhanced macrocell includes double independent buried feedback that allows designers to
pack more logic (particularly shifters and latches) into a smaller CPLD or leave spare room for
later revisions. The Atmel ATF15xxSE family delivers enhanced functionality and flexibility
with no additional design effort and is highly cost effective.
The Atmel ATF15xxSE Family includes all popular configurations and speeds.
Table 1. ATF15xxSE Family Device Features
Feature
ATF1502SE(L)
ATF1504SE(L)
ATF1508SE(L)
ATF1516SE(L)
Usable Gates
Macrocells
750
1500
3000
128
6000
256
32
64
Logic Blocks
Max. # Pins
Max. User I/Os
2
4
100
8
16
44
36
256
256
68
100
164
T
PD Grades (ns)
5, 6, 7, 10(15)
5, 6, 7, 10(15)
6, 7, 10(15)
7, 10(15)
The Atmel ATF15xxSE Family includes pin-compatible products in all popular packages.
Table 2. ATF15xxSE Family Device Packages and Number of Signal Pins(1)(2)
Packages
ATF1502SE(L)
ATF1504SE(L)
ATF1508SE(L)
ATF1516SE(L)
44-pin PLCC
44-pin TQFP
84-pin PLCC
100-pin TQFP
100-pin PQFP
160-pin PQFP
208-pin PQFP
208-pin RQFP
36
36
36
36
68
68
68
84
84
100
164
164
Notes: 1. Contact Atmel for up-to-date information on device and package availability.
2. When the JTAG port is used for In System Programming (ISP) or Boundary-scan Testing
(BST), the four associated pins become JTAG pins and are unavailable for user I/O.
2
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
Functional
Description
The ATF15xxSE Family of 5.0 Volt supply, high-performance, high-density complex program-
mable logic devices (CPLDs) utilizes Atmel’s proven electrically erasable non-volatile
technology. With up to 512 macrocells, they easily integrate logic from several TTL, SSI, MSI,
LSI and classic PLDs. The ATF15xxSE Family’s enhanced macrocell architecture, switch
matrices and routing increase usable gate count for new designs and increase odds of suc-
cessful pin-locked design modifications while maintaining pin-compatibility with industry
standard CPLDs.
The ATF15xxSE Family devices have four dedicated input pins and depending on the type of
device and package, up to 208 bi-directional I/O pins. Each dedicated input pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these control
signals can be selected for use individually within each macrocell. Each input and I/O pin also
feeds into the global bus.
The macrocells are organized into groups of sixteen called logic blocks. The switch matrix in
each logic block selects 40 individual signals from the global bus. Macrocells within a given
logic block may share their sixteen foldback signals on a regional foldback bus. Cascade logic
between macrocells in the Logic Block allows fast, efficient generation of complex logic func-
tions. All macrocells are capable of being I/Os, however, the actual number of I/O pins
depends on the device and package type. The ATF15xxSE Family members contain two, four,
eight, sixteen or thirty-two such logic blocks, each capable of creating sum term logic with a
fan-in of 40 inputs from the switch matrix having access to up to 80 product terms.
Unused macrocells are automatically disabled by the fitter software to decrease power con-
sumption. A security fuse, when programmed, protects the contents of the other fuses. Two
bytes (16 bits) of User Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Signature is accessible regardless of
the state of the security fuse.
The ATF15xxSE Family devices are in-system programmable (ISP) devices. They use the
industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and are fully-compliant with
JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be pro-
grammed without removing it from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to be made in the field via software.
Global Bus/Switch
Matrix
The global bus (Figure 1) contains all input and I/O pin signals as well as the buried feedback
signals from all macrocells. The switch matrix in each logic block receives as its inputs all sig-
nals from the global bus. Up to 40 of these signals can be selected as inputs to the individual
logic blocks by the fitter software. Atmel’s ATF15xx Family of CPLDs use a single level switch
matrix signal distribution structure, where each logic block input has access to the same num-
ber of global bus inputs, maximizing the number of possible ways to route a global bus signal.
This single level structure is in contrast with split switch matrix structures used by others in
which routing a particular global bus input to a particular logic block input makes that signal
unavailable to some other logic blocks, thus greatly limiting the available opportunities to
route.
The ATF15xxSE Family macrocell, shown in Figure 2, consists of five sections: product terms
and product term select multiplexer, OR/XOR/CASCADE logic, foldback bus, a flip-flop and
output buffer. Extra fan-in and signal routing are provided throughout. Each macrocell can
generate a foldback logic term from the product term mux and a buried feedback with extra
routing that go to the global bus.
3
2401D–PLD–09/02
Figure 1. ATF15xxSE Family Typical Block Diagram
6 to 16
N
6 to 16
N-1
4
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
Figure 2. ATF15xxSE Family Macrocell with Enhanced Features In Red
Product Terms and
Select Mux
Within each macrocell are five product terms. Each product term may receive as its inputs any
combination of the signals from the switch matrix or regional foldback bus. The product term
select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic
gates and control signals. The PTMUX programming is determined by the fitter software,
which selects the optimum macrocell configuration.
OR/XOR/
CASCADE Logic
Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-
input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can
be expanded to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input
allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimiza-
tion of product terms. The XOR gate may be fed from the flip-flop output to emulate T- and JK-
type flip-flops, or fed to the buried feedback to synthesize an extra latch.
Foldback Bus
Each macrocell can also generate a foldback product term. This signal goes to the regional
bus and is available to the 16 macrocells in a given logic block. The foldback is an inverse
polarity of one of the macrocell’s product terms. Although Cascade Logic is the preferred
method for expanding the number of macrocell inputs to as many as 40, the 16 foldback terms
in each region can also generate additional fan-in sum terms with nominal additional delay.
5
2401D–PLD–09/02
Flip-flop
The ATF15xxSE Family’s flip-flop has very flexible data and control functions. The data input
can come from either the XOR gate, from a separate product term or directly from the I/O pin.
Selecting the separate product term allows creation of a buried registered feedback within a
combinatorial output or vice-versa. (This enhanced function is automatically implemented by
the fitter software). The flip-flop can be configured for D, T, JK and SR operation, and changes
state on the clock’s rising edge. It can also be configured as a flow-through latch. In this mode,
data passes through when the clock is high and is latched when the clock is low.
When a GCK signal is used as the clock, one of the macrocell product terms can be selected
as a clock enable. When the clock enable function is active and the enable signal (product
term) is low, all clock edges are ignored. The flip-flop has asynchronous reset and preset. The
flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product
term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchro-
nous preset (AP) can be a product term or always off.
Extra Feedback
I/O Control
The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The
extra buried feedback signal can be either combinatorial or registered signal regardless of
whether the output is combinatorial or registered. (This enhanced function is automatically
implemented by the fitter software) Feedback of a buried combinatorial output allows the cre-
ation of a second latch within a macrocell.
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-
vidually configured as an input, output or for bi-directional operation. The output enable for
each macrocell can be selected from the true or compliment of the two output enable pins, a
subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done
by the fitter software when the I/O is configured as an input, all macrocell resources are still
available, including the buried feedback, expander and cascade logic.
The buffer has a fast/slow slew rate option to control EMI and an open-collector option which
enables the device to provide control signals such as an interrupt that can be asserted by any
of the several devices.
Programmable
Pin-keeper Option
for Inputs and I/Os
The ATF15xxSE Family offers the option of programming all input and I/O pins with pin-keeper
circuits enabled. When any pin is driven high or low and then subsequently left floating, the pin
keeper circuit will hold it at that previous high or low-level. This circuitry prevents unused input
and I/O lines from floating to intermediate voltage levels, which causes unnecessary power
consumption and system noise. The pin-keeper circuits eliminate the need for external pull-up
resistors and eliminate their DC power consumption.
6
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
Input Diagram
PROGRAMMABLE
OPTION (PIN KEEPER)
I/O Diagram
PROGRAMMABLE
OPTION (PIN KEEPER)
Speed/Power
Management
The ATF15xxSE Family has several speed and power management features.
Multiple Power
Supplies, Power
Sequencing and
Hot-Socketing
Because the ATF15xxSE Family can be used in a system with mixture of power supplies, it
has been designed to function with the VCCINT and VCCIO power supplies applied in any
sequence. Also, until the power up sequence completes, the input/output buffers are kept in a
high impedance state, and so may be driven but do not drive power out.
7
2401D–PLD–09/02
Power-on Reset
The ATF15xx Family devices are designed with a power-on reset, a feature critical for state
machine initialization. At a point delayed slightly from VCC crossing VRST, all registers will be
initialized, and the state of each output will depend on the polarity of its buffer. However, due
to the asynchronous nature of reset and uncertainty of how VCC actually rises in the system,
the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin high, and,
3. The clock must remain stable during TD.
The ATF15xx Family has two options for the hysteresis about the reset level, VRST, Small and
Large. In applications where the supply voltage may drop below 4.0V, Atmel recommends that
during the fitting process users configure the device with the Power-on Reset hysteresis set to
Large to ensure a robust operating environment.
Power Down of
Unused
To conserve power, Atmel fitters automatically power down all unused macrocells.
Macrocells
Input Transition
Detection/
Automatic Power
Down
The ATF15xxSEL versions provide automatic power-down to µA level stand-by power (the “L”
suffix indicates “Low” power) through Atmel’s patented Input Transition Detection (ITD) cir-
cuitry on Global Clocks, Inputs and I/O. These ITD circuits automatically put the device into a
low-power standby mode when no logic transitions are occurring. This reduces power con-
sumption during inactive periods, and so provides proportional power savings for most
applications running at system speeds below fCRITICAL (~5 MHz).
In clocked applications, where the device is operated at a frequency high enough to keep the
device from going into stand-by (above fCRITICAL), the device will perform at the faster speeds
given in the next faster speed column. These higher speeds can be achieved in combinatorial
designs as well, as long as once activated by an initial input transition, the device continues to
receive input transitions often enough to keep the device from going into standby mode again.
That is, the time between input transitions is less than 1/fCRITICAL
.
Reduced-Power
per Macrocell
To further reduce power, each ATF15xxSE Family macrocell has a reduced-power bit feature.
With this feature the designer can reduce power by 50% or more for logic that does not need
to operate at the maximum switching speed. The reduced-power bit may be activated by
changing the default OFF to ON for any or all macrocells. For macrocells in reduced-power
mode (reduced-power bit turned on), the reduced- power adder, tRPA, must be added to the
AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP. All power-down
AC characteristic parameters are computed from external input or I/O pins, with the reduced-
power bit turned on.
Slew Rate Control
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching. The slew rate option is selected in the design source file.
Pin Controlled
Power-down
All ATF15xx Family devices also have an optional pin-controlled power-down mode. When
activated, one or both of two pins, PD1 and PD2, can act as power-down pins. The device
goes into power-down when either PD1 or PD2 pins (or both) are high, and the device supply
current is reduced to less than 1 mA. Also, all internal logic signals are latched and held, as
are any enabled outputs. Therefore, all registered and combinatorial output data remain valid.
Any outputs that were in a high-Z state at the onset will remain at high-Z. Input and I/O hold
8
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
latches remain active to ensure that pins do not float to indeterminate levels, further reducing
system power. All pin transitions are ignored until the PD pin is brought low. When the power-
down feature is enabled for PD1 or PD2, that pin cannot be used as a logic input or output.
However, the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals. The power-down option is selected in the design source file.
Power
Consumption
Estimates
An estimate of power consumption can be made based on typical designs and operation con-
ditions, but because it is sensitive to these factors, power consumption must be verified with
actual pattern and operation conditions. The equations given below are based on a pattern of
16-bit up/down counters in each logic block and may be used to estimate power consumption
for both operating modes.
Standby Power
1. Pstandby = Iccstandby x Vsupply
Where:
Iccstandby = the standby current given for the particular device and standby mode (e.g. pin con-
trolled Power Down)
Vsupply= the power supply voltage
Active Power
2. Pactive = Pinternal + Pload = Iccinternal x Vsupply + Pload
Where:
Iccinternal = the internal current estimated from equation 3 below
Vsupply= the power supply voltage
Pload = depends on the device output load capacitance and switching frequency on each out-
put pin.
Pload and additional power savings at low frequencies using Atmel Input Transition Detection
(“L” versions) can be estimated according to the methods discussed in the Atmel Application
Note “Saving Power with Atmel PLDs”
3.
I
ccinternal = [K1 x (MCinuse – MCreducedpower )] + (K2 x MCreducedpower) + (K3 x MCinuse x fop
x
NS)
Where:
MCreducedpower = the number of macrocells operating at reduced power (from fitter report file)
MCinuse= the number of macrocells in use (from fitter report file. Unused macrocells are pow-
ered down.)
NS = the proportion of logic nodes switching (typically 10-20%)
fop = the switching frequency
K1, K2,and K3 = device constants given in the table below.
Device
K1 (mA/MC)
K2 (mA/MC)
K3 (mA/MC · MHz)
0.015
ATF1502SE
ATF1504SE
ATF1508SE
ATF1516SE
0.6
0.6
0.6
0.6
0.3
0.3
0.3
0.3
0.015
0.015
0.015
Note:
Shaded data is preliminary and subject to change without notice.
9
2401D–PLD–09/02
Design
Software
Atmel ATF15xxSE Family fitters allow logic synthesis using a variety of high-level description
languages and formats. ATF15xxSE Family designs are supported by Atmel specific design
tools as well as by several third-party tools. Free conversion software is also offered for indus-
try standard devices. Check the Atmel web site or contact your authorized Atmel sales
representative for up-to-date design software information.
Programming
ATF15xxSE Family devices can be programmed using standard third-party programmers.
With third-party programmers, the JTAG ISP port can be disabled thereby allowing four addi-
tional I/O pins to be used for logic. Check the Atmel web site, contact your authorized Atmel
sales representative or Atmel PLD Applications for details of third-party programmers.
ATF15xxSE Family devices are in-system programmable (ISP) devices utilizing the 4-pin
JTAG protocol. This capability eliminates package handling normally required for program-
ming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware
and software to allow programming of the ATF15xxSE Family via the PC. ISP is performed by
using either a download cable, a compatible board tester or a simple microprocessor interface.
It is most common to devote the JTAG pins to ISP, but it is possible to use ISP to program the
part through the JTAG pins, and set these four pins I/O pins. However, this will effectively dis-
able further ISP and the device will need to be erased on a programmer to re-enable ISP.
Contact Atmel PLD Applications by email at pld@atmel.com or call our Hotline at (408) 436-
4333 for details.
To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial
Vector Format (SVF) files can be created by the Atmel ISP software. Conversion to other ATE
tester formats is also possible. Check the Atmel web site for up-to-date programming and soft-
ware support information.
ISP
The ATF15xxSE Family also incorporates a protection feature that locks the device and pre-
vents the inputs and I/O from driving if the programming process is interrupted for any reason.
The inputs and I/O default to high-Z state during such a condition. In addition the pin-keeper
option preserves the former state during device programming.
Programming
Protection
All ATF15xxSE Family devices are initially shipped in the erased state thereby making them
ready to use for ISP.
For more information refer to the “Designing for In-System Programmability with Atmel
CPLDs” application note.
Security Fuse
Usage
A single fuse is provided to prevent unauthorized copying of the ATF15xxSE Family fuse pat-
terns. Once programmed, fuse verify is inhibited. However, the User Signature and device ID
remain accessible.
10
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
JTAG-BST
Overview
The JTAG-BST (JTAG boundary-scan testing) is controlled by the Test Access Port (TAP)
controller. The boundary-scan technique involves the inclusion of a shift-register stage (con-
tained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing principles. Each input pin and
I/O pin has its own Boundary-scan Cell (BSC) in order to support boundary-scan testing. The
ATF15xxSE Family does not currently include a Test Reset (TRST) input pin because the TAP
controller is automatically reset at power-up. The ATF15xxSE Family implements six BST
instructions, and seven Atmel-defined In System Programming (ISP) instructions. All ATF15xx
Family BST and ISP instructions have a length of 10 bits.
JTAG BST Instructions
Description
SAMPLE/PRELOAD
Captures signals at the device pins for later examination,
or loads a data pattern prior to an EXTEST instruction.
EXTEST
Allows testing of off-chip circuitry and interconnections
by forcing a pattern on the output pins or capturing
signals from the input pins.
BYPASS
Places a single shift register stage between TDI and
TDO, allowing test BST data to pass through a particular
device in a chain of devices.
IDCODE
Places the 32-bit IDCODE register between TDI and
TDO, allowing the IDCODE data to be shifted out of
TDO.
UESCODE
HIGHZ
Places the 16-bit user electronic signature register
between TDI and TDO, allowing the UESCODE data to
be shifted out of TDO.
Places the BYPASS register between TDI and TDO in a
high impedance mode, protecting the device from
damage from externally applied test signals.
7 ISP instructions
These seven instructions allow in-system programming
via the four JTAG pins.
The ATF15xxSE Family BST implementation complies with the Boundary-scan Definition Lan-
guage (BSDL) described in the JTAG specification (IEEE Standard 1149.1). Any third-party
tool that supports the BSDL format can be used to perform BST on the ATF15xxSE Family.
The ATF15xxSE Family also has the option of using four JTAG-standard I/O pins for in-system
programming (ISP). The ATF15xxSE Family is programmable through the four JTAG pins
using programming-compatible with the IEEE JTAG Standard 1149.1. Programming is per-
formed by using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG
feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG
control pins are available as I/O pins. Refer to Atmel Application Note “Designing for In-Sys-
tem Programmability with Atmel CPLDs for more details.
11
2401D–PLD–09/02
JTAG
The ATF15xxSE Family has four dedicated input pins and a number of I/O pins depending on
the device type and package type selected. Each input pin and I/O pin has a boundary-scan
cell (BSC) which supports boundary-scan testing as described in detail by IEEE Standard
1149.1. A typical BSC consists of three capture registers or scan registers and up to two
update registers. There are two types of BSCs, one for input or I/O pin, and one for the macro-
cells. The BSCs in the device are chained together through the (BST) capture registers. Input
to the capture register chain is fed in from the TDI pin while the output is directed to the TDO
pin. Capture registers are used to capture active device data signals, to shift data in and out of
the device and to load data into the update registers. Control signals are generated internally
by the JTAG TAP controller.
Boundary-scan
Cell (BSC)
Testing
IDCODE
Boundary-Scan
Register Length
Device
MSB
LSB
ATF1502SE
ATF1504SE
ATF1508SE
ATF1516SE
96
0000,0001,0101,0100,0010,0000,0011,1111
0000,0001,0101,0100,0100,0000,0011,1111
0000,0001,0101,0100,1000,0000,0011,1111
0000,0001,0101,0101,0000,0000,0011,1111
192
352
672
Note:
Shaded data is preliminary and subject to change without notice.
Boundary-scan
Definition
Language
These are now available in all package types via the Atmel web site. These models conform to
the IEEE 1149.1 standard and can be used for Boundary-scan Test Operation of the
ATF15xxSE Family.
(BSDL) Models
The BSC configuration for the input and I/O pins and macrocells are shown on page 13.
12
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
BSC
Configuration
for Pins (Except
JTAG TAP Pins)
BSC
Configuration
for Macrocell
TDO
OEJ
0
1
0
1
D Q
D Q
OUTJ
0
Pin
1
0
1
D Q
D Q
Capture
Register
Update
Register
Mode
TDI
Clock
Shift
Macrocell BSC
13
2401D–PLD–09/02
PCI Compliance
The ATF15xx Family also supports peripheral component interconnect (PCI) interface stan-
dard in PCI-based designs and specifications. The PCI interface calls for high current drivers,
which are much larger than the traditional TTL drivers.
PCI Voltage-to-
Current Curves for
+5V Signaling in
Pull-up Mode
Pull Up
VCC
Test Point
2.4
DC
drive point
1.4
AC drive
point
Current (mA)
-44
-2
-178
PCI Voltage-to-
Current Curves for
+5V Signaling in
Pull-down Mode
Pull Down
VCC
2.2
AC drive
point
DC
drive point
0.55
Test Point
Current (mA)
95
3,6
380
14
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
PCI DC Characteristics
Symbol
VCC
VIH
Parameter
Conditions
Min
4.75
2.0
Max
5.25
Units
V
Supply Voltage
Input High Voltage
Input Low Voltage
VCC + 0.5
0.8
V
VIL
-0.5
V
IIH
Input High Leakage Current
Input Low Leakage Current
Output High Voltage
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
Pin Inductance
VIN = 2.7V
VIN = 0.5V
70
µA
µA
V
IIL
-70
VOH
VOL
IOUT = -2 mA
2.4
IOUT = 3 mA, 6 mA
0.55
10
12
8
V
CIN
pF
pF
pF
nH
CCLK
CIDSEL
LPIN
20
Note:
Leakage current is without pin-keeper off.
PCI AC Characteristics
Symbol
Parameter
Switching
Conditions
Min
Max
Units
mA
IOH(AC)
0 < VOUT ≤ 1.4
-44
Current High
1.4 < VOUT < 2.4
3.1 < VOUT < VCC
VOUT = 3.1V
-44+(VOUT - 1.4)/0.024
mA
Equation A
-142
mA
(Test High)
Switching
µA
IOL(AC)
VOUT > 2.2V
95
mA
Current Low
2.2 > VOUT > 0
0.1 > VOUT > 0
VOUT = 0.71
VOUT/0.023
mA
Equation B
206
mA
(Test Point)
mA
ICL
Low Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
-5 < VIN ≤ -1
-25+(VIN + 1)/0.015
mA
SLEWR
SLEWF
0.4V to 2.4V load
2.4V to 0.4V load
0.5
0.5
3.0
3.0
V/ns
V/ns
Notes: 1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.
2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V.
15
2401D–PLD–09/02
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Ambient Temperature Under Bias.................. -65°C to +135°C
Storage Temperature ..................................... -65°C to +150°C
Junction Temperature ..............................................150°C(MAX)
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
Note:
1. For currents less than 100 mA, minimum voltage
is -0.6 VDC and maximum voltage is VCC
with Respect to Ground
+
During Programming.....................................-2.0V to +14.0V(1)
0.75 VDC. Pulses of less than 20µs may under-
shoot to -2.0V or overshoot to 7.0V.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
DC Output Current per Pin ................................ -25 to +25 mA
DC and AC Operating Conditions
Commercial
Industrial
-40°C - 85°C
–
Operating Temperature (Ambient), TA
0°C - 70°C
–
(1)
Junction Temperature, TJ
V
CCINT (5.0V) Power Supply
VCCIO (5.0V) Power Supply
CCIO (3.3V) Power Supply
VI Input Voltage
O Output Voltage
5V ± 5%
5V ± 5%
3.0 - 3.6
5V ± 10%
5V ± 10%
3.0 - 3.6
V
-0.5 - VCCINT + .5
0 - VCCIO
-0.5 - VCCINT + .5
0 - VCCIO
V
tR
tF
40 ns Max
40 ns Max
40 ns Max
40 ns Max
Note:
1. Junction temperature is package and device dependant and can be calculated as follows: TJ(MAX) = TA(MAX) + (θJA|Air Flow =
0*P(MAX)). For more information see “Thermal Characteristics of Atmel Packages.”
16
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
DC Characteristics(1) ATFxxSE Family
Symbol Parameter
Condition
Min
Typ
-2
Min
-10
10
Unit
µA
IIL
IIH
Input or I/O Low Leakage Current
VIN = VCC
Input or I/O High Leakage Current
Tri-State Output Off-State Current
Power Supply Current, Standby
2
µA
IOZ
ICC1
VO = VCC or GND
-40
40
µA
(3)
(3)
VCC = Max
VIN = 0, VCC
Std Mode
Com.
Ind.
mA
mA
mA
mA
mA
“ITD”
Mode
Com.
Ind.
1
1
ICC2
Power Supply Current,
Power-down Mode
VCC = Max
VIN = 0, VCC
PD Mode
0.1
1
(2)
(3)
(3)
ICC3
Reduced-power Mode Supply
Current, Standby
VCC = Max
VIN = 0, VCC
Std Mode
Com.
Ind.
mA
mA
V
VIL
VIH
Input Low Voltage
Input High Voltage
-0.3
2.0
0.8
VCCINT
+0.5
V
VOL
5.0V Output Low Voltage (TTL)
3.3V Output Low Voltage (TTL)
3.3V Output Low Voltage (CMOS)
5.0V Output High Voltage (TTL)
3.3V Output High Voltage (TTL)
3.3V Output High Voltage (CMOS)
IOL = 12 mA, VCCIO = 4.75V
OL = 12 mA, VCCIO = 3.0V
0.45
0.45
0.2
V
V
V
V
V
V
I
IOL = 0.1 mA, VCCIO = 3.0V
IOH = -4 mA, VCCIO = 4.75V
VOH
2.4
2.4
I
OH = -4 mA, VCCIO = 3.0V
IOH = -0.1 mA, VCCIO = 3.0V
VCCIO – 0.2
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned ON.
3. See characteristic curves for each device.
Power-down AC Characteristics(1) ATFxxSE Family
-5
-6
-7
-10
-15
Symbol Parameter
Min
5.0
5.0
5.0
Max
Min
6.0
6.0
6.0
Max
Min
7.0
7.0
7.0
Max
Min
10
Max
Min
15
Max Unit
tIVDH
tGVDH
tCVDH
tDHIX
tDHGX
tDHCX
tDLIV
Valid 1, I/O before PD High
ns
ns
ns
Valid 1, OE(2) before PD High
Valid 1, Clock(2) before PD High
I, I/O Don’t Care after PD High
OE(2) Don’t Care after PD High
Clock(2) Don’t Care after PD High
PD Low to Valid I, I/O
10
15
10
15
9.0
9.0
9.0
1.0
1.0
1.0
1.0
10.0
10.0
10.0
1.0
12
12
15.0
15.0
15.0
1.0
25
25
ns
ns
ns
µs
µs
µs
µs
12
25
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
tDLGV
tDLCV
tDLOV
PD Low to Valid OE, (Pin or Term)
PD Low to Valid Clock, (Pin or Term)
PD Low to Valid Output
1.0
1.0
1.0
1.0
1.0
1.0
Notes: 1. For slow slew outputs, add tSSO
.
2. Pin or product term.
17
2401D–PLD–09/02
Timing Model
U
Pin Capacitance
Typ(1)
Max
10
Units
pF
Condition
CIN
8
8
VIN = 0V; f = 1.0 MHz
VOUT = 0V; f = 1.0 MHz
CI/O
10
pF
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage
pin during programming) has a maximum capacitance of 12 pF.
Input Test
Waveforms and
Measurement
Levels
Output AC Test
Loads
5.0V
(3.3V)
464
(703
)
C = C
L
250
(8060
)
18
ATF15xxSE Family
2401D–PLD–09/02
ATF1502SE
AC Characteristics(1) ATF1502SE(L)
SE -5
SE -6
SE -7
SE -10
SEL -15(6)
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tPD1
Input or Feedback to Non-
registered Output
5.0
6.0
7.5
10
15
ns
tPD2
I/O Input or Feedback to Non-
registered Feedback
5.0
6.0
7.5
10
12
ns
tSU
tH
Global Clock Setup Time
Global Clock Hold Time
2.9
0.0
2.5
4.0
0.0
2.5
5.0
0.0
2.5
7.0
0.0
3.0
11
0.0
3.0
ns
ns
ns
tFSU
Global Clock Setup Time of Fast
Input
tFH
tCO1
tCH
Global Clock Hold of Fast Input
Global Clock to Output Delay
Global Clock High Time
Global Clock Low Time
Array Clock Setup Time
Array Clock Hold Time
0.0
0.0
0.0
0.0
1.0
ns
ns
3.2
5.4
3.5
5.4
4.3
6.6
5.0
8.2
8.0
2.0
2.0
0.7
1.8
2.5
2.5
0.9
2.1
3.0
3.0
1.1
2.7
4.0
4.0
2.0
3.0
5.0
5.0
4.0
4.0
ns
tCL
ns
tASU
tAH
ns
ns
tACO1
tACH
tACL
tCNT
Array Clock Output Delay
Array Clock High Time
15
ns
2.5
2.5
2.5
2.5
3.0
3.0
4.0
4.0
6.0
6.0
ns
Array Clock Low Time
ns
Minimum Clock Global Period
5.7
7.0
7.0
8.6
8.6
10.0
10.0
13
13
ns
(3)
fCNT
Maximum Internal Global Clock
Frequency
175.4
143
117
100
77 or
MHz
100(6)
tACNT
Minimum Array Clock Period
5.7
ns
(4)
fACNT
Maximum Internal Array Clock
Frequency
175.4
250
143
200
117
167
100
125
77 or
MHz
100(6)
(5)
fMAX
Maximum Clock Frequency
80 or
MHz
125(6)
tIN
tIO
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
0.2
0.2
2.2
3.1
0.9
2.6
2.5
0.7
0.2
0.2
0.2
2.1
3.8
1.1
3.3
3.3
0.8
0.3
0.3
0.3
2.5
4.6
1.4
4.0
4.0
1.0
0.4
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
1.0
1.0
1.5
8.0
1.0
6.0
6.0
3.0
2.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tFIN
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
Foldback Term Delay
Cascade Logic Delay
Logic Array Delay
Logic Control Delay
Internal Output Enable Delay
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO
5V; CL= 35 pF)
=
19
2401D–PLD–09/02
AC Characteristics(1) ATF1502SE(L) (Continued)
SE -5
SE -6
SE -7
SE -10
SEL -15(6)
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tOD2
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO
3.3V; CL= 35 pF)
0.7
5.2
4.0
4.5
9.0
0.8
5.3
4.0
4.5
9.0
0.9
5.4
4.0
4.5
9.0
2.0
5.5
5.0
5.5
9.0
3.0
6.0
7.0
7.0
10
ns
=
tOD3
tZX1
tZX2
tZX3
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V
or 3.3V; CL= 35 pF)
ns
ns
ns
ns
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO
5V; CL= 35 pF)
=
=
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO
3.3V; CL= 35 pF)
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V
or 3.3V;
CL= 35 pF)
tXZ
Output Buffer Disable Delay
(CL= 5 pF)
4.0
4.0
4.0
5.0
6.0
ns
tSU
tH
Register Setup Time
Register Hold Time
0.8
1.7
1.9
1.0
2.0
1.7
1.3
2.5
1.7
2.0
3.0
3.0
4.0
4.0
5.0
ns
ns
ns
tFSU
Register Setup Time of Fast
Input
tFH
tRD
tCOMB
tIC
Register Hold Time of Fast Input
Register Delay
0.6
0.7
0.8
0.5
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.2
0.9
2.7
2.6
1.6
2.0
2.0
1.1
8
1.6
1.1
3.4
3.3
1.4
2.4
2.4
1.1
9
1.2
1.0
2.0
1.0
1.3
1.9
3.0
1.4
10
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
11
2.0
2.0
7.0
7.0
1.0
5.0
5.0
2.0
13
Combinatorial Delay
Array Clock Delay
tEN
Register Enable Time
Global Control Delay
Register Preset Time
Register Clear Time
Switch Matrix Delay
Reduced Power Adder
tGLOB
tPRE
tCLR
tUIM
(2)
tRPA
Notes: 1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reduced-
power mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipelined data.
6. For clocked applications and frequencies above fCRITICAL, OR, non-clocked applications with dormant times less than 1/fCRIT-
ICAL, the device will achieve the speeds of the –10 column. See “Input Transition Detection/ Automatic Power Down” on page
8.
20
ATF1502SE
2401D–PLD–09/02
ATF1502SE
STAND-BY ICC VS.
NORMALIZED ICC VS. TEMP
SUPPLY VOLTAGE (TA = 25°C)
1.4
1.2
1.0
0.8
0.6
0.4
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY CURRENT VS.
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
1.000
0.800
0.600
0.400
0.200
0.000
140.000
120.000
100.000
80.000
60.000
40.000
20.000
0.000
TBD
TBD
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0
-10
-20
-30
-40
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
TBD
TBD
-50
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
VOH (V)
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
48
46
44
42
40
38
36
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
TBD
TBD
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
21
2401D–PLD–09/02
INPUT CLAMP CURRENT VS.
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 35°C)
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
40
30
20
10
0
0
-20
-40
TBD
-60
TBD
-80
-10
-20
-30
-100
-120
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
NORMALIZED TPD VS. VCC
NORMALIZED TPD VS. TEMP
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
NORMALIZED TCO VS. VCC
NORMALIZED TCO VS. TEMP
1.3
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
-40.0
0.0
25.0
75.0
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
NORMALIZED TSU VS. TEMP
1.2
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
22
ATF1502SE
2401D–PLD–09/02
ATF1502SE
DELTA TPD VS.
DELTA TCO VS.
OUTPUT LOADING
OUTPUT LOADING
8
6
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
4
TBD
TBD
2
0
-2
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
DELTA TPD VS. # OF OUTPUT SWITCHING
0.0
-0.1
-0.2
-0.3
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
TBD
TBD
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
23
2401D–PLD–09/02
ATF1502SE(L) Pinouts
44-lead TQFP - Top View
TDI/I/O
I/O
7
8
9
39 I/O
38 I/O/TDO
37 I/O
I/O
GND 10
PD1/I/O 11
I/O 12
36 I/O
35 VCC
34 I/O
ATF1502SE(L)
ATF1504SE(L)
I/O/TMS 13
I/O 14
33 I/O
32 I/O/TCK
31 I/O
VCC 15
I/O 16
30 GND
29 I/O
I/O 17
44-lead PLCC - Top View
I/O/TDI
I/O
1
2
3
4
5
6
7
8
9
33 I/O
32 I/O/TDO
31 I/O
30 I/O
29 VCC
28 I/O
27 I/O
26 I/O/TCK
25 I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
ATF1502SE(L)
ATF1504SE(L)
VCC
I/O 10
I/O 11
24 GND
23 I/O
24
ATF1502SE
2401D–PLD–09/02
ATF1502SE
ATF1502SE(L) Dedicated Pinouts
44-PLCC
J-lead
44-lead
TQFP
Dedicated Pin
INPUT/GCLK1
INPUT/GCLR
INPUT/OE1
43
1
37
39
44
38
INPUT/OE2/GCLK2
I/O/GCLK3
2
40
41
35
I/O/PD (1,2)
I/O/TDI (JTAG)
I/O/TMS (JTAG)
I/O/TCK (JTAG)
I/O/TDO (JTAG)
GNDINT
11, 25
7
5, 19
1
13
7
32
26
38
32
22, 42
10, 30
3, 23
15, 35
36
16, 36
4, 24
17, 41
9, 29
36
GNDIO
VCCINT
VCCIO
# of Signal Pins
# User I/O Pins
32
32
OE (1, 2) Global OE pins
GCLR Global Clear pin
GCLK (1, 2, 3) Global Clock pins
PD (1, 2) Power-down pins
TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming
GNDINT Ground pins for the internal device logic
GNDIO Ground pins for the I/O drivers
VCCINT VCC pins for the internal device logic (+3.3V)
VCCIO VCC for the I/O drivers
25
2401D–PLD–09/02
ATF1502SE(L) I/O Pinouts
MC
PLC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
44-lead PLCC
44-lead TQFP
1
4
42
43
44
1
2
5
3
6
4/TDI
5
7
8
2
6
9
3
7/PD1
8
11
12
13
14
16
17
18
19
20
21
41
40
39
38
37
36
34
33
32
31
29
28
27
26
25
24
5
6
9/TMS
10
7
8
11
10
11
12
13
14
15
35
34
33
32
31
30
28
27
26
25
23
22
21
20
19
18
12
13
14
15
16
17
18
19
20/TDO
21
22
23
24
25/TCK
26
27
28
29
30
31/PD2
32
26
ATF1502SE
2401D–PLD–09/02
ATF1502SE
ATF1502SE(L) Ordering Information
tPD
tCO1
(ns)
FMAX
(ns)
(MHz)
Ordering Code
Package
Operation Range
5.0
6.0
7.5
3.2
3.5
4.3
250
200
167
ATF1502SE-5 AC44
ATF1502SE-5 JC44
44A
44J
Commercial
(0°C to 70°C)
ATF1502SE-6 AC44
ATF1502SE-6 JC44
44A
44J
Commercial
(0°C to 70°C)
ATF1502SE-7 AC44
ATF1502SE-7 JC44
44A
44J
Commercial
(0°C to 70°C)
ATF1502SE-7 AI44
ATF1502SE-7 JI44
44A
44J
Industrial
(-40°C to +85°C)
10
15
5.0
8.0
125
77
ATF1502SE-10 AC44
ATF1502SE-10 JC44
44A
44J
Commercial
(0°C to 70°C)
ATF1502SE-10 AI44
ATF1502SE-10 JI44
44A
44J
Industrial
(-40°C to +85°C)
ATF1502SEL-15 AC44
ATF1502SEL-15 JC44
44A
44J
Commercial
(0°C to 70°C)
Using “C” Product for Industrial
To use commercial product for industrial temperature ranges, downgrade one speed grade from the “I” to the “C” device,
and de-rate power by 30%.
Package Type
44A
44J
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
27
2401D–PLD–09/02
AC Characteristics(1) ATF1504SE(L)
SE -5
SE -6
SE -7
SE -10
SEL -15(6)
Symbol Parameter
tPD1 Input or Feedback to Non-
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
5.0
6.0
7.5
10
15
ns
registered Output
tPD2
I/O Input or Feedback to Non-
registered Feedback
5.0
6.0
7.5
10
12
ns
tSU
tH
Global Clock Setup Time
Global Clock Hold Time
2.9
0.0
2.5
3.6
0.0
2.5
6.0
0.0
3.0
7.0
0.0
3.0
11
0.0
3.0
ns
ns
ns
tFSU
Global Clock Setup Time of Fast
Input
tFH
tCO1
tCH
Global Clock Hold of Fast Input
Global Clock to Output Delay
Global Clock High Time
Global Clock Low Time
Array Clock Setup Time
Array Clock Hold Time
0.0
0.0
0.5
0.5
1.0
ns
ns
3.2
5.4
4.0
6.7
4.5
7.5
5.0
9.0
2.0
2.0
0.7
1.8
2.5
2.5
0.9
2.9
3.0
3.0
2.0
2.0
4.0
4.0
2.0
3.0
5.0
5.0
5.0
4.0
ns
tCL
ns
tASU
tAH
ns
ns
tACO1
tACH
tACL
tCNT
Array Clock Output Delay
Array Clock High Time
10.0
15
ns
2.5
2.5
2.5
2.5
3.0
3.0
4.0
4.0
6.0
6.0
ns
Array Clock Low Time
ns
Minimum Clock Global Period
5.7
5.7
7.1
7.1
8.0
8.0
10
10
13
13
ns
(3)
fCNT
Maximum Internal Global Clock
Frequency
176
141
125
100
77
MHz
tACNT
Minimum Array Clock Period
ns
(4)
fACNT
Maximum Internal Array Clock
Frequency
176
250
141
200
125
167
100
125
77
77
MHz
(5)
fMAX
tIN
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.2
0.2
2.2
3.1
0.9
2.6
2.5
0.7
0.2
0.2
0.2
2.6
3.8
1.1
3.2
3.2
0.8
0.3
0.5
0.5
1.0
4.0
0.8
3.0
3.0
2.0
2.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
1.0
1.0
2.0
8.0
1.0
6.0
6.0
3.0
2.5
tIO
tFIN
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
Foldback Term Delay
Cascade Logic Delay
Logic Array Delay
Logic Control Delay
Internal Output Enable Delay
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO
5V; CL= 35 pF)
=
28
ATF1504SE(L)
2401D–PLD–09/02
ATF1504SE(L)
AC Characteristics(1) ATF1504SE(L) (Continued)
SE -5
SE -6
SE -7
SE -10
SEL -15(6)
Symbol Parameter
Output Buffer and Pad Delay
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tOD2
tOD3
tZX1
tZX2
tZX3
tXZ
0.7
5.2
4.0
4.5
9.0
4.0
0.8
5.3
4.0
4.5
9.0
4.0
2.5
7.0
4.0
4.5
9.0
4.0
2.0
3.0
ns
(slow slew rate = OFF; VCCIO
3.3V; CL= 35 pF)
=
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V
or 3.3V; CL= 35 pF)
5.5
5.0
5.5
9.0
5.0
6.0
7.0
7.0
10
ns
ns
ns
ns
ns
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO
5V; CL= 35 pF)
=
=
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO
3.3V; CL= 35 pF)
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V
or 3.3V; CL= 35 pF)
Output Buffer Disable Delay
(CL= 5 pF)
6.0
tSU
tH
Register Setup Time
Register Hold Time
0.8
1.7
1.9
1.0
2.0
1.8
3.0
2.0
3.0
2.0
3.0
3.0
5.0
4.0
5.0
ns
ns
ns
tFSU
Register Setup Time of Fast
Input
tFH
tRD
tCOMB
tIC
Register Hold Time of Fast Input
Register Delay
0.6
0.7
0.5
0.5
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.2
0.9
2.7
2.6
1.6
2.0
2.0
1.1
8.0
1.6
1.0
3.3
3.2
1.9
2.4
2.4
1.3
9.0
1.0
1.0
3.0
3.0
1.0
2.0
2.0
1.0
1.0
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
11
2.0
2.0
6.0
6.0
2.0
4.0
4.0
2.0
13
Combinatorial Delay
Array Clock Delay
tEN
Register Enable Time
Global Control Delay
Register Preset Time
Register Clear Time
Switch Matrix Delay
Reduced Power Adder
tGLOB
tPRE
tCLR
tUIM
(2)
tRPA
Notes: 1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reduced-
power mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipelined data.
6. For clocked applications and frequencies above fCRITICAL, OR, non-clocked applications with dormant times less than 1/fCRIT-
ICAL, the device will achieve the speeds of the –10 column. See “Input Transition Detection/ Automatic Power Down” on page
8.
29
2401D–PLD–09/02
STAND-BY ICC VS.
NORMALIZED ICC VS. TEMP
SUPPLY VOLTAGE (TA = 25°C)
1.4
1.2
1.0
0.8
0.6
0.4
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY CURRENT VS.
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
1.000
0.800
0.600
0.400
0.200
0.000
140.000
120.000
100.000
80.000
60.000
40.000
20.000
0.000
TBD
TBD
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0
-10
-20
-30
-40
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
TBD
TBD
-50
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
VOH (V)
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
48
46
44
42
40
38
36
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
TBD
TBD
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
30
ATF1504SE(L)
2401D–PLD–09/02
ATF1504SE(L)
INPUT CLAMP CURRENT VS.
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 35°C)
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
40
30
20
10
0
0
-20
-40
TBD
-60
TBD
-80
-10
-20
-30
-100
-120
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
NORMALIZED TPD VS. VCC
NORMALIZED TPD VS. TEMP
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
NORMALIZED TCO VS. VCC
NORMALIZED TCO VS. TEMP
1.3
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
-40.0
0.0
25.0
75.0
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
NORMALIZED TSU VS. TEMP
1.2
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
31
2401D–PLD–09/02
DELTA TPD VS.
DELTA TCO VS.
OUTPUT LOADING
OUTPUT LOADING
8
6
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
4
TBD
TBD
2
0
-2
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
DELTA TPD VS. # OF OUTPUT SWITCHING
0.0
-0.1
-0.2
-0.3
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
TBD
TBD
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
32
ATF1504SE(L)
2401D–PLD–09/02
ATF1504SE(L)
ATF1504SE(L) Pinouts
44-lead TQFP – Top View
I/O/TDI
I/O
1
2
3
4
5
6
7
8
9
33 I/O
32 I/O/TDO
31 I/O
30 I/O
29 VCC
28 I/O
27 I/O
26 I/O/TCK
25 I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
ATF1502SE(L)
ATF1504SE(L)
VCC
I/O 10
I/O 11
24 GND
23 I/O
44-lead PLCC – Top View
TDI/I/O
7
8
9
39 I/O
I/O
I/O
38 I/O/TDO
37 I/O
GND 10
PD1/I/O 11
I/O 12
36 I/O
35 VCC
34 I/O
ATF1502SE(L)
ATF1504SE(L)
I/O/TMS 13
I/O 14
33 I/O
32 I/O/TCK
31 I/O
VCC 15
I/O 16
30 GND
29 I/O
I/O 17
33
2401D–PLD–09/02
84-lead PLCC – Top View
I/O/PD1 12
VCCIO 13
I/O/TDI 14
I/O 15
74 I/O
73 I/O
72 GND
71 I/O/TDO
70 I/O
I/O 16
I/O 17
69 I/O
I/O 18
68 I/O
GND 19
I/O 20
67 I/O
66 VCCIO
65 I/O
I/O 21
ATF1504SE(L)
ATF1508SE(L)
I/O 22
64 I/O
I/O/TMS 23
I/O 24
63 I/O
62 I/O/TCK
61 I/O
I/O 25
VCCIO 26
I/O 27
60 I/O
59 GND
58 I/O
I/O 28
I/O 29
57 I/O
I/O 30
56 I/O
I/O 31
55 I/O
GND 32
54 I/O
100-lead TQFP – Top View
I/O/PD1
I/O
1
2
3
4
5
6
7
8
9
75 I/O
74 GND
73 I/O/TDO
72 I/O
VCCIO
I/O/TDI
I/O
71 I/O
I/O
70 I/O
I/O
69 I/O
I/O
68 I/O
I/O
67 I/O
I/O 10
GND 11
I/O 12
66 VCCIO
65 I/O
64 I/O
I/O 13
63 I/O
ATF1508SE(L)
I/O 14
62 I/O/TCK
61 I/O
I/O/TMS 15
I/O 16
60 I/O
I/O 17
59 GND
58 I/O
VCCIO 18
I/O 19
57 I/O
I/O 20
56 I/O
I/O 21
55 I/O
I/O 22
54 I/O
I/O 23
53 I/O
I/O 24
52 I/O
I/O 25
51 VCCIO
34
ATF1504SE(L)
2401D–PLD–09/02
ATF1504SE(L)
ATF1504SE(L) Dedicated Pinouts
44-lead
44-lead
PLCC
84-lead
PLCC
100-lead
TQFP
Dedicated Pin
INPUT/GCLK1
INPUT/GCLR
INPUT/OE1
TQFP
37
43
1
83
87
89
39
1
38
44
84
88
INPUT/OE2/GCLK2
I/O /GCLK3
40
2
2
90
35
41
81
85
I/O/PD (1,2)
5, 19
1
11, 25
7
20, 46
12, 42
4
I/O/TDI (JTAG)
I/O/TMS (JTAG)
I/O/TCK (JTAG)
I/O/TDO (JTAG)
GNDINT
14
7
13
23
15
26
32
62
71
62
32
38
73
16, 36
4, 24
22, 44
10, 30
42, 82
38, 86
GNDIO
7, 18, 32,47, 69, 72
11, 26, 43,
59, 74, 95
VCCINT
VCCIO
17, 41
9, 29
3, 23
3, 43
39, 91
15, 35
13, 26, 33,
53, 66, 78
3, 18, 34,
51, 66, 82
N/C
-
-
-
1, 2, 5, 7, 22,
24, 27, 28, 49,
50, 53, 55, 70,
72, 77, 78
# of Signal Pins
# User I/O Pins
36
32
36
32
68
64
68
64
OE (1, 2) Global OE pins
GCLR Global Clear pin
GCLK (1, 2, 3) Global Clock pins
PD (1, 2) Power-down pins
TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming
GNDINT Ground pins for the internal device logic
GNDIO Ground pins for the I/O pins
VCCINT VCC pins for the internal device logic
VCCIO VCC for the I/O drivers
35
2401D–PLD–09/02
ATF1504SE(L) I/O Pinouts
44-lead
PLCC
44-lead
TQFP
84-lead
PLCC
100-lead
TQFP
44-lead
PLCC
44-lead
TQFP
84-lead
PLCC
100-lead
TQFP
MC
1
PLC
A
MC
33
PLC
C
12
-
6
-
22
21
14
13
24
-
18
-
44
45
40
41
2
A
34
C
A/
PD1
C/
PD2
3
11
5
20
12
35
25
19
46
42
4
5
6
7
A
A
A
A
9
8
-
3
2
-
18
17
16
15
10
9
36
37
38
39
C
C
C
C
26
27
-
20
21
-
48
49
50
51
44
45
46
47
8
-
-
6
-
-
8/
TDI
A
7
1
14
4
40
C
28
22
52
48
9
A
A
A
A
A
A
A
-
-
-
-
12
11
10
9
100
99
98
97
96
94
93
41
42
43
44
45
46
47
C
C
C
C
C
C
C
29
-
23
-
54
55
56
57
58
60
61
52
54
56
57
58
60
61
10
11
12
13
14
15
6
-
44
-
-
-
-
-
-
-
8
-
-
5
-
43
-
6
31
-
25
-
5
48/
TCK
16
A
4
42
4
92
C
32
26
62
62
17
18
19
20
21
22
23
B
B
B
B
B
B
B
21
-
15
-
41
40
39
37
36
35
34
37
36
35
33
32
31
30
49
50
51
52
53
54
55
D
D
D
D
D
D
D
33
-
27
-
63
64
65
67
68
69
70
63
64
65
67
68
69
71
20
19
18
-
14
13
12
-
34
36
37
-
28
30
31
-
-
-
-
-
56/
TDO
24
B
17
11
33
29
D
38
32
71
73
25
26
27
28
29
30
31
B
B
B
B
B
B
B
16
-
10
-
31
30
29
28
27
25
24
25
23
21
20
19
17
16
57
58
59
60
61
62
63
D
D
D
D
D
D
D
39
-
33
-
73
74
75
76
77
79
80
75
76
79
80
81
83
84
-
-
-
-
-
-
-
-
-
-
-
-
14
-
8
-
40
-
34
-
32/
TMS
D/
GCLK3
B
13
7
23
15
64
41
35
81
85
36
ATF1504SE(L)
2401D–PLD–09/02
ATF1504SE(L)
ATF1504SE(L) Ordering Information
tPD
tCO1
(ns)
fMAX
(ns)
(MHz)
Ordering Code
Package
Operation Range
5.0
6.0
7.5
3.2
4.0
4.5
250
200
167
ATF1504SE-5 AC44
ATF1504SE-5 JC44
ATF1504SE-5 JC84
ATF1504SE-5 AC100
44A
44J
Commercial
(0°C to 70°C)
84J
100A
ATF1504SE-6 AC44
ATF1504SE-6 JC44
ATF1504SE-6 JC84
ATF1504SE-6 AC100
44A
44J
Commercial
(0°C to 70°C)
84J
100A
ATF1504SE-7 AC44
ATF1504SE-7 JC44
ATF1504SE-7 JC84
ATF1504SE-7 AC100
44A
44J
Commercial
(0°C to 70°C)
84J
100A
ATF1504SE-7 AI44
ATF1504SE-7 JI44
ATF1504SE-7 J84
ATF1504SE-7 AI100
44A
44J
Industrial
(-40°C to +85°C)
84J
100A
10
5.0
125
ATF1504SE-10 AC44
ATF1504SE-10 JC44
ATF1504SE-10 JC84
ATF1504SE-10 AC100
44A
44J
Commercial
(0°C to 70°C)
84J
100A
ATF1504SE-10 AI44
ATF1504SE-10 JI44
ATF1504SE-10 JI84
ATF1504SE-10 AI100
44A
44J
Industrial
(-40°C to +85°C)
84J
100A
15
9.0
77
ATF1504SEL-15 AC44
ATF1504SEL-15 JC44
ATF1504SEL-15 JC84
ATF1504SEL-15 AC100
44A
44J
Commercial
(0°C to 70°C)
84J
100A
Using “C” Product for Industrial
To use commercial product for industrial temperature ranges, down grade one speed grade from the “I” to the “C” device,
and de-rate power by 30%.
Package Type
44A
44J
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100A
100-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP)
37
2401D–PLD–09/02
AC Characteristics(1) ATF1508SE(L)
SE -6
SE -7
SE -10
SEL -15(6)
Symbol Parameter
Min
Max
Min
Max
Min
Max
Min
15
15
11
0.0
3.0
1
Max
Unit
ns
tPD1
tPD2
tSU
Input or Feedback to Non-registered Output
I/O Input or Feedback to Non-registered Feedback
Global Clock Setup Time
6
6
7.5
7.5
10
10
ns
3.4
0.0
2.5
0
6.0
0.0
3.0
0.5
7.0
0.0
3.0
0.5
ns
tH
Global Clock Hold Time
ns
tFSU
tFH
tCO1
tCH
Global Clock Setup Time of Fast Input
Global Clock Hold of Fast Input
Global Clock to Output Delay
Global Clock High Time
ns
ns
4.0
6.5
4.5
7.5
5.0
8.0
ns
3
3
3.0
3.0
3.0
2.0
4.0
4.0
2.0
5.0
5.0
5.0
4.0
4.0
ns
tCL
Global Clock Low Time
ns
tASU
tAH
Array Clock Setup Time
0.9
1.8
ns
Array Clock Hold Time
ns
tACO1
tACH
tACL
tCNT
Array Clock Output Delay
10
15
ns
Array Clock High Time
3.0
3.0
3
3
4.0
4.0
6.0
6.0
ns
Array Clock Low Time
ns
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
6.8
6.8
8.0
8.0
10
10
13
13
ns
(3)
fCNT
150
125
100
77
MHz
ns
tACNT
(4)
fACNT
150
167
125
167
100
125
77
MHz
MHz
ns
(5)
fMAX
tIN
100
0.2
0.2
2.6
3.7
1.1
3.0
3.0
0.7
0.4
0.5
0.5
1.0
4.0
0.8
3.0
3.0
2.0
2.0
0.5
0.5
1.0
5.0
0.0
5.0
5.0
2.0
1.5
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
tIO
ns
tFIN
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
Foldback Term Delay
ns
Cascade Logic Delay
ns
Logic Array Delay
ns
Logic Control Delay
ns
Internal Output Enable Delay
ns
Output Buffer and Pad Delay
ns
(slow slew rate = OFF; VCCIO = 5V; CL= 35 pF)
tOD2
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF)
0.9
5.4
2.5
7.0
2.0
5.5
5.0
8.0
ns
ns
tOD3
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
CL= 35 pF)
tZX1
Output Buffer Enable Delay
4.0
4.0
5
6.0
ns
(slow slew rate = OFF; VCCIO = 5V; CL= 35 pF)
38
ATF1508SE(L)
2401D–PLD–09/02
ATF1508SE(L)
AC Characteristics(1) ATF1508SE(L) (Continued)
SE -6
SE -7
SE -10
SEL -15(6)
Symbol Parameter
tZX2 Output Buffer Enable Delay
Min
Max
Min
Max
Min
Max
Min
Max
Unit
4.5
4.5
5.5
7.0
ns
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF)
tZX3
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
CL= 35 pF)
9
4
9
9
5
10.0
6.0
ns
tXZ
tSU
Output Buffer Disable Delay (CL= 5 pF)
Register Setup Time
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.0
1.7
1.9
0.6
3.0
2.0
3.0
0.5
2.0
5.0
3.0
0.5
4.0
4.0
2.0
1.0
tH
Register Hold Time
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
tRD
1.4
1.0
3.1
3.0
2.0
2.4
2.4
1.4
10
1.0
1.0
3.0
3.0
1.0
2.0
2.0
1.0
10
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
11
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
13
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
tEN
Register Enable Time
Global Control Delay
tGLOB
tPRE
tCLR
tUIM
Register Preset Time
Register Clear Time
Switch Matrix Delay
(2)
tRPA
Reduced Power Adder
Notes: 1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reduced-
power mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipelined data.
6. For clocked applications and frequencies above fCRITICAL, OR, non-clocked applications with dormant times less than 1/fCRIT-
ICAL, the device will achieve the speeds of the –10 column. See “Input Transition Detection/ Automatic Power Down” on page
8.
39
2401D–PLD–09/02
STAND-BY ICC VS.
NORMALIZED ICC VS. TEMP
SUPPLY VOLTAGE (TA = 25°C)
1.4
1.2
1.0
0.8
0.6
0.4
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY CURRENT VS.
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
140.000
120.000
100.000
80.000
60.000
40.000
20.000
0.000
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
1.000
0.800
0.600
0.400
0.200
0.000
TBD
TBD
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
OUTPUT SOURCE CURRENT VS.
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
0
-10
-20
-30
-40
TBD
TBD
-50
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
OH (V)
V
OUTPUT SINK CURRENT VS.
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
48
46
44
42
40
38
36
TBD
TBD
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
40
ATF1508SE(L)
2401D–PLD–09/02
ATF1508SE(L)
INPUT CLAMP CURRENT VS.
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 35°C)
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
40
30
20
10
0
0
-20
-40
TBD
-60
TBD
-80
-10
-20
-30
-100
-120
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
NORMALIZED TPD VS. VCC
NORMALIZED TPD VS. TEMP
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
NORMALIZED TCO VS. VCC
NORMALIZED TCO VS. TEMP
1.3
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
-40.0
0.0
25.0
75.0
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
NORMALIZED TSU VS. TEMP
1.2
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
41
2401D–PLD–09/02
DELTA TPD VS.
DELTA TCO VS.
OUTPUT LOADING
OUTPUT LOADING
8
6
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
4
TBD
TBD
2
0
-2
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
DELTA TPD VS. # OF OUTPUT SWITCHING
0.0
-0.1
-0.2
-0.3
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
TBD
TBD
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
42
ATF1508SE(L)
2401D–PLD–09/02
ATF1508SE(L)
ATF1508SE(L) Pinouts
84-lead PLCC – Top View
I/O/PD1 12
74 I/O
VCCIO 13
I/O/TDI 14
I/O 15
73 I/O
72 GND
71 I/O/TDO
70 I/O
I/O 16
I/O 17
69 I/O
I/O 18
68 I/O
GND 19
I/O 20
67 I/O
66 VCCIO
65 I/O
I/O 21
ATF1504SE(L)
ATF1508SE(L)
I/O 22
64 I/O
I/O/TMS 23
I/O 24
63 I/O
62 I/O/TCK
61 I/O
I/O 25
VCCIO 26
I/O 27
60 I/O
59 GND
58 I/O
I/O 28
I/O 29
57 I/O
I/O 30
56 I/O
I/O 31
55 I/O
GND 32
54 I/O
100-lead TQFP – Top View
I/O/PD1
I/O
1
2
3
4
5
6
7
8
9
75 I/O
74 GND
73 I/O/TDO
72 I/O
VCCIO
I/O/TDI
I/O
71 I/O
I/O
70 I/O
I/O
69 I/O
I/O
68 I/O
I/O
67 I/O
I/O 10
GND 11
I/O 12
66 VCCIO
65 I/O
64 I/O
I/O 13
63 I/O
ATF1508SE(L)
I/O 14
62 I/O/TCK
61 I/O
I/O/TMS 15
I/O 16
60 I/O
I/O 17
59 GND
58 I/O
VCCIO 18
I/O 19
57 I/O
I/O 20
56 I/O
I/O 21
55 I/O
I/O 22
54 I/O
I/O 23
53 I/O
I/O 24
52 I/O
I/O 25
51 VCCIO
43
2401D–PLD–09/02
100-lead PQFP – Top View
NC
NC
1
2
3
4
5
6
7
8
9
80 NC
79 NC
78 I/O
77 I/O
76 GND
75 I/O/TDO
74 NC
73 I/O
72 NC
71 I/O
70 I/O
69 I/O
68 VCCIO
67 I/O
66 I/O
65 I/O
64 I/O/TCK
63 I/O
62 I/O
61 GND
60 I/O
59 I/O
58 I/O
57 NC
56 I/O
55 NC
54 I/O
53 VCCIO
52 NC
51 NC
I/O
I/O
VCCIO
I/O/TDI
NC
I/O
NC
I/O 10
I/O 11
I/O 12
GND 13
I/O/PD1 14
I/O 15
I/O 16
I/O/TMS 17
I/O 18
I/O 19
VCCIO 20
I/O 21
I/O 22
I/O 23
NC 24
I/O 25
NC 26
I/O 27
GND 28
NC 29
NC 30
160-lead TQFP – Top View
1
120
ATF1508SE(L)
20
101
44
ATF1508SE(L)
2401D–PLD–09/02
ATF1508SE(L)
ATF1508SE(L) Dedicated Pinouts
84-PLCC J-
Dedicated Pin
INPUT/GCLK1
INPUT/GCLR
INPUT/OE1
INPUT/OE2/GCK2
I/O/GCLK3
Lead
100-pin TQFP
100-pin PQFP
160-lead PQFP
83
87
89
89
91
139
141
140
142
137
63,159
9
1
84
88
90
2
90
92
81
85
87
I/O PD (1,2)
TDI (JTAG)
12, 45
14
1,41
4
3, 43
6
TMS (JTAG)
TCK (JTAG)
TDO (JTAG)
GNDINT
23
15
17
22
62
62
64
99
71
73
75
112
60,138
42, 82
38,86
40,88
GNDIO
7, 19, 32, 47,
59, 72
11, 26, 43, 59,
74, 95
13, 28, 61,
76, 45, 97
17, 42,113, 66, 95,148
61,143
VCCINT
VCCIO
3, 43
39, 91
41,93
13, 26, 38, 53,
66, 78
3, 18, 34, 51,
66, 82
5,20,36,53,68,84
8,26,55,79,104,133
No Connect
-
-
1,2,3,4,5,6,7,34,35,36,
37,38,39,40,44,45,46,
47,74,75,76,77,81,82,
83,84,85,86,87,114,
115,116,117,118,119,
120,124,125,126,127,
154,155,156,157
–
# of Signal pins
68
64
84
80
84
80
100
96
# of User I/O pins
OE (1,2) Global OE pins.
GCLR Global Clear pin.
GCLK (1,2,3) Global Clock pins.
TDI, TMS, TCK, TDO JTAG pins used for In System Programming or Boundary-scan Testing.
GNDINT Ground pins for the internal device logic.
GNDIO Ground pins for the I/O drivers.
VCCINT VCC pins for the internal device logic.
VCCIO VCC pins for the I/O drivers.
45
2401D–PLD–09/02
ATF1508SE(L) I/O Pinouts
84-PLCC
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
84-PLCC
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
MC
1
PLB
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
MC
33
PLB
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
–
–
4
2
–
160
–
–
–
27
–
25
–
41
–
2
–
34
3/PD1
4
12
–
3
1
159
158
153
152
–
35
31
–
26
–
24
–
33
32
31
30
–
–
–
36
5
11
10
–
2
100
99
–
37
30
29
–
25
24
–
23
22
–
6
1
38
7
–
39
8
9
100
99
–
98
97
–
151
150
–
40
28
–
23
22
–
21
20
–
29
28
–
9
–
41
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
–
42
–
8
98
–
96
–
149
147
146
145
–
43
27
–
21
–
19
–
27
25
24
23
–
–
44
6
96
95
–
94
93
–
45
25
24
–
19
18
–
17
16
–
5
46
–
47
4
94
16
–
92
14
–
144
21
–
48/TMS
49
23
41
–
17
39
–
15
37
–
22
59
–
22
–
50
21
–
15
–
13
–
20
19
18
16
–
51
40
–
38
–
36
–
58
57
56
54
–
52
20
–
14
12
–
12
10
–
53
39
–
37
35
–
35
33
–
54
–
55
–
18
17
–
11
10
–
9
15
14
–
56
37
36
–
34
33
–
32
31
–
53
52
–
8
57
–
58
16
–
9
7
13
12
11
10
–
59
35
–
32
–
30
–
51
50
49
48
–
–
–
60
15
–
8
6
61
34
–
31
30
–
29
28
–
7
5
62
–
–
–
63
–
32/
TDI
B/
14
6
4
9
64
D
33
29
27
43
46
ATF1508SE(L)
2401D–PLD–09/02
ATF1508SE(L)
ATF1508SE(L) I/O Pinouts (Continued)
84-PLCC
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
84-PLCC
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
MC
65
PLB
E
MC
97
PLB
G
44
–
42
–
40
–
62
–
63
–
65
–
63
–
100
–
66
E
98
G
E
67/PD2
45
43
41
63
99
G
64
66
64
101
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
E
E
E
E
E
E
E
E
E
E
E
E
E
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
–
46
–
–
44
46
–
–
42
44
–
64
65
67
–
100
101
102
103
104
105
106
107
108
109
110
111
112/TDO
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
G
G
G
G
G
G
G
G
G
G
G
G
G
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
–
65
–
–
67
69
–
–
65
67
–
102
103
105
–
–
–
48
49
–
47
48
–
45
46
–
68
69
–
67
68
–
70
71
–
68
69
–
106
107
–
50
–
49
–
47
–
70
71
72
73
–
69
–
72
–
70
–
108
109
110
111
–
51
–
50
51
–
48
49
–
70
–
73
74
–
71
72
–
–
–
52
–
52
54
–
50
52
–
78
80
–
71
–
75
77
–
73
75
–
112
121
–
–
–
54
–
55
–
53
–
88
89
90
91
–
73
–
78
–
76
–
122
123
128
129
–
55
56
–
56
57
–
54
55
–
74
75
–
79
80
–
77
78
–
57
–
58
59
–
56
57
–
92
93
–
76
–
81
82
–
79
80
–
130
131
–
–
–
58
–
60
–
58
–
94
96
97
98
–
77
–
83
–
81
–
132
134
135
136
–
60
61
–
62
63
–
60
61
–
79
80
–
85
86
–
83
84
–
F/
TCK
96
62
64
62
99
128/GCLK3
H
81
87
85
137
47
2401D–PLD–09/02
ATF1508SE(L) Ordering Information
tPD
tCO1
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
6.0
4.0
4.5
167
ATF1508SE-5 JC84
ATF1508SE-5 AC100
ATF1508SE-5 QC100
ATF1508SE-5 QC160
84J
Commercial
100A
100Q4
160Q1
(0°C to 70°C)
7.5
167
ATF1508SE-7 JC84
ATF1508SE-7 AC100
ATF1508SE-7 QC100
ATF1508SE-7 QC160
84J
Commercial
100A
100Q4
160Q1
(0°C to 70°C)
ATF1508SE-7 JI84
ATF1508SE-7 AI100
ATF1508SE-7 QI100
ATF1508SE-7 QI160
84J
Industrial
100A
100Q4
160Q1
(-40°C to +85°C)
10
5.0
125
ATF1508SE-10 JC84
ATF1508SE-10 AC100
ATF1508SE-10 QC100
ATF1508SE-10 QC160
84J
Commercial
100A
100Q4
160Q1
(0°C to 70°C)
ATF1508SE-10 JI84
ATF1508SE-10 AI100
ATF1508SE-10 QI100
ATF1508SE-10 QI160
84J
Industrial
100A
100Q4
160Q1
(-40°C to +85°C)
15
8.0
100
ATF1508SEL-15 JC84
ATF1508SEL-15 AC100
ATF1508SEL-15 QC100
ATF1508SEL-15 QC160
84J
Commercial
100A
100Q4
160Q1
(0°C to 70°C)
Using “C” Product for Industrial
To use commercial product for industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
and de-rate power by 30%.
Package Type
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100A
100Q4
160Q1
100-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP)
100-lead, Plastic Quad Pin Flat Package (PQFP)
160-lead, Plastic Quad Pin Flat Package (PQFP)
48
ATF1508SE(L)
2401D–PLD–09/02
ATF1516SE(L)
AC Characteristics(1) ATF1516SE(L)
SE -7
SE -10
SEL -15(6)
Symbol Parameter
Min
Max
7.5
Min
Max
Min
Max
15
Unit
ns
tPD1
tPD2
tSU
Input or Feedback to Non-registered Output
I/O Input or Feedback to Non-registered Feedback
Global Clock Setup Time
10
10
7.5
12
ns
3.9
0.0
3.9
0.0
7.0
0.0
3.0
0.5
11
0.0
3.0
1
ns
tH
Global Clock Hold Time
ns
tFSU
tFH
tCO1
tCH
Global Clock Setup Time of Fast Input
Global Clock Hold of Fast Input
Global Clock to Output Delay
Global Clock High Time
ns
ns
4.7
7.3
5.0
8.0
ns
3.0
3.0
0.8
1.9
4.0
4.0
2.0
3.0
1
5.0
5
ns
tCL
Global Clock Low Time
ns
tASU
tAH
Array Clock Setup Time
4.0
4.0
ns
Array Clock Hold Time
ns
tACO1
tACH
tACL
tCNT
Array Clock Output Delay
10
15
ns
Array Clock High Time
3.0
3.0
4
6
6
ns
Array Clock Low Time
4
ns
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
7.8
7.8
10
10
13
13
ns
(3)
fCNT
130
100
77
MHz
ns
tACNT
(4)
fACNT
130
167
100
125
77
MHz
MHz
ns
(5)
fMAX
tIN
100
0.3
0.3
3.4
3.9
1.1
2.6
2.6
0.8
0.5
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
tIO
ns
tFIN
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
Foldback Term Delay
ns
Cascade Logic Delay
ns
Logic Array Delay
ns
Logic Control Delay
ns
Internal Output Enable Delay
ns
Output Buffer and Pad Delay
ns
(slow slew rate = OFF; VCCIO = 5V; CL= 35 pF)
tOD2
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF)
1.0
5.5
2.0
5.5
5.0
8.0
ns
ns
tOD3
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
CL= 35 pF)
tZX1
Output Buffer Enable Delay
4.0
5.0
6.0
ns
(slow slew rate = OFF; VCCIO = 5V; CL= 35 pF)
49
2401D–PLD–09/02
AC Characteristics(1) ATF1516SE(L) (Continued)
SE -7
SE -10
SEL -15(6)
Symbol Parameter
tZX2 Output Buffer Enable Delay
Min
Max
Min
Max
Min
Max
Unit
4.5
5.5
7.0
ns
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF)
tZX3
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35
pF)
9.0
4.0
9.0
10.0
ns
tXZ
tSU
Output Buffer Disable Delay (CL= 5 pF)
Register Setup Time
5.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.1
1.6
2.4
0.6
2.0
3.0
3.0
0.5
4.0
4.0
2.0
1.0
tH
Register Hold Time
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
tRD
1.1
1.1
2.9
2.6
2.8
2.7
2.7
3.0
10
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
11
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
13
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
tEN
Register Enable Time
Global Control Delay
tGLOB
tPRE
tCLR
tUIM
tRPA
Register Preset Time
Register Clear Time
Switch Matrix Delay
Reduced Power Adder(2)
Notes: 1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reduced-
power mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipelined data.
6. For clocked applications and frequencies above fCRITICAL, OR, non-clocked applications with dormant times less than 1/fCRIT-
ICAL, the device will achieve the speeds of the –10 column. See “Input Transition Detection/ Automatic Power Down” on page
8.
50
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
STAND-BY ICC VS.
NORMALIZED ICC VS. TEMP
SUPPLY VOLTAGE (TA = 25°C)
1.4
1.2
1.0
0.8
0.6
0.4
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY CURRENT VS.
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
1.000
0.800
0.600
0.400
0.200
0.000
140.000
120.000
100.000
80.000
60.000
40.000
20.000
0.000
TBD
TBD
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0
-10
-20
-30
-40
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
TBD
TBD
-50
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
VOH (V)
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
48
46
44
42
40
38
36
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
TBD
TBD
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
51
2401D–PLD–09/02
INPUT CLAMP CURRENT VS.
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 35°C)
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
40
30
20
10
0
0
-20
-40
TBD
-60
TBD
-80
-10
-20
-30
-100
-120
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
NORMALIZED TPD VS. VCC
NORMALIZED TPD VS. TEMP
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
NORMALIZED TCO VS. VCC
NORMALIZED TCO VS. TEMP
1.3
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
-40.0
0.0
25.0
75.0
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
NORMALIZED TSU VS. TEMP
1.2
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
52
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
DELTA TPD VS.
DELTA TCO VS.
OUTPUT LOADING
OUTPUT LOADING
8
6
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
4
TBD
TBD
2
0
-2
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
DELTA TPD VS. # OF OUTPUT SWITCHING
0.0
-0.1
-0.2
-0.3
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
TBD
TBD
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
53
2401D–PLD–09/02
ATF1516SE(L) Dedicated Pinouts
208-lead PQFP and RQFP – Top View
1
156
ATF1516SE(L)
26
131
54
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
ATF1516SE(L) Dedicated Pinouts
Dedicated Pin
INPUT/GCLK1
INPUT/GCLR
INPUT/OE1
INPUT/OE2/GCK2
I/O/GCLK3
208-pin PQFP
208-pin RQFP
184
184
182
182
183
183
181
181
TBD
TBD
I/O PD (1,2)
TDI (JTAG)
TBD
TBD
176
176
TMS (JTAG)
TCK (JTAG)
TDO (JTAG)
GNDINT
127
127
30
189
30
189
75, 82, 180, 185
75, 82, 180, 185
GNDIO
14, 32, 50, 72, 94, 116, 134, 152, 174,
200
14, 32, 50, 72, 94, 116, 134, 152, 174,
200
VCCINT
VCCIO
74, 83, 179, 186
74, 83, 179, 186
5, 23, 41, 63, 85, 107, 125, 143, 165, 191 5, 23, 41, 63, 85, 107, 125, 143, 165, 191
No Connect
1,2, 51, 52, 53, 54, 103, 104, 105, 106,
155, 156, 157, 158, 207, 208
1,2, 51, 52, 53, 54, 103, 104, 105, 106,
155, 156, 157, 158, 207, 208
# of Signal pins
164
160
164
160
# of User I/O pins
OE (1,2) Global OE pins.
GCLR Global Clear pin.
GCLK (1,2,3) Global Clock pins.
TDI, TMS, TCK, TDO JTAG pins used for In System Programming or Boundary-scan Testing.
GNDINT Ground pins for the internal device logic.
GNDIO Ground pins for the I/O drivers.
VCCINT VCC pins for the internal device logic.
VCCIO VCC pins for the I/O drivers.
55
2401D–PLD–09/02
ATF1516SE(L) I/O Pinouts
MC
PLB
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
208-pin PQFP
208-pin RQRP
MC
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PLB
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
208-pin PQFP
208-pin RQFP
1
153
-
153
-
108
-
108
-
2
3
154
-
154
-
109
-
109
-
4
5
159
160
-
159
160
-
110
111
-
110
111
-
6
7
8
161
162
-
161
162
-
112
113
-
112
113
-
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
163
-
163
-
114
-
114
-
164
166
-
164
166
-
115
117
-
115
117
-
167
141
-
167
141
-
118
92
-
118
92
-
142
-
142
-
93
-
93
-
144
145
-
144
145
-
95
96
-
95
96
-
146
147
-
146
147
-
97
98
-
97
98
-
148
-
148
-
99
-
99
-
149
150
-
149
150
-
100
101
-
100
101
-
151
151
102
102
56
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
ATF1516SE(L) I/O Pinouts (Continued)
MC
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
PLB
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
F
208-pin PQFP
208-pin RQRP
MC
97
PLB
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
208-pin PQFP
208-pin RQFP
168
-
168
-
119
-
119
-
98
169
-
169
-
99
120
-
120
-
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
170
171
-
170
171
-
121
122
-
121
122
-
172
173
-
172
173
-
123
124
-
123
124
-
175
-
175
-
126
-
126
-
176
177
-
176
177
-
127
128
-
127
128
-
178
130
-
178
130
-
129
79
-
129
79
-
F
F
131
-
131
-
80
-
80
-
F
F
132
133
-
132
133
-
81
84
-
81
84
-
F
F
F
135
136
-
135
136
-
86
87
-
86
87
-
F
F
F
137
-
137
-
88
-
88
-
F
F
138
139
-
138
139
-
89
90
-
89
90
-
F
F
F
140
140
91
91
57
2401D–PLD–09/02
ATF1516SE(L) I/O Pinouts (Continued)
MC
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
PLB
208-pin PQFP
208-pin RQRP
MC
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
PLB
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
L
208-pin PQFP
208-pin RQFP
I
I
197
-
197
-
38
-
38
-
I
196
-
196
-
37
-
37
-
I
I
195
194
-
195
194
-
36
35
-
36
35
-
I
I
I
193
192
-
193
192
-
34
33
-
34
33
-
I
I
I
190
-
190
-
31
-
31
-
I
I
189
188
-
189
188
-
30
29
-
30
29
-
I
I
I
187
27
-
187
27
-
28
78
-
28
78
-
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
L
26
-
26
-
L
77
-
77
-
L
25
24
-
25
24
-
L
76
73
-
76
73
-
L
L
22
21
-
22
21
-
L
71
70
-
71
70
-
L
L
20
-
20
-
L
69
-
69
-
L
19
18
-
19
18
-
L
68
67
-
68
67
-
L
L
17
17
L
66
66
58
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
ATF1516SE(L) I/O Pinouts (Continued)
MC
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
PLB
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
N
208-pin PQFP
208-pin RQRP
MC
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
PLB
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
P
208-pin PQFP
208-pin RQFP
4
-
4
-
49
-
49
-
3
3
48
-
48
-
-
-
206
205
-
206
205
-
47
46
-
47
46
-
204
203
-
204
203
-
45
44
-
45
44
-
202
-
202
-
43
-
43
-
201
199
-
201
199
-
42
40
-
42
40
-
198
16
-
198
16
-
39
65
-
39
65
-
N
P
N
15
-
15
-
P
64
-
64
-
N
P
N
13
12
-
13
12
-
P
62
61
-
62
61
-
N
P
N
P
N
11
10
-
11
10
-
P
60
59
-
60
59
-
N
P
N
P
N
9
9
P
58
-
58
-
N
-
-
P
N
8
8
P
57
56
-
57
56
-
N
7
7
P
N
-
-
P
N
6
6
P
55
55
59
2401D–PLD–09/02
ATF1516SE(L) Ordering Information
tPD
tCO1
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
7.5
10
15
4.7
5.0
8.0
167
125
100
ATF1516SE-7 QC208
ATF1516SE-7 RC208
208Q1
208Q2
Commercial
(0°C to 70°C)
ATF1516SE-7 QI208
ATF1516SE-7 RI208
208Q1
208Q2
Industrial
(-40°C to +85°C)
ATF1516SE-10 QC208
ATF1516SE-10 RC208
208Q1
208Q2
Commercial
(0°C to 70°C)
ATF1516SE-10 QI208
ATF1516SE-10 RI208
208Q1
208Q2
Industrial
(-40°C to +85°C)
ATF1516SEL-15 QC208
ATF1516SEL-15 RC208
208Q1
208Q2
Commercial
(0°C to 70°C)
Using “C” Product for Industrial
To use commercial product for industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device,
and de-rate power by 30%.
Package Type
208Q1
208Q2
208-lead, 28 x 28 mm Body, 2.6 Form Opt., Plastic Quad Flatpack (PQFP)
208-lead, 28 x 28 mm Body, 2.6 Form Opt., Plastic Quad Flatpack with Heat Spreader (PQFP)
60
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
Package Information
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44A
B
R
61
2401D–PLD–09/02
44J – PLCC
1.14(0.045) X 45°
PIN NO. 1
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45° MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
17.399
16.510
17.399
16.510
–
17.653
D1
E
–
16.662 Note 2
17.653
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
16.662 Note 2
16.002
D2/E2 14.986
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
44J
B
R
62
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
84J – PLCC
1.14(0.045) X 45°
PIN NO. 1
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45° MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
30.099
29.210
30.099
29.210
–
30.353
D1
E
–
29.413 Note 2
30.353
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AF.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
29.413 Note 2
28.702
D2/E2 27.686
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
84J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
63
2401D–PLD–09/02
100A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.17
0.09
0.45
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
14.10 Note 2
0.27
C
–
0.20
3. Lead coplanarity is 0.08 mm maximum.
L
–
0.75
e
0.50 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
100A
C
R
64
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
100Q4 – PQFP
D1
D
E
E1
Top View
Bottom View
A2
A1
e
b
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
0.25
2.50
MAX
0.50
2.90
NOM
–
NOTE
SYMBOL
A1
A2
D
5
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing
MS-022, Variation GC-1, for additional information.
2.70
23.20 BSC
20.00 BSC
17.20 BSC
14.00 BSC
0.65 BSC
2
3
2
3
2. To be determined at seating plane.
D1
E
3. Regardless of the relative size of the upper and lower body sections,
dimensions D1 and E1 are determined at the largest feature of the body
exclusive of mold Flash and gate burrs, but including any mismatch
between the upper and lower sections of the molded body.
4. Dimension b does not include Dambar protrusion. The Dambar
protrusion(s) shall not cause the lead width to exceed b maximum by more
than 0.08 mm. Dambar cannot be located on the lower radius or the lead
foot.
E1
e
b
0.22
0.40
4
L1
1.60 REF
5. A1 is defined as the distance from the seating plane to the lowest
point of the package body.
3/29/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
100Q4, 100-lead, 14 x 20 mm Body, 3.2 Form Opt.,
Plastic Quad Flat Pack (PQFP)
100Q4
A
R
65
2401D–PLD–09/02
160Q1 – PQFP
D1
D
E
E1
Top View
Bottom View
A2
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
e
b
L1
MIN
0.25
3.20
MAX
0.50
SYMBOL
NOM
–
NOTE
Side View
A1
A2
D
5
3.40
3.60
31.20 BSC
28.00 BSC
31.20 BSC
28.00 BSC
0.65 BSC
–
2
3
2
3
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing
MS-022, Variation DD-1, for additional information.
D1
E
2. To be determined at seating plane.
3. Regardless of the relative size of the upper and lower body sections,
dimensions D1 and E1 are determined at the largest feature of the body
exclusive of mold Flash and gate burrs, but including any mismatch
between the upper and lower sections of the molded body.
4. Dimension b does not include Dambar protrusion. The Dambar
protrusion(s) shall not cause the lead width to exceed b maximum by more
than 0.08 mm. Dambar cannot be located on the lower radius or the lead
foot.
E1
e
b
0.22
0.40
4
L1
1.60 REF
5. A1 is defined as the distance from the seating plane to the lowest point of
the package body.
3/28/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
160Q1, 160-lead, 28 x 28 mm Body, 3.2 Form Opt.,
Plastic Quad Flat Pack (PQFP)
160Q1
A
R
66
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
208Q1 – PQFP
D1
A2
A1
L1
E1
Side View
e
b
Top View
D
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.25
3.20
MAX
0.50
3.60
NOM
–
NOTE
SYMBOL
A1
A2
D
3.40
E
30.60 BSC
28.00 BSC
30.60 BSC
28.00 BSC
0.50 BSC
–
D1
E
2, 3
2, 3
4
E1
e
b
0.17
0.27
L1
1.30 REF
Bottom View
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-129, Variation FA-1, for proper dimensions, tolerances, datums, etc.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
body size dimensions including mold mismatch.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b
dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion
and an adjacent lead is 0.07 mm.
07/23/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
208Q1, 208-lead (28 x 28 mm Body, 2.6 Form Opt.),
Plastic Quad Flat Pack (PQFP)
208Q1
B
R
67
2401D–PLD–09/02
208Q2 – PQFP
D1
A2
L1
A1
E1
Side View
e
b
Top View
D
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.05
3.20
MAX
0.25
3.60
NOM
–
NOTE
SYMBOL
A1
A2
D
3.40
E
30.60 BSC
28.00 BSC
30.60 BSC
28.00 BSC
0.50 BSC
–
D1
E
2, 3
2, 3
4
E1
e
b
0.17
0.27
L1
1.30 REF
Bottom View
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-129, Variation FA-2, for proper dimensions, tolerances, datums, etc.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
body size dimensions including mold mismatch.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b
dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion
and an adjacent lead is 0.07 mm.
07/23/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
208Q2, 208-lead (28 x 28 mm Body, 2.6 Form Opt.),
Plastic Quad Flat Pack (PQFP)
208Q2
A
R
68
ATF1516SE(L)
2401D–PLD–09/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
Europe
Microcontrollers
Atmel Sarl
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
TEL (41) 26-426-5555
FAX (41) 26-426-5500
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
ASIC/ASSP/Smart Cards
Zone Industrielle
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
Japan
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
FAX 1(719) 540-1759
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL® is the registered trademark of Atmel; Logic Doubling™ is the trademark of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
2401D–PLD–09/02
xM
相关型号:
ATF1502SE-5AC44
EE PLD, 5ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44
ATMEL
ATF1502SE-6AC44
EE PLD, 6ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44
ATMEL
ATF1502SE-7AC44
EE PLD, 7.5ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44
ATMEL
ATF1502SE-7AI44
EE PLD, 7.5ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44
ATMEL
ATF1502SEL-15AC44
EE PLD, 15ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44
ATMEL
©2020 ICPDF网 联系我们和版权申明