ATF1500A-10AU [ATMEL]
Highperformance EPLD; 高性能的EPLD
| 型号： | ATF1500A-10AU |
| 厂家： | 
ATMEL |
| 描述： | Highperformance EPLD |
| 文件： | 总19页 (文件大小：596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-density, High-performance Electrically-erasable Complex
Programmable Logic Device
– 44-pin, 32 I/O CPLD
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation Up to 125 MHz
– Fully Connected Input and Feedback Logic Array
– Backward Compatibility with ATF1500/L Software and Hardware
• Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
High-
performance
EPLD
• Advanced Power Management Features
– Automatic 3 mA Standby (ATF1500AL)
– Pin-controlled 10 mA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-lead PLCC and TQFP Packages
• Advanced Flash Technology
ATF1500A
– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
ATF1500AL
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• Supported by Popular third-arty Tools
• Security Fuse Feature
• Pin-compatible with the Most Commonly Used Devices
• Green (Pb/Halide-fee/RoHS Compliant) Package Options
Description
The ATF1500A is a high-performance, high-density complex PLD. Built on an
advanced Flash technology, it has maximum pin-to-pin delays of 7.5 ns and supports
sequential logic operation at speeds up to 125 MHz. With 32 logic macrocells and up
to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic PLDs.
The ATF1500A’s global input and feedback architecture simplifies logic placement
and eliminates pinout changes due to design changes.
(continued)
Pin Configurations
Pin
PLCC
TQFP
Name
CLK
I
Function
Clock
Top View
Top View
Logic Inputs
Bi-directional
Buffers
I/O
I/O
I/O
7
8
9
39 I/O
38 I/O
37 I/O
36 I/O
35 VCC
34 I/O
33 I/O
32 I/O
31 I/O
30 GND
29 I/O
I/O
I/O
I/O
1
2
3
4
5
6
7
8
9
33 I/O
32 I/O
31 I/O
30 I/O
29 VCC
28 I/O
27 I/O
26 I/O
25 I/O
24 GND
23 I/O
I/O
GND 10
I/O 11
I/O 12
I/O 13
I/O 14
VCC 15
I/O 16
I/O 17
GND
I/O
Register Reset
(active low)
GCLR
I/O
I/O
I/O
OE1,
OE2
Output Enable
(active low)
VCC
I/O 10
I/O 11
VCC
PD
+5V Supply
Rev. 0759F–6/05
Power-down
(active high)
Functional Logic Diagram(1)
Note:
1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.
The ATF1500A has 32 bi-directional I/O pins and four dedi-
cated input pins. Each dedicated input pin can also serve
as a global control signal: register clock, register reset or
output enable. Each of these control signals can be
selected for use individually within each macrocell.
Each of the 32 logic macrocells generates a buried feed-
back, which goes to the global bus. Each input and I/O pin
also feeds into the global bus. Because of this global bus-
ing, each of these signals is always available to all 32 mac-
rocells in the device.
ATF1500A(L)
2
ATF1500A(L)
Each macrocell also generates a foldback logic term, which
goes to a regional bus. All signals within a regional bus are
connected to all 16 macrocells within the region.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
Cascade logic between macrocells in the ATF1500A allows
fast, efficient generation of complex logic functions. The
ATF1500A contains four such logic chains, each capable of
creating sum term logic with a fan-in of up to 40 product
terms.
Design Software Support
ATF1500A designs are supported by several third-party
tools. Automated fitters allow logic synthesis using a variety
of high-level description languages and formats.
Bus-friendly Pin-keeper Input and I/O’s
All Input and I/O pins on the ATF1500A have programma-
ble “pin-keeper” circuits. If activated, when any pin is driven
high or low and then subsequently left floating, it will stay at
that previous high or low level.
Input Diagram
VCC
This circuitry prevents unused Input and I/O lines from
floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The
keeper circuits eliminate the need for external pull-up resis-
tors and eliminate their DC power consumption.
INPUT
100K
Pin-keeper circuits can be disabled. Programming is con-
trolled in the logic design file. Once the pin-keeper circuits
are disabled, normal termination procedures are required
for unused inputs and I/Os.
ESD
PROTECTION
CIRCUIT
PROGRAMMABLE
OPTION
I/O Diagram
Speed/Power Management
The ATF1500A has several built-in speed and power man-
agement features. The ATF1500A contains circuitry that
automatically puts the device into a low-power standby
mode when no logic transitions are occurring. This not only
reduces power consumption during inactive periods, but
also provides proportional power savings for most applica-
tions running at system speeds below 10 MHz.
VCC
OE
DATA
I/O
VCC
All ATF1500As also have an optional pin-controlled power-
down mode. In this mode, current drops to below 10 mA.
When the power-down option is selected, the PD pin is
used to power-down the part. The power-down option is
selected in the design source file. When enabled, the
device goes into power-down when the PD pin is high. In
the power-down mode, all internal logic signals are latched
and held, as are any enabled outputs. All pin transitions are
ignored until the PD is brought low. When the power-down
feature is enabled, the PD cannot be used as a logic input
or output. However, the PD pin’s macrocell may still
be used to generate buried foldback and cascade
logic signals.
100K
PROGRAMMABLE
OPTION
3
ATF1500A(L) Macrocell
ATF1500A Macrocell
The ATF1500A macrocell is flexible enough to support
highly-complex logic functions operating at high speed. The
macrocell consists of five sections: product terms and prod-
uct term select multiplexer, OR/XOR/CASCADE logic, a
flip-flop, output select and enable, and logic array inputs.
routed to the OR gate, creating a five input AND/OR sum
term. With the addition of the CASIN from neighboring
macrocells, this can be expanded to as many as 40 product
terms with little small additional delay.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato-
rial outputs, the fixed level input allows output polarity
selection. For registered functions, the fixed levels allow De
Morgan minimization of the product terms. The XOR gate is
also used to emulate T-type flip-flops.
Product Terms and Select Mux
Each ATF1500A macrocell has five product terms. Each
product term receives as its inputs all signals from both the
global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is deter-
mined by the design compiler that selects the optimum
macrocell configuration.
Flip-flop
The ATF1500A’s flip-flop has very flexible data and control
functions. The data input can come from either the XOR
gate or from a separate product term. Selecting the sepa-
rate product term allows creation of a buried registered
feedback within a combinatorial output macrocell.
OR/XOR/CASCADE Logic
The ATF1500A macrocell’s OR/XOR/CASCADE logic
structure is designed to efficiently support all types of logic.
Within a single macrocell, all the product terms can be
ATF1500A(L)
4
ATF1500A(L)
In addition to D, T, JK and SR operation, the flip-flop can
also be configured as a flow-through latch. In this mode,
data passes through when the clock is high and is latched
when the clock is low.
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configu-
ration all the macrocell resources are still available, includ-
ing the buried feedback, expander and CASCADE logic.
The clock itself can be either the global CLK pin or an indi-
vidual product term. The flip-flop changes state on the
clock’s rising edge. When the CLK pin is used as the clock,
one of the macrocell product terms can be selected as a
clock enable. When the clock enable function is active and
the enable signal (product term) is low, all clock edges are
ignored.
The output enable for each macrocell can also be selected
as either of the two OE pins or as an individual product
term.
Global/Regional Busses
The global bus contains all Input and I/O pin signals as well
as the buried feedback signal from all 32 macrocells.
Together with the complement of each signal, this provides
a 68-bit bus as input to every product term. Having the
entire global bus available to each macrocell eliminates
any potential routing problems. With this architecture
designs can be modified without requiring pinout changes.
The flip-flop’s asynchronous reset signal (AR) can be either
the pin global clear (GCLR), a product term, or always off.
AR can also be a logic OR of GCLR with a product term.
The asynchronous preset (AP) can be a product term or
always off.
Output Select and Enable
The ATF1500A macrocell output can be selected as regis-
tered or combinatorial. When the output is registered, the
same registered signal is fed back internally to the global
bus. When the output is combinatorial, the buried feedback
can be either the same combinatorial signal or it can be the
register output if the separate product term is chosen as
the flip-flop input.
Each macrocell also generates a foldback product term.
This signal goes to the regional bus, and is available to 16
macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 16 foldback terms in each
region allow generation of high fan-in sum terms (up to 21
product terms) with little additional delay.
5
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is VCC + 0.75V DC,
which may overshoot to 5.25V for pulses of less
than 20 ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
DC and AC Operating Conditions
Commercial
0°C - 70°C
5V ± 5%
Industrial
-40°C - 85°C
5V ± 10%
Operating Temperature (ambient)
VCC Power Supply
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
Input or I/O
Low Leakage Current
IIL
0 ≤ VIN ≤ VIL (Max)
-10
µA
Input or I/O
High Leakage Current
IIH
VIH, Min ≤ VIN ≤ VCC
10
µA
Com.
70
mA
mA
mA
mA
ATF1500A
Ind.
100
VCC = Max,
IN = 0, VCC
Power Supply Current,
Standby
(1)
ICC1
V
Com.
Ind.
3
5
ATF1500AL
Power Supply Current,
Pin-Controlled Power
Down Mode
VCC = Max,
VIN = 0, VCC
ICC2
2
10
mA
Output Short Circuit
Current
IOS
VOUT = 0.5V
-130
0.8
mA
V
VCC, Min < VCC
VIL
Input Low Voltage
-0.5
2.0
< VCC, Max
VIH
Input High Voltage
Output Low Voltage
VCC + 1
0.45
V
V
V
V
VOL
VCC = Min
VCC = Min
IOL = 12 mA
IOH = -4 mA
2.4
VOH
Output High Voltage
IOH = -0.2 mA
VCC - 0.2
Note:
1. All ICC parameters measured with outputs open, and a 16-bit loadable, up/down counter programmed into each region.
ATF1500A(L)
6
ATF1500A(L)
AC Waveforms
Register AC Characteristics, Input Pin Clock
-7
-10
-12
-15
-20
-25
Symbol Parameter
Min
Max
4.5
2
Min
2
Max
5
Min
2
Max
6
Min
2
Max
8
Min
2
Max
9
Min
2
Max Units
(1)
tCOS
tCFS
tSIS
Clock to Output
9
2
ns
ns
ns
Clock to Feedback
I, I/O Setup Time
2
2
2
2
6
8
10
11
14
16
Feedback Setup
Time
tSFS
tHS
6
8
10
11
12
13
ns
ns
Input, I/O, Feedback
Hold Time
0
0
0
0
0
0
tPS
Clock Period
6
3
8
4
9
10
5
11
12
6
ns
ns
tWS
Clock Width
4.5
5.5
External Feedback
95
76.9
62.5
52.6
43
40
MHz
1/(tSIS + tCOS
)
fMAXS
Internal Feedback
125
100
125
83.3
111
76.9
100
71
91
66
83
MHz
MHz
ns
1/(tSFS + tCFS
)
No Feedback 1/(tPS
)
166.7
Reset Pin Recovery
Time
tRPRS
2
6
3
9
3
4
5
5
Reset Term
Recovery Time
tRTRS
10
12
13
14
ns
Note:
1. For slow slew outputs, add tSSO
.
7
Register AC Characteristics, Product Term Clock
-7
-10
-12
-15
-20
-25
Symbol Parameter
Min
Max
7.5
5
Min
Max
10
7
Min
Max
12
7
Min
Max
15
9
Min
Max
18
Min
Max Units
(1)
tCOA
tCFA
tSIA
Clock to Output
20
15
ns
ns
ns
Clock to Feedback
I, I/O Setup Time
12
3
3
3
3
4
4
4
4
8
10
15
Feedback Setup
Time
tSFA
tHA
12
ns
ns
Input, I/O, Feedback
Hold Time
2
3
4
4
5
5
tPA
Clock Period
6
3
8
4
10
5
12
6
24
12
30
15
ns
ns
tWA
Clock Width
External Feedback
95.2
76.9
62.5
52.6
38
33.3
MHz
1/(tSIA + tCOA
)
fMAXA
Internal Feedback
125
100
125
90.9
100
76.9
83.3
41.7
41.7
0
33.3
33.3
MHz
MHz
ns
1/(tSFA + tCFA
)
No Feedback 1/(tPA)
166.7
Reset Pin Recovery
Time
tRPRA
0
4
0
5
0
6
0
6
0
8
Reset Term
Recovery Time
tRTRA
7
ns
Note:
1. For slow slew outputs, add tSSO
.
ATF1500A(L)
8
ATF1500A(L)
AC Characteristics
-7
-10
-12
Max
-15
Max
-20
Max
-25
Max
Symbol Parameter
Min
2
Max
7.5
5
Min
3
Max
10
7
Min
3
Min
3
Min
3
Min
3
Units
ns
I, I/O or FB to
Non-Registered
Output
(1)
tPD
12
8
15
9
20
12
20
25
14
25
tPD2
I, I/O to Feedback
ns
Feedback to
Non-Registered
Output
(1)
tPD3
2
7.5
3
10
3
12
3
15
3
3
ns
Feedback to
Feedback
tPD4
5
7
10
10
7
8
12
12
8
9
15
15
9
12
20
20
10
14
25
25
11
ns
ns
ns
ns
OE Term to Output
Enable
(1)
tEA
2
2
7.5
7.5
5.5
3
2
3
2
3
2
3
2
3
2
OE Term to Output
Disable
tER
OE Pin to Output
Enable
(1)
tPZX
tPXZ
tPF
2
2
2
2
2
2
OE Pin to Output
Disable
1.5
5.5
6
1..5
7
9
1.5
8
9
1.5
9
1.5
10
18
23
1.5
11
20
25
ns
ns
ns
Preset to Feedback
12
20
Preset to Registered
Output
(1)
tPO
8.5
12
14
Reset Pin to
Feedback
tRPF
3
5.5
6
4
7
9
3
8
9
5
5.5
13
15
6
ns
ns
ns
Reset Pin to
Registered Output
(1)
tRPO
tRTF
11
12
15
20
Reset Term to
Feedback
Reset Term to
Registered Output
(1)
tRTO
tCAS
tSSO
8.5
0.8
3
12
0.8
3
14
1
20
1
23
1.5
4
25
1.5
4
ns
ns
ns
ns
Cascade Logic Delay
Slow Slew Output
Adder
3
4
tFLD
Foldback Term Delay
4
5
7
8
10
12
Note:
1. For slow slew outputs, add tSSO .
9
Power Down AC Characteristics
-7
-10
-12
-15
-20
-25
Symbol
Parameter
Min
7
Max
Min
10
Max
Min
12
Max
Min
15
Max
Min
20
Max
Min
25
Max Units
Valid I, I/O Before
PD High
tIVDH
ns
Valid OE(2)
Before PD High
tGVDH
tCVDH
tDHIX
7
7
10
10
12
12
15
15
20
20
25
25
ns
ns
Valid Clock(2)
Before PD High
Input Don't Care
After PD High
15
15
15
1
20
20
20
1
22
22
22
1
25
25
25
1
30
30
30
1
35
35
35
1
ns
ns
ns
µs
µs
µs
µs
OE Don't Care
After PD High
tDHGX
tDHCX
tDLIV
Clock Don't Care
After PD High
PD Low to Valid I,
I/O
PD Low to Valid
OE(2)
tDLGV
tDLCV
1
1
1
1
1
1
PD Low to Valid
Clock(2)
1
1
1
1
1
1
PD Low to Valid
Output
(1)
tDLOV
1
1
1
1
1
1
Notes: 1. For slow slew outputs, add tSSO
2. Pin or Product Term.
.
Input Test Waveforms and
Measurement Levels
Output Test Load
3.0V
AC
AC
DRIVING
LEVELS
MEASUREMENT
LEVEL
1.5V
0.0V
t , t ≤ 1.5 ns
r
f
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
Max
5.5
Units
Conditions
VIN = 0V
CIN
4.5
3.5
pF
pF
COUT
4.5
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
ATF1500A(L)
10
ATF1500A(L)
when vectors are run by any approved programmers. The
preload mode is enabled by raising an input pin to a high
voltage level. Contact Atmel PLD Applications for PRE-
LOAD pin assignments, timing and voltage requirements.
Power-up Reset
The ATF1500A’s registers are designed to reset during
power-up. At a point delayed slightly from VCC crossing
V
RST, all registers will be reset to the low state. As a result,
the registered output state will always be low on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic, from below 0.7 volt,
2. After reset occurs, all input and feedback setup times
must be met before driving the clock signal high, and
3. Signals from which clocks are derived must remain sta-
ble during tPR
.
Power-down Mode
The ATF1500A includes an optional pin-controlled power-
down feature. When this mode is enabled, the PD pin acts
as the power down pin. When the PD pin is high, the device
supply current is reduced to less than 10 mA. During
power-down, all output data and internal logic states are
latched and held. Therefore, all registered and combinato-
rial output data remain valid. Any outputs that were in a
high-Z state at the onset of power-down will remain at
high-Z. During power-down, all input signals except the
power-down pin are blocked. Input and I/O hold latches
remain active to ensure that pins do not float to indetermi-
nate levels, further reducing system power. The power-
down pin feature is enabled in the logic design file. Designs
using the power-down pin may not use the PD pin logic
array input. However, all other PD pin macrocell resources
may still be used, including the buried feedback and fold-
back product term array inputs.
Parameter
Description
Typ
Max
Units
Power-up
Reset Time
tPR
2
10
µs
Power-up
Reset
Voltage
VRST
3.8
4.5
V
Output Slew Rate Control
Each ATF1500A macrocell contains a configuration bit for
each I/O to control its output slew rate. This allows selected
data paths to operate at maximum throughput while reduc-
ing system noise from outputs that are not speed-critical.
Outputs default to slow edges, and may be individually set
to fast in the design file. Output transition times for outputs
configured as “slow” have a tSSO delay adder.
Security Fuse Usage
Register Preload
A single fuse is provided to prevent unauthorized copying
of the ATF1500A fuse patterns. Once programmed, fuse
verify and preload are prohibited. However, the 160-bit
User Signature remains accessible.
The ATF1500A’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with preload vectors is compiled. Once downloaded, the
JEDEC file preload sequence will be done automatically
The security fuse should be programmed last, as its effect
is immediate.
11
SUPPLY CURRENT
vs. FREQUENCY
ATF1500AL (VCC = 5V, TA = 25˚C)
NORMALIZED SUPPLY CURRENT
vs. INPUT FREQUENCY
ATF1500A (V = 5V, TA = 25˚C)
cc
ICC mA
ICC
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
ATF1500 (VCC = 5V)
ATF1500 (TA = 25˚C)
ICC
I
CC mA
OUTPUT SOURCE CURRENT
OUTPUT SINK SURRENT
vs. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25˚C)
vs. SUPPLY VOLTAGE (TA = 25˚C, VOL = 0.45V)
IOH
IOL mA
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE (VOH = 2.4V, TA = 25˚C)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE (VCC = 5V, TA = 25˚C)
IOH mA
IOH mA
ATF1500A(L)
12
ATF1500A(L)
NORMALIZED tPD
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE (VCC = 5V, TA = 25˚C)
vs. AMBIENT TEMPERATURE (VCC = 5V)
IOL mA
t
PD
INPUT CLAMP CURRENT
vs. INPUT VOLTAGE
NORMALIZED tCOS
vs. AMBIENT TEMPERATURE (VCC = 5V)
t
COS
INPUT CURRENT vs. INPUT VOLTAGE
(VCC = 5V, TA = 25˚C)
NORMALIZED tCOA
vs. AMBIENT TEMPERATURE (VCC = 5V)
tCOA
NORMALIZED tCOS
vs. SUPPLY VOLTAGE (TA = 25˚C)
t
COS
13
NORMALIZED tSIS
NORMALIZED tSIS
vs. SUPPLY VOLTAGE (TA = 25˚C)
vs. AMBIENT TEMPERATURE (VCC = 5V)
tSIS
tSIS
NORMALIZED tSIA
NORMALIZED tSIA
vs. SUPPLY VOLTAGE (TA = 25˚C)
vs. AMBIENT TEMPERATURE (VCC = 5V)
t
SIA
tSIA
ATF1500A(L)
14
ATF1500A(L)
Ordering Information
Standard Package Options
tPD
(ns)
tCOS
(ns)
fMAX
(MHz)
Ordering Code
Package
Operation Range
ATF1500A-7AC
ATF1500A-7JC
44A
44J
Commercial
7.5
10
4.5
5
95
(0°C to 70°C)
ATF1500A-10AC
ATF1500A-10JC
44A
44J
Commercial
(0°C to 70°C)
76.9
ATF1500A-10AI
ATF1500A-10JI
44A
44J
Industrial
(-40°C to 85°C)
ATF1500A-12AC
ATF1500A-12JC
44A
44J
Commercial
(0°C to 70°C)
12
15
20
6
8
9
62.5
52.6
40
ATF1500A-12AI
ATF1500A-12JI
44A
44J
Industrial
(-40°C to 85°C)
ATF1500A-15AC
ATF1500A-15JC
44A
44J
Commercial
(0°C to 70°C)
ATF1500A-15AI
ATF1500A-15JI
44A
44J
Industrial
(-40°C to 85°C)
ATF1500AL-20AC
ATF1500AL-20JC
44A
44J
Commercial
(0°C to 70°C)
ATF1500AL-20AI
ATF1500AL-20JI
44A
44J
Industrial
(-40°C to 85°C)
Note:
1. The last time buy date is Sept. 30, 2005 for shaded parts. The replacements for fast-speed grade is the ATF1502AS (pin
compatible). For others, suggested replacements are available in Green packages.
2. The ATF1500AL-25AC, -25AI, -25JC and -25JI were obsoleted in August 1999. The replacement was the ATF1500AL-20.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
tCOS
(ns)
fMAX
(MHz)
Ordering Code
Package
Operation Range
ATF1500A-10AU
ATF1500A-10JU
44A
44J
Industrial
10
20
5
9
76.9
40
(-40°C to 85°C)
ATF1500AL-20AU
ATF1500AL-20JU
44A
44J
Industrial
(-40°C to 85°C)
Package Type
44A
44J
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
15
Packaging Information
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44A
B
R
ATF1500A(L)
16
ATF1500A(L)
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
17.399
16.510
17.399
16.510
–
17.653
D1
E
–
16.662 Note 2
17.653
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
16.662 Note 2
16.002
D2/E2 14.986
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
44J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
17
Revision History
Revision
Comments
Green package options added.
0759F
ATF1500A(L)
18
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
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Tel: 1(719) 576-3300
Europe
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Tel: (41) 26-426-5555
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Fax: 1(719) 540-1759
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Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
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Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Asia
Room 1219
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Tel: (852) 2721-9778
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Tel: (33) 4-42-53-60-00
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Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
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Printed on recycled paper.
0759F–6/05/xM
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