ATA5745-PXPW [ATMEL]
UHF ASK/FSK Receiver; 超高频ASK / FSK接收器
| 型号： | ATA5745-PXPW |
| 厂家： | 
ATMEL |
| 描述： | UHF ASK/FSK Receiver |
| 文件： | 总44页 (文件大小：739K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Transparent RF Receiver ICs for 315 MHz (ATA5746) and 433.92 MHz (ATA5745) With
High Receiving Sensitivity
• Fully Integrated PLL With Low Phase Noise VCO, PLL, and Loop Filter
• High FSK/ASK Sensitivity:–105 dBm (ATA5746, FSK, 9.6 Kbits/s, Manchester, BER 10-3)
–114 dBm (ATA5746, ASK, 2.4 Kbits/s, Manchester, BER 10-3)
–104 dBm (ATA5745, FSK, 9.6 Kbits/s, Manchester, BER 10-3)
–113 dBm (ATA5745, ASK, 2.4 Kbits/s, Manchester, BER 10-3)
• Supply Current: 6.5 mA in Active Mode (3V, 25°C, ASK Mode)
• Data Rate: 1 Kbit/s to 10 Kbits/s Manchester ASK, 1 Kbit/s to 20 Kbits/s Manchester
FSK With Four Programmable Bit Rate Ranges
UHF ASK/FSK
Receiver
• Switching Between Modulation Types ASK/FSK and Different Data Rates Possible in
≤1 ms Typically, Without Hardware Modification on Board to Allow Different Modulation
Schemes for RKE, TPMS
• Low Standby Current: 50 µA at 3V, 25°C
ATA5745
ATA5746
• ASK/FSK Receiver Uses a Low-IF Architecture With High Selectivity, Blocking, and
Low Intermodulation (Typical 3-dB Blocking 68.0 dBC at ±3 MHz/74.0 dBC at
±20.0 MHz, System I1dBCP = –31 dBm/System IIP3 = –24 dBm)
• Telegram Pause Up to 52 ms Supported in ASK Mode
• Wide Bandwidth AGC to Handle Large Out-of-band Blockers above the System I1dBCP
• 440-kHz IF Frequency With 30-dB Image Rejection and 420-kHz IF Bandwidth to
Support PLL Transmitters With Standard Crystals or SAW-based Transmitters
• RSSI (Received Signal Strength Indicator) With Output Signal Dynamic Range of 65 dB
• Low In-band Sensitivity Change of Typically ±2.0 dB Within ±160-kHz Center
Frequency Change in the Complete Temperature and Supply Voltage Range
• Sophisticated Threshold Control and Quasi-peak Detector Circuit in the Data Slicer
• Fast and Stable XTO Start-up Circuit (> –1.4 kΩWorst-case Start Impedance)
• Clock Generation for Microcontroller
Preliminary
• ESD Protection at all Pins (±4 kV HBM, ±200V MM, ±500V FCDM)
• Dual Supply Voltage Range: 2.7V to 3.3V or 4.5V to 5.5V
• Temperature Range: –40°C to +105°C
• Small 5 mm × 5 mm QFN24 Package
Applications
• Automotive Keyless Entry and Tire Pressure Monitoring Systems
• Alarm, Telemetering and Energy Metering Systems
Benefits
• Supports Header and Blanking Periods of Protocols Common in RKE and TPM
Systems (Up to 52 ms in ASK Mode)
• All RF Relevant Functions are Integrated. The Single-ended RF Input is Suited for Easy
Adaptation to λ / 4 or Printed-loop Antennas
• Allows a Low-cost Application With Only 8 Passive Components
• Suitable for use in a Receiver for Joint RKE and TPMS
• Optimal Bandwidth Maximizes Sensitivity while Maintaining SAW Transmitter
Compatibility
• Clock Output Provides an External Microcontroller Crystal-precision Time Reference
• Well Suited for Use With PLL Transmitter ATA5756/ATA5757
4596B–RKE–06/07
1. General Description
The ATA5745/ATA5746 is a UHF ASK/FSK transparent receiver IC with low power consumption
supplied in a small QFN24 package (body 5 mm × 5 mm, pitch 0.65 mm). ATA5745 is used in
the 433 MHz to 435 MHz band of operation, and ATA5746 in 313 MHz to 317 MHz. The IC com-
bines the functionality of remote keyless entry (RKE - typically low bit rate ASK) and tire
pressure monitoring (TPM - typically high bit rate FSK) into one receiver under the control of an
external microcontroller such as an ATmega48 (AVR®).
For improved image rejection and selectivity, the IF frequency is fixed to 440 kHz. The IF block
uses an 8th-order band pass yielding a receive bandwidth of 420 kHz. This enables the use of
the receiver in both SAW- and PLL-based transmitter systems utilizing various types of data-bit
encoding such as pulse width modulation, Manchester modulation, variable pulse modulation,
pulse position modulation, and NRZ. Prevailing encryption protocols such as Keeloq® are easily
supported due to the receiver’s ability to hold the current data slicer threshold for up to 52 ms
when incoming RF telegrams contain a blanking interval. This feature eliminates erroneous
noise from appearing on the demodulated data output pin, and simplifies software decoding
algorithms. The decoding of the data stream must be carried out by a connected microcontroller
device. Because of the highly integrated design, the only required RF components are for the
purpose of receiver antenna matching.
ATA5745 and ATA5746 support Manchester bit rates of 1 Kbit/s to 10 Kbits/s in ASK and 1 Kbit/s
to 20 Kbits/s in FSK mode. The four discrete bit rate passbands are selectable and cover
1.0 Kbit/s to 2.5 Kbits/s, 2.0 Kbits/s to 5.0 Kbits/s, 4.0 Kbits/s to 10.0 Kbits/s, and 8.0 Kbits/s to
10.0 Kbits/s or 20.0 Kbits/s (for ASK or FSK, respectively). The receiver contains an RSSI output
to provide an indication of received signal strength and a SENSE input to allow the customer to
select a threshold below which the DATA signal is gated off. ASK/FSK and bit rate ranges are
selected by the connected microcontroller device via pins ASK_NFSK, BR0, and BR1.
Figure 1-1. System Block Diagram
ATA5745/ATA5746
Digital Control
Logic
Power
Supply
Antenna
RF Receiver
Microcontroller
4 ... 8
(LNA, Mixer,
VCO, PLL,
IF Filter,
Microcontroller
Interface
RSSI Amp.,
Demodulator)
XTO
2
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
Figure 1-2. Pinning QFN24
24 23 22 21 20 19
18
TEST2
TEST1
1
2
3
4
5
6
TEST3
17
16
15
14
13
RSSI
CLK_OUT
SENSE_CTRL
SENSE
CLK_OUT_CTRL1
CLK_OUT_CTRL0
ENABLE
LNA_IN
LNA_GND
7
8
9 10 11 12
Table 1-1.
Pin Description
Symbol
Pin
1
Function
TEST2
Test pin, during operation at GND
Test pin, during operation at GND
2
TEST1
3
CLK_OUT
CLK_OUT_CTRL1
CLK_OUT_CTRL0
ENABLE
XTAL2
Output to clock a connected microcontroller
Input to control CLK_OUT (MSB)
Input to control CLK_OUT (LSB)
Input to enable the XTO
4
5
6
7
Reference crystal
8
XTAL1
Reference crystal
9
DVCC
Digital voltage supply blocking
Power supply input for voltage range 4.5V to 5.5V
Power supply input for voltage range 2.7V to 3.3V
Ground
10
11
12
13
14
15
VS5V
VS3V_AVCC
GND
LNA_GND
LNA_IN
RF ground
RF input
SENSE
Sensitivity control resistor
Sensitivity selection
Low: Normal sensitivity, High: Reduced sensitivity
16
SENSE_CTRL
17
18
19
20
21
RSSI
TEST3
RX
Output of the RSSI amplifier
Test pin, during operation at GND
Input to activate the receiver
Bit rate selection, LSB
BR0
BR1
Bit rate selection, MSB
FSK/ASK selection
Low: FSK, High: ASK
22
ASK_NFSK
23
24
CDEM
DATA_OUT
GND
Capacitor to adjust the lower cut-off frequency data filter
Data output
Ground/backplane (exposed die pad)
3
4596B–RKE–06/07
Figure 1-3. Block Diagram
ASK
FSK
ASK/FSK
Demo-
dulator
VS3V_AVCC
VS5V
Power
Supply
CDEM
ASK/FSK
Control
ASK_NFSK
IF Amp
SENSE
Data
DATA_OUT
BR0
Slicer
SENSE_CTRL
IF Filter
LPF
BR1
GND
Standby
Logic Control
RX
CLK_OUT_CTRL1
CLK_OUT_CTRL0
CLK_OUT
XTO
Div. by 3, 6, 12
DVCC
IF Amp
LPF
RSSI
PLL
(/24, /32)
XTO
ENABLE
TEST1
TEST2
TEST3
LNA_IN
LNA
VCO
LNA_GND
XTAL2
XTAL1
4
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
2. RF Receiver
As seen in Figure 1-3 on page 4, the RF receiver consists of a low-noise amplifier (LNA), a local
oscillator, and the signal processing part with mixer, IF filter, IF amplifier with analog RSSI,
FSK/ASK demodulator, data filter, and data slicer.
In receive mode, the LNA pre-amplifies the received signal which is converted down to a
440-kHz intermediate frequency (IF), then filtered and amplified before it is fed into an FSK/ASK
demodulator, data filter, and data slicer. The received signal strength indicator (RSSI) signal is
available at the pin RSSI.
2.1
Low-IF Receiver
The receive path consists of a fully integrated low-IF receiver. It fulfills the sensitivity, blocking,
selectivity, supply voltage, and supply current specification needed to design an automotive inte-
grated receiver for RKE and TPM systems. A benefit of the integrated receive filter is that no
external components needed.
At 315 MHz, the ATA5745 receiver (433.92 MHz for the ATA5746 receiver) has a typical system
noise figure of 6.0 dB (7.0 dB), a system I1dBCP of –31 dBm (–30 dBm), and a system IIP3 of
–24 dBm (–23 dBm). The signal path is linear for out-of-band disturbers up to the I1dBCP and
hence there is no AGC or switching of the LNA needed, and a better blocking performance is
achieved. This receiver uses an IF (intermediate frequency) of 440 kHz, the typical image rejec-
tion is 30 dB and the typical 3-dB IF filter bandwidth is 420 kHz (fIF = 440 kHz ± 210 kHz,
flo_IF = 230 kHz and fhi_IF = 650 kHz). The demodulator needs a signal-to-noise ratio of 8.5 dB for
10 Kbits/s Manchester with ±38 kHz frequency deviation in FSK mode, thus, the resulting sensi-
tivity at 315 MHz (433.92 MHz) is typically –105 dBm (–104 dBm).
Due to the low phase noise and spurs of the synthesizer together with the 8th-order integrated IF
filter, the receiver has a better selectivity and blocking performance than more complex double
superhet receivers, without using external components and without numerous spurious receiv-
ing frequencies.
A low-IF architecture is also less sensitive to second-order intermodulation (IIP2) than direct
conversion receivers where every pulse or amplitude modulated signal (especially the signals
from TDMA systems like GSM) demodulates to the receiving signal band at second-order
non-linearities.
5
4596B–RKE–06/07
2.2
Input Matching at LNA_IN
The measured input impedances as well as the values of a parallel equivalent circuit of these
impedances can be seen in Table 2-1. The highest sensitivity is achieved with power matching
of these impedances to the source impedance.
Table 2-1.
Measured Input Impedances of the LNA_IN Pin
fRF [MHz]
ZIn(RF_IN) [Ω]
(72.4 – j298)
(55 – j216)
RIn_p//CIn_p [pF]
1300Ω//1.60
900Ω//1.60
315
433.92
The matching of the LNA input to 50Ω is done using the circuit shown in Figure 2-1 and the val-
ues of the matching elements given in Table 2-2. The reflection coefficients were always
≤ –10 dB. Note that value changes of C1 and L1 may be necessary to compensate individual
board layout parasitics. The measured typical FSK and ASK Manchester-code sensitivities with
a bit error rate (BER) of 10–3 are shown in Table 2-3 and Table 2-4 on page 7. These measure-
ments were done with wire-wound inductors having quality factors reported in Table 2-2,
resulting in estimated matching losses of 0.8 dB at 315 MHz and 433.92 MHz. These losses can
be estimated when calculating the parallel equivalent resistance of the inductor with
R
loss = 2 × π × f × L × QL and the matching loss with 10 log(1+RIn_p / Rloss).
Figure 2-1. Input Matching to 50Ω
ATA5745/ATA5746
RFIN
C1
14
LNA_IN
L1
Table 2-2.
Input Matching to 50Ω
fRF [MHz]
C1 [pF]
2.2
L1 [nH]
68
QL1
20
315
433.92
2.2
36
15
6
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
Table 2-3.
Measured Typical Sensitivity FSK, ±38 kHz, Manchester, BER = 10–3
BR_Range_0
1.0 Kbit/s
BR_Range_0
2.5 Kbits/s
BR_Range_1
5 Kbits/s
BR_Range_2
10 Kbits/s
BR_Range_3
10 Kbits/s
BR_Range_3
20 Kbits/s
RF Frequency
315 MHz
–108 dBm
–107 dBm
–108 dBm
–107 dBm
–107 dBm
–106 dBm
–105 dBm
–104 dBm
–104 dBm
–103 dBm
–104 dBm
–103 dBm
433.92 MHz
Table 2-4.
Measured Typical Sensitivity 100% ASK, Manchester, BER = 10–3
BR_Range_0
1.0 Kbit/s
BR_Range_0
2.5 Kbits/s
BR_Range_1
5 Kbits/s
BR_Range_2
10 Kbits/s
BR_Range_3
RF Frequency
315 MHz
10 Kbits/s
–109 dBm
–108 dBm
–114 dBm
–113 dBm
–114 dBm
–113 dBm
–113 dBm
–112 dBm
–111 dBm
–110 dBm
433.92 MHz
Conditions for the sensitivity measurement:
The given sensitivity values are valid for Manchester-modulated signals. For the sensitivity mea-
surement the distance from edge to edge must be evaluated. As can be seen in Figure 6-1 on
page 24, in a Manchester-modulated data stream, the time segments TEE and 2 × TEE occur.
To reach the specified sensitivity for the evaluation of TEE and 2 × TEE in the data stream, the
following limits should be used (TEE min, TEE max, 2 × TEE min, 2 × TEE max).
Table 2-5.
Bit Rate
Limits for Sensitivity Measurements
TEE Min
260 µs
110 µs
55 µs
TEE Typ
500 µs
208 µs
100 µs
52 µs
TEE Max
790 µs
310 µs
155 µs
78 µs
2 × TEE Min
800 µs
2 × TEE Typ
1000 µs
416 µs
2 × TEE Max
1340 µs
525 µs
1.0 Kbit/s
2.4 Kbits/s
5.0 Kbits/s
9.6 Kbits/s
320 µs
160 µs
200 µs
260 µs
27 µs
81 µs
104 µs
131 µs
2.3
Sensitivity Versus Supply Voltage, Temperature and Frequency Offset
To calculate the behavior of a transmission system, it is important to know the reduction of the
sensitivity due to several influences. The most important are frequency offset due to crystal
oscillator (XTO) and crystal frequency (XTAL) errors, temperature and supply voltage depen-
dency of the noise figure, and IF-filter bandwidth of the receiver. Figure 2-2 and Figure 2-3 on
page 8 show the typical sensitivity at 315 MHz, ASK, 2.4 Kbits/s and 9.6 Kbits/s, Manchester,
Figure 2-4 and Figure 2-5 on page 9 show a typical sensitivity at 315 MHz, FSK, 2.4 Kbits/s and
9.6 Kbits/s, ±38 kHz, Manchester versus the frequency offset between transmitter and receiver
at Tamb = –40°C, +25°C, and +105°C and supply voltage VS = VS3V_AVCC = VS5V = 2.7V,
3.0V and 3.3V.
7
4596B–RKE–06/07
Figure 2-2. Measured Sensitivity (315 MHz, ASK, 2.4 Kbits/s, Manchester) Versus Fre-
quency Offset
Input Sensitivity (dBm) at BER < 1e-3, ATA5746, ASK, 2.4 Kbits/s (Manchester),
BR = 0
-118.00
-117.00
-116.00
-115.00
-114.00
2.7V / -40˚C
-113.00
3.0V / -40˚C
-112.00
3.3V / -40˚C
2.7V / 27˚C
3.0V / 27˚C
3.3V / 27˚C
2.7V / 105˚C
3.0V / 105˚C
3.3V / 105˚C
-111.00
-110.00
-109.00
-108.00
-107.00
-106.00
-105.00
-104.00
-103.00
-300
-200
-100
0
100
200
300
delta RF (kHz) at 315 MHz
Figure 2-3. Measured Sensitivity (315 MHz, ASK, 9.6 Kbits/s, Manchester) Versus Fre-
quency Offset
Input Sensitivity (dBm) at BER < 1e-3, ATA5746, ASK, 9.6 Kbits/s (Manchester),
BR = 2
-115.00
-114.00
-113.00
-112.00
-111.00
-110.00
2.7V / -40˚C
-109.00
-108.00
-107.00
-106.00
-105.00
-104.00
-103.00
-102.00
-101.00
-100.00
3.0V / -40˚C
3.3V / -40˚C
2.7V / 27˚C
3.0V / 27˚C
3.3V / 27˚C
2.7V / 105˚C
3.0V / 105˚C
3.3V / 105˚C
-300
-200
-100
0
100
200
300
delta RF (kHz) at 315 MHz
8
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
Figure 2-4. Measured Sensitivity (315 MHz, FSK, 2.4 Kbits/s, ±38 kHz, Manchester) Versus
Frequency Offset
Input Sensitivity (dBm) at BER < 1e-3, ATA5746, FSK, 2.4 Kbits/s
(Manchester), BR0
-112.00
-111.00
-110.00
-109.00
-108.00
-107.00
2.7V / -40˚C
3.0V / -40˚C
-106.00
3.3V / -40˚C
2.7V / 27˚C
3.0V / 27˚C
3.3V / 27˚C
2.7V / 105˚C
3.0V / 105˚C
3.3V / 105˚C
-105.00
-104.00
-103.00
-102.00
-101.00
-100.00
-99.00
-98.00
-300
-200
-100
0
100
200
300
delta RF (kHz) at 315 MHz
Figure 2-5. Measured Sensitivity (315 MHz, FSK, 9.6 Kbits/s, ±38 kHz, Manchester) Versus
Frequency Offset
Input Sensitivity (dBm) at BER < 1e-3, ATA5746, FSK, 9.6 Kbits/s (Manchester),
BR = 2
-110.00
-109.00
-108.00
-107.00
2.7V / -40˚C
-106.00
-105.00
-104.00
-103.00
-102.00
-101.00
-100.00
-99.00
-98.00
-97.00
-96.00
3.0V / -40˚C
3.3V / -40˚C
2.7V / 27˚C
3.0V / 27˚C
3.3V / 27˚C
2.7V / 105˚C
3.0V / 105˚C
3.3V / 105˚C
-95.00
-300
-200
-100
0
100
200
300
delta RF (kHz) at 315 MHz
9
4596B–RKE–06/07
As can be seen in Figure 2-5 on page 9, the supply voltage has almost no influence. The tem-
perature has an influence of about ±1.0 dB, and a frequency offset of ±160 kHz also influences
by about ±1 dB. All these influences, combined with the sensitivity of a typical IC (–105 dB), are
then within a range of –103.0 dBm and –107.0 dBm over temperature, supply voltage, and fre-
quency offset. The integrated IF filter has an additional production tolerance of ±10 kHz, hence,
a frequency offset between the receiver and the transmitter of ±160 kHz can be accepted for
XTAL and XTO tolerances.
Note:
For the demodulator used in the ATA5745/ATA5746, the tolerable frequency offset does not
change with the data frequency. Hence, the value of ±160 kHz is valid for 1 Kbit/s to 10 Kbits/s.
This small sensitivity change over supply voltage, frequency offset, and temperature is very
unusual in such a receiver. It is achieved by an internal, very fast, and automatic frequency cor-
rection in the FSK demodulator after the IF filter, which leads to a higher system margin. This
frequency correction tracks the input frequency very quickly. If, however, the input frequency
makes a larger step (for example, if the system changes between different communication part-
ners), the receiver has to be restarted. This can be done by switching back to Standby mode
and then again to Active mode (pin RX 1 →0 →1) or by generating a positive pulse on pin
ASK_NFSK (0 →1 →0).
2.4
Frequency Accuracy of the Crystals in a Combined RKE and TPM System
In a tire pressure measurement system working at 315 MHz and using an ATA5756 as transmit-
ter and an ATA5746 is receiver, the higher frequency tolerances and the tolerance of the
frequency deviation of the transmitter has to be considered.
In the TPM transmitter, the crystal has a frequency error over temperature –40°C to 125°C,
aging, and tolerance of ±80 ppm (±25.2 kHz at 315 MHz). The tolerances of the XTO, the
capacitors used for FSK modulation, and the stray capacitances cause an additional frequency
error of ±30 ppm (±9.45 kHz at 315 MHz). The frequency deviation of such a transmitter varies
between ±16 kHz and ±24 kHz, since a higher frequency deviation is equivalent to a frequency
error this has to be considered as an additional ±24 kHz – ±19.5 kHz = ±4.5kHz frequency toler-
ance (19.5 kHz is constant). All tolerances added, these transmitters have a worst-case
frequency offset of ±39.15 kHz.
For the receiver in the car, a tolerance of ±160 kHz – ±39.15 kHz = ±120.85 kHz (±383.6 ppm)
remains. The needed frequency stability of the crystals over temperature and aging is
±383.6 ppm – ±5 ppm = ±378.6 ppm. The aging of such a crystal is ±10 ppm, leaving a reason-
able ±368.6 ppm for the temperature dependency of the crystal frequency in the car.
Since the receiver in the car is able to receive these TPM transmitter signals with high frequency
offsets, the component specification in the key can be largely relaxed.
This system calculation is based on worst-case tolerances of all the components; this leads in
practice to a system with margin.
For a 433.92 MHz TPM system using ATA5757 as transmitter and ATA5745 as receiver, the
same calculation must be done, but since the RF frequency is higher, every ppm of crystal toler-
ances results in higher frequency offset and either the system must have lower tolerances or a
lower margin at this frequency.
10
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
2.5
RX Supply Current Versus Temperature and Supply Voltage
Table 2-7 shows the typical supply current of the receiver in Active mode versus supply voltage
and temperature with VS = VS3V_AVCC = VS5V.
Table 2-6.
Measured Current in Active Mode ASK
VS = VS3V_AVCC = VS5V
Tamb = –40°C
2.7V
3.0V
3.3V
5.4 mA
6.4 mA
7.4 mA
5.5 mA
6.5 mA
7.5 mA
5.6 mA
6.6 mA
7.6 mA
Tamb = 25°C
Tamb = 105°C
Table 2-7.
Measured Current in Active Mode FSK
VS = VS3V_AVCC = VS5V
Tamb = –40°C
2.7V
3.0V
3.3V
5.6 mA
6.6 mA
7.6 mA
5.7 mA
6.7 mA
7.7 mA
5.8 mA
6.8 mA
7.8 mA
Tamb = 25°C
Tamb = 105°C
2.6
Blocking, Selectivity
As can be seen in Figure 2-6 on page 11, and Figure 2-7 and Figure 2-8 on page 12, the
receiver can receive signals 3 dB higher than the sensitivity level in the presence of large block-
ers of –34.5 dBm or –28 dBm with small frequency offsets of ±3 MHz or ±20 MHz.
Figure 2-6, and Figure 2-7 on page 12 show the narrow-band blocking, and Figure 2-8 on page
12 shows the wide-band blocking characteristic. The measurements were done with a useful
signal of 315 MHz, FSK, 10 Kbits/s, ±38 kHz, Manchester, BR_Range2 with a level of
–105 dBm + 3 dB = –102 dBm, which is 3 dB above the sensitivity level. The figures show how
much larger than –102 dBm a continuous wave signal can be, until the BER is higher than 10–3.
The measurements were done at the 50Ω input shown in Figure 2-1 on page 6. At 3 MHz, for
example, the blocker can be 67.5 dBC higher than –102 dBm, or
–102 dBm + 67.5 dBC = –34.5 dBm.
Figure 2-6. Close-in 3-dB Blocking Characteristic and Image Response at 315 MHz
70.0
60.0
50.0
40.0
30.0
20.0
10 . 0
0.0
-10.0
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
Distance from Interfering to Receiving Signal (MHz)
11
4596B–RKE–06/07
Figure 2-7. Narrow-band 3-dB Blocking Characteristic at 315 MHz
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10 . 0
0.0
-10.0
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
Distance from Interfering to Receiving Signal (MHz)
Figure 2-8. Wide-band 3-dB Blocking Characteristic at 315 MHz
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10 . 0
0.0
-10.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
10.0
20.0
30.0
40.0
50.0
Distance from Interfering to Receiving Signal (MHz)
Table 2-8 shows the blocking performance measured relative to –102 dBm for some frequen-
cies. Note that sometimes the blocking is measured relative to the sensitivity level 104 dBm
(denoted dBS), instead of the carrier –102 dBm (denoted dBC)
Table 2-8.
Frequency Offset
Blocking 3 dB Above Sensitivity Level With BER < 10–3
Blocking Level
–44.5 dBm
–44.5 dBm
–39.0 dBm
–36.0 dBm
–34.5 dBm
–34.5 dBm
–28.0 dBm
–28.0 dBm
Blocking
+1.5 MHz
–1.5 MHz
+2 MHz
–2 MHz
57.5 dBC, 60.5 dBS
57.5 dBC, 60.5 dBS
63 dBC, 66 dBS
66 dBC, 69 dBS
67.5 dBC, 70.5 dBS
67.5 dBC, 70.5 dBS
74 dBC, 77 dBS
74 dBC, 77 dBS
+3 MHz
–3 MHz
+20 MHz
–20 MHz
12
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
The ATA5745/ATA5746 can also receive FSK and ASK modulated signals if they are much
higher than the I1dBCP. It can typically receive useful signals at –10 dBm. This is often referred
to as the nonlinear dynamic range (that is, the maximum to minimum receiving signal), and is
95 dB for 10 Kbits/s Manchester (FSK). This value is useful if the transmitter and receiver are
very close to each other.
2.7
In-band Disturbers, Data Filter, Quasi-peak Detector, Data Slicer
If a disturbing signal falls into the received band, or if a blocker is not a continuous wave, the
performance of a receiver strongly depends on the circuits after the IF filter. Hence, the demod-
ulator, data filter, and data slicer are important.
The data filter of the ATA5745/ATA5746 functions also as a quasi-peak detector. This results in a
good suppression of above mentioned disturbers and exhibits a good carrier-to-noise perfor-
mance. The required useful-signal-to-disturbing-signal ratio, at a BER of 10–3, is less than 14 dB
in ASK mode and less than 3 dB (BR_Range_0 to BR_Range_2) and 6 dB (BR_Range_3) in
FSK mode. Due to the many different possible waveforms, these numbers are measured for the
signal, as well as for disturbers, with peak amplitude values. Note that these values are
worst-case values and are valid for any type of modulation and modulating frequency of the dis-
turbing signal, as well as for the receiving signal. For many combinations, lower
carrier-to-disturbing-signal ratios are needed.
2.8
RSSI Output
The output voltage of the pin RSSI is an analog voltage, proportional to the input power level.
Using the RSSI output signal, the signal strength of different transmitters can be distinguished.
The usable dynamic range of the RSSI amplifier is 65 dB, the input power range P(RFIN) is
–110 dBm to –45 dBm, and the gain is 15 mV/dB. Figure 2-9 shows the RSSI characteristic of a
typical device at 315 MHz with VS3V_AVCC = VS5V = 2.7V to 3.3V and Tamb = –40°C to
+105°C with a matched input as shown in Table 2-2 and Figure 2-1 on page 6. At 433.92 MHz,
1 dB more signal level is needed for the same RSSI results.
Figure 2-9. Typical RSSI Characteristic at 315 MHz Versus Temperature and Supply Voltage
1.7
1.6
1.5
1.4
min; -9dB
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
max; +9dB
2.7V, -40˚C
3.0V, -40˚C
3.3V, -40˚C
2.7V, 27˚C
3.0V, 27˚C
3.3V, 27˚C
2.7V, 105˚C
3.0V, 105˚C
3.3V, 105˚C
-130 -120 -110 -100 -90
-80
-70
-60
-50
-40
-30
-20
-10
Pin (dBm)
13
4596B–RKE–06/07
As can be seen in Figure 2-9 on page 13, for single devices there is a variance over temperature
and supply voltage range of ±3 dB. The total variance over production, temperature, and supply
voltage range is ±9 dB.
2.9
Frequency Synthesizer
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal
oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) gen-
erates the drive voltage frequency fLO for the mixer. fLO is divided by the factor 24 (ATA5746) or
32 (ATA5745). The divided frequency is compared to fXTO by the phase frequency detector. The
current output of the phase frequency detector is connected to the fully integrated loop filter, and
thereby generates the control voltage for the VCO. By means of that configuration, the VCO is
controlled in a way, such that fLO / 24 (fLO / 32) is equal to fXTO. If fLO is determined, fXTO can be
calculated using the following formula: fXTO = fLO / 24 (fXTO = fLO / 32). The synthesizer has a
phase noise of –130 dBC/Hz at 3 MHz and spurs of –75 dBC.
Care must be taken with the harmonics of the CLK output signal, as well as with the harmonics
produced by a microprocessor clocked using the signal, as these harmonics can disturb the
reception of signals.
3. XTO
The XTO is an amplitude-regulated Pierce oscillator type with external load capacitances
(2 × 16 pF). Due to additional internal and board parasitics (CP) of approximately 2 pF on each
side, the load capacitance amounts to 2 × 18 pF (9 pF total).
The XTO oscillation frequency fXTO is the reference frequency for the integer-N synthesizer.
When designing the system in terms of receiving and transmitting frequency offset, the accuracy
of the crystal and XTO have to be considered.
The XTO’s additional pulling (including the RM tolerance) is only ±5 ppm. The XTAL versus tem-
perature, aging, and tolerances is then the main source of frequency error in the local oscillator.
The XTO frequency depends on XTAL properties and the load capacitances CL1,2 at pin XTAL1
and XTAL2. The pulling (p) of fXTO from the nominal fXTAL is calculated using the following for-
mula:
Cm
------- ---------------------------------------------------------------
× 10 ppm
C
LN – CL
-6
p =
×
2
(CO + CLN) × (CO + CL)
Cm, the crystal's motional capacitance; C0, the shunt capacitance; and CLN, the nominal load
capacitance of the XTAL, are found in the datasheet. CL is the total actual load capacitance of
the crystal in the circuit, and consists of CL1 and CL2 connected in series.
14
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
Figure 3-1. Crystal Equivalent Circuit
Crystal Equivalent Circuit
C0
XTAL
Lm
Rm
Cm
CL1
CL2
CL = CL1 × CL2/ (CL1 + CL2
)
With Cm ≤10 fF, C0 ≥ 1.0 pF, CLN = 9 pF and CL1,2 = 16 pF ±1%, the pulling amounts to
P ≤±1 ppm.
The C0 of the XTAL has to be lower than CLmin / 2 = 7.9 pF for a Pierce oscillator type in order to
not enter the steep region of pulling versus load capacitance where there is risk of an unstable
oscillation.
To ensure proper start-up behavior, the small signal gain and the negative resistance provided
by this XTO at start is very large. For example, oscillation starts up even in the worst case with a
crystal series resistance of 1.5 kΩ at C0 ≤2.2 pF with this XTO. The negative resistance is
approximately given by
Z1 × Z3 + Z2 × Z3 + Z1 × Z3 × gm
----------------------------------------------------------------------------------------
Re{Zxtocore} = Re
Z1 + Z2 + Z3 + Z1 × Z2 × gm
with Z1 and Z2 as complex impedances at pins XTAL1 and XTAL2, hence
Z1 = –j / (2 × p × fXTO × CL1) + 5Ω and Z2 = –j / (2 × p × fXTO × CL2) + 5Ω.
Z3 consists of crystal C0 in parallel with an internal 110-kΩ resistor, hence
Z3 = –j / (2 × p × fXTO × C0) / 110 kΩ, gm is the internal transconductance between XTAL1 and
XTAL2, with typically 20 mS at 25°C.
With fXTO = 13.5 MHz, gm = 20 mS, CL = 9 pF, and C0 = 2.2 pF, this results in a negative resis-
tance of about 2 kΩ. The worst case for technology, supply voltage, and temperature variations
is then always higher than 1.4 kΩ for C0 ≤2.2 pF.
Due to the large gain at start, the XTO is able to meet a very low start-up time. The oscillation
start-up time can be estimated with the time constant τ .
2
τ = ------------------------------------------------------------------------------------------------------------------
4 × π2 × fXTAL2 × Cm × (Re(Zxtocore) + Rm)
After 10τ to 20τ , an amplitude detector detects the oscillation amplitude and sets XTO_OK to
High if the amplitude is large enough; this activates the CLK_OUT output if it is enabled via the
pins CLK_OUT_CTRL0 and CLK_OUT_CTRL1. Note that the necessary conditions of the
DVCC voltage also have to be fulfilled.
It is recommended to use a crystal with Cm = 3.0 fF to 10 fF, CLN = 9 pF, Rm < 120Ω and
C0 = 1.0 pF to 2.2 pF.
15
4596B–RKE–06/07
Lower values of Cm can be used, slightly increasing the start-up time. Lower values of C0 or
higher values of Cm (up to 15 fF) can also be used, with only little influence on pulling.
Figure 3-2. XTO Block Diagram
CL1
CL2
XTAL1
XTAL2
CLK_OUT_CTRL0 CLK_OUT_CTRL1
CLK_OUT
&
fFXTO
Divider
/3, /6, /12
XTO_OK
Amplitude
Detector
Divider
/16
fDCLK
The relationship between fXTO and the fRF is shown in Table 3-1.
Table 3-1.
Calculation of fRF
Frequency [MHz]
fXTO [MHz]
13.57375
13.1433
fRF
433.92 (ATA5745)
315.0 (ATA5746)
fXTO x 32 – 440 kHz
fXTO x 24 – 440 kHz
Attention must be paid to the harmonics of the CLK_OUT output signal fCLK_OUT as well as to the
harmonics produced by an microprocessor clocked with it, since these harmonics can disturb
the reception of signals if they get to the RF input. If the CLK_OUT signal is used, it must be
carefully laid out on the application PCB. The supply voltage of the microcontroller must also be
carefully blocked.
16
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
3.1
Pin CLK_OUT
Pin CLK_OUT is an output to clock a connected microcontroller. The clock is available in
Standby and Active modes. The frequency fCLK_OUT can be adjusted via the pins
CLK_OUT_CTRL0 and CLK_OUT_CTRL1, and is calculated as follows:
Table 3-2.
Setting of fCLK_OUT
CLK_OUT_CTRL1
CLK_OUT_CTRL0
Function
Clock on pin CLK_OUT is switched off
(Low level on pin CLK_OUT)
0
0
0
1
1
1
0
1
fCLK_OUT = fXTO / 3
fCLK_OUT = fXTO / 6
fCLK_OUT = fXTO / 12
The signal at CLK_OUT output has a nominal 50% duty cycle. To save current, it is recom-
mended that CLK_OUT be switched off during Standby mode.
3.2
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry is derived from one clock. As seen in Figure 3-2 on
page 16, this clock cycle, TDCLK, is derived from the crystal oscillator (XTO) in combination with a
divider.
fXTO
fDCLK = ----------
16
TDCLK controls the following application relevant parameters:
- Debouncing of the data signal stream
- Start-up time of the RX signal path
The start-up time and the debounce characteristic depend on the selected bit rate range
(BR_Range) which is defined by pins BR0 and BR1. The clock cycle TXDCLK is defined by the fol-
lowing formulas for further reference:
BR_Range
BR_Range 0: TXDCLK = 8 × TDCLK
BR_Range 1: TXDCLK = 4 × TDCLK
BR_Range 2: TXDCLK = 2 × TDCLK
BR_Range 3: TXDCLK = 1 × TDCLK
17
4596B–RKE–06/07
4. Sensitivity Reduction
The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red
.
V
Th_red is determined by the value of the external resistor RSense. RSense is connected between
the pins SENSE and VS3V_AVCC (see Figure 10-1 on page 28). The output of the comparator
is fed into the digital control logic. By this means, it is possible to operate the receiver at a lower
sensitivity.
If the level on input pin SENSE_CTRL is low, the receiver operates at full sensitivity.
If the level on input pin SENSE_CTRL is high, the receiver operates at a lower sensitivity. The
reduced sensitivity is defined by the value of RSense, the maximum sensitivity by the sig-
nal-to-noise ratio of the LNA input. The reduced sensitivity depends on the signal strength at the
output of the RSSI amplifier.
Since different RF input networks may exhibit slightly different values for the LNA gain, the sen-
sitivity values given in the electrical characteristics refer to a specific input matching. This
matching is illustrated in Figure 2-1 on page 6 and exhibits the best possible sensitivity.
If the sensitivity reduction feature is not used, pin SENSE can be left open, pin SENSE_CTRL
must be set to GND.
To operate with reduced sensitivity, pin SENSE_CTRL must be set to high before the RX signal
path will be enabled by setting pin RX to high (see Figure 4-1 on page 19). As long as the RSSI
level is lower than VTh_red (defined by the external resistor RSense) no data stream is available on
pin DATA_OUT (low level on pin DATA_OUT). An internal RS flip-flop will be set to high the first
time the RSSI voltage crosses VTh_red, and from then on the data stream will be available on pin
DATA_OUT. From then on the receiver also works with full sensitivity. This makes sure that a
telegram will not be interrupted if the RSSI level varies during the transmission. The RS flip-flop
can be set back, and thus the receiver switched back to reduced sensitivity, by generating a pos-
itive pulse on pin ASK_NFSK (see Figure 4-2 on page 19). In FSK mode, operating with reduced
sensitivity follows the same way.
18
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
Figure 4-1. Reduced Sensitivity Active
ENABLE
ASK_NFSK
SENSE_CTRL
RX
V
Th_red
RSSI
t
t
Startup_PLL Startup_Sig_Proc
DATA_OUT
Figure 4-2. Restart Reduced Sensitivity
ENABLE
ASK_NFSK
SENSE_CTRL
RX
V
Th_red
RSSI
t
Startup_Sig_Proc
DATA_OUT
19
4596B–RKE–06/07
5. Power Supply
Figure 5-1. Power Supply
VS3V_AVCC
SW_DVCC
IN
OUT
V_REG
3.0V typ.
VS5V
RX
DVCC
EN
The supply voltage range of the ATA5745/ATA5746 is 2.7V to 3.3V or 4.5V to 5.5V.
Pin VS3V_AVCC is the supply voltage input for the range 2.7V to 3.3V, and is used in battery
applications using a single lithium 3V cell. Pin VS5V is the voltage input for the range 4.5V to
5.5V (car applications) in this case the voltage regulator V_REG regulates VS3V_AVCC to typi-
cally 3.0V. If the voltage regulator is active, a blocking capacitor of 2.2 µF has to be connected to
VS3V_AVCC (see Figure 10-1 on page 28).
DVCC is the internal operating voltage of the digital control logic and is fed via the switch
SW_DVCC by VS3V_AVCC. DVCC must be blocked on pin DVCC with 68 nF (see Figure 9-1
on page 27 and Figure 10-1 on page 28).
Pin RX is the input to activate the RX signal processing and set the receiver to Active mode.
5.1
OFF Mode
A low level on pin RX and ENABLE will set the receiver to OFF mode (low power mode). In this
mode, the crystal oscillator is shut down and no clock is available on pin CLK_OUT. The
receiver is not sensitive to a transmitter signal in this mode.
Table 5-1.
Standby Mode
RX
ENABLE
Function
0
0
OFF mode
5.2
Standby Mode
The receiver activates the Standby mode if pin ENABLE is set to “1”.
In Standby mode, the XTO is running and the clock on pin CLK_OUT is available after the
start-up time of the XTO has elapsed (dependent on pin CLK_OUT_CTRL0 and
CLK_OUT_CTRL1). During Standby mode, the receiver is not sensitive to a transmitter signal.
In Standby mode, the RX signal path is disabled and the power consumption IStandby is typically
50 µA (CLK_OUT output off, VS3V_AVCC = VS5V = 3V). The exact value of this current is
strongly dependent on the application and the exact operation mode, therefore check the sec-
tion “Electrical Characteristics: General” on page 29 for the appropriate application case.
20
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
Table 5-2.
Standby Mode
RX
ENABLE
Function
0
1
Standby mode
Figure 5-2. Standby Mode (CLK_OUT_CTRL0 or CLK_OUT_CTRL1 = 1)
CLK_OUT
t
XTO_Startup
ENABLE
Standby Mode
5.3
Active Mode
The Active mode is enabled by setting the level on pin RX to high. In Active mode, the RX signal
path is enabled and if a valid signal is present it will be transferred to the connected
microcontroller.
Table 5-3.
Active Mode
RX
ENABLE
Function
1
1
Active mode
During TStartup_PLL the PLL is enabled and starts up. If the PLL is locked, the signal processing
circuit starts up (TStartup_Sig_Proc). After the start-up time, all circuits are in stable condition and
ready to receive. The duration of the start-up sequence depends on the selected bit rate range.
Figure 5-3. Active Mode
CLK_OUT
ENABLE
RX
DATA_OUT
DATA_OUT valid
t
I
t
Startup_Sig_Proc
Startup_PLL
Startup_PLL
I
I
I
Active
Standby
Active
Standby Mode
Startup
Active Mode
21
4596B–RKE–06/07
Table 5-4.
Start-up Time
ATA5745 (433.92 MHz)
ATA5746 (315 MHz)
BR1
BR0
TStartup_PLL
TStartup_Sig_Proc
1096 µs
644 µs
TStartup_PLL
TStartup_Sig_Proc
0
0
1
1
0
1
0
1
1132 µs
665 µs
431 µs
324 µs
261 µs
269 µs
417 µs
304 µs
Table 5-5.
Modulation Scheme
ASK_NFSK
RFIN at Pin LNA_IN
fFSK_H
fFSK_L
Level at Pin DATA_OUT
1
0
1
0
0
fASK on
fASK off
1
22
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
6. Bit Rate Ranges
Configuration of the bit rate ranges is carried out via the two pins BR0 and BR1. The microcon-
troller uses these two interface lines to set the corner frequencies of the band-pass data filter.
Switching the bit rate ranges while the RF front end is in Active mode can be done on the fly and
will not take longer than 100 µs if done while remaining in either ASK or FSK mode. If the modu-
lation scheme is changed at the same time, the switching time is (TStartup_Sig_Proc, see Figure 7-1
on page 25). Each BR_Range is defined by a minimum edge-to-edge time. To maintain full sen-
sitivity of the receiver, edge-to-edge transition times of incoming data should not be less than the
minimum for the selected BR_Range.
Table 6-1.
BR Ranges ASK
Minimum Edge-to-edge
Edge-to-edge Time Period TEE of
Recommended Bit Rate
(Manchester)(1)
Time Period TEE of the Data the Data Signal During the Start-up
BR1
BR0
BR_Range
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Signal(2)
200 µs
100 µs
50 µs
Period(3)
0
0
1
1
0
1
0
1
1.0 Kbit/s to 2.5 Kbits/s
2.0 Kbits/s to 5.0 Kbits/s
4.0 Kbits/s to 10.0 Kbits/s
8.0 Kbits/s to 10.0 Kbits/s
200 µs to 500 µs
100 µs to 250 µs
50 µs to 125 µs
50 µs to 62.5 µs
50 µs
Table 6-2.
BR Ranges FSK
Minimum Edge-to-edge
Edge-to-edge Time Period TEE of
Recommended Bit Rate
(Manchester)(1)
Time Period TEE of the Data the Data Signal During the Start-up
BR1
BR0
BR_Range
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Signal(2)
200 µs
100 µs
50 µs
Period(3)
0
0
1
0
1
1.0 Kbit/s to 2.5 Kbits/s
2.0 Kbits/s to 5.0 Kbits/s
4.0 Kbits/s to 10.0 Kbits/s
8.0 Kbits/s to 20.0 Kbits/s
200 µs to 500 µs
100 µs to 250 µs
50 µs to 125 µs
25 µs to 62.5 µs
0
1
1
25 µs
Note:
If during the start-up period (TStartup_PLL + TStartup_Sig_Proc) there is no RF signal, the data filter settles to the noise floor, leading
to noise on pin DATA_OUT.
Notes: 1. As can be seen, a bit stream of, for example, 2.5 Kbits/s can be received in BR_Range0 and BR_Range1 (overlapping
BR_Ranges). To get the full sensitivity, always use the lowest possible BR_Range (here, BR_Range0). The advantage in
the next higher BR_Range (BR_Range1) is the shorter start-up period, meaning lower current consumption during Polling
mode. Thus, it is a decision between sensitivity and current consumption.
2. The receiver is also capable of receiving non-Manchester-modulated signals, such as PWM, PPM, VPWM, NRZ. In ASK
mode, the header and blanking periods occurring in Keeloq-like protocols (up to 52 ms) are supported.
3. To ensure an accurate settling of the data filter during the start-up period (TStartup_PLL + TStartup_Sig_Proc), the edge-to-edge
time TEE of the data signal (preamble) must be inside the given limits during this period.
23
4596B–RKE–06/07
Figure 6-1. Examples of Supported Modulation Formats
T
T
T
T
T
T
EE
EE
EE
EE
MAN:
PWM:
Logic 0
Logic 0
Logic 1
Logic 1
T
T
T
T
EE
EE
EE
EE
EE
EE
Logic 0
Logic 1
T
T
T
EE
EE
EE
VPWM:
On Transition Low to High
Logic 0
Logic 1
T
T
T
EE
EE
EE
On Transition High to Low
T
T
T
T
T
T
T
EE
EE
EE
EE
EE
EE
PPM:
NRZ:
Logic 0
Logic 0
Logic 1
Logic 1
T
EE
EE
Figure 6-2. Supported Header and Blanking Periods
Preamble
Header
Data Burst
Guard Time
Data Burst
24
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
7. ASK_NFSK
The ASK_NFSK pin allows the microcontroller to rapidly switch the RF front end between
demodulation modes. A logic 1 on this pin selects ASK mode, and a logic 0 FSK mode. The time
to change modes (TStartup_Sig_Proc) depends on the bit rate range being selected (not current bit
rate range) and is given in Table 5-4 on page 22. This response time is specified for applications
that require an ASK preamble followed by FSK data (for typical TPM applications). During
TStartup_Sig_Proc, the level on pin DATA_OUT is low.
Figure 7-1. ASK Preamble 2.4 Kbits/s followed by FSK Data 9.6 Kbits/s
ENABLE
RX
BR1
BR0
ASK_NFSK
DATA_OUT
Data valid BR0
Data valid BR3
T
Startup_Sig_Proc
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4596B–RKE–06/07
8. Polling Current Calculation
Figure 8-1. Polling Cycle
ENABLE
RX
I
I
Active
Active
I
I
I
Standby
Supply
Standby
T
T
T
(= 1 / Signal_Bitrate (average)
Bitcheck
(Startup Signal Processing)
Startup_Sig_Proc
(Startup RF-PLL)
Startup_PLL
In an RKE and TPM system, the average chip current in Polling mode, IPolling, is an important
parameter. The polling period must be controlled by the connected microcontroller via the pins
ENABLE and RX. The polling current can be calculated as follows:
I
Polling = (TStartup_PLL / TPolling_Period) × IStartup_PLL + (TStartup_Sig_Proc / TPolling_Period) × IActive
(TBitcheck / TPolling_Period) × IActive + (TPolling_Period – TStartup_PLL – TStartup_Sig_Proc – TBitcheck) /
Polling_Period × IStandby
+
T
TStartup_PLL
TStartup_Sig_Proc
:
depends on 315 MHz/433.92 MHz application.
depends on 315 MHz/433.92 MHz application and the selected bit
rate range.
:
TBitcheck
TPolling_Period
IStartup_PLL
IActive
:
depends on the signal bit rate (1 / Signal_Bit_Rate).
depends on the transmitter telegram (preburst).
depends on 3V or 5V application and the setting of pin CLK_OUT.
depends on 3V or 5V application, ASK or FSK mode and the setting of
pin CLK_OUT.
:
:
:
IStandby
:
depends on 3V or 5V application and the setting of pin CLK_OUT.
Example:-
315-MHz application (ATA5746), bit rate: 9.6 Kbits/s, TPolling_Period = 8 ms
--> TStartup_PLL
--> TStartup_Sig_Proc
--> TBitcheck
=
=
=
269 µs
324 µs
104 µs
(Bit Rate Range 3)
3V application; ASK mode, CLK_OUT disabled
--> IStartup_PLL
--> IActive
--> IStandby
=
=
=
4.5 mA
6.5 mA
0.05 mA
--> IPolling = 0.545 mA
26
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
9. 3V Application
Figure 9-1. 3V Application
15 nF
output
output
output
output
input
TEST2
TEST3
RSSI
TEST1
ATA5745/
ATA5746
CLK_OUT
SENSE_CTRL
CLK_OUT_CTRL1
SENSE
RF
2.2 pF
IN
CLK_OUT_CTRL0
ENABLE
LNA_IN
68 nH/36 nH
LNA_GND
output
315 MHz/433.92 MHz
VSS VCC
68 nF
18 pF
18 pF
68 nF
VCC = 2.7V to 3.3V
Note:
Paddle (backplane) must be connected to GND
27
4596B–RKE–06/07
10. 5V Application
Figure 10-1. 5V Application With Reduced/Full Sensitivity
15 nF
output
output
output
output
output
input
TEST2
TEST3
RSSI
TEST1
ATA5745/
ATA5746
CLK_OUT
CLK_OUT_CTRL1
SENSE_CTRL
SENSE
R
Sense
2.2 pF
CLK_OUT_CTRL0
ENABLE
LNA_IN
RF
IN
LNA_GND
output
VSS VCC
68 nH/36 nH
315 MHz/433.92 MHz
68 nF
18 pF
18 pF
2.2 µF
68 nF
VCC = 4.5V to 5.5V
Note:
Paddle (backplane) must be connected to GND
28
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
11. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Tj
Min.
Max.
+150
+125
+105
+6
Unit
°C
°C
°C
V
Junction temperature
Storage temperature
Ambient temperature
Supply voltage VS5V
Tstg
–55
–40
Tamb
VS
ESD (Human Body Model ESD S 5.1)
every pin
HBM
MM
–4
+4
kV
V
ESD (Machine Model JEDEC A115A)
every pin
–200
–500
+200
ESD (Field Induced Charge Device Model ESD
STM 5.3.1-1999) every pin
FCDM
Pin_max
+500
0
V
Maximum input level, input matched to 50Ω
dBm
12. Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
RthJA
25
K/W
13. Electrical Characteristics: General
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit Type*
1
OFF Mode
VVS3V_AVCC = VVS5V ≤ 3V
VVS5V = 5V
CLK_OUT disabled
10, 11
10
2
2
µA
µA
A
A
Supply current in OFF
mode
1.1
ISOFF
2
Standby Mode
ATA5746
ATA5745
14
14
fRF
fRF
313
433
317
435
MHz
MHz
A
A
RF operating frequency
range
2.1
XTO running
VVS3V_AVCC = VVS5V ≤ 3V
CLK_OUT disabled
10,11
10,11
IStandby
50
50
80
80
µA
µA
ms
A
A
A
Supply current
Standby mode
2.2
XTO running
VVS5V = 5V
IStandby
CLK_OUT disabled
XTO startup
XTAL: Cm = 5 fF,
C0 = 1.8 pF, Rm = 15Ω
2.3 System start-up time
TXTO_Startup
0.3
0.8
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo-
nent values as in Table 2-2 on page 6 (RFIN).
29
4596B–RKE–06/07
13. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit Type*
From Standby mode to
Active mode
2.4 Active mode start-up time BR_Range_3
TStartup_PLL
TStartup_Sig_Proc
+
A
ATA5745
ATA5746
565
593
µs
µs
3
Active Mode
VVS3V_AVCC = VVS5V = 3V
ASK mode
CLK_OUT disabled
SENSE_CTRL = 0
10,11
10,11
10
IActive
IActive
IActive
IActive
6.5
6.7
6.7
6.9
9.6
9.8
9.8
10
mA
mA
mA
mA
A
A
A
A
VVS3V_AVCC = VVS5V = 3V
FSK mode
CLK_OUT disabled
SENSE_CTRL = 0
Supply current Active
mode
3.1
VVS5V = 5V
ASK mode
CLK_OUT disabled
SENSE_CTRL = 0
VVS5V = 5V
FSK mode
CLK_OUT disabled
SENSE_CTRL = 0
10
VVS3V_AVCC = VVS5V = 3V
TPolling_Period = 8 ms
BR_Range_3, ASK mode, 10,11
CLK_OUT disabled
Supply current Polling
mode
3.2
IPolling
545
µA
C
Data rate = 9.6 Kbits/s
FSK deviation
fDEV = ±38 kHz
BER = 10–
3
Tamb = 25°C
Bit rate 9.6 Kbits/s BR2
Bit rate 2.4 Kbits/s BR0
(14)
(14)
PREF_FSK
PREF_FSK
–103
–106
–105
–108
–106.5
–109.5
dBm
dBm
B
B
Input sensitivity FSK
fRF = 315 MHz
3.3
FSK deviation ±18 kHz to
±50 kHz
Bit rate 9.6 Kbits/s BR2
Bit rate 2.4 Kbits/s BR0
ASK 100% level of carrier,
(14)
(14)
PREF_FSK
PREF_FSK
–101
–104
dBm
dBm
B
B
BER = 10–
3
Input sensitivity ASK
fRF = 315 MHz
Tamb = 25°C
3.4
Bit rate 9.6 Kbits/s BR2
Bit rate 2.4 Kbits/s BR0
(14)
(14)
PREF_ASK
PREF_ASK
–109
–112
–111
–114
–112.5
–115.5
dBm
dBm
B
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo-
nent values as in Table 2-2 on page 6 (RFIN).
30
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
13. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Sensitivity change at
Test Conditions
RF = 315 MHz to
Pin(1)
Symbol
Min.
Typ.
Max.
Unit Type*
f
fRF = 433.92 MHz
compared to
fRF = 433.92 MHz
P = PREF_ASK + ∆PREF1
P = PREF_FSK + ∆PREF1
3.5
3.6
(14)
∆PREF1
+1
dB
B
fRF = 315 MHz
FSK fDEV = ±38 kHz
∆fOFFSET ≤ ±160 kHz
Sensitivity change versus ASK 100%
temperature, supply
voltage and frequency
offset
∆fOFFSET ≤ ±160 kHz
P = PREF_ASK + ∆PREF1
∆PREF2
(14)
∆PREF2
+4.5
–1.5
B
+
+
P = PREF_FSK + ∆PREF1
∆PREF2
RSense connected from
pin SENSE to
pin VS3V_AVCC
dBm
(peak
level)
PRef_Red
RSense = 62 kΩ
fin = 433.92 MHz
–76
–88
–76
–88
dBm
dBm
dBm
dBm
C
C
C
C
Reduced sensitivity
RSense = 82 kΩ
fin = 433.92 MHz
3.7
RSense = 62 kΩ
fin = 315 MHz
RSense = 82 kΩ
fin = 315 MHz
Reduced sensitivity
variation over full
operating range
RSense = 62 kΩ
RSense = 82 kΩ
PRed = PRef_Red + P∆Red
∆PRed
–10
+10
dB
Maximum frequency
difference of fRF between
receiver and transmitter in
FSK mode (fRF is the
center frequency of the
FSK signal with
Maximum frequency
offset in FSK mode
3.8
(14)
∆fOFFSET
–160
+160
kHz
B
fBIT = 10 Kbits/s
fDEV = ±38 kHz
With up to 2 dB
loss of sensitivity.
Note that the tolerable
frequency offset is 12 kHz
lower for fDEV = ±50 kHz
than for fDEV = ±38 kHz,
hence,
Supported FSK
frequency deviation
3.9
(14)
fDEV
±18
±38
±50
kHz
B
∆fOFFSET ≤ ±148 kHz
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo-
nent values as in Table 2-2 on page 6 (RFIN).
31
4596B–RKE–06/07
13. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
fRF = 315 MHz
Pin(1)
Symbol
NF
Min.
Typ.
6.0
Max.
9
Unit Type*
(14)
dB
dB
B
B
A
A
3.10 System noise figure
fRF = 433.92 MHz
fRF = 433.92 MHz
fRF = 315 MHz
(14)
NF
7.0
10
fIF
440
440
kHz
kHz
3.11 Intermediate frequency
3.12 System bandwidth
fIF
3 dB bandwidth
This value is for
information only!
Note that for crystal and
system frequency offset
calculations, ∆fOFFSET
must be used.
(14)
(14)
SBW
IIP3
435
kHz
A
∆fmeas1 = 1.8 MHz
∆fmeas2 = 3.6 MHz
fRF = 315 MHz
System out-band
3.13 3rd-order input intercept
point
–24
dBm
C
fRF = 433.92 MHz
(14)
(14)
IIP3
–23
–31
dBm
dBm
C
C
∆fmeas1 = 1 MHz
fRF = 315 MHz
I1dBCP
–36
–35
System outband input
3.14
1-dB compression point
f
RF = 433.92 MHz
(14)
14
I1dBCP
Zin_LNA
Zin_LNA
PIN_max
PIN_max
–30
(72.4 – j298)
(55 – j216)
+5
dBm
Ω
C
C
C
C
C
C
C
fRF = 315 MHz
3.15 LNA input impedance
fRF = 433.92 MHz
14
Ω
–
3
BER < 10 , ASK: 100%
FSK: fDEV = ±38 kHz
f < 1 GHz
(14)
(14)
(14)
(14)
–10
–10
–57
–47
dBm
dBm
dBm
dBm
Maximum peak RF input
3.16
level, ASK and FSK
+5
f >1 GHz
fLO = 315.44 MHz
2 × fLO
4 × fLO
–90
–94
–68
(14)
(14)
dBm
dBm
C
C
3.17 LO spurs at LNA_IN
fLO = 434.36 MHz
2 × fLO
4 × fLO
–92
–88
–58
With the complete image
band
fRF = 315 MHz
A
A
3.18 Image rejection
(14)
(14)
24
24
30
30
dB
dB
f
RF = 433.92 MHz
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo-
nent values as in Table 2-2 on page 6 (RFIN).
32
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
13. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit Type*
Peak level of useful signal
to peak level of interferer
for BER < 10–3 with any
modulation scheme of
interferer
Useful signal to interferer
ratio
3.19
FSK BR_Ranges 0, 1, 2
FSK BR_Range_3
(14)
(14)
SNRFSK0-2
SNRFSK3
SNRASK
DRSSI
2
4
3
6
dB
dB
dB
dB
B
B
B
A
ASK (PRF < PRFIN_High
Dynamic range
)
(14)
10
65
14
(14),17
Lower level of range
fRF = 315 MHz
(14),17
(14),17
PRFIN_Low
–110
dBm
dBm
A
A
f
RF = 433.92 MHz
3.20 RSSI output
Upper level of range
fRF = 315 MHz
fRF = 433.92 MHz
PRFIN_High
–45
15
Gain
(14),17
(14),17
mV/dB
mV
A
A
Output voltage range
VRSSI
RRSSI
350
8
1600
12.5
Output resistance
RSSI pin
3.21
17
10
kΩ
C
–
3
Sensitivity (BER = 10 ) is
reduced by 3 dB if a
continuous wave blocking
signal at ±∆f is ∆PBlock
higher than the useful
signal level
(Bit rate = 10 Kbits/s,
FSK, fDEV ± 38 kHz,
Manchester code,
BR_Range2)
fRF = 315 MHz
∆f ± 1.5 MHz
∆f ± 2 MHz
∆f ± 3 MHz
∆f ± 10 MHz
∆f ± 20 MHz
3.22 Blocking
57.5
63.0
67.5
72.0
74.0
(14)
∆PBlock
dBC
C
fRF = 433.92 MHz
∆f ± 1.5 MHz
∆f ± 2 MHz
∆f ± 3 MHz
∆f ± 10 MHz
∆f ± 20 MHz
56.5
62.0
66.5
71.0
73.0
(14)
23
∆PBlock
dBC
nF
C
D
Capacitor connected to
pin 23 (CDEM)
3.23 CDEM
–5%
15
+5%
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo-
nent values as in Table 2-2 on page 6 (RFIN).
33
4596B–RKE–06/07
13. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit Type*
4
XTO
At startup; after startup
the amplitude is regulated
to VPPXTAL
Transconductance XTO at
start
4.1
7,8
gm, XTO
20
mS
B
C0 ≤ 2.2 pF
4.2 XTO start-up time
Cm < 14 fF
7,8
7,8
TXTO_Startup
C0max
300
800
3.8
µs
A
D
R
m ≤ 120Ω
4.3 Maximum C0 of XTAL
Pulling of LO frequency
pF
1.0 pF ≤ C0 ≤ 2.2 pF
Cm = 4.0 fF to 7.0 fF
fLO due to XTO, CL1 and
4.4
3
∆fXTO
–5
+5
ppm
C
CL2 versus temperature
R
m ≤ 120Ω
and supply changes
Cm = 5 fF, C0 = 1.8 pF
m = 15Ω
R
Amplitude XTAL after
startup
V(XTAL1, XTAL2)
peak-to-peak value
4.5
7,8
7,8
VPPXTAL
VPPXTAL
700
350
mVpp
mVpp
C
C
V(XTAL1)
peak-to-peak value
C0 ≤ 2.2 pF, small signal
start impedance, this
value is important for
crystal oscillator startup
Maximum series
4.6 resistance Rm of XTAL at
startup
7,8
ZXTAL12_START –1400
–2000
Ω
B
Maximum series
4.7 resistance Rm of XTAL
after startup
C0 ≤ 2.2 pF
Cm < 14 fF
7,8
7,8
Rm_max
15
120
Ω
B
D
Nominal XTAL load
4.8
f
RF = 433.92 MHz
13.57375
13.1433
fXTAL
MHz
resonant frequency
fRF = 315 MHz
CLK_OUT_CRTL1 = 0
CLK_OUT_CTRL0 = 0
--> CLK_OUT disabled
fCLK disabled (low level on pin
CLK_OUT)
CLK_OUT_CRTL1 = 0
CLK_OUT_CTRL0 = 1
--> division ratio = 3
fXTO
fCLK = ----------
3
External CLK_OUT
frequency
4.9
3
fCLK_OUT
MHz
A
CLK_OUT_CRTL1 = 1
CLK_OUT_CTRL0 = 0
--> division ratio = 6
fXTO
fCLK = ----------
6
CLK_OUT_CRTL1 = 1
CLK_OUT_CTRL0 = 1
--> division ratio = 12
fXTO
fCLK = ----------
12
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo-
nent values as in Table 2-2 on page 6 (RFIN).
34
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
13. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 315 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit Type*
fRF = 433.92 MHz
CLK_OUT division ratio
= 3
= 6
= 12
4.52458
2.26229
1.13114
3
fCLK_OUT
MHz
D
CLK_OUT has nominal
50% duty cycle
f
RF = 315 MHz
CLK_OUT division ratio
= 3
= 6
4.3811
2.190
3
fCLK_OUT
MHz
mV
D
C
= 12
1.0952
CLK_OUT has nominal
50% duty cycle
VDC (XTAL1, XTAL2)
4.10 DC voltage after startup XTO running (Standby
mode, Active mode)
7,8
VDCXTO
–250
–45
5
Synthesizer
At ±fCLK_OUT
,
CLK_OUT enabled
(division ratio = 3)
fRF = 315 MHz
SPRX
SPRX
–75
–75
–70
–70
dBC
dBC
C
A
5.1 Spurs in Active mode
fRF = 433.92 MHz
at ±fXTO
fRF = 315 MHz
fRF = 433.92 MHz
Phase noise at 3 MHz
Active mode
fRF = 315 MHz
fRF = 433.92 MHz
5.2
LRX3M
–130
–135
–127 dBC/Hz
–132 dBC/Hz
A
B
Phase noise at 20 MHz
Active mode
5.3
Noise floor
LRX20M
6
Microcontroller Interface
fCLK_OUT < 4.5 MHz
CL = 10 pF
CL = Load capacitance on
pin CLK_OUT
2.7V ≤ VVS5V ≤ 3.3V or
4.5V ≤ VVS5V ≤ 5.5V
20% to 80% VVS5V
trise
tfall
20
20
30
30
ns
ns
CLK_OUT output rise and
fall time
6.1
3
3
B
B
Internal equivalent
capacitance
Used for current
calculation
6.2
CCLK_OUT
8
pF
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in parenthesis were measured with RF_IN matched to 50Ω according to Figure 2-1 on page 6 with compo-
nent values as in Table 2-2 on page 6 (RFIN).
35
4596B–RKE–06/07
14. Electrical Characteristic: 3V Application
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
7
3V Application
Supply current in OFF VVS3V_AVCC = VVS5V ≤ 3V
7.1
10, 11
10, 11
ISOFF
2
µA
V
A
A
mode
CLK_OUT disabled
Supported voltage
range
VVS3V_AVCC
,
7.2
7.3
3V application
2.7
3.3
VVS5V
VVS3V_AVCC
VS5V ≤ 3V
=
V
external load C on pin
CLK_OUT = 12 pF
CLK enabled
(division ratio 3)
CLK enabled
(division ratio 6)
CLK enabled
(division ratio 12)
CLK disabled
C
C
C
A
420
290
220
50
670
460
350
80
Current in Standby
mode (XTO is running)
10, 11
IStandby
µA
VVS3V_AVCC
VS5V ≤ 3V
CLK disabled
=
Current during
TStartup_PLL
7.4
7.5
V
10, 11
10, 11
IStartup_PLL
4.5
mA
mA
C
A
VVS3V_AVCC
VS5V ≤ 3V
=
Current in Active mode
ASK
V
IActive
6.5
9.6
9.8
CLK disabled
SENSE_CTRL = 0
VVS3V_AVCC
VS5V ≤ 3V
=
Current in Active mode
FSK
V
7.6
10, 11
IActive
6.7
mA
A
CLK disabled
SENSE_CTRL = 0
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
36
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
15. Electrical Characteristics: 5V Application
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No.
8
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
5V Application
Supply current in OFF
mode
VVS5V = 5V
CLK_OUT disabled
8.1
8.2
10
10
ISOFF
2
µA
V
A
A
Supported voltage
range
5V application
VVS5V
4.5
5.5
VVS5V ≤ 5V
external load C on pin
CLK_OUT = 12 pF
CLK enabled
(division ratio 3)
CLK enabled
(division ratio 6)
CLK enabled
(division ratio 12)
CLK disabled
700
490
370
1120
780
590
80
C
C
C
Current in Standby
mode (XTO is
running)
8.3
10
IStandby
µA
50
A
C
Current during
TStartup_PLL
VVS5V = 5V
CLK disabled
8.4
8.5
10
10
IStartup_PLL
4.7
mA
mA
VVS5V = 5V
CLK disabled
SENSE_CTRL = 0
Current in Active
mode ASK
IActive
6.7
6.9
9.8
10
A
A
VVS5V = 5V
Current in Active
mode FSK
8.6
CLK disabled
SENSE_CTRL = 0
10
IActive
mA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
37
4596B–RKE–06/07
16. Digital Timing Characteristics
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
9
Basic Clock Cycle of the Digital Circuitry
Basic clock cycle
9.1
TDCLK
16 / fXTO
16 / fXTO
µs
A
BR_Range_0
8
8
BR_Range_1
Extended basic clock
BR_Range_2
4
2
1
4
2
1
9.2
TXDCLK
µs
µs
A
cycle
BR_Range_3
× TDCLK
× TDCLK
10
Active Mode
15 µs +
208 ×
TDCLK
10.1 Startup PLL
TStartup_PLL
A
A
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
929.5
545.5
TStartup_Sig_Proc 353.5
257.5
929.5
545.5
353.5
Startup signal
10.2
processing
257.5
× TDCLK
× TDCLK
ASK
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
FSK
1.0
2.0
4.0
2.5
5.0
10.0
10.0
8.0
10.3 Bit rate range
BR_Range
Kbits/s
A
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
1.0
2.0
4.0
8.0
2.5
5.0
10.0
20.0
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
Minimum time period
10.4 between edges at pin
DATA_OUT
10 ×
TDATA_OUT_min
TXDCLK
24
µs
µs
A
B
Edge-to-edge time
BR_Range_0
period of the data signal BR_Range_1
200
500
250
125
62.5
100
50
10.5
TDATA_OUT
for full sensitivity in
Active mode
BR_Range_2
BR_Range_3
25
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
38
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
17. Digital Port Characteristics
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
11
Digital Ports
0.2 × VS
VS = VVS3V_AVCC
VVS5V = 2.7V to 3.3V
=
ENABLE input
- Low level input
voltage
6
VIl
V
A
VS = VVS5V
=
0.12 ×
VS
4.5V to 5.5V
11.1
VS = VVS3V_AVCC
=
VVS5V = 2.7V to 3.3V
- High level input
voltage
6
VIh
0.8 × VS
V
V
V
V
V
V
V
V
V
A
A
A
A
A
A
A
A
A
VS = VVS5V = 4.5V to
5.5V
0.2 × VS
VS = VVS3V_AVCC
VVS5V = 2.7V to 3.3V
VS = VVS5V
=
RX input
- Low level input
voltage
19
19
20
20
21
21
22
22
VIl
=
0.12 ×
VS
4.5V to 5.5V
11.2
VS = VVS3V_AVCC
=
VVS5V = 2.7V to 3.3V
- High level input
voltage
VIh
0.8 × VS
VS = VVS5V
=
4.5V to 5.5V
0.2 × VS
VS = VVS3V_AVCC
=
BR0 input
- Low level input
voltage
VVS5V = 2.7V to 3.3V
VIl
VS = VVS5V
=
0.12 ×
VS
4.5V to 5.5V
11.3
11.4
11.5
VS = VVS3V_AVCC
=
VVS5V = 2.7V to 3.3V
- High level input
voltage
VIh
0.8 × VS
0.8 × VS
0.8 × VS
VS = VVS5V
=
4.5V to 5.5V
VS = VVS3V_AVCC
=
0.2 × VS
BR1 input
- Low level input
voltage
VVS5V = 2.7V to 3.3V
VIl
0.12 ×
VS
VS = VVS5V
=
4.5V to 5.5V
VS = VVS3V_AVCC
=
VVS5V = 2.7V to 3.3V
- High level input
voltage
VIh
VS = VVS5V
=
4.5V to 5.5V
VS = VVS3V_AVCC
=
0.2 × VS
ASK_NFSK input
- Low level input
voltage
VVS5V = 2.7V to 3.3V
VIl
0.12 ×
VS
VS = VVS5V
=
4.5V to 5.5V
VS = VVS3V_AVCC
=
VVS5V = 2.7V to 3.3V
VS = VVS5V
4.5V to 5.5V
- High level input
voltage
VIh
=
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
39
4596B–RKE–06/07
17. Digital Port Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS = VVS3V_AVCC
VVS5V = 2.7V to 3.3V
=
0.2 × VS
SENSE_CTRL input
- Low level input
voltage
16
VIl
V
A
VS = VVS5V
=
0.12 ×
VS
4.5V to 5.5V
11.6
11.7
11.8
VS = VVS3V_AVCC
VVS5V = 2.7V to 3.3V
=
- High level input
voltage
16
5
VIh
0.8 × VS
V
V
V
V
V
A
A
A
A
A
VS = VVS5V
=
4.5V to 5.5V
VS = VVS3V_AVCC
=
0.2 × VS
CLK_OUT_CTRL0
input
- Low level input
voltage
VVS5V = 2.7V to 3.3V
VIl
VS = VVS5V
=
0.12 ×
VS
4.5V to 5.5V
VS = VVS3V_AVCC
VVS5V = 2.7V to 3.3V
=
- High level input
voltage
5
VIh
0.8 × VS
VS = VVS5V
=
4.5V to 5.5V
VS = VVS3V_AVCC
VVS5V = 2.7V to 3.3V
=
0.2 × VS
CLK_OUT_CTRL1
input
- Low level input
voltage
4
VIl
VS = VVS5V
=
0.12 ×
VS
4.5V to 5.5V
VS = VVS3V_AVCC
VVS5V = 2.7V to 3.3V
=
- High level input
voltage
4
VIh
0.8 × VS
VS = VVS5V
=
4.5V to 5.5V
TEST1 input must
always be connected
directly to GND
11.9 TEST1 input
11.10 TEST2 output
11.11 TEST3 input
2
1
0
0
0
0
0
0
V
V
V
D
D
D
TEST2 output must
always be connected
directly to GND
TEST3 input must
always be connected
directly to GND
18
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
40
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
17. Digital Port Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS3V_AVCC = VVS5V = 2.7V to 3.3V, and VVS5V = 4.5V to 5.5V.
Typical values are given at VVS3V_AVCC = VVS5V = 3V, Tamb = 25°C, and fRF = 433.92 MHz unless otherwise specified. Details about current
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS = VVS3V_AVCC
=
VVS5V = 2.7V to 3.3V
DATA_OUT output
- Saturation voltage
low
VS = VVS5V
=
24
Vol
0.15
0.4
V
B
4.5V to 5.5V
IDATA_OUT = 250 µA
11.12
VS = VVS3V_AVCC
VVS5V = 2.7V to 3.3V
VS = VVS5V
=
- Saturation voltage
high
VVS –
0.15
=
24
3
Voh
VVS – 0.4
V
V
V
B
B
B
4.5V to 5.5V
IDATA_OUT = –250 µA
VS = VVS3V_AVCC
VVS5V = 2.7V to 3.3V
VS = VVS5V
=
CLK_OUT output
- Saturation voltage
low
=
Vol
0.15
0.4
4.5V to 5.5V
IDATA_OUT = 100 µA
11.13
VS = VVS3V_AVCC
VVS5V = 2.7V to 3.3V
VS = VVS5V
=
- Saturation voltage
high
VVS –
0.15
=
3
Voh
VVS – 0.4
4.5V to 5.5V
IDATA_OUT = –100 µA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
41
4596B–RKE–06/07
18. Ordering Information
Extended Type Number
Package
QFN24
QFN24
QFN24
QFN24
MOQ
Remarks
ATA5745-PXPW
1500 pcs
1500 pcs
6000 pcs
6000 pcs
5 mm × 5 mm, Pb-free, 433.92 MHz
5 mm × 5 mm, Pb-free, 315 MHz
5 mm × 5 mm, Pb-free, 433.92 MHz
5 mm × 5 mm, Pb-free, 315 MHz
ATA5746-PXPW
ATA5745-PXQW
ATA5746-PXQW
19. Package Information
Package: QFN 24 - 5 x 5
Exposed pad 3.6 x 3.6
(acc. JEDEC OUTLINE No. MO-220)
Dimensions in mm
Not indicated tolerances ±0.05
5
0.9±0.1
+0
0.05-0.05
3.6
24
19
24
1
6
18
13
1
technical drawings
according to DIN
specifications
6
7
12
0.65 nom.
Drawing-No.: 6.543-5122.01-4
Issue: 1; 15.11.05
3.25
42
ATA5745/ATA5746 [Preliminary]
4596B–RKE–06/07
ATA5745/ATA5746 [Preliminary]
20. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Put datasheet in a new template
• Section 13 “Electrical Characteristics: General” numbers 2.1, 2.2 and 3.1
on pages 29 to 30 changed
4596B-RKE-06/07
• Section 14 “Electrical Characteristics: 3V Application” numbers 7.3, 7.5
and 7.6 on page 36 changed
• Section 15 “Electrical Characteristics: 5V Application” numbers 8.3, 8.5
and 8.6 on page 37 changed
43
4596B–RKE–06/07
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