AT91SAM9260-QU [ATMEL]
AT91 ARM Thumb Microcontrollers; AT91 ARM的Thumb微控制器
| 型号： | AT91SAM9260-QU |
| 厂家： | 
ATMEL |
| 描述： | AT91 ARM Thumb Microcontrollers |
| 文件： | 总45页 (文件大小：915K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
– DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration
– 8-KByte Data Cache, 8-KByte Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE™, Debug Communication Channel Support
• Additional Embedded Memories
– One 32 KByte Internal ROM, Single-cycle Access At Maximum Matrix Speed
– Two 4 KByte Internal SRAM, Single-cycle Access At Maximum Matrix Speed
• External Bus Interface (EBI)
– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash®
• USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
• USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-lead PQFP
Package and Double Port in 217-ball LFBGA Package
– Single or Dual On-chip Transceivers
AT91 ARM
Thumb
Microcontrollers
AT91SAM9260
Preliminary
Summary
– Integrated FIFOs and Dedicated DMA Channels
• Ethernet MAC 10/100 Base T
– Media Independent Interface or Reduced Media Independent Interface
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
• Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
• Bus Matrix
– Six 32-bit-layer Matrix
– Boot Mode Select Option, Remap Command
• Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
• Reset Controller (RSTC)
– Based on a Power-on Reset Cell, Reset Source Identification and Reset Output
Control
• Clock Generator (CKGR)
– Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on
Battery Backup Power Supply, Providing a Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator, One up to 240 MHz PLL and One up to 130 MHz PLL
• Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization
Capabilities
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
– Two Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious
Interrupt Protected
6221ES–ATARM–12-Mar-07
• Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
• Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
• Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
• Real-time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
• One 4-channel 10-bit Analog-to-Digital Converter
• Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC)
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
– High-current Drive I/O Lines, Up to 16 mA Each
• Peripheral DMA Controller Channels (PDC)
• One Two-slot MultiMedia Card Interface (MCI)
– SDCard/SDIO and MultiMediaCard™ Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
• One Synchronous Serial Controller (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Signal Control on USART0
• Two 2-wire UARTs
• Two Master/Slave Serial Peripheral Interfaces (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications
• Two Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
– High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2
• One Two-wire Interface (TWI)
– Master, Multi-master and Slave Mode Operation
– General Call Supported in Slave Mode
• IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
• Required Power Supplies:
– 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL
– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
– 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)
• Available in a 208-lead PQFP Green and a 217-ball LFBGA RoHS-compliant Package
2
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
1. Description
The AT91SAM9260 is based on the integration of an ARM926EJ-S processor with fast ROM
and RAM memories and a wide range of peripherals.
The AT91SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host control-
ler. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer
Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface.
The AT91SAM9260 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth
of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide
range of memory devices.
2. AT91SAM9260 Block Diagram
The block diagram shows all the features for the 217-LFBGA package. Some functions are not
accessible in the 208-pin PQFP package and the unavailable pins are highlighted in “Multiplex-
ing on PIO Controller A” on page 34, “Multiplexing on PIO Controller B” on page 35,
“Multiplexing on PIO Controller C” on page 36. The USB Host Port B is not available in the 208-
pin package. Table 2-1 on page 3 defines all the multiplexed and not multiplexed pins not avail-
able in the 208-PQFP package.
Table 2-1.
Unavailable Signals in 208-lead PQFP Package
PIO
Peripheral A
HDPB
HDMB
SCK2
SCK0
TXD5
Peripheral B
-
-
-
-
PA30
PA31
PB12
PB13
PC2
PC3
PC12
RXD4
TXD4
ISI_D10
ISI_D11
PCK1
RXD5
AD2
AD3
SPI1_NPCS3
NCS7
IRQ0
3
6221ES–ATARM–12-Mar-07
MASTER
SLAVE
System
Controller
JTAG Selection and Boundary Scan
TST
Transc. Transc.
FIQ
IRQ0-IRQ2
In-Circuit Emulator
AIC
Image
Sensor
Interface
10/100 Ethernet
MAC
USB
OHCI
ARM926EJ-S Processor
DBGU
PDC
DRXD
DTXD
ICache
8 Kbytes
DCache
8 Kbytes
FIFO
FIFO
MMU
PCK0-PCK1
PMC
DMA
DMA
DMA
Bus Interface
PLLRCA
PLLA
I
D
PLLB
OSC
WDT
XIN
XOUT
6-layer Matrix
PIT
4GPREG
RC
OSCSEL
XIN32
XOUT32
OSC
RTT
D0-D15
PIOA
PIOB
A0/NBS0
ROM
32 Kbytes
Fast SRAM
4 Kbytes
Fast SRAM
4 Kbytes
SHDN
WKUP
A1/NBS2/NWR2
A2-A15, A18-A20
A16/BA0
EBI
SHDC
Peripheral
Bridge
22-channel
Peripheral
DMA
CompactFlash
NAND Flash
VDDBU
POR
POR
A17/BA1
PIOC
NCS0
NCS1/SDCS
VDDCORE
NRST
RSTC
NRD
NWR0/NWE
NWR1/NBS1
NWR3/NBS3
SDCK, SDCKE
RAS, CAS
SDWE, SDA10
NANDOE, NANDWE
A21/NANDALE
A22/NANDCLE
D16-D31
APB
SDRAM
Controller
PDC
MCI
PDC
SPI0
PDC
USART0
USART1
USART2
USART3
USART4
USART5
PDC
SSC
PDC
DPRAM
Static
Memory
Controller
TC0
TC1
TC2
TC3
TC4
TC5
4-channel
10-bit ADC
USB
Device
TWI
SPI1
NWAIT
A23-A24
NCS4/CFCS0
NCS5/CFCS1
A25/CFRNW
CFCE1-CFCE2
ECC
Controller
NCS2, NCS6, NCS7
NCS3/NANDCS
Transceiver
SPI0_, SPI1_
AT91SAM9260 Preliminary
3. Signal Description
Table 3-1.
Signal Description List
Active
Signal Name
Function
Type
Level
Comments
Power Supplies
EBI I/O Lines Power Supply
VDDIOM
VDDIOP0
VDDIOP1
VDDBU
Power
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
1.65V to 1.95V or 3.0V to3.6V
3.0V to 3.6V
Peripherals I/O Lines Power Supply
Peripherals I/O Lines Power Supply
Backup I/O Lines Power Supply
Analog Power Supply
PLL Power Supply
1.65V to 3.6V
1.65V to 1.95V
3.0V to 3.6V
VDDANA
VDDPLL
VDDCORE
GND
1.65V to 1.95V
1.65V to 1.95V
Core Chip Power Supply
Ground
GNDPLL
GNDANA
GNDBU
PLL and Oscillator Ground
Analog Ground
Backup Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
Output
Input
XOUT
XIN32
XOUT32
Main Oscillator Output
Slow Clock Oscillator Input
Slow Clock Oscillator Output
Output
Accepts between 0V and
VDDBU.
OSCSEL
Slow Clock Oscillator Selection
Input
PLLRCA
PLL A Filter
Input
PCK0 - PCK1
Programmable Clock Output
Output
Shutdown, Wakeup Logic
Driven at 0V only. Do not tie
over VDDBU.
SHDN
WKUP
Shutdown Control
Wake-up Input
Output
Input
Accepts between 0V and
VDDBU.
ICE and JTAG
NTRST
TCK
Test Reset Signal
Test Clock
Input
Input
Low
Pull-up resistor
No pull-up resistor
No pull-up resistor
TDI
Test Data In
Input
TDO
TMS
Test Data Out
Test Mode Select
Output
Input
No pull-up resistor
Pull-down resistor. Accepts
between 0V and VDDBU.
JTAGSEL
RTCK
JTAG Selection
Input
Return Test Clock
Output
5
6221ES–ATARM–12-Mar-07
Table 3-1.
Signal Description List (Continued)
Active
Level
Signal Name
Function
Type
Comments
Reset/Test
NRST
TST
Microcontroller Reset
Test Mode Select
Boot Mode Select
I/O
Low
Pull-up resistor
Pull-down resistor. Accepts
between 0V and VDDBU.
Input
Input
BMS
Debug Unit - DBGU
DRXD
DTXD
Debug Receive Data
Debug Transmit Data
Input
Output
Advanced Interrupt Controller - AIC
IRQ0 - IRQ2
FIQ
External Interrupt Inputs
Fast Interrupt Input
Input
Input
PIO Controller - PIOA - PIOB - PIOC
PA0 - PA31
PB0 - PB31
PC0 - PC31
Parallel IO Controller A
I/O
I/O
I/O
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Parallel IO Controller B
Parallel IO Controller C
External Bus Interface - EBI
D0 - D31
A0 - A25
NWAIT
Data Bus
I/O
Pulled-up input at reset
0 at reset
Address Bus
Output
Input
External Wait Signal
Low
Static Memory Controller - SMC
NCS0 - NCS7
NWR0 - NWR3
NRD
Chip Select Lines
Write Signal
Output
Low
Low
Low
Low
Low
Output
Read Signal
Output
Output
NWE
Write Enable
NBS0 - NBS3
Byte Mask Signal
Output
CompactFlash Support
CFCE1 - CFCE2
CFOE
CompactFlash Chip Enable
CompactFlash Output Enable
CompactFlash Write Enable
CompactFlash IO Read
Output
Output
Output
Output
Output
Output
Output
Low
Low
Low
Low
Low
CFWE
CFIOR
CFIOW
CompactFlash IO Write
CFRNW
CompactFlash Read Not Write
CompactFlash Chip Select Lines
CFCS0 - CFCS1
Low
NAND Flash Support
NANDCS
NANDOE
NAND Flash Chip Select
Output
Output
Low
Low
NAND Flash Output Enable
6
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
Table 3-1.
Signal Description List (Continued)
Active
Signal Name
NANDWE
Function
Type
Output
Output
Output
Level
Low
Low
Comments
NAND Flash Write Enable
NANDALE
NANDCLE
NAND Flash Address Latch Enable
NAND Flash Command Latch Enable
SDRAM Controller
Low
SDCK
SDRAM Clock
Output
Output
Output
Output
Output
Output
Output
SDCKE
SDCS
SDRAM Clock Enable
SDRAM Controller Chip Select
Bank Select
High
Low
BA0 - BA1
SDWE
SDRAM Write Enable
Row and Column Signal
SDRAM Address 10 Line
Low
Low
RAS - CAS
SDA10
Multimedia Card Interface MCI
MCCK
Multimedia Card Clock
Output
I/O
MCCDA
Multimedia Card Slot A Command
Multimedia Card Slot A Data
Multimedia Card Slot B Command
Multimedia Card Slot B Data
MCDA0 - MCDA3
MCCDB
I/O
I/O
MCDB0 - MCDB3
I/O
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
TXDx
RXDx
RTSx
CTSx
DTR0
DSR0
DCD0
RI0
USARTx Serial Clock
I/O
I/O
USARTx Transmit Data
USARTx Receive Data
USARTx Request To Send
USARTx Clear To Send
USART0 Data Terminal Ready
USART0 Data Set Ready
USART0 Data Carrier Detect
USART0 Ring Indicator
Input
Output
Input
Output
Input
Input
Input
Synchronous Serial Controller - SSC
TD
RD
TK
RK
TF
RF
SSC Transmit Data
Output
Input
I/O
SSC Receive Data
SSC Transmit Clock
SSC Receive Clock
I/O
SSC Transmit Frame Sync
SSC Receive Frame Sync
I/O
I/O
Timer/Counter - TCx
7
6221ES–ATARM–12-Mar-07
Table 3-1.
Signal Description List (Continued)
Active
Level
Signal Name
TCLKx
Function
Type
Input
I/O
Comments
TC Channel x External Clock Input
TIOAx
TC Channel x I/O Line A
TC Channel x I/O Line B
TIOBx
I/O
Serial Peripheral Interface - SPIx_
SPIx_MISO
Master In Slave Out
I/O
I/O
SPIx_MOSI
Master Out Slave In
SPIx_SPCK
SPI Serial Clock
I/O
SPIx_NPCS0
SPI Peripheral Chip Select 0
SPI Peripheral Chip Select
I/O
Low
Low
SPIx_NPCS1-SPIx_NPCS3
Output
Two-Wire Interface
TWD
Two-wire Serial Data
Two-wire Serial Clock
I/O
I/O
TWCK
USB Host Port
HDPA
HDMA
HDPB
HDMB
USB Host Port A Data +
USB Host Port A Data -
USB Host Port B Data +
USB Host Port B Data +
Analog
Analog
Analog
Analog
USB Device Port
Ethernet 10/100
DDM
DDP
USB Device Port Data -
USB Device Port Data +
Analog
Analog
ETXCK
ERXCK
ETXEN
ETX0-ETX3
ETXER
ERXDV
ERX0-ERX3
ERXER
ECRS
Transmit Clock or Reference Clock
Receive Clock
Input
Input
MII only, REFCK in RMII
MII only
Transmit Enable
Output
Output
Output
Input
Transmit Data
ETX0-ETX1 only in RMII
MII only
Transmit Coding Error
Receive Data Valid
Receive Data
RXDV in MII , CRSDV in RMII
ERX0-ERX1 only in RMII
Input
Receive Error
Input
Carrier Sense and Data Valid
Collision Detect
Input
MII only
MII only
ECOL
Input
EMDC
Management Data Clock
Management Data Input/Output
Force 100Mbit/sec.
Output
I/O
EMDIO
EF100
Output
High
Image Sensor Interface
8
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
Table 3-1.
Signal Description List (Continued)
Active
Signal Name
Function
Type
Input
Output
Input
Input
Input
Level
Comments
ISI_D0-ISI_D11
ISI_MCK
Image Sensor Data
Image Sensor Reference Clock
Image Sensor Horizontal Synchro
Image Sensor Vertical Synchro
Image Sensor Data clock
ISI_HSYNC
ISI_VSYNC
ISI_PCK
Analog to Digital Converter
Digital pulled-up inputs at
reset
AD0-AD3
Analog Inputs
Analog
ADVREF
ADTRG
Analog Positive Reference
ADC Trigger
Analog
Input
9
6221ES–ATARM–12-Mar-07
4. Package and Pinout
The AT91SAM9260 is available in two packages:
• 208-pin PQFP Green package (0.5mm pitch) (Figure 4-1)
• 217-ball LFBGA RoHS-compliant package (0.8 mm ball pitch) (Figure 4-2).
4.1
208-pin PQFP Package Outline
Figure 4-1 shows the orientation of the 208-pin PQFP package.
A detailed mechanical description is given in the section “AT91SAM9260 Mechanical Character-
istics” of the product datasheet.
Figure 4-1. 208-pin PQFP Package
156
105
157
104
208
53
1
52
10
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
4.2
208-pin PQFP Pinout
Table 4-1.
Pinout for 208-pin PQFP Package
Pin
1
2
3
4
5
6
7
8
Signal Name
PA24
PA25
PA26
PA27
VDDIOP0
GND
PA28
PA29
PB0
PB1
PB2
PB3
VDDIOP0
GND
PB4
PB5
PB6
PB7
PB8
PB9
PB14
PB15
PB16
VDDIOP0
GND
PB17
PB18
PB19
TDO
TDI
TMS
VDDIOP0
GND
TCK
NTRST
NRST
RTCK
VDDCORE
GND
Pin
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
Signal Name
GND
DDM
DDP
PC13
PC11
PC10
PC14
PC9
PC8
PC4
PC6
PC7
VDDIOM
GND
PC5
NCS0
CFOE/NRD
CFWE/NWE/NWR0
NANDOE
NANDWE
A22
A21
A20
A19
VDDCORE
GND
A18
BA1/A17
BA0/A16
A15
A14
A13
A12
A11
A10
A9
A8
VDDIOM
GND
A7
A6
A5
A4
A3
A2
NWR2/NBS2/A1
NBS0/A0
SDA10
CFIOW/NBS3/NWR3
CFIOR/NBS1/NWR1
SDCS/NCS1
CAS
Pin
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Signal Name
RAS
D0
D1
D2
D3
D4
D5
D6
Pin
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Signal Name
ADVREF
PC0
PC1
VDDANA
PB10
PB11
PB20
PB21
PB22
PB23
PB24
PB25
VDDIOP1
GND
PB26
PB27
GND
VDDCORE
PB28
PB29
PB30
PB31
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VDDIOP0
GND
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
VDDIOP0
GND
PA18
PA19
VDDCORE
GND
PA20
PA21
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VDDIOM
SDCK
SDWE
SDCKE
D7
D8
D9
D10
D11
D12
D13
D14
D15
PC15
PC16
PC17
PC18
PC19
VDDIOM
GND
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
GND
VDDCORE
VDDPLL
XIN
XOUT
GNDPLL
NC
GNDPLL
PLLRCA
VDDPLL
GNDANA
BMS
OSCSEL
TST
JTAGSEL
GNDBU
XOUT32
XIN32
VDDBU
WKUP
SHDN
HDMA
HDPA
VDDIOP0
PA22
PA23
11
6221ES–ATARM–12-Mar-07
4.3
217-ball LFBGA Package Outline
Figure 4-2 shows the orientation of the 217-ball LFBGA package.
A detailed mechanical description is given in the section “AT91SAM9260 Mechanical Character-
istics” of the product datasheet.
Figure 4-2.
217-ball LFBGA Package (Top View)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B C D E F G H J K L M N P R T U
Ball A1
12
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
4.4
217-ball LFBGA Pinout
Table 4-2.
Pin
Pinout for 217-ball LFBGA Package
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
A1
A2
A3
A4
A5
A6
A7
A8
CFIOW/NBS3/NWR3
NBS0/A0
NWR2/NBS2/A1
A6
A8
A11
A13
BA0/A16
D5
D6
D7
D8
A5
GND
A10
GND
VDDCORE
GND
VDDIOM
GND
DDM
HDPB
NC
VDDBU
XIN32
D10
D5
D3
J14
J15
J16
J17
K1
K2
K3
K4
K8
TDO
PB19
TDI
P17
R1
R2
R3
R4
R5
R6
R7
R8
PB5
NC
GNDANA
PC29
VDDANA
PB12
PB23
GND
PB26
PB28
PA0
PB16
PC24
PC20
D15
PC21
GND
GND
GND
PB4
PB17
GND
PB15
GND
PC26
PC25
VDDIOP0
PA28
PB9
D9
D10
D11
D12
D13
D14
D15
D16
D17
E1
E2
E3
E4
E14
E15
E16
E17
F1
F2
F3
F4
F14
F15
F16
F17
G1
G2
G3
G4
G14
G15
G16
G17
H1
A9
A18
A21
A22
A10
A11
A12
A13
A14
A15
A16
A17
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
D1
K9
R9
K10
K14
K15
K16
K17
L1
L2
L3
L4
L14
L15
L16
L17
M1
M2
M3
M4
M14
M15
M16
M17
N1
N2
N3
N4
N14
N15
N16
N17
P1
P2
P3
P4
P5
P6
P7
P8
P9
R10
R11
R12
R13
R14
R15
R16
R17
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
CFWE/NWE/NWR0
PA4
PA5
CFOE/NRD
NCS0
PC5
PC6
PC4
SDCK
CFIOR/NBS1/NWR1
SDCS/NCS1
SDA10
A3
A7
A12
A15
A20
NANDWE
PC7
PC10
PC13
PC11
PC14
PC8
WKUP
D8
D1
CAS
A2
A4
A9
A14
BA1/A17
A19
NANDOE
PC9
PC12
DDP
HDMB
NC
VDDIOP0
SHDN
D9
PA10
PA21
PA23
PA24
PA29
PLLRCA
GNDPLL
PC0
D4
HDPA
HDMA
GNDBU
XOUT32
D13
SDWE
D6
GND
OSCSEL
BMS
JTAGSEL
TST
PC15
D7
SDCKE
VDDIOM
GND
NRST
RTCK
TMS
PC18
D14
D12
D11
GND
GND
PB8
PC1
PB14
VDDCORE
PC31
GND
PC22
PB1
PB2
PB3
PB7
XIN
VDDPLL
PC23
PC27
PA31
PA30
PB0
PB10
PB22
GND
PB29
PA2
PA6
PA8
PA11
VDDCORE
PA20
GND
PA22
PA27
GNDPLL
ADVREF
PC2
H2
H3
H4
H8
PB6
PC3
XOUT
VDDPLL
PC30
PC28
PB11
PB13
PB24
VDDIOP1
PB30
PB31
PA1
PA3
PA7
PA9
PA26
PA25
PB20
PB21
PB25
PB27
PA12
PA13
PA14
PA15
PA19
PA17
PA16
PA18
VDDIOP0
H9
H10
H14
H15
H16
H17
J1
J2
J3
J4
J8
GND
VDDCORE
TCK
NTRST
PB18
PC19
PC17
VDDIOM
PC16
GND
P10
P11
P12
P13
P14
P15
P16
D2
D3
D4
D2
RAS
D0
J9
J10
GND
GND
13
6221ES–ATARM–12-Mar-07
5. Power Considerations
5.1
Power Supplies
The AT91SAM9XE512 has several types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the embedded memories and the
peripherals; voltage ranges from 1.65V and 1.95V, 1.8V nominal.
• VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and
1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V nominal). The expected voltage range is
selectable by software.
• VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from
3.0V and 3.6V, 3V or 3.3V nominal.
• VDDIOP1 pins: Power the Peripherals I/O lines involving the Image Sensor Interface; voltage
ranges from 1.65V and 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal.
• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage
ranges from 1.65V to 1.95V, 1.8V nominal.
• VDDPLL pin: Powers the Main Oscillator and PLL cells; voltage ranges from 1.65V and
1.95V, 1.8V nominal.
• VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V and 3.6V,
3.3V nominal.
The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and the
multiplexing tables. These supplies enable the user to power the device differently for interfacing
with memories and for interfacing with peripherals.
Ground pins GND are common to VDDCORE, VDDIOM, VDDIOP0 and VDDIOP1 pins power
supplies. Separated ground pins are provided for VDDBU, VDDPLL and VDDANA. These
ground pins are respectively GNDBU, GNDPLL and GNDANA.
5.2
5.3
Power Consumption
The AT91SAM9260 consumes about 500 µA of static current on VDDCORE at 25°C. This static
current rises up to 5 mA if the temperature increases to 85°C.
On VDDBU, the current does not exceed 10 µA in worst case conditions.
For dynamic power consumption, the AT91SAM9260 consumes a maximum of 100 mA on
VDDCORE at maximum conditions (1.8V, 25°C, processor running full-performance algorithm
out of high speed memories).
Programmable I/O Lines Power Supplies
The power supplies pins VDDIOM accept two voltage ranges. This allows the device to reach its
maximum speed either out of 1.8V or 3.3V external memories.
The target maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 30 pF for
power supply at 1.8V and 50 pF for power supply at 3.3V. The other signals (control, address
and data signals) do not exceed 50 MHz.
The voltage ranges are determined by programming registers in the Chip Configuration registers
located in the Matrix User Interface.
At reset, the selected voltage defaults to 3.3V nominal, and power supply pins can accept either
1.8V or 3.3V. Obviously, the device cannot reach its maximum speed if the voltage supplied to
14
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
the pins is 1.8V only. The user must program the EBI voltage range before getting the device out
of its Slow Clock Mode.
6. I/O Line Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied
to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩto GNDBU, so that it can
be left unconnected for normal operations.
The NTRST signal is described in Section 6.3.
All the JTAG signals are supplied with VDDIOP0.
6.2
6.3
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-
nent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
This pin is supplied with VDDBU.
Reset Pins
NRST is a bidirectional with an open-drain output integrating a non-programmable pull-up resis-
tor. It can be driven with voltage at up to VDDIOP0.
NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the
processor.
As the product integrates power-on reset cells, which manages the processor and the JTAG
reset, the NRST and NTRST pins can be left unconnected.
The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value
can be found in the table “DC Characteristics” in the section “AT91SAM9260 Electrical Charac-
teristics” in the product datasheet.
The NRST signal is inserted in the Boundary Scan.
6.4
PIO Controllers
All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor.
Refer to the section on DC Characteristics in “AT91SAM9260 Electrical Characteristics” for
more information. Programming of this pull-up resistor is performed independently for each I/O
line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals and that must be enabled as Peripheral
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing
tables.
15
6221ES–ATARM–12-Mar-07
6.5
6.6
I/O Line Drive Levels
The PIO lines are high-drive current capable. Each of these I/O lines can drive up to 16 mA
permanently.
Shutdown Logic Pins
The SHDN pin is an output only, which is driven by the Shutdown Controller.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
6.7
Slow Clock Selection
The AT91SAM9260 slow clock can be generated either by an external 32,768 Hz crystal or the
on-chip RC oscillator.
Table 6-1 on page 16 defines the states for OSCSEL signal.
Table 6-1.
Slow Clock Selection
Slow Clock
OSCSEL
Startup Time
240 µs
0
1
Internal RC
External 32768 Hz
1200 ms
The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. The
32,768 Hz startup delay is 1200 ms whereas it is 200 µs for the internal RC oscillator (refer to
Table 6-1). The pin OSCSEL must be tied either to GND or VDDBU for correct operation of the
device.
7. Processor and Architecture
7.1
ARM926EJ-S Processor
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
• Two Instruction Sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
• 8-Kbyte Data Cache, 8-Kbyte Instruction Cache
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
16
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
• Write Buffer
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
• Standard ARM v4 and v5 Memory Management Unit (MMU)
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
each quarter of the page
– 16 embedded domains
• Bus Interface Unit (BIU)
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete Matrix
system flexibility
– Separate Address and Data Buses for both the 32-bit instruction interface and the
32-bit data interface
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
(Words)
7.2
Bus Matrix
• 6-layer Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master
or fixed default master
• Burst Management
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
• One Address Decoder provided per Master
– Three different slaves may be assigned to each decoded memory area: one for
internal boot, one for external boot, one after remap
• Boot Mode Select
– Non-volatile Boot Memory can be internal or external
– Selection is made by BMS pin sampled at reset
• Remap Command
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
17
6221ES–ATARM–12-Mar-07
7.2.1
Matrix Masters
The Bus Matrix of the AT91SAM9260 manages six Masters, which means that each master can
perform an access concurrently with others, according the slave it accesses is available.
Each Master has its own decoder that can be defined specifically for each master. In order to
simplify the addressing, all the masters have the same decodings.
Table 7-1.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
List of Bus Matrix Masters
ARM926™ Instruction
ARM926 Data
PDC
ISI Controller
Ethernet MAC
USB Host DMA
7.2.2
Matrix Slaves
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 7-2.
Slave 0
List of Bus Matrix Slaves
Internal SRAM0 4kBytes
Slave 1
Internal SRAM1 4kBytes
Internal ROM
Slave 2
USB Host User Interface
External Bus Interface
Internal Peripherals
Slave 3
Slave 4
7.2.3
Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
such as allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths
are forbidden or simply not wired, and shown “-” in the following table.
Table 7-3.
AT91SAM9260 Masters to Slaves Access
Master
0 & 1
2
3
4
5
ARM926
Instruction &
Data
Peripheral
DMA
Controller
ISI
Controller
Ethernet
MAC
USB Host
Controller
Slave
Internal SRAM
4 KBytes
0
1
X
X
X
X
X
X
X
X
X
X
Internal SRAM
4 KBytes
Internal ROM
X
X
X
X
X
-
-
-
-
-
X
-
2
UHP User Interface
External Bus Interface
Internal Peripherals
3
4
X
X
X
-
X
-
X
X
18
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
7.3
Peripheral DMA Controller
• Acting as one Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
of the processor.
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Twenty-two channels
– Two for each USART
– Two for the Debug Unit
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for Multimedia Card Interface
– One for Analog-to-Digital Converter
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
– DBGU Transmit Channel
– USART5 Transmit Channel
– USART4 Transmit Channel
– USART3 Transmit Channel
– USART2 Transmit Channel
– USART1 Transmit Channel
– USART0 Transmit Channel
– SPI1 Transmit Channel
– SPI0 Transmit Channel
– SSC Transmit Channel
– DBGU Receive Channel
– USART5 Receive Channel
– USART4 Receive Channel
– USART3 Receive Channel
– USART2 Receive Channel
– USART1 Receive Channel
– USART0 Receive Channel
– ADC Receive Channel
– SPI1 Receive Channel
– SPI0 Receive Channel
– SSC Receive Channel
– MCI Transmit/Receive Channel
7.4
Debug and Test Features
• ARM926 Real-time In-circuit Emulator
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
19
6221ES–ATARM–12-Mar-07
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
• Debug Unit
– Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
20
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
8. Memories
Figure 8-1. AT91SAM9260 Memory Mapping
Address Memory Space
Internal Memory Mapping
Notes :
(1) Can be ROM, EBI_NCS0 or SRAM
0x0000 0000
0x0000 0000
0x10 0000
0x10 8000
0x20 0000
0x20 1000
0x30 0000
0x30 1000
0x50 0000
0x50 4000
depending on BMS and REMAP
Boot Memory (1)
ROM
Internal Memories 256M Bytes
32K Bytes
4K Bytes
4K Bytes
0x0FFF FFFF
0x1000 0000
Reserved
EBI
Chip Select 0
256M Bytes
SRAM0
0x1FFF FFFF
0x2000 0000
Reserved
EBI
Chip Select 1/
256M Bytes
SRAM1
SDRAMC
0x2FFF FFFF
0x3000 0000
Reserved
UHP
EBI
Chip Select 2
16K Bytes
256M Bytes
256M Bytes
0x3FFF FFFF
0x4000 0000
Reserved
EBI
0x0FFF FFFF
Chip Select 3/
NANDFlash
0x4FFF FFFF
0x5000 0000
EBI
Chip Select 4/
Compact Flash
Slot 0
256M Bytes
256M Bytes
0x5FFF FFFF
0x6000 0000
EBI
Peripheral Mapping
Chip Select 5/
Compact Flash
Slot 1
0xF000 0000
0xFFFA 0000
System Controller Mapping
0x6FFF FFFF
0x7000 0000
Reserved
TCO, TC1, TC2
UDP
0xFFFF C000
16K Bytes
EBI
Chip Select 6
256M Bytes
256M Bytes
Reserved
ECC
0xFFFA 4000
0xFFFA 8000
0xFFFF E800
0xFFFF EA00
0xFFFF EC00
0xFFFF EE00
16K Bytes
0x7FFF FFFF
0x8000 0000
512 Bytes
512 Bytes
512 Bytes
EBI
Chip Select 7
16K Bytes
16K Bytes
MCI
TWI
0xFFFA C000
SDRAMC
SMC
0x8FFF FFFF
0x9000 0000
0xFFFB 0000
0xFFFB 4000
0xFFFB 8000
0xFFFB C000
0xFFFC 0000
0xFFFC 4000
0xFFFC 8000
USART0
USART1
USART2
SSC
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
MATRIX
CCFG
0xFFFF EF10
0xFFFF F000
512 Bytes
512 Bytes
AIC
0xFFFF F200
0xFFFF F400
0xFFFF F600
DBGU
PIOA
512 Bytes
512 Bytes
512 bytes
ISI
EMAC
1,518M Bytes
Undefined
(Abort)
SPI0
PIOB
PIOC
0xFFFC C000
0xFFFF F800
0xFFFF FA00
0xFFFF FC00
0xFFFF FD00
SPI1
512 bytes
0xFFFD 0000
0xFFFD 4000
16K Bytes
16K Bytes
16K Bytes
USART3
Reserved
USART4
PMC
256 Bytes
0xFFFD 8000
0xFFFD C000
0xFFFE 0000
0xFFFE 4000
0xFFFF C000
USART5
RSTC
16 Bytes
16 Bytes
0xFFFF FD10
0xFFFF FD20
SHDC
RTTC
PITC
TC3, TC4, TC5
16K Bytes
16K Bytes
16 Bytes
16 Bytes
0xFFFF FD30
0xFFFF FD40
ADC
0xEFFF FFFF
0xF000 0000
WDTC
GPBR
16 Bytes
16 Bytes
0xFFFF FD50
0xFFFF FD60
Reserved
SYSC
Internal Peripherals 256M Bytes
16K Bytes
Reserved
0xFFFF FFFF
0xFFFF FFFF
0xFFFF FFFF
21
6221ES–ATARM–12-Mar-07
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes. The banks 1 to
7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to
EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level
of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals
and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master. However, in order to simplify the mappings, all the masters have a similar address
decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot, one after remap. Refer to Table 8-1, “Internal Memory Mapping,” on page 22 for details.
A complete memory map is presented in Figure 8-1 on page 21.
8.1
Embedded Memories
• 32 KB ROM
– Single Cycle Access at full matrix speed
• Two 4 KB Fast SRAM
– Single Cycle Access at full matrix speed
8.1.1
Boot Strategies
Table 8-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap
status and the BMS state at reset.
Table 8-1.
Internal Memory Mapping
REMAP = 0
REMAP = 1
SRAM0 4K
Address
BMS = 1
ROM
BMS = 0
0x0000 0000
EBI_NCS0
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,
the memory layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This
is done by software once the system has booted. When REMAP = 1, BMS is ignored. Refer to
the Bus Matrix Section for more details.
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory. This is done via hardware at reset.
Note:
Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in Figure 8-1 on page 21.
22
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
The AT91SAM9260 matrix manages a boot memory that depends on the level on the BMS pin
at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved
for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
8.1.1.1
BMS = 1, Boot on Embedded ROM
The system boots using the Boot Program.
• Boot on slow clock (On-chip RC or 32,768 Hz)
• Auto baudrate detection
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader on a non-volatile memory
– SPI DataFlash® connected on NPCS0 and NPCS1 of the SPI0
– 8-bit and/or 16-bit NANDFlash
• SAM-BA™ Boot in case no valid program is detected in external NVM, supporting
– Serial communication on a DBGU
– USB Device Port
8.1.1.2
BMS = 0, Boot on External Memory
• Boot on slow clock (On-chip RC or 32,768 Hz)
• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit
data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take
the following steps:
1. Program the PMC (main oscillator enable or bypass mode).
2. Program and start the PLL.
3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them
to the new clock.
4. Switch the main clock to the new value.
8.2
External Memories
The external memories are accessed through the External Bus Interface. Each Chip Select line
has a 256-Mbyte memory area assigned.
Refer to the memory map in Figure 8-1 on page 21.
8.2.1
External Bus Interface
• Integrates three External Memory Controllers
– Static Memory Controller
– SDRAM Controller
23
6221ES–ATARM–12-Mar-07
– ECC Controller
• Additional logic for NANDFlash
• Full 32-bit External Data Bus
• Up to 26-bit Address Bus (up to 64MBytes linear)
• Up to 8 chip selects, Configurable Assignment:
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3, Optional NAND Flash support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
– Static Memory Controller on NCS6-NCS7
8.2.2
Static Memory Controller
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
• Multiple device adaptability
– Compliant with LCD Module
– Control signals programmable setup, pulse and hold time for each Memory Bank
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
• Slow Clock mode supported
8.2.3
SDRAM Controller
• Supported devices
– Standard and Low-power SDRAM (Mobile SDRAM)
• Numerous configurations supported
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Datapath
• Programming facilities
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
• Energy-saving capabilities
– Self-refresh, power down and deep power down modes supported
24
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
• Error detection
– Refresh Error Interrupt
• SDRAM Power-up Initialization by software
• CAS Latency of 1, 2 and 3 supported
• Auto Precharge Command not used
8.2.4
Error Corrected Code Controller
• Tracking the accesses to a NAND Flash device by trigging on the corresponding chip select
• Single bit error correction and 2-bit Random detection
• Automatic Hamming Code Calculation while writing
– ECC value available in a register
• Automatic Hamming Code Calculation while reading
– Error Report, including error flag, correctable error flag and word address being
detected erroneous
– Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes
pages
25
6221ES–ATARM–12-Mar-07
9. System Controller
The System Controller is a set of peripherals that allows handling of key elements of the system,
such as power, resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds the registers that configure the Matrix and a
set of registers for the chip configuration. The chip configuration registers configure EBI chip
select assignment and voltage range for external memories
The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address
space, between addresses 0xFFFF E800 and 0xFFFF FFFF.
However, all the registers of System Controller are mapped on the top of the address space. All
the registers of the System Controller can be addressed from a single pointer by using the stan-
dard ARM instruction set, as the Load/Store instruction has an indexing mode of ±4 Kbytes.
Figure 9-1 on page 27 shows the System Controller block diagram.
Figure 8-1 on page 21 shows the mapping of the User Interfaces of the System Controller
peripherals.
26
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
9.1
Block Diagram
Figure 9-1. AT91SAM9260 System Controller Block Diagram
System Controller
VDDCORE Powered
nirq
irq0-irq2
Advanced
Interrupt
nfiq
fiq
periph_irq[2..24]
Controller
pit_irq
rtt_irq
int
wdt_irq
dbgu_irq
pmc_irq
rstc_irq
ntrst
ARM926EJ-S
por_ntrst
proc_nreset
MCK
Debug
dbgu_irq
dbgu_txd
periph_nreset
Unit
PCK
dbgu_rxd
debug
MCK
Periodic
Interval
Timer
debug
pit_irq
periph_nreset
jtag_nreset
Boundary Scan
TAP Controller
SLCK
debug
Watchdog
Timer
wdt_irq
idle
proc_nreset
MCK
wdt_fault
WDRPROC
Bus Matrix
periph_nreset
NRST
rstc_irq
por_ntrst
jtag_nreset
periph_nreset
proc_nreset
VDDCORE
POR
Reset
UHPCK
Controller
backup_nreset
periph_clk[20]
USB Host
Port
VDDBU
periph_nreset
periph_irq[20]
VDDBU Powered
VDDBU
POR
SLCK
SLCK
rtt_irq
rtt_alarm
Real-time
Timer
backup_nreset
UDPCK
SLCK
SHDN
WKUP
periph_clk[10]
periph_nreset
periph_irq[10]
USB
Device
Port
Shutdown
Controller
RC
OSC
backup_nreset
rtt0_alarm
OSC_SEL
SLOW
CLOCK
OSC
4 General-purpose
Backup Registers
XIN32
XOUT32
SLCK
periph_clk[2..27]
pck[0-1]
int
XIN
PCK
MAINCK
MAIN
OSC
XOUT
Power
Management
Controller
UDPCK
UHPCK
PLLRCA
PLLA
PLLB
PLLACK
PLLBCK
MCK
pmc_irq
idle
periph_nreset
periph_clk[6..24]
periph_nreset
periph_nreset
periph_clk[2..4]
dbgu_rxd
periph_irq[2..4]
irq0-irq2
fiq
Embedded
Peripherals
PIO
Controllers
periph_irq[6..24]
PA0-PA31
PB0-PB31
PC0-PC31
dbgu_txd
in
out
enable
27
6221ES–ATARM–12-Mar-07
9.2
Reset Controller
• Based on two Power-on-reset cells
– One on VDDBU and one on VDDCORE
• Status of the last reset
– Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software
reset, user reset or watchdog reset
• Controls the internal resets and the NRST pin output
– Allows shaping a reset signal for the external devices
9.3
9.4
Shutdown Controller
• Shutdown and Wake-up logic
– Software programmable assertion of the SHDWN pin
– Deassertion Programmable on a WKUP pin level change or on alarm
Clock Generator
• Embeds a Low-power 32,768 Hz Slow Clock Oscillator and a Low-power RC oscillator
selectable with OSCSEL signal
– Provides the permanent Slow Clock SLCK to the system
• Embeds the Main Oscillator
– Oscillator bypass feature
– Supports 3 to 20 MHz crystals
• Embeds 2 PLLs
– PLLA outputs 80 to 240 MHz clock
– PLLB outputs 70 to 130 MHz clock
– Both integrate an input divider to increase output accuracy
– PLLB embeds its own filter
28
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
Figure 9-2. Clock Generator Block Diagram
Clock Generator
OSC_SEL
On Chip
RC OSC
Slow Clock
SLCK
XIN32
XOUT32
XIN
Slow Clock
Oscillator
Main
Oscillator
Main Clock
MAINCK
XOUT
PLL and
Divider A
PLLA Clock
PLLACK
PLLRCA
PLL and
Divider B
PLLB Clock
PLLBCK
Status
Control
Power
Management
Controller
9.5
Power Management Controller
• Provides:
– the Processor Clock PCK
– the Master Clock MCK, in particular to the Matrix and the memory interfaces
– the USB Device Clock UDPCK
– independent peripheral clocks, typically at the frequency of MCK
– 2 programmable clock outputs: PCK0, PCK1
• Five flexible operating modes:
– Normal Mode, processor and peripherals running at a programmable frequency
– Idle Mode, processor stopped waiting for an interrupt
– Slow Clock Mode, processor and peripherals running at low frequency
– Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency,
processor stopped waiting for an interrupt
– Backup Mode, Main Power Supplies off, VDDBU powered by a battery
29
6221ES–ATARM–12-Mar-07
Figure 9-3. AT91SAM9260 Power Management Controller Block Diagram
Processor
Clock
Controller
PCK
int
Master Clock Controller
Idle Mode
SLCK
MAINCK
PLLACK
PLLBCK
Divider
/1,/2,/3,/4
Prescaler
/1,/2,/4,...,/64
MCK
Peripherals
Clock Controller
periph_clk[..]
ON/OFF
Programmable Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
ON/OFF
Prescaler
/1,/2,/4,...,/64
pck[..]
USB Clock Controller
ON/OFF
UDPCK
UHPCK
Divider
/1,/2,/4
PLLBCK
9.6
Periodic Interval Timer
• Includes a 20-bit Periodic Counter, with less than 1 µs accuracy
• Includes a 12-bit Interval Overlay Counter
• Real Time OS or Linux®/Windows CE® compliant tick generator
9.7
9.8
Watchdog Timer
• 16-bit key-protected only-once-Programmable Counter
• Windowed, prevents the processor being in a dead-lock on the watchdog access
Real-time Timer
– Real-time Timer 32-bit free-running back-up Counter
– Integrates a 16-bit programmable prescaler running on slow clock
– Alarm Register capable of generating a wake-up of the system through the
Shutdown Controller
9.9
General-purpose Back-up Registers
• Four 32-bit backup general-purpose registers
9.10 Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
30
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6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
• Three External Sources plus the Fast Interrupt signal
• 8-level Priority Controller
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
• Protect Mode
– Easy debugging by preventing automatic operations when protect models are
enabled
• Fast Forcing
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
processor
9.11 Debug Unit
• Composed of two functions:
– Two-pin UART
– Debug Communication Channel (DCC) support
• Two-pin UART
– Implemented features are 100% compatible with the standard Atmel ® USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
• Debug Communication Channel Support
– Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from
the ARM Processor’s ICE Interface
9.12 Chip Identification
• Chip ID: 0x019803A0
• JTAG ID: 0x05B1303F
• ARM926 TAP ID: 0x0792603F
31
6221ES–ATARM–12-Mar-07
10. Peripherals
10.1 User Interface
The peripherals are mapped in the upper 256 Mbytes of the address space between the
addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of
address space. A complete memory map is presented in Figure 8-1 on page 21.
10.2 Identifiers
Table 10-1 defines the Peripheral Identifiers of the AT91SAM9XE512. A peripheral identifier is
required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for
the control of the peripheral clock with the Power Management Controller.
Table 10-1. AT91SAM9260 Peripheral Identifiers
Peripheral ID
Peripheral Mnemonic
Peripheral Name
Advanced Interrupt Controller
System Controller Interrupt
Parallel I/O Controller A
Parallel I/O Controller B
Parallel I/O Controller C
Analog to Digital Converter
USART 0
External Interrupt
0
AIC
FIQ
1
SYSC
PIOA
PIOB
PIOC
ADC
US0
US1
US2
MCI
UDP
TWI
SPI0
SPI1
SSC
-
2
3
4
5
6
7
USART 1
8
USART 2
9
Multimedia Card Interface
USB Device Port
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Two-wire Interface
Serial Peripheral Interface 0
Serial Peripheral Interface 1
Synchronous Serial Controller
Reserved
-
Reserved
TC0
TC1
TC2
UHP
EMAC
ISI
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
USB Host Port
Ethernet MAC
Image Sensor Interface
USART 3
US3
US4
US5
TC3
TC4
TC5
AIC
USART 4
USART 5
Timer/Counter 3
Timer/Counter 4
Timer/Counter 5
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
IRQ0
IRQ1
IRQ2
AIC
AIC
Note:
Setting AIC, SYSC, UHP, ADC and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. The ADC clock is auto-
matically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion.
32
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AT91SAM9260 Preliminary
10.2.1
Peripheral Interrupts and Clock Control
10.2.1.1
System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
• the SDRAM Controller
• the Debug Unit
• the Periodic Interval Timer
• the Real-time Timer
• the Watchdog Timer
• the Reset Controller
• the Power Management Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
10.2.1.2
External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to
IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these
peripheral IDs.
10.3 Peripheral Signal Multiplexing on I/O Lines
The AT91SAM9XE512 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O
lines of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral
functions, A or B. Table 10-2 on page 34, Table 10-3 on page 35 and Table 10-4 on page 36
define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The
two columns “Function” and “Comments” have been inserted in this table for the user’s own
comments; they may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only might be duplicated within both
tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral
mode. If I/O appears, the PIO Line resets in input with the pull-up enabled, so that the device is
maintained in a static state as soon as the reset is released. As a result, the bit corresponding to
the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name appears in the “Reset State” column, the PIO Line is assigned to this function
and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories,
in particular the address lines, which require the pin to be driven as soon as the reset is
released. Note that the pull-up resistor is also enabled in this case.
33
6221ES–ATARM–12-Mar-07
10.3.1
PIO Controller A Multiplexing
Table 10-2. Multiplexing on PIO Controller A
PIO Controller A
Application Usage
I/O Line
PA0
Peripheral A
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
RTS2
Peripheral B
MCDB0
Comments
Reset State Power Supply Function
Comments
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
PA1
MCCDB
PA2
PA3
MCDB3
MCDB2
MCDB1
PA4
PA5
CTS2
PA6
MCDA0
MCCDA
MCCK
PA7
PA8
PA9
MCDA1
MCDA2
MCDA3
ETX0
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30(1)
PA31(1)
ETX2
ETX3
ETX1
ERX0
ERX1
ETXEN
ERXDV
ERXER
ETXCK
EMDC
EMDIO
ADTRG
TWD
ETXER
ETX2
TWCK
ETX3
TCLK0
TIOA0
ERX2
ERX3
ERXCK
ECRS
ECOL
RXD4
TXD4
TIOA1
TIOA2
SCK1
SCK2
SCK0
Note:
1. Not available in the 208-lead PQFP package.
34
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6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
10.3.2
PIO Controller B Multiplexing
Table 10-3. Multiplexing on PIO Controller B
PIO Controller B
Application Usage
I/O Line
PB0
Peripheral A
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
SPI1_NPCS0
TXD0
Peripheral B
TIOA3
Comments Reset State Power Supply Function
Comments
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
PB1
TIOB3
PB2
TIOA4
PB3
TIOA5
PB4
PB5
RXD0
TXD1
PB6
TCLK1
TCLK2
PB7
RXD1
TXD2
PB8
PB9
RXD2
TXD3
PB10
PB11
PB12(1)
PB13(1)
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
ISI_D8
ISI_D9
ISI_D10
ISI_D11
RXD3
TXD5
RXD5
DRXD
DTXD
TK0
TCLK3
TCLK4
TIOB4
TF0
TD0
RD0
TIOB5
RK0
ISI_D0
RF0
ISI_D1
DSR0
DCD0
DTR0
ISI_D2
ISI_D3
ISI_D4
RI0
ISI_D5
RTS0
ISI_D6
CTS0
ISI_D7
RTS1
ISI_PCK
ISI_VSYNC
ISI_HSYNC
ISI_MCK
CTS1
PCK0
PCK1
Note:
1. Not available in the 208-lead PQFP package.
35
6221ES–ATARM–12-Mar-07
10.3.3
PIO Controller C Multiplexing
Table 10-4. Multiplexing on PIO Controller C
PIO Controller C
Application Usage
I/O Line
PC0
Peripheral A
Peripheral B
SCK3
Comments
AD0
Reset State Power Supply Function
Comments
I/O
I/O
I/O
I/O
A23
A24
I/O
I/O
I/O
I/O
A25
I/O
I/O
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
PC1
PCK0
AD1
PC2(1)
PC3(1)
PC4
PCK1
AD2
SPI1_NPCS3
SPI1_NPCS2
SPI1_NPCS1
CFCE1
AD3
A23
PC5
A24
PC6
TIOB2
PC7
TIOB1
CFCE2
PC8
NCS4/CFCS0
NCS5/CFCS1
A25/CFRNW
NCS2
RTS3
PC9
TIOB0
PC10
PC11
PC12(1)
CTS3
SPI0_NPCS1
NCS7
IRQ0
RDY/BUSY
signal for
NANDFlash in
the ROM boot
PC13
FIQ
NCS6
I/O
VDDIOM
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
NCS3/NANDCS
NWAIT
D16
IRQ2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
IRQ1
SPI0_NPCS2
SPI0_NPCS3
SPI1_NPCS1
SPI1_NPCS2
SPI1_NPCS3
EF100
D17
D18
D19
D20
D21
D22
TCLK5
D23
D24
D25
D26
D27
D28
D29
D30
D31
Note:
1. Not available in the 208-lead PQFP package.
36
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6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
10.4 Embedded Peripherals
10.4.1
Serial Peripheral Interface
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
10.4.2
10.4.3
Two-wire Interface
• Master, MultiMaster and Slave modes supported
• General Call supported in Slave mode
USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Optional modem signal management DTR-DSR-DCD-RI
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
37
6221ES–ATARM–12-Mar-07
• IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
The USART contains features allowing management of the Modem Signals DTR, DSR, DCD
and RI. In the AT91SAM9260, only the USART0 implements these signals, named DTR0,
DSR0, DCD0 and RI0.
The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1
and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features.
Thus, programming the USART1, USART2 or the USART3 in Modem Mode may lead to unpre-
dictable results. In these USARTs, the commands relating to the Modem Mode have no effect
and the status bits relating the status of the modem signals are never activated.
10.4.4
Serial Synchronous Controller
• Provides serial synchronous communication links used in audio and telecom applications
(with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
• Contains an independent receiver and transmitter and a common clock divider
• Offers a configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal
10.4.5
Timer Counter
• Six 16-bit Timer Counter Channels
• Wide range of functions including
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
• Each channel is user-configurable and contains
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
• Two global registers that act on all three TC Channels
10.4.6
Multimedia Card Interface
• One double-channel MultiMedia Card Interface
• Compatibility with MultiMedia Card Specification Version 2.2
• Compatibility with SD Memory Card Specification Version 1.0
38
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
• Compatibility with SDIO Specification Version V1.0.
• Card clock rate up to Master Clock divided by 2
• Embedded power management to slow down clock rate when not used
• MCI has two slots, each supporting
– One slot for one MultiMediaCard bus (up to 30 cards) or
– One SD Memory Card
• Support for stream, block and multi-block data read and write
10.4.7
USB Host Port
• Compliance with Open HCI Rev 1.0 Specification
• Compliance with USB V2.0 Full-speed and Low-speed Specification
• Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices
• Root hub integrated with two downstream USB ports in the 217-LFBGA package
• Two embedded USB transceivers
• Supports power management
• Operates as a master on the Matrix
10.4.8
USB Device Port
• USB V2.0 full-speed compliant, 12 MBits per second
• Embedded USB V2.0 full-speed transceiver
• Embedded 2,432-byte dual-port RAM for endpoints
• Suspend/Resume logic
• Ping-pong mode (two memory banks) for isochronous and bulk endpoints
• Six general-purpose endpoints
– Endpoint 0 and 3: 64 bytes, no ping-pong mode
– Endpoint 1 and 2: 64 bytes, ping-pong mode
– Endpoint 4 and 5: 512 bytes, ping-pong mode
• Embedded pad pull-up
10.4.9
Ethernet 10/100 MAC
• Compatibility with IEEE Standard 802.3
• 10 and 100 MBits per second data throughput capability
• Full- and half-duplex operations
• MII or RMII interface to the physical layer
• Register Interface to address, data, status and control registers
• DMA Interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 28-byte transmit and 28-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Support promiscuous mode where all valid frames are copied to memory
• Support physical layer management through MDIO interface
39
6221ES–ATARM–12-Mar-07
10.4.10 Image Sensor Interface
• ITU-R BT. 601/656 8-bit mode external interface support
• Support for ITU-R BT.656-4 SAV and EAV synchronization
• Vertical and horizontal resolutions up to 2048 x 2048
• Preview Path up to 640*480
• Support for packed data formatting for YCbCr 4:2:2 formats
• Preview scaler to generate smaller size image
• Programmable frame capture rate
10.4.11 Analog-to-Digital Converter
• 4-channel ADC
• 10-bit 312K samples/sec. Successive Approximation Register ADC
• -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity
• Individual enable and disable of each channel
• External voltage reference for better accuracy on low voltage inputs
• Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter
0 to 2 outputs TIOA0 to TIOA2 trigger
• Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep
mode after conversions of all enabled channels
• Four analog inputs shared with digital signals
40
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
11. Package Drawings
Figure 11-1. 208-lead TQFP Package Drawing
41
6221ES–ATARM–12-Mar-07
Figure 11-2. 217-ball LFBGA Package Drawing
42
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
AT91SAM9260 Preliminary
12. AT91SAM9260 Ordering Information
Table 12-1. AT91SAM9260 Ordering Information
Ordering Code
AT91SAM9260-QU
AT91SAM9260-CJ
Package
PQFP208
BGA217
Package Type
Temperature Operating Range
Green
Industrial
-40°C to 85°C
RoHS-compliant
43
6221ES–ATARM–12-Mar-07
13. Revision History
Table 13-1. Revision History
Change Request
Ref.
Revision
Comments
6221AS
First issue.
Power consumption figures updated with current values in Section 5.2 ”Power
Consumption” on page 14.
6221BS
2843
2874
Change to signal name for pin 47 in Section 4-1 ”Pinout for 208-pin PQFP Package”
on page 11.
For VDDIOP1, added supported voltage levels in Table 3-1, “Signal Description List,”
on page 5 and corrected supported voltage levels in Section 5.2 ”Power
Consumption” on page 14.
Removed package marking and updated package outline information in Section 4.
”Package and Pinout” on page 10.
2922
2907
2947
2979
Change to signal name for pin 147 in Section 4-1 ”Pinout for 208-pin PQFP Package”
on page 11.
6221CS
Inserted new voltage information for JTAGSEL signal in Table 3-1, “Signal Description
List” and in Section 6.1 ”JTAG Port Pins” on page 15.
In Table 3-1, “Signal Description List,” on page 5, added new voltage information for
OSCSEL and TST pins.
In Section 6.3 ”Reset Pins” on page 15, new information on NRST and NRTST pins.
Corrected ADC features in Section 10.4.11 ”Analog-to-Digital Converter” on page 40.
3003
2923
Removed references to VDDOSC in “Features” , in Table 3-1, “Signal Description
List”, and in Section 5.1 ”Power Supplies” on page 14. Corrected VDDPLLA and
VDDPLLB with VDDPLL and GNDPLLA and GNDPLLB with GNDPLL in Table 4-1,
“Pinout for 208-pin PQFP Package,” on page 11 and in Table 4-2, “Pinout for 217-ball
LFBGA Package,” on page 13.
3183
In Figure 2-1 on page 4, corrected range for SCKx pins; label change on matrix block. 3235, 3071
6221DS
In Figure 2-1 on page 4 and Section 7.3 ”Peripheral DMA Controller” on page 19,
3066
removed TWI PDC channels.
In Section 6.3 ”Reset Pins” on page 15, added NRST as bidirectional.
In Figure 9-3 on page 30, added UHPCK as USB Clock Controller output.
In Section 10.4.3 ”USART” on page 37, added information on modem signals.
3236
3237
3245
Updated information on programmable pull-up resistor in Section 6.4 ”PIO
Controllers” on page 15.
3972
Updated Section 6.7 ”Slow Clock Selection” on page 16.
6221ES
In Table 10-1, “AT91SAM9260 Peripheral Identifiers,” on page 32, added Note on
clocking and corrected Peripheral Name for PID12, PID13 and PID14.
3504 and 3543
3406
Placed comment on RDY/BUSY with PC13 in Table 10-4, “Multiplexing on PIO
Controller C,” on page 36.
44
AT91SAM9260 Preliminary
6221ES–ATARM–12-Mar-07
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