AT90CAN32-16AU [ATMEL]
Microcontroller with 32K/64K/128K Bytes of ISP Flash and CAN Controller; 单片机具有ISP功能的Flash和CAN控制器32K / 64K / 128K字节型号: | AT90CAN32-16AU |
厂家: | ATMEL |
描述: | Microcontroller with 32K/64K/128K Bytes of ISP Flash and CAN Controller |
文件: | 总16页 (文件大小:273K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
High-performance, Low-power AVR® 8-bit Microcontroller
Advanced RISC Architecture
•
•
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
•
Non volatile Program and Data Memories
8-bit
– 32K/64K/128K Bytes of In-System Reprogrammable Flash (AT90CAN32/64/128)
• Endurance: 10,000 Write/Erase Cycles
Microcontroller
with
– Optional Boot Code Section with Independent Lock Bits
• Selectable Boot Size: 1K Bytes, 2K Bytes, 4K Bytes or 8K Bytes
• In-System Programming by On-Chip Boot Program (CAN, UART)
• True Read-While-Write Operation
32K/64K/128K
Bytes of
– 1K/2K/4K Bytes EEPROM (Endurance: 100,000 Write/Erase Cycles) (AT90CAN32/64/128
– 2K/4K/4K Bytes Internal SRAM (AT90CAN32/64/128)
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Programming Flash (Hardware ISP), EEPROM, Lock & Fuse Bits
– Extensive On-chip Debug Support
)
ISP Flash
and
•
•
CAN Controller
CAN Controller 2.0A & 2.0B - ISO 16845 Certified
– 15 Full Message Objects with Separate Identifier Tags and Masks
– Transmit, Receive, Automatic Reply and Frame Buffer Receive Modes
– 1Mbits/s Maximum Transfer Rate at 8 MHz
– Time stamping, TTC & Listening Mode (Spying or Autobaud)
Peripheral Features
AT90CAN32
AT90CAN64
AT90CAN128
•
– Programmable Watchdog Timer with On-chip Oscillator
– 8-bit Synchronous Timer/Counter-0
• 10-bit Prescaler
• External Event Counter
Summary
• Output Compare or 8-bit PWM Output
– 8-bit Asynchronous Timer/Counter-2
• 10-bit Prescaler
• External Event Counter
• Output Compare or 8-Bit PWM Output
• 32Khz Oscillator for RTC Operation
– Dual 16-bit Synchronous Timer/Counters-1 & 3
• 10-bit Prescaler
• Input Capture with Noise Canceler
• External Event Counter
• 3-Output Compare or 16-Bit PWM Output
• Output Compare Modulation
– 8-channel, 10-bit SAR ADC
• 8 Single-ended Channels
• 7 Differential Channels
• 2 Differential Channels With Programmable Gain at 1x, 10x, or 200x
Rev. 7679BS–CAN–11/06
– On-chip Analog Comparator
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USART
– Master/Slave SPI Serial Interface
• Programming Flash (Hardware ISP)
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– 8 External Interrupt Sources
– 5 Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down & Standby
– Software Selectable Clock Frequency
– Global Pull-up Disable
•
•
I/O and Packages
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-lead QFN
Operating Voltages
•
•
•
– 2.7 - 5.5V
Operating temperature
– Industrial (-40°C to +85°C)
Maximum Frequency
– 8 MHz at 2.7V - Industrial range
– 16 MHz at 4.5V - Industrial range
1. Description
1.1
Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128
AT90CAN32, AT90CAN64 and AT90CAN128 are all hardware and software compatible with
each other, the only difference is the memory size.
Table 1-1.
Device
Memory Size Summary
Flash
EEPROM
1K Byte
2K Bytes
4K Byte
RAM
AT90CAN32
AT90CAN64
AT90CAN128
32K Bytes
2K Bytes
4K Bytes
4K Bytes
64K Bytes
128K Bytes
1.2
Part Desription
The AT90CAN32/64/128 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
AT90CAN32/64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
2
AT90CAN32/64/128
7679BS–CAN–11/06
AT90CAN32/64/128
The AT90CAN32/64/128 provides the following features: 32K/64K/128K bytes of In-System Pro-
grammable Flash with Read-While-Write capabilities, 1K/2K/4K bytes EEPROM, 2K/4K/4K
bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a CAN con-
troller, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2
USARTs, a byte oriented Two-wire Serial Interface, an 8-channel 10-bit ADC with optional differ-
ential input stage with programmable gain, a programmable Watchdog Timer with Internal
Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for
accessing the On-chip Debug system and programming and five software selectable power sav-
ing modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI/CAN ports and
interrupt system to continue functioning. The Power-down mode saves the register contents but
freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware
Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to main-
tain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops
the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise
during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the
rest of the device is sleeping. This allows very fast start-up combined with low power
consumption.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel AT90CAN32/64/128 is a powerful microcontroller that provides a highly flexible and
cost effective solution to many embedded control applications.
The AT90CAN32/64/128 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula-
tors, and evaluation kits.
3
7679BS–CAN–11/06
1.3
Block Diagram
Figure 1-1. Block Diagram
4
AT90CAN32/64/128
7679BS–CAN–11/06
AT90CAN32/64/128
1.4
Pin Configurations
Figure 1-2. Pinout AT90CAN32/64/128 - TQFP
5
7679BS–CAN–11/06
Figure 1-3. Pinout AT90CAN32/64/128 - QFN
Note:
The large center pad underneath the QFN package is made of metal and internally connected to
GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center
pad is left unconnected, the package might loosen from the board.
6
AT90CAN32/64/128
7679BS–CAN–11/06
AT90CAN32/64/128
1.5
Pin Descriptions
1.5.1
VCC
Digital supply voltage.
1.5.2
1.5.3
GND
Ground.
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the AT90CAN32/64/128 as listed
on I/O-Ports paragraph of the complete Datasheet.
1.5.4
1.5.5
1.5.6
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the AT90CAN32/64/128 as listed
on I/O-Ports paragraph of the complete Datasheet.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the AT90CAN32/64/128 as listed on I/O-
Ports paragraph of the complete Datasheet.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the AT90CAN32/64/128 as listed
on I/O-Ports paragraph of the complete Datasheet.
1.5.7
Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
7
7679BS–CAN–11/06
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the AT90CAN32/64/128 as listed
on I/O-Ports paragraph of the complete Datasheet.
1.5.8
Port F (PF7..PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull-
up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.
1.5.9
Port G (PG4..PG0)
Port G is a 5-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output
buffers have symmetrical drive characteristics with both high sink and source capability. As
inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are
activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port G also serves the functions of various special features of the AT90CAN32/64/128 as listed
on I/O-Ports paragraph of the complete Datasheet.
1.5.10
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset. The minimum pulse length is given in characteristics. Shorter pulses are not guaranteed
to generate a reset. The I/O ports of the AVR are immediately reset to their initial state even if
the clock is not running. The clock is needed to reset the rest of the AT90CAN32/64/128.
1.5.11
1.5.12
1.5.13
XTAL1
XTAL2
AVCC
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier.
AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally con-
nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
1.5.14
AREF
This is the analog reference pin for the A/D Converter.
8
AT90CAN32/64/128
7679BS–CAN–11/06
AT90CAN32/64/128
2. Register Summary
Name
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Comment
(0xFF)
(0xFE)
(0xFD)
(0xFC)
(0xFB)
(0xFA)
(0xF9)
(0xF8)
(0xF7)
(0xF6)
(0xF5)
(0xF4)
(0xF3)
(0xF2)
(0xF1)
(0xF0)
(0xEF)
(0xEE)
(0xED)
(0xEC)
(0xEB)
(0xEA)
(0xE9)
(0xE8)
(0xE7)
(0xE6)
(0xE5)
(0xE4)
(0xE3)
(0xE2)
(0xE1)
(0xE0)
(0xDF)
(0xDE)
(0xDD)
(0xDC)
(0xDB)
(0xDA)
(0xD9)
(0xD8)
(0xD7)
(0xD6)
(0xD5)
(0xD4)
(0xD3)
(0xD2)
(0xD1)
(0xD0)
(0xCF)
(0xCE)
(0xCD)
(0xCC)
(0xCB)
(0xCA)
(0xC9)
(0xC8)
(0xC7)
(0xC6)
(0xC5)
(0xC4)
(0xC3)
(0xC2)
(0xC1)
(0xC0)
(0xBF)
Reserved
Reserved
Reserved
Reserved
Reserved
CANMSG
CANSTMH
CANSTML
CANIDM1
CANIDM2
CANIDM3
CANIDM4
CANIDT1
CANIDT2
CANIDT3
CANIDT4
CANCDMOB
CANSTMOB
CANPAGE
CANHPMOB
CANREC
CANTEC
CANTTCH
CANTTCL
CANTIMH
CANTIML
CANTCON
CANBT3
CANBT2
CANBT1
CANSIT1
CANSIT2
CANIE1
MSG 7
TIMSTM15
TIMSTM7
IDMSK28
IDMSK20
IDMSK12
MSG 6
TIMSTM14
TIMSTM6
IDMSK27
IDMSK19
IDMSK11
MSG 5
TIMSTM13
TIMSTM5
IDMSK26
IDMSK18
IDMSK10
MSG 4
TIMSTM12
TIMSTM4
IDMSK25
IDMSK17
MSG 3
TIMSTM11
TIMSTM3
IDMSK24
IDMSK16
MSG 2
TIMSTM10
TIMSTM2
IDMSK23
IDMSK15
MSG 1
TIMSTM9
TIMSTM1
IDMSK22
IDMSK14
MSG 0
TIMSTM8
TIMSTM0
IDMSK21
IDMSK13
IDMSK
9
1
IDMSK
8
0
IDMSK
7
IDMSK
6
IDMSK5
IDMSK
4
IDMSK
3
IDMSK
2
IDMSK
IDMSK
RTRMSK
IDT23
–
IDEMSK
IDT21
IDT28
IDT20
IDT12
IDT27
IDT19
IDT11
IDT26
IDT18
IDT10
IDT25
IDT17
IDT24
IDT16
IDT22
IDT14
IDT15
IDT13
IDT
9
1
IDT
IDT
8
0
IDT
7
IDT6
IDT5
IDT
4
IDT3
IDT2
IDT
RTRTAG
DLC2
RB1TAG
DLC1
RB0TAG
DLC0
CONMOB1
DLCW
MOBNB3
HPMOB3
REC7
TEC7
TIMTTC15
TIMTTC7
CANTIM15
CANTIM7
TPRSC7
–
CONMOB0
TXOK
RPLV
RXOK
IDE
BERR
DLC3
SERR
CERR
FERR
AERR
MOBNB2
HPMOB2
REC6
MOBNB1
HPMOB1
REC5
MOBNB0
HPMOB0
REC4
AINC
INDX2
INDX1
INDX0
CGP0
CGP3
CGP2
CGP1
REC3
REC2
REC1
REC0
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
TIMTTC14
TIMTTC6
CANTIM14
CANTIM6
TPRSC6
PHS22
TIMTTC13
TIMTTC5
CANTIM13
CANTIM5
TPRSC5
PHS21
SJW0
TIMTTC12
TIMTTC4
CANTIM12
CANTIM4
TPRSC4
PHS20
–
TIMTTC11
TIMTTC3
CANTIM11
CANTIM3
TPRSC3
PHS12
PRS2
TIMTTC10
TIMTTC2
CANTIM10
CANTIM2
TPRSC2
PHS11
PRS1
TIMTTC9
TIMTTC1
CANTIM9
CANTIM1
TRPSC1
PHS10
PRS0
TIMTTC8
TIMTTC0
CANTIM8
CANTIM0
TPRSC0
SMP
–
SJW1
–
–
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
–
–
SIT14
SIT13
SIT12
SIT11
SIT10
SIT9
SIT8
SIT7
SIT6
SIT5
SIT4
SIT3
SIT2
SIT1
SIT0
–
IEMOB14
IEMOB6
ENMOB14
ENMOB6
ENBOFF
BOFFIT
OVRG
IEMOB13
IEMOB5
ENMOB13
ENMOB5
ENRX
IEMOB12
IEMOB4
ENMOB12
ENMOB4
ENTX
IEMOB11
IEMOB3
ENMOB11
ENMOB3
ENERR
SERG
IEMOB10
IEMOB2
ENMOB10
ENMOB2
ENBX
IEMOB9
IEMOB1
ENMOB9
ENMOB1
ENERG
FERG
IEMOB8
IEMOB0
ENMOB8
ENMOB0
ENOVRT
AERG
CANIE2
IEMOB7
–
CANEN1
CANEN2
CANGIE
ENMOB7
ENIT
CANGIT
CANIT
–
OVRTIM
–
BXOK
CERG
CANGSTA
CANGCON
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UDR1
TXBSY
SYNTTC
RXBSY
LISTEN
ENFG
BOFF
ERRP
ABRQ
OVRQ
TTC
TEST
ENA/STB
SWRES
UDR17
–
UDR16
–
UDR15
–
UDR14
–
UDR13
UBRR111
UBRR13
UDR12
UBRR110
UBRR12
UDR11
UBRR19
UBRR11
UDR10
UBRR18
UBRR10
UBRR1H
UBRR1L
Reserved
UCSR1C
UCSR1B
UCSR1A
Reserved
UDR0
UBRR17
UBRR16
UBRR15
UBRR14
–
UMSEL1
TXCIE1
TXC1
UPM11
UDRIE1
UDRE1
UPM10
RXEN1
FE1
USBS1
TXEN1
DOR1
UCSZ11
UCSZ12
UPE1
UCSZ10
RXB81
U2X1
UCPOL1
TXB81
RXCIE1
RXC1
MPCM1
UDR07
–
UDR06
–
UDR05
–
UDR04
–
UDR03
UBRR011
UBRR03
UDR02
UBRR010
UBRR02
UDR01
UBRR09
UBRR01
UDR00
UBRR08
UBRR00
UBRR0H
UBRR0L
Reserved
UCSR0C
UCSR0B
UCSR0A
Reserved
UBRR07
UBRR06
UBRR05
UBRR04
–
UMSEL0
TXCIE0
TXC0
UPM01
UDRIE0
UDRE0
UPM00
RXEN0
FE0
USBS0
TXEN0
DOR0
UCSZ01
UCSZ02
UPE0
UCSZ00
RXB80
U2X0
UCPOL0
TXB80
RXCIE0
RXC0
MPCM0
9
7679BS–CAN–11/06
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Comment
(0xBE)
(0xBD)
(0xBC)
(0xBB)
(0xBA)
(0xB9)
(0xB8)
(0xB7)
(0xB6)
(0xB5)
(0xB4)
(0xB3)
(0xB2)
(0xB1)
(0xB0)
(0xAF)
(0xAE)
(0xAD)
(0xAC)
(0xAB)
(0xAA)
(0xA9)
(0xA8)
(0xA7)
(0xA6)
(0xA5)
(0xA4)
(0xA3)
(0xA2)
(0xA1)
(0xA0)
(0x9F)
(0x9E)
(0x9D)
(0x9C)
(0x9B)
(0x9A)
(0x99)
(0x98)
(0x97)
(0x96)
(0x95)
(0x94)
(0x93)
(0x92)
(0x91)
(0x90)
(0x8F)
(0x8E)
(0x8D)
(0x8C)
(0x8B)
(0x8A)
(0x89)
(0x88)
(0x87)
(0x86)
(0x85)
(0x84)
(0x83)
(0x82)
(0x81)
(0x80)
(0x7F)
(0x7E)
(0x7D)
Reserved
Reserved
TWCR
TWINT
TWDR7
TWAR6
TWS7
TWEA
TWDR6
TWAR5
TWS6
TWSTA
TWDR5
TWAR4
TWS5
TWSTO
TWDR4
TWAR3
TWS4
TWWC
TWDR3
TWAR2
TWS3
TWEN
TWDR2
TWAR1
–
–
TWIE
TWDR
TWDR1
TWAR0
TWPS1
TWBR1
TWDR0
TWGCE
TWPS0
TWBR0
TWAR
TWSR
TWBR
TWBR7
TWBR6
TWBR5
TWBR4
TWBR3
TWBR2
Reserved
ASSR
–
–
–
EXCLK
AS2
TCN2UB
OCR2UB
TCR2UB
Reserved
Reserved
OCR2A
OCR2A7
TCNT27
OCR2A6
TCNT26
OCR2A5
TCNT25
OCR2A4
TCNT24
OCR2A3
TCNT23
OCR2A2
TCNT22
OCR2A1
TCNT21
OCR2A0
TCNT20
TCNT2
Reserved
TCCR2A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OCR3CH
OCR3CL
OCR3BH
OCR3BL
OCR3AH
OCR3AL
ICR3H
FOC2A
WGM20
COM2A1
COM2A0
WGM21
CS22
CS21
CS20
OCR3C15
OCR3C7
OCR3B15
OCR3B7
OCR3A15
OCR3A7
ICR315
OCR3C14
OCR3C6
OCR3B14
OCR3B6
OCR3A14
OCR3A6
ICR314
OCR3C13
OCR3C5
OCR3B13
OCR3B5
OCR3A13
OCR3A5
ICR313
OCR3C12
OCR3C4
OCR3B12
OCR3B4
OCR3A12
OCR3A4
ICR312
OCR3C11
OCR3C3
OCR3B11
OCR3B3
OCR3A11
OCR3A3
ICR311
OCR3C10
OCR3C2
OCR3B10
OCR3B2
OCR3A10
OCR3A2
ICR310
OCR3C9
OCR3C1
OCR3B9
OCR3B1
OCR3A9
OCR3A1
ICR39
OCR3C8
OCR3C0
OCR3B8
OCR3B0
OCR3A8
OCR3A0
ICR38
ICR3L
ICR37
ICR36
ICR35
ICR34
ICR33
ICR32
ICR31
ICR30
TCNT3H
TCNT3L
Reserved
TCCR3C
TCCR3B
TCCR3A
Reserved
Reserved
OCR1CH
OCR1CL
OCR1BH
OCR1BL
OCR1AH
OCR1AL
ICR1H
TCNT315
TCNT37
TCNT314
TCNT36
TCNT313
TCNT35
TCNT312
TCNT34
TCNT311
TCNT33
TCNT310
TCNT32
TCNT39
TCNT31
TCNT38
TCNT30
FOC3A
ICNC3
FOC3B
ICES3
FOC3C
–
–
–
–
–
WGM33
COM3B0
WGM32
COM3C1
CS32
CS31
CS30
COM3A1
COM3A0
COM3B1
COM3C0
WGM31
WGM30
OCR1C15
OCR1C7
OCR1B15
OCR1B7
OCR1A15
OCR1A7
ICR115
OCR1C14
OCR1C6
OCR1B14
OCR1B6
OCR1A14
OCR1A6
ICR114
OCR1C13
OCR1C5
OCR1B13
OCR1B5
OCR1A13
OCR1A5
ICR113
OCR1C12
OCR1C4
OCR1B12
OCR1B4
OCR1A12
OCR1A4
ICR112
OCR1C11
OCR1C3
OCR1B11
OCR1B3
OCR1A11
OCR1A3
ICR111
OCR1C10
OCR1C2
OCR1B10
OCR1B2
OCR1A10
OCR1A2
ICR110
OCR1C9
OCR1C1
OCR1B9
OCR1B1
OCR1A9
OCR1A1
ICR19
OCR1C8
OCR1C0
OCR1B8
OCR1B0
OCR1A8
OCR1A0
ICR18
ICR1L
ICR17
ICR16
ICR15
ICR14
ICR13
ICR12
ICR11
ICR10
TCNT1H
TCNT1L
Reserved
TCCR1C
TCCR1B
TCCR1A
DIDR1
TCNT115
TCNT17
TCNT114
TCNT16
TCNT113
TCNT15
TCNT112
TCNT14
TCNT111
TCNT13
TCNT110
TCNT12
TCNT19
TCNT11
TCNT18
TCNT10
FOC1A
ICNC1
COM1A1
–
FOC1B
ICES1
COM1A0
–
FOC1C
–
–
–
–
–
–
WGM13
COM1B0
–
WGM12
COM1C1
–
CS12
COM1C0
–
CS11
CS10
COM1B1
–
WGM11
AIN1D
ADC1D
WGM10
AIN0D
ADC0D
DIDR0
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
Reserved
10
AT90CAN32/64/128
7679BS–CAN–11/06
AT90CAN32/64/128
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Comment
(0x7C)
(0x7B)
ADMUX
ADCSRB
ADCSRA
ADCH
REFS1
–
REFS0
ACME
ADLAR
–
MUX4
–
MUX3
–
MUX2
ADTS2
ADPS2
- / ADC4
ADC2 / -
MUX1
ADTS1
MUX0
ADTS0
(0x7A)
ADEN
- / ADC9
ADSC
ADATE
- / ADC7
ADC5 / -
ADIF
ADIE
ADPS1
ADPS0
(0x79)
- / ADC8
- / ADC6
ADC4 / -
- / ADC5
ADC3 / -
ADC9 / ADC3
ADC1 / -
ADC8 / ADC2
ADC0 /
(0x78)
ADCL
ADC7 / ADC1 ADC6 / ADC0
(0x77)
Reserved
Reserved
XMCRB
XMCRA
Reserved
Reserved
TIMSK3
TIMSK2
TIMSK1
TIMSK0
Reserved
Reserved
Reserved
EICRB
(0x76)
(0x75)
XMBK
SRE
–
–
–
–
XMM2
XMM1
XMM0
(0x74)
SRL2
SRL1
SRL0
SRW11
SRW10
SRW01
SRW00
(0x73)
(0x72)
(0x71)
–
–
–
–
–
–
–
–
ICIE3
–
–
–
–
–
OCIE3C
OCIE3B
OCIE3A
OCIE2A
OCIE1A
OCIE0A
TOIE3
TOIE2
TOIE1
TOIE0
(0x70)
–
OCIE1C
–
–
OCIE1B
–
(0x6F)
ICIE1
–
(0x6E)
(0x6D)
(0x6C)
(0x6B)
(0x6A)
ISC71
ISC31
ISC70
ISC30
ISC61
ISC21
ISC60
ISC20
ISC51
ISC11
ISC50
ISC10
ISC41
ISC01
ISC40
ISC00
(0x69)
EICRA
(0x68)
Reserved
Reserved
OSCCAL
Reserved
Reserved
Reserved
Reserved
CLKPR
WDTCR
SREG
(0x67)
(0x66)
–
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
(0x65)
(0x64)
(0x63)
(0x62)
(0x61)
CLKPCE
–
–
–
–
–
WDCE
S
CLKPS3
WDE
V
CLKPS2
WDP2
N
CLKPS1
WDP1
Z
CLKPS0
WDP0
C
(0x60)
–
I
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
T
H
SPH
SP15
SP7
SP14
SP6
SP13
SP5
SP12
SP4
SP11
SP3
SP10
SP2
SP9
SP8
SPL
SP1
SP0
Reserved
RAMPZ
Reserved
Reserved
Reserved
SPMCSR
Reserved
MCUCR
MCUSR
SMCR
(1)
–
–
–
–
–
–
–
RAMPZ0
SPMIE
RWWSB
–
–
–
–
–
RWWSRE
BLBSET
PGWRT
–
PGERS
–
SPMEN
–
–
JTD
–
–
–
–
–
–
–
–
PUD
JTRF
–
–
IVSEL
EXTRF
SM0
IVCE
PORF
SE
WDRF
SM2
BORF
SM1
–
Reserved
OCDR
IDRD/OCDR7
ACD
OCDR6
ACBG
OCDR5
ACO
OCDR4
ACI
OCDR3
ACIE
OCDR2
ACIC
OCDR1
ACIS1
OCDR0
ACIS0
ACSR
Reserved
SPDR
SPD7
SPIF
SPD6
WCOL
SPD5
–
SPD4
–
SPD3
–
SPD2
–
SPD1
–
SPD0
SPI2X
SPSR
SPCR
SPIE
SPE
DORD
GPIOR25
GPIOR15
MSTR
CPOL
CPHA
SPR1
SPR0
GPIOR2
GPIOR1
Reserved
Reserved
OCR0A
TCNT0
GPIOR27
GPIOR17
GPIOR26
GPIOR16
GPIOR24
GPIOR14
GPIOR23
GPIOR13
GPIOR22
GPIOR12
GPIOR21
GPIOR11
GPIOR20
GPIOR10
OCR0A7
TCNT07
OCR0A6
TCNT06
OCR0A5
TCNT05
OCR0A4
TCNT04
OCR0A3
TCNT03
OCR0A2
TCNT02
OCR0A1
TCNT01
OCR0A0
TCNT00
Reserved
TCCR0A
GTCCR
EEARH
EEARL
FOC0A
TSM
WGM00
–
COM0A1
–
COM0A0
–
WGM01
–
CS02
–
CS01
PSR2
CS00
PSR310
EEAR8
EEAR0
EEDR0
EERE
(2)
–
–
–
–
EEAR11
EEAR3
EEDR3
EERIE
GPIOR03
INT3
EEAR10
EEAR2
EEDR2
EEMWE
GPIOR02
INT2
EEAR9
EEAR1
EEDR1
EEWE
GPIOR01
INT1
EEAR7
EEDR7
–
EEAR6
EEDR6
–
EEAR5
EEDR5
–
EEAR4
EEDR4
–
EEDR
EECR
GPIOR0
EIMSK
GPIOR07
INT7
GPIOR06
INT6
GPIOR05
INT5
GPIOR04
INT4
GPIOR00
INT0
EIFR
INTF7
INTF6
INTF5
INTF4
INTF3
INTF2
INTF1
INTF0
Reserved
11
7679BS–CAN–11/06
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Comment
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
Reserved
Reserved
TIFR3
TIFR2
TIFR1
TIFR0
PORTG
DDRG
PING
–
–
–
–
ICF3
–
–
OCF3C
–
OCF3B
–
OCF3A
OCF2A
OCF1A
OCF0A
PORTG1
DDG1
TOV3
TOV2
–
–
–
ICF1
–
OCF1C
–
OCF1B
–
TOV1
–
–
–
–
TOV0
–
–
–
PORTG4
DDG4
PING4
PORTF4
DDF4
PINF4
PORTE4
DDE4
PINE4
PORTD4
DDD4
PIND4
PORTC4
DDC4
PINC4
PORTB4
DDB4
PINB4
PORTA4
DDA4
PINA4
PORTG3
DDG3
PING3
PORTF3
DDF3
PORTG2
DDG2
PING2
PORTF2
DDF2
PORTG0
DDG0
–
–
–
–
–
–
PING1
PORTF1
DDF1
PING0
PORTF0
DDF0
PORTF
DDRF
PINF
PORTF7
DDF7
PINF7
PORTE7
DDE7
PINE7
PORTD7
DDD7
PIND7
PORTC7
DDC7
PINC7
PORTB7
DDB7
PINB7
PORTA7
DDA7
PINA7
PORTF6
DDF6
PINF6
PORTE6
DDE6
PINE6
PORTD6
DDD6
PIND6
PORTC6
DDC6
PINC6
PORTB6
DDB6
PINB6
PORTA6
DDA6
PINA6
PORTF5
DDF5
PINF5
PORTE5
DDE5
PINE5
PORTD5
DDD5
PIND5
PORTC5
DDC5
PINC5
PORTB5
DDB5
PINB5
PORTA5
DDA5
PINA5
PINF3
PORTE3
DDE3
PINF2
PORTE2
DDE2
PINF1
PINF0
PORTE
DDRE
PINE
PORTE1
DDE1
PORTE0
DDE0
PINE3
PORTD3
DDD3
PINE2
PORTD2
DDD2
PINE1
PINE0
PORTD0
DDD0
PORTD
DDRD
PIND
PORTD1
DDD1
PIND3
PORTC3
DDC3
PIND2
PORTC2
DDC2
PIND1
PORTC1
DDC1
PIND0
PORTC0
DDC0
PORTC
DDRC
PINC
PINC3
PORTB3
DDB3
PINC2
PORTB2
DDB2
PINC1
PORTB1
DDB1
PINC0
PORTB0
DDB0
PORTB
DDRB
PINB
PINB3
PORTA3
DDA3
PINB2
PORTA2
DDA2
PINB1
PINB0
PORTA0
DDA0
PORTA
DDRA
PINA
PORTA1
DDA1
PINA3
PINA2
PINA1
PINA0
Notes: 1. Address bits exceeding PCMSB (c.f. complete Datasheet) are don’t care.
2. Address bits exceeding EEAMSB (c.f. complete Datasheet) are don’t care.
3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
4. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
5. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
6. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90CAN32/64/128 is
a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for
the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
12
AT90CAN32/64/128
7679BS–CAN–11/06
AT90CAN32/64/128
3. Ordering Information
(1)
Ordering Code
Speed (MHz)
Power Supply (V)
Package
Operation Range
Product Marking
AT90CAN32-16AI
AT90CAN32-16MI
16
16
2.7 - 5.5
2.7 - 5.5
64A
Industrial (-40°to +85°C)
Industrial (-40°to +85°C)
AT90CAN32-IL
AT90CAN32-IL
64M1
Industrial (-40°to +85°C)
Green
AT90CAN32-16AU
AT90CAN32-16MU
16
16
2.7 - 5.5
2.7 - 5.5
64A
AT90CAN32-UL
AT90CAN32-UL
Industrial (-40°to +85°C)
Green
64M1
AT90CAN64-16AI
AT90CAN64-16MI
16
16
2.7 - 5.5
2.7 - 5.5
64A
Industrial (-40°to +85°C)
Industrial (-40°to +85°C)
AT90CAN64-IL
AT90CAN64-IL
64M1
Industrial (-40°to +85°C)
Green
AT90CAN64-16AU
AT90CAN64-16MU
16
16
2.7 - 5.5
2.7 - 5.5
64A
AT90CAN64-UL
AT90CAN64-UL
Industrial (-40°to +85°C)
Green
64M1
AT90CAN128-16AI
AT90CAN128-16MI
16
16
2.7 - 5.5
2.7 - 5.5
64A
Industrial (-40°to +85°C)
Industrial (-40°to +85°C)
AT90CAN128-IL
AT90CAN128-IL
64M1
Industrial (-40°to +85°C)
Green
AT90CAN128-16AU
AT90CAN128-16MU
16
16
2.7 - 5.5
2.7 - 5.5
64A
AT90CAN128-UL
AT90CAN128-UL
Industrial (-40°to +85°C)
Green
64M1
Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-
tion and minimum quantities.
4. Packaging Information
Package Type
64A
64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
64-Lead, Quad Flat No lead (QFN)
64M1
13
7679BS–CAN–11/06
4.1
TQFP64
14
AT90CAN32/64/128
7679BS–CAN–11/06
AT90CAN32/64/128
4.2
QFN64
15
7679BS–CAN–11/06
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Printed on recycled paper.
7679BS–CAN–11/06
相关型号:
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